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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[net-next-2.6.git] / drivers / net / atlx / atl1.c
CommitLineData
f3cc28c7
JC		 1/*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
305282ba 3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
e8f720fd 4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
f3cc28c7
JC		 5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called COPYING.
25 *
26 * Contact Information:
c8f2d9bc
JC		 27 * Xiong Huang <xiong.huang@atheros.com>
28 * Jie Yang <jie.yang@atheros.com>
f3cc28c7
JC		 29 * Chris Snook <csnook@redhat.com>
30 * Jay Cliburn <jcliburn@gmail.com>
31 *
c8f2d9bc 32 * This version is adapted from the Attansic reference driver.
f3cc28c7
JC		 33 *
34 * TODO:
53ffb42c 35 * Add more ethtool functions.
f3cc28c7
JC		 36 * Fix abstruse irq enable/disable condition described here:
37 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
38 *
39 * NEEDS TESTING:
40 * VLAN
41 * multicast
42 * promiscuous mode
43 * interrupt coalescing
44 * SMP torture testing
45 */
46
305282ba
JC		 47#include <asm/atomic.h>
48#include <asm/byteorder.h>
49
50#include <linux/compiler.h>
51#include <linux/crc32.h>
52#include <linux/delay.h>
53#include <linux/dma-mapping.h>
f3cc28c7 54#include <linux/etherdevice.h>
f3cc28c7 55#include <linux/hardirq.h>
305282ba
JC		 56#include <linux/if_ether.h>
57#include <linux/if_vlan.h>
58#include <linux/in.h>
f3cc28c7 59#include <linux/interrupt.h>
305282ba 60#include <linux/ip.h>
f3cc28c7 61#include <linux/irqflags.h>
305282ba
JC		 62#include <linux/irqreturn.h>
63#include <linux/jiffies.h>
64#include <linux/mii.h>
65#include <linux/module.h>
66#include <linux/moduleparam.h>
f3cc28c7 67#include <linux/net.h>
305282ba
JC		 68#include <linux/netdevice.h>
69#include <linux/pci.h>
70#include <linux/pci_ids.h>
f3cc28c7 71#include <linux/pm.h>
305282ba
JC		 72#include <linux/skbuff.h>
73#include <linux/slab.h>
74#include <linux/spinlock.h>
75#include <linux/string.h>
f3cc28c7 76#include <linux/tcp.h>
305282ba
JC		 77#include <linux/timer.h>
78#include <linux/types.h>
79#include <linux/workqueue.h>
f3cc28c7 80
f3cc28c7
JC		 81#include <net/checksum.h>
82
f3cc28c7
JC		 83#include "atl1.h"
84
5ad18900
AC		 85#define ATLX_DRIVER_VERSION "2.1.3"
86MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, \
44ebb952 87Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>");
5ad18900
AC		 88MODULE_LICENSE("GPL");
89MODULE_VERSION(ATLX_DRIVER_VERSION);
90
305282ba
JC		 91/* Temporary hack for merging atl1 and atl2 */
92#include "atlx.c"
f3cc28c7 93
ff2d8d6c 94static const struct ethtool_ops atl1_ethtool_ops;
95
8ec7226a
CS		 96/*
97 * This is the only thing that needs to be changed to adjust the
98 * maximum number of ports that the driver can manage.
99 */
100#define ATL1_MAX_NIC 4
101
102#define OPTION_UNSET -1
103#define OPTION_DISABLED 0
104#define OPTION_ENABLED 1
105
106#define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
107
108/*
109 * Interrupt Moderate Timer in units of 2 us
110 *
111 * Valid Range: 10-65535
112 *
113 * Default Value: 100 (200us)
114 */
115static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
b79d8fff 116static unsigned int num_int_mod_timer;
8ec7226a
CS		 117module_param_array_named(int_mod_timer, int_mod_timer, int,
118 &num_int_mod_timer, 0);
119MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
120
121#define DEFAULT_INT_MOD_CNT 100 /* 200us */
122#define MAX_INT_MOD_CNT 65000
123#define MIN_INT_MOD_CNT 50
124
125struct atl1_option {
126 enum { enable_option, range_option, list_option } type;
127 char *name;
128 char *err;
129 int def;
130 union {
131 struct { /* range_option info */
132 int min;
133 int max;
134 } r;
135 struct { /* list_option info */
136 int nr;
137 struct atl1_opt_list {
138 int i;
139 char *str;
140 } *p;
141 } l;
142 } arg;
143};
144
145static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
146 struct pci_dev *pdev)
147{
148 if (*value == OPTION_UNSET) {
149 *value = opt->def;
150 return 0;
151 }
152
153 switch (opt->type) {
154 case enable_option:
155 switch (*value) {
156 case OPTION_ENABLED:
157 dev_info(&pdev->dev, "%s enabled\n", opt->name);
158 return 0;
159 case OPTION_DISABLED:
160 dev_info(&pdev->dev, "%s disabled\n", opt->name);
161 return 0;
162 }
163 break;
164 case range_option:
165 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
166 dev_info(&pdev->dev, "%s set to %i\n", opt->name,
167 *value);
168 return 0;
169 }
170 break;
171 case list_option:{
172 int i;
173 struct atl1_opt_list *ent;
174
175 for (i = 0; i < opt->arg.l.nr; i++) {
176 ent = &opt->arg.l.p[i];
177 if (*value == ent->i) {
178 if (ent->str[0] != '\0')
179 dev_info(&pdev->dev, "%s\n",
180 ent->str);
181 return 0;
182 }
183 }
184 }
185 break;
186
187 default:
188 break;
189 }
190
191 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
192 opt->name, *value, opt->err);
193 *value = opt->def;
194 return -1;
195}
196
197/*
198 * atl1_check_options - Range Checking for Command Line Parameters
199 * @adapter: board private structure
200 *
201 * This routine checks all command line parameters for valid user
202 * input. If an invalid value is given, or if no user specified
203 * value exists, a default value is used. The final value is stored
204 * in a variable in the adapter structure.
205 */
9dc20f55 206static void __devinit atl1_check_options(struct atl1_adapter *adapter)
8ec7226a
CS		 207{
208 struct pci_dev *pdev = adapter->pdev;
209 int bd = adapter->bd_number;
210 if (bd >= ATL1_MAX_NIC) {
211 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
212 dev_notice(&pdev->dev, "using defaults for all values\n");
213 }
214 { /* Interrupt Moderate Timer */
215 struct atl1_option opt = {
216 .type = range_option,
217 .name = "Interrupt Moderator Timer",
218 .err = "using default of "
219 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
220 .def = DEFAULT_INT_MOD_CNT,
221 .arg = {.r = {.min = MIN_INT_MOD_CNT,
222 .max = MAX_INT_MOD_CNT} }
223 };
224 int val;
225 if (num_int_mod_timer > bd) {
226 val = int_mod_timer[bd];
227 atl1_validate_option(&val, &opt, pdev);
228 adapter->imt = (u16) val;
229 } else
230 adapter->imt = (u16) (opt.def);
231 }
232}
233
f3cc28c7
JC		 234/*
235 * atl1_pci_tbl - PCI Device ID Table
236 */
a3aa1884 237static DEFINE_PCI_DEVICE_TABLE(atl1_pci_tbl) = {
e81e557a 238 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
f3cc28c7
JC		 239 /* required last entry */
240 {0,}
241};
f3cc28c7
JC		 242MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
243
460578bf
JC		 244static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
245 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
246
247static int debug = -1;
248module_param(debug, int, 0);
249MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
250
f3cc28c7 251/*
6446a860
JC		 252 * Reset the transmit and receive units; mask and clear all interrupts.
253 * hw - Struct containing variables accessed by shared code
254 * return : 0 or idle status (if error)
f3cc28c7 255 */
6446a860 256static s32 atl1_reset_hw(struct atl1_hw *hw)
f3cc28c7 257{
6446a860
JC		 258 struct pci_dev *pdev = hw->back->pdev;
259 struct atl1_adapter *adapter = hw->back;
260 u32 icr;
261 int i;
f3cc28c7 262
6446a860
JC		 263 /*
264 * Clear Interrupt mask to stop board from generating
265 * interrupts & Clear any pending interrupt events
266 */
267 /*
268 * iowrite32(0, hw->hw_addr + REG_IMR);
269 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
270 */
f3cc28c7 271
6446a860
JC		 272 /*
273 * Issue Soft Reset to the MAC. This will reset the chip's
274 * transmit, receive, DMA. It will not effect
275 * the current PCI configuration. The global reset bit is self-
276 * clearing, and should clear within a microsecond.
277 */
278 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
279 ioread32(hw->hw_addr + REG_MASTER_CTRL);
f3cc28c7 280
6446a860
JC		 281 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
282 ioread16(hw->hw_addr + REG_PHY_ENABLE);
f3cc28c7 283
6446a860
JC		 284 /* delay about 1ms */
285 msleep(1);
f3cc28c7 286
6446a860
JC		 287 /* Wait at least 10ms for All module to be Idle */
288 for (i = 0; i < 10; i++) {
289 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
290 if (!icr)
291 break;
292 /* delay 1 ms */
293 msleep(1);
294 /* FIXME: still the right way to do this? */
295 cpu_relax();
296 }
05ffdd7b 297
6446a860
JC		 298 if (icr) {
299 if (netif_msg_hw(adapter))
300 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
301 return icr;
302 }
05ffdd7b 303
6446a860 304 return 0;
05ffdd7b
JC		 305}
306
6446a860
JC		 307/* function about EEPROM
308 *
309 * check_eeprom_exist
310 * return 0 if eeprom exist
311 */
312static int atl1_check_eeprom_exist(struct atl1_hw *hw)
05ffdd7b 313{
6446a860
JC		 314 u32 value;
315 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
316 if (value & SPI_FLASH_CTRL_EN_VPD) {
317 value &= ~SPI_FLASH_CTRL_EN_VPD;
318 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
319 }
05ffdd7b 320
6446a860
JC		 321 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
322 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
05ffdd7b
JC		 323}
324
6446a860 325static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
05ffdd7b 326{
6446a860
JC		 327 int i;
328 u32 control;
05ffdd7b 329
6446a860
JC		 330 if (offset & 3)
331 /* address do not align */
332 return false;
05ffdd7b 333
6446a860
JC		 334 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
335 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
336 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
337 ioread32(hw->hw_addr + REG_VPD_CAP);
05ffdd7b 338
6446a860
JC		 339 for (i = 0; i < 10; i++) {
340 msleep(2);
341 control = ioread32(hw->hw_addr + REG_VPD_CAP);
342 if (control & VPD_CAP_VPD_FLAG)
343 break;
344 }
345 if (control & VPD_CAP_VPD_FLAG) {
346 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
347 return true;
348 }
349 /* timeout */
350 return false;
05ffdd7b
JC		 351}
352
f3cc28c7 353/*
6446a860
JC		 354 * Reads the value from a PHY register
355 * hw - Struct containing variables accessed by shared code
356 * reg_addr - address of the PHY register to read
f3cc28c7 357 */
ff2d8d6c 358static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
f3cc28c7 359{
6446a860
JC		 360 u32 val;
361 int i;
f3cc28c7 362
6446a860
JC		 363 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
364 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
365 MDIO_CLK_SEL_SHIFT;
366 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
367 ioread32(hw->hw_addr + REG_MDIO_CTRL);
f3cc28c7 368
6446a860
JC		 369 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
370 udelay(2);
371 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
372 if (!(val & (MDIO_START | MDIO_BUSY)))
373 break;
374 }
375 if (!(val & (MDIO_START | MDIO_BUSY))) {
376 *phy_data = (u16) val;
377 return 0;
f3cc28c7 378 }
6446a860
JC		 379 return ATLX_ERR_PHY;
380}
f3cc28c7 381
6446a860
JC		 382#define CUSTOM_SPI_CS_SETUP 2
383#define CUSTOM_SPI_CLK_HI 2
384#define CUSTOM_SPI_CLK_LO 2
385#define CUSTOM_SPI_CS_HOLD 2
386#define CUSTOM_SPI_CS_HI 3
f3cc28c7 387
6446a860
JC		 388static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
389{
390 int i;
391 u32 value;
f3cc28c7 392
6446a860
JC		 393 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
394 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
2ca13da7 395
6446a860
JC		 396 value = SPI_FLASH_CTRL_WAIT_READY |
397 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
398 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
399 SPI_FLASH_CTRL_CLK_HI_MASK) <<
400 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
401 SPI_FLASH_CTRL_CLK_LO_MASK) <<
402 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
403 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
404 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
405 SPI_FLASH_CTRL_CS_HI_MASK) <<
406 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
407 SPI_FLASH_CTRL_INS_SHIFT;
f3cc28c7 408
6446a860 409 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
f3cc28c7 410
6446a860
JC		 411 value |= SPI_FLASH_CTRL_START;
412 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
413 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
f3cc28c7 414
6446a860
JC		 415 for (i = 0; i < 10; i++) {
416 msleep(1);
417 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
418 if (!(value & SPI_FLASH_CTRL_START))
419 break;
420 }
f3cc28c7 421
6446a860
JC		 422 if (value & SPI_FLASH_CTRL_START)
423 return false;
f3cc28c7 424
6446a860 425 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
2ca13da7 426
6446a860 427 return true;
f3cc28c7
JC		 428}
429
f3cc28c7 430/*
6446a860
JC		 431 * get_permanent_address
432 * return 0 if get valid mac address,
f3cc28c7 433 */
6446a860 434static int atl1_get_permanent_address(struct atl1_hw *hw)
f3cc28c7 435{
6446a860
JC		 436 u32 addr[2];
437 u32 i, control;
438 u16 reg;
439 u8 eth_addr[ETH_ALEN];
440 bool key_valid;
f3cc28c7 441
6446a860
JC		 442 if (is_valid_ether_addr(hw->perm_mac_addr))
443 return 0;
444
445 /* init */
446 addr[0] = addr[1] = 0;
447
448 if (!atl1_check_eeprom_exist(hw)) {
449 reg = 0;
450 key_valid = false;
451 /* Read out all EEPROM content */
452 i = 0;
453 while (1) {
454 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
455 if (key_valid) {
456 if (reg == REG_MAC_STA_ADDR)
457 addr[0] = control;
458 else if (reg == (REG_MAC_STA_ADDR + 4))
459 addr[1] = control;
460 key_valid = false;
461 } else if ((control & 0xff) == 0x5A) {
462 key_valid = true;
463 reg = (u16) (control >> 16);
464 } else
465 break;
466 } else
467 /* read error */
468 break;
469 i += 4;
05ffdd7b 470 }
6446a860
JC		 471
472 *(u32 *) &eth_addr[2] = swab32(addr[0]);
473 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
474 if (is_valid_ether_addr(eth_addr)) {
475 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
476 return 0;
05ffdd7b
JC		 477 }
478 }
f3cc28c7 479
6446a860
JC		 480 /* see if SPI FLAGS exist ? */
481 addr[0] = addr[1] = 0;
482 reg = 0;
483 key_valid = false;
484 i = 0;
485 while (1) {
486 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
487 if (key_valid) {
488 if (reg == REG_MAC_STA_ADDR)
489 addr[0] = control;
490 else if (reg == (REG_MAC_STA_ADDR + 4))
491 addr[1] = control;
492 key_valid = false;
493 } else if ((control & 0xff) == 0x5A) {
494 key_valid = true;
495 reg = (u16) (control >> 16);
496 } else
497 /* data end */
498 break;
499 } else
500 /* read error */
501 break;
502 i += 4;
503 }
f3cc28c7 504
6446a860
JC		 505 *(u32 *) &eth_addr[2] = swab32(addr[0]);
506 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
507 if (is_valid_ether_addr(eth_addr)) {
508 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
509 return 0;
510 }
f3cc28c7 511
6446a860
JC		 512 /*
513 * On some motherboards, the MAC address is written by the
514 * BIOS directly to the MAC register during POST, and is
515 * not stored in eeprom. If all else thus far has failed
516 * to fetch the permanent MAC address, try reading it directly.
517 */
518 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
519 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
520 *(u32 *) &eth_addr[2] = swab32(addr[0]);
521 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
522 if (is_valid_ether_addr(eth_addr)) {
523 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
524 return 0;
525 }
f3cc28c7 526
6446a860 527 return 1;
f3cc28c7
JC		 528}
529
05ffdd7b 530/*
6446a860
JC		 531 * Reads the adapter's MAC address from the EEPROM
532 * hw - Struct containing variables accessed by shared code
05ffdd7b 533 */
9dc20f55 534static s32 atl1_read_mac_addr(struct atl1_hw *hw)
f3cc28c7 535{
6446a860 536 u16 i;
f3cc28c7 537
6446a860
JC		 538 if (atl1_get_permanent_address(hw))
539 random_ether_addr(hw->perm_mac_addr);
f3cc28c7 540
6446a860
JC		 541 for (i = 0; i < ETH_ALEN; i++)
542 hw->mac_addr[i] = hw->perm_mac_addr[i];
543 return 0;
f3cc28c7
JC		 544}
545
546/*
6446a860
JC		 547 * Hashes an address to determine its location in the multicast table
548 * hw - Struct containing variables accessed by shared code
549 * mc_addr - the multicast address to hash
05ffdd7b 550 *
6446a860
JC		 551 * atl1_hash_mc_addr
552 * purpose
553 * set hash value for a multicast address
554 * hash calcu processing :
555 * 1. calcu 32bit CRC for multicast address
556 * 2. reverse crc with MSB to LSB
f3cc28c7 557 */
ff2d8d6c 558static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
f3cc28c7 559{
6446a860
JC		 560 u32 crc32, value = 0;
561 int i;
f3cc28c7 562
6446a860
JC		 563 crc32 = ether_crc_le(6, mc_addr);
564 for (i = 0; i < 32; i++)
565 value |= (((crc32 >> i) & 1) << (31 - i));
f3cc28c7 566
6446a860 567 return value;
f3cc28c7
JC		 568}
569
6446a860
JC		 570/*
571 * Sets the bit in the multicast table corresponding to the hash value.
572 * hw - Struct containing variables accessed by shared code
573 * hash_value - Multicast address hash value
574 */
ff2d8d6c 575static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
f3cc28c7 576{
6446a860
JC		 577 u32 hash_bit, hash_reg;
578 u32 mta;
579
580 /*
581 * The HASH Table is a register array of 2 32-bit registers.
582 * It is treated like an array of 64 bits. We want to set
583 * bit BitArray[hash_value]. So we figure out what register
584 * the bit is in, read it, OR in the new bit, then write
585 * back the new value. The register is determined by the
586 * upper 7 bits of the hash value and the bit within that
587 * register are determined by the lower 5 bits of the value.
05ffdd7b 588 */
6446a860
JC		 589 hash_reg = (hash_value >> 31) & 0x1;
590 hash_bit = (hash_value >> 26) & 0x1F;
591 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
592 mta |= (1 << hash_bit);
593 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
05ffdd7b 594}
f3cc28c7 595
6446a860
JC		 596/*
597 * Writes a value to a PHY register
598 * hw - Struct containing variables accessed by shared code
599 * reg_addr - address of the PHY register to write
600 * data - data to write to the PHY
601 */
602static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
05ffdd7b 603{
6446a860
JC		 604 int i;
605 u32 val;
f3cc28c7 606
6446a860
JC		 607 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
608 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
609 MDIO_SUP_PREAMBLE |
610 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
611 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
612 ioread32(hw->hw_addr + REG_MDIO_CTRL);
f3cc28c7 613
6446a860
JC		 614 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
615 udelay(2);
616 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
617 if (!(val & (MDIO_START | MDIO_BUSY)))
618 break;
05ffdd7b 619 }
f3cc28c7 620
6446a860 621 if (!(val & (MDIO_START | MDIO_BUSY)))
305282ba 622 return 0;
f3cc28c7 623
6446a860
JC		 624 return ATLX_ERR_PHY;
625}
f3cc28c7 626
6446a860
JC		 627/*
628 * Make L001's PHY out of Power Saving State (bug)
629 * hw - Struct containing variables accessed by shared code
630 * when power on, L001's PHY always on Power saving State
631 * (Gigabit Link forbidden)
632 */
633static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
634{
635 s32 ret;
636 ret = atl1_write_phy_reg(hw, 29, 0x0029);
637 if (ret)
638 return ret;
639 return atl1_write_phy_reg(hw, 30, 0);
640}
641
6446a860
JC		 642/*
643 * Resets the PHY and make all config validate
644 * hw - Struct containing variables accessed by shared code
645 *
646 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
647 */
648static s32 atl1_phy_reset(struct atl1_hw *hw)
649{
650 struct pci_dev *pdev = hw->back->pdev;
651 struct atl1_adapter *adapter = hw->back;
652 s32 ret_val;
653 u16 phy_data;
654
655 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
656 hw->media_type == MEDIA_TYPE_1000M_FULL)
657 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
658 else {
05ffdd7b
JC		 659 switch (hw->media_type) {
660 case MEDIA_TYPE_100M_FULL:
6446a860
JC		 661 phy_data =
662 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
663 MII_CR_RESET;
05ffdd7b
JC		 664 break;
665 case MEDIA_TYPE_100M_HALF:
666 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
667 break;
668 case MEDIA_TYPE_10M_FULL:
669 phy_data =
670 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
671 break;
305282ba
JC		 672 default:
673 /* MEDIA_TYPE_10M_HALF: */
05ffdd7b
JC		 674 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
675 break;
f3cc28c7 676 }
f3cc28c7 677 }
f3cc28c7 678
6446a860
JC		 679 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
680 if (ret_val) {
681 u32 val;
682 int i;
683 /* pcie serdes link may be down! */
684 if (netif_msg_hw(adapter))
685 dev_dbg(&pdev->dev, "pcie phy link down\n");
686
687 for (i = 0; i < 25; i++) {
688 msleep(1);
689 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
690 if (!(val & (MDIO_START | MDIO_BUSY)))
691 break;
692 }
f3cc28c7 693
6446a860
JC		 694 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
695 if (netif_msg_hw(adapter))
696 dev_warn(&pdev->dev,
697 "pcie link down at least 25ms\n");
698 return ret_val;
699 }
700 }
305282ba 701 return 0;
2ca13da7
JC		 702}
703
6446a860
JC		 704/*
705 * Configures PHY autoneg and flow control advertisement settings
706 * hw - Struct containing variables accessed by shared code
707 */
708static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
05ffdd7b 709{
6446a860
JC		 710 s32 ret_val;
711 s16 mii_autoneg_adv_reg;
712 s16 mii_1000t_ctrl_reg;
f3cc28c7 713
6446a860
JC		 714 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
715 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
f3cc28c7 716
6446a860
JC		 717 /* Read the MII 1000Base-T Control Register (Address 9). */
718 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
f3cc28c7 719
6446a860
JC		 720 /*
721 * First we clear all the 10/100 mb speed bits in the Auto-Neg
722 * Advertisement Register (Address 4) and the 1000 mb speed bits in
723 * the 1000Base-T Control Register (Address 9).
724 */
725 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
726 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
f3cc28c7 727
6446a860
JC		 728 /*
729 * Need to parse media_type and set up
730 * the appropriate PHY registers.
731 */
732 switch (hw->media_type) {
733 case MEDIA_TYPE_AUTO_SENSOR:
734 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
735 MII_AR_10T_FD_CAPS |
736 MII_AR_100TX_HD_CAPS |
737 MII_AR_100TX_FD_CAPS);
738 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
739 break;
f3cc28c7 740
6446a860
JC		 741 case MEDIA_TYPE_1000M_FULL:
742 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
743 break;
f3cc28c7 744
6446a860
JC		 745 case MEDIA_TYPE_100M_FULL:
746 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
747 break;
f3cc28c7 748
6446a860
JC		 749 case MEDIA_TYPE_100M_HALF:
750 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
751 break;
f3cc28c7 752
6446a860
JC		 753 case MEDIA_TYPE_10M_FULL:
754 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
05ffdd7b 755 break;
6446a860 756
05ffdd7b 757 default:
6446a860 758 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
05ffdd7b 759 break;
f3cc28c7 760 }
f3cc28c7 761
6446a860
JC		 762 /* flow control fixed to enable all */
763 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
f3cc28c7 764
6446a860
JC		 765 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
766 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
f3cc28c7 767
6446a860
JC		 768 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
769 if (ret_val)
770 return ret_val;
f3cc28c7 771
6446a860
JC		 772 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
773 if (ret_val)
774 return ret_val;
f3cc28c7 775
6446a860 776 return 0;
f3cc28c7 777}
f3cc28c7 778
05ffdd7b 779/*
6446a860
JC		 780 * Configures link settings.
781 * hw - Struct containing variables accessed by shared code
782 * Assumes the hardware has previously been reset and the
783 * transmitter and receiver are not enabled.
05ffdd7b 784 */
6446a860 785static s32 atl1_setup_link(struct atl1_hw *hw)
f3cc28c7 786{
6446a860
JC		 787 struct pci_dev *pdev = hw->back->pdev;
788 struct atl1_adapter *adapter = hw->back;
789 s32 ret_val;
f3cc28c7 790
6446a860
JC		 791 /*
792 * Options:
793 * PHY will advertise value(s) parsed from
794 * autoneg_advertised and fc
795 * no matter what autoneg is , We will not wait link result.
796 */
797 ret_val = atl1_phy_setup_autoneg_adv(hw);
798 if (ret_val) {
799 if (netif_msg_link(adapter))
800 dev_dbg(&pdev->dev,
801 "error setting up autonegotiation\n");
802 return ret_val;
803 }
804 /* SW.Reset , En-Auto-Neg if needed */
805 ret_val = atl1_phy_reset(hw);
806 if (ret_val) {
807 if (netif_msg_link(adapter))
808 dev_dbg(&pdev->dev, "error resetting phy\n");
809 return ret_val;
810 }
811 hw->phy_configured = true;
812 return ret_val;
813}
f3cc28c7 814
6446a860 815static void atl1_init_flash_opcode(struct atl1_hw *hw)
f3cc28c7 816{
6446a860
JC		 817 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
818 /* Atmel */
819 hw->flash_vendor = 0;
f3cc28c7 820
6446a860
JC		 821 /* Init OP table */
822 iowrite8(flash_table[hw->flash_vendor].cmd_program,
823 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
824 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
825 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
826 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
827 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
828 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
829 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
830 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
831 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
832 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
833 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
834 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
835 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
836 iowrite8(flash_table[hw->flash_vendor].cmd_read,
837 hw->hw_addr + REG_SPI_FLASH_OP_READ);
f3cc28c7 838}
f3cc28c7 839
6446a860
JC		 840/*
841 * Performs basic configuration of the adapter.
842 * hw - Struct containing variables accessed by shared code
843 * Assumes that the controller has previously been reset and is in a
844 * post-reset uninitialized state. Initializes multicast table,
845 * and Calls routines to setup link
846 * Leaves the transmit and receive units disabled and uninitialized.
847 */
848static s32 atl1_init_hw(struct atl1_hw *hw)
05ffdd7b 849{
6446a860 850 u32 ret_val = 0;
f3cc28c7 851
6446a860
JC		 852 /* Zero out the Multicast HASH table */
853 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
854 /* clear the old settings from the multicast hash table */
855 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
f3cc28c7 856
6446a860 857 atl1_init_flash_opcode(hw);
f3cc28c7 858
6446a860
JC		 859 if (!hw->phy_configured) {
860 /* enable GPHY LinkChange Interrrupt */
861 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
862 if (ret_val)
863 return ret_val;
864 /* make PHY out of power-saving state */
865 ret_val = atl1_phy_leave_power_saving(hw);
866 if (ret_val)
867 return ret_val;
868 /* Call a subroutine to configure the link */
869 ret_val = atl1_setup_link(hw);
870 }
871 return ret_val;
f3cc28c7 872}
f3cc28c7
JC		 873
874/*
6446a860
JC		 875 * Detects the current speed and duplex settings of the hardware.
876 * hw - Struct containing variables accessed by shared code
877 * speed - Speed of the connection
878 * duplex - Duplex setting of the connection
f3cc28c7 879 */
6446a860 880static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
f3cc28c7 881{
6446a860
JC		 882 struct pci_dev *pdev = hw->back->pdev;
883 struct atl1_adapter *adapter = hw->back;
884 s32 ret_val;
885 u16 phy_data;
f3cc28c7 886
6446a860
JC		 887 /* ; --- Read PHY Specific Status Register (17) */
888 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
889 if (ret_val)
890 return ret_val;
f3cc28c7 891
6446a860
JC		 892 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
893 return ATLX_ERR_PHY_RES;
f3cc28c7 894
6446a860
JC		 895 switch (phy_data & MII_ATLX_PSSR_SPEED) {
896 case MII_ATLX_PSSR_1000MBS:
897 *speed = SPEED_1000;
898 break;
899 case MII_ATLX_PSSR_100MBS:
900 *speed = SPEED_100;
901 break;
902 case MII_ATLX_PSSR_10MBS:
903 *speed = SPEED_10;
904 break;
905 default:
906 if (netif_msg_hw(adapter))
907 dev_dbg(&pdev->dev, "error getting speed\n");
908 return ATLX_ERR_PHY_SPEED;
909 break;
f3cc28c7 910 }
6446a860
JC		 911 if (phy_data & MII_ATLX_PSSR_DPLX)
912 *duplex = FULL_DUPLEX;
913 else
914 *duplex = HALF_DUPLEX;
915
916 return 0;
05ffdd7b 917}
f3cc28c7 918
ff2d8d6c 919static void atl1_set_mac_addr(struct atl1_hw *hw)
05ffdd7b 920{
6446a860
JC		 921 u32 value;
922 /*
923 * 00-0B-6A-F6-00-DC
924 * 0: 6AF600DC 1: 000B
925 * low dword
926 */
927 value = (((u32) hw->mac_addr[2]) << 24) |
928 (((u32) hw->mac_addr[3]) << 16) |
929 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
930 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
931 /* high dword */
932 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
933 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
05ffdd7b 934}
f3cc28c7
JC		 935
936/*
937 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
938 * @adapter: board private structure to initialize
939 *
940 * atl1_sw_init initializes the Adapter private data structure.
941 * Fields are initialized based on PCI device information and
942 * OS network device settings (MTU size).
943 */
944static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
945{
946 struct atl1_hw *hw = &adapter->hw;
947 struct net_device *netdev = adapter->netdev;
f3cc28c7 948
2a49128f 949 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
a3093d9b 950 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
f3cc28c7
JC		 951
952 adapter->wol = 0;
953 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
6446a860 954 adapter->ict = 50000; /* 100ms */
f3cc28c7
JC		 955 adapter->link_speed = SPEED_0; /* hardware init */
956 adapter->link_duplex = FULL_DUPLEX;
957
958 hw->phy_configured = false;
959 hw->preamble_len = 7;
960 hw->ipgt = 0x60;
961 hw->min_ifg = 0x50;
962 hw->ipgr1 = 0x40;
963 hw->ipgr2 = 0x60;
964 hw->max_retry = 0xf;
965 hw->lcol = 0x37;
966 hw->jam_ipg = 7;
967 hw->rfd_burst = 8;
968 hw->rrd_burst = 8;
969 hw->rfd_fetch_gap = 1;
970 hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
971 hw->rx_jumbo_lkah = 1;
972 hw->rrd_ret_timer = 16;
973 hw->tpd_burst = 4;
974 hw->tpd_fetch_th = 16;
975 hw->txf_burst = 0x100;
976 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
977 hw->tpd_fetch_gap = 1;
978 hw->rcb_value = atl1_rcb_64;
979 hw->dma_ord = atl1_dma_ord_enh;
980 hw->dmar_block = atl1_dma_req_256;
981 hw->dmaw_block = atl1_dma_req_256;
982 hw->cmb_rrd = 4;
983 hw->cmb_tpd = 4;
984 hw->cmb_rx_timer = 1; /* about 2us */
985 hw->cmb_tx_timer = 1; /* about 2us */
986 hw->smb_timer = 100000; /* about 200ms */
987
f3cc28c7
JC		 988 spin_lock_init(&adapter->lock);
989 spin_lock_init(&adapter->mb_lock);
990
991 return 0;
992}
993
05ffdd7b
JC		 994static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
995{
996 struct atl1_adapter *adapter = netdev_priv(netdev);
997 u16 result;
998
999 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
1000
1001 return result;
1002}
1003
1004static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
1005 int val)
1006{
1007 struct atl1_adapter *adapter = netdev_priv(netdev);
1008
1009 atl1_write_phy_reg(&adapter->hw, reg_num, val);
1010}
1011
1012/*
1013 * atl1_mii_ioctl -
1014 * @netdev:
1015 * @ifreq:
1016 * @cmd:
1017 */
1018static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1019{
1020 struct atl1_adapter *adapter = netdev_priv(netdev);
1021 unsigned long flags;
1022 int retval;
1023
1024 if (!netif_running(netdev))
1025 return -EINVAL;
1026
1027 spin_lock_irqsave(&adapter->lock, flags);
1028 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
1029 spin_unlock_irqrestore(&adapter->lock, flags);
1030
1031 return retval;
1032}
1033
f3cc28c7
JC		 1034/*
1035 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
1036 * @adapter: board private structure
1037 *
1038 * Return 0 on success, negative on failure
1039 */
6446a860 1040static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
f3cc28c7
JC		 1041{
1042 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1043 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1044 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1045 struct atl1_ring_header *ring_header = &adapter->ring_header;
1046 struct pci_dev *pdev = adapter->pdev;
1047 int size;
1048 u8 offset = 0;
1049
1050 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
1051 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
1052 if (unlikely(!tpd_ring->buffer_info)) {
6446a860
JC		 1053 if (netif_msg_drv(adapter))
1054 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n",
1055 size);
f3cc28c7
JC		 1056 goto err_nomem;
1057 }
1058 rfd_ring->buffer_info =
53ffb42c 1059 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
f3cc28c7 1060
6446a860
JC		 1061 /*
1062 * real ring DMA buffer
53ffb42c
JC		 1063 * each ring/block may need up to 8 bytes for alignment, hence the
1064 * additional 40 bytes tacked onto the end.
1065 */
1066 ring_header->size = size =
1067 sizeof(struct tx_packet_desc) * tpd_ring->count
1068 + sizeof(struct rx_free_desc) * rfd_ring->count
1069 + sizeof(struct rx_return_desc) * rrd_ring->count
1070 + sizeof(struct coals_msg_block)
1071 + sizeof(struct stats_msg_block)
1072 + 40;
f3cc28c7
JC		 1073
1074 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
53ffb42c 1075 &ring_header->dma);
f3cc28c7 1076 if (unlikely(!ring_header->desc)) {
6446a860
JC		 1077 if (netif_msg_drv(adapter))
1078 dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
f3cc28c7
JC		 1079 goto err_nomem;
1080 }
1081
1082 memset(ring_header->desc, 0, ring_header->size);
1083
1084 /* init TPD ring */
1085 tpd_ring->dma = ring_header->dma;
1086 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
1087 tpd_ring->dma += offset;
1088 tpd_ring->desc = (u8 *) ring_header->desc + offset;
1089 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
f3cc28c7
JC		 1090
1091 /* init RFD ring */
1092 rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
1093 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
1094 rfd_ring->dma += offset;
1095 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
1096 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
2ca13da7 1097
f3cc28c7
JC		 1098
1099 /* init RRD ring */
1100 rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
1101 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
1102 rrd_ring->dma += offset;
1103 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
1104 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
2ca13da7 1105
f3cc28c7
JC		 1106
1107 /* init CMB */
1108 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
1109 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
1110 adapter->cmb.dma += offset;
53ffb42c
JC		 1111 adapter->cmb.cmb = (struct coals_msg_block *)
1112 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
f3cc28c7
JC		 1113
1114 /* init SMB */
1115 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
1116 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
1117 adapter->smb.dma += offset;
1118 adapter->smb.smb = (struct stats_msg_block *)
53ffb42c
JC		 1119 ((u8 *) adapter->cmb.cmb +
1120 (sizeof(struct coals_msg_block) + offset));
f3cc28c7 1121
6446a860 1122 return 0;
f3cc28c7
JC		 1123
1124err_nomem:
1125 kfree(tpd_ring->buffer_info);
1126 return -ENOMEM;
1127}
1128
3d2557f6 1129static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
f3cc28c7 1130{
2ca13da7
JC		 1131 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1132 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1133 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
f3cc28c7 1134
2ca13da7
JC		 1135 atomic_set(&tpd_ring->next_to_use, 0);
1136 atomic_set(&tpd_ring->next_to_clean, 0);
f3cc28c7 1137
2ca13da7
JC		 1138 rfd_ring->next_to_clean = 0;
1139 atomic_set(&rfd_ring->next_to_use, 0);
1140
1141 rrd_ring->next_to_use = 0;
1142 atomic_set(&rrd_ring->next_to_clean, 0);
f3cc28c7
JC		 1143}
1144
f3cc28c7 1145/*
05ffdd7b 1146 * atl1_clean_rx_ring - Free RFD Buffers
f3cc28c7
JC		 1147 * @adapter: board private structure
1148 */
05ffdd7b 1149static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
f3cc28c7 1150{
05ffdd7b
JC		 1151 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1152 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1153 struct atl1_buffer *buffer_info;
1154 struct pci_dev *pdev = adapter->pdev;
1155 unsigned long size;
1156 unsigned int i;
f3cc28c7 1157
05ffdd7b
JC		 1158 /* Free all the Rx ring sk_buffs */
1159 for (i = 0; i < rfd_ring->count; i++) {
1160 buffer_info = &rfd_ring->buffer_info[i];
1161 if (buffer_info->dma) {
1162 pci_unmap_page(pdev, buffer_info->dma,
1163 buffer_info->length, PCI_DMA_FROMDEVICE);
1164 buffer_info->dma = 0;
1165 }
1166 if (buffer_info->skb) {
1167 dev_kfree_skb(buffer_info->skb);
1168 buffer_info->skb = NULL;
1169 }
1170 }
f3cc28c7 1171
05ffdd7b
JC		 1172 size = sizeof(struct atl1_buffer) * rfd_ring->count;
1173 memset(rfd_ring->buffer_info, 0, size);
f3cc28c7 1174
05ffdd7b
JC		 1175 /* Zero out the descriptor ring */
1176 memset(rfd_ring->desc, 0, rfd_ring->size);
f3cc28c7 1177
05ffdd7b
JC		 1178 rfd_ring->next_to_clean = 0;
1179 atomic_set(&rfd_ring->next_to_use, 0);
f3cc28c7 1180
05ffdd7b
JC		 1181 rrd_ring->next_to_use = 0;
1182 atomic_set(&rrd_ring->next_to_clean, 0);
f3cc28c7
JC		 1183}
1184
05ffdd7b
JC		 1185/*
1186 * atl1_clean_tx_ring - Free Tx Buffers
1187 * @adapter: board private structure
1188 */
1189static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
f3cc28c7 1190{
05ffdd7b
JC		 1191 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1192 struct atl1_buffer *buffer_info;
53ffb42c 1193 struct pci_dev *pdev = adapter->pdev;
05ffdd7b
JC		 1194 unsigned long size;
1195 unsigned int i;
f3cc28c7 1196
05ffdd7b
JC		 1197 /* Free all the Tx ring sk_buffs */
1198 for (i = 0; i < tpd_ring->count; i++) {
1199 buffer_info = &tpd_ring->buffer_info[i];
1200 if (buffer_info->dma) {
1201 pci_unmap_page(pdev, buffer_info->dma,
1202 buffer_info->length, PCI_DMA_TODEVICE);
1203 buffer_info->dma = 0;
f3cc28c7
JC		 1204 }
1205 }
1206
05ffdd7b
JC		 1207 for (i = 0; i < tpd_ring->count; i++) {
1208 buffer_info = &tpd_ring->buffer_info[i];
1209 if (buffer_info->skb) {
1210 dev_kfree_skb_any(buffer_info->skb);
1211 buffer_info->skb = NULL;
f3cc28c7 1212 }
f3cc28c7
JC		 1213 }
1214
05ffdd7b
JC		 1215 size = sizeof(struct atl1_buffer) * tpd_ring->count;
1216 memset(tpd_ring->buffer_info, 0, size);
f3cc28c7 1217
05ffdd7b
JC		 1218 /* Zero out the descriptor ring */
1219 memset(tpd_ring->desc, 0, tpd_ring->size);
f3cc28c7 1220
05ffdd7b
JC		 1221 atomic_set(&tpd_ring->next_to_use, 0);
1222 atomic_set(&tpd_ring->next_to_clean, 0);
f3cc28c7
JC		 1223}
1224
1225/*
05ffdd7b
JC		 1226 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1227 * @adapter: board private structure
1228 *
1229 * Free all transmit software resources
f3cc28c7 1230 */
6446a860 1231static void atl1_free_ring_resources(struct atl1_adapter *adapter)
f3cc28c7 1232{
f3cc28c7 1233 struct pci_dev *pdev = adapter->pdev;
05ffdd7b
JC		 1234 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1235 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1236 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1237 struct atl1_ring_header *ring_header = &adapter->ring_header;
f3cc28c7 1238
05ffdd7b
JC		 1239 atl1_clean_tx_ring(adapter);
1240 atl1_clean_rx_ring(adapter);
f3cc28c7 1241
05ffdd7b
JC		 1242 kfree(tpd_ring->buffer_info);
1243 pci_free_consistent(pdev, ring_header->size, ring_header->desc,
1244 ring_header->dma);
f3cc28c7 1245
05ffdd7b
JC		 1246 tpd_ring->buffer_info = NULL;
1247 tpd_ring->desc = NULL;
1248 tpd_ring->dma = 0;
f3cc28c7 1249
05ffdd7b
JC		 1250 rfd_ring->buffer_info = NULL;
1251 rfd_ring->desc = NULL;
1252 rfd_ring->dma = 0;
f3cc28c7 1253
05ffdd7b
JC		 1254 rrd_ring->desc = NULL;
1255 rrd_ring->dma = 0;
3f5a2a71
LT		 1256
1257 adapter->cmb.dma = 0;
1258 adapter->cmb.cmb = NULL;
1259
1260 adapter->smb.dma = 0;
1261 adapter->smb.smb = NULL;
f3cc28c7
JC		 1262}
1263
05ffdd7b 1264static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
f3cc28c7 1265{
f3cc28c7 1266 u32 value;
05ffdd7b
JC		 1267 struct atl1_hw *hw = &adapter->hw;
1268 struct net_device *netdev = adapter->netdev;
1269 /* Config MAC CTRL Register */
1270 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1271 /* duplex */
1272 if (FULL_DUPLEX == adapter->link_duplex)
1273 value |= MAC_CTRL_DUPLX;
1274 /* speed */
1275 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
1276 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1277 MAC_CTRL_SPEED_SHIFT);
1278 /* flow control */
1279 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1280 /* PAD & CRC */
1281 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1282 /* preamble length */
1283 value |= (((u32) adapter->hw.preamble_len
1284 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1285 /* vlan */
1286 if (adapter->vlgrp)
1287 value |= MAC_CTRL_RMV_VLAN;
1288 /* rx checksum
1289 if (adapter->rx_csum)
1290 value |= MAC_CTRL_RX_CHKSUM_EN;
1291 */
1292 /* filter mode */
1293 value |= MAC_CTRL_BC_EN;
1294 if (netdev->flags & IFF_PROMISC)
1295 value |= MAC_CTRL_PROMIS_EN;
1296 else if (netdev->flags & IFF_ALLMULTI)
1297 value |= MAC_CTRL_MC_ALL_EN;
1298 /* value |= MAC_CTRL_LOOPBACK; */
1299 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1300}
f3cc28c7 1301
05ffdd7b
JC		 1302static u32 atl1_check_link(struct atl1_adapter *adapter)
1303{
1304 struct atl1_hw *hw = &adapter->hw;
1305 struct net_device *netdev = adapter->netdev;
1306 u32 ret_val;
1307 u16 speed, duplex, phy_data;
1308 int reconfig = 0;
f3cc28c7 1309
05ffdd7b
JC		 1310 /* MII_BMSR must read twice */
1311 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1312 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
6446a860
JC		 1313 if (!(phy_data & BMSR_LSTATUS)) {
1314 /* link down */
1315 if (netif_carrier_ok(netdev)) {
1316 /* old link state: Up */
1317 if (netif_msg_link(adapter))
1318 dev_info(&adapter->pdev->dev, "link is down\n");
05ffdd7b
JC		 1319 adapter->link_speed = SPEED_0;
1320 netif_carrier_off(netdev);
f3cc28c7 1321 }
6446a860 1322 return 0;
f3cc28c7
JC		 1323 }
1324
05ffdd7b
JC		 1325 /* Link Up */
1326 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
1327 if (ret_val)
1328 return ret_val;
f3cc28c7 1329
05ffdd7b
JC		 1330 switch (hw->media_type) {
1331 case MEDIA_TYPE_1000M_FULL:
1332 if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
1333 reconfig = 1;
1334 break;
1335 case MEDIA_TYPE_100M_FULL:
1336 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1337 reconfig = 1;
1338 break;
1339 case MEDIA_TYPE_100M_HALF:
1340 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1341 reconfig = 1;
1342 break;
1343 case MEDIA_TYPE_10M_FULL:
1344 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1345 reconfig = 1;
1346 break;
1347 case MEDIA_TYPE_10M_HALF:
1348 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1349 reconfig = 1;
1350 break;
1351 }
f3cc28c7 1352
05ffdd7b
JC		 1353 /* link result is our setting */
1354 if (!reconfig) {
8e95a202
JP		 1355 if (adapter->link_speed != speed ||
1356 adapter->link_duplex != duplex) {
05ffdd7b
JC		 1357 adapter->link_speed = speed;
1358 adapter->link_duplex = duplex;
1359 atl1_setup_mac_ctrl(adapter);
6446a860
JC		 1360 if (netif_msg_link(adapter))
1361 dev_info(&adapter->pdev->dev,
1362 "%s link is up %d Mbps %s\n",
1363 netdev->name, adapter->link_speed,
1364 adapter->link_duplex == FULL_DUPLEX ?
1365 "full duplex" : "half duplex");
05ffdd7b 1366 }
6446a860
JC		 1367 if (!netif_carrier_ok(netdev)) {
1368 /* Link down -> Up */
05ffdd7b 1369 netif_carrier_on(netdev);
05ffdd7b 1370 }
6446a860 1371 return 0;
f3cc28c7 1372 }
f3cc28c7 1373
6446a860 1374 /* change original link status */
05ffdd7b
JC		 1375 if (netif_carrier_ok(netdev)) {
1376 adapter->link_speed = SPEED_0;
1377 netif_carrier_off(netdev);
1378 netif_stop_queue(netdev);
f3cc28c7 1379 }
f3cc28c7 1380
05ffdd7b
JC		 1381 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
1382 hw->media_type != MEDIA_TYPE_1000M_FULL) {
1383 switch (hw->media_type) {
1384 case MEDIA_TYPE_100M_FULL:
1385 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
1386 MII_CR_RESET;
1387 break;
1388 case MEDIA_TYPE_100M_HALF:
1389 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
1390 break;
1391 case MEDIA_TYPE_10M_FULL:
1392 phy_data =
1393 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
1394 break;
6446a860
JC		 1395 default:
1396 /* MEDIA_TYPE_10M_HALF: */
05ffdd7b
JC		 1397 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
1398 break;
f3cc28c7 1399 }
05ffdd7b 1400 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
6446a860 1401 return 0;
f3cc28c7 1402 }
f3cc28c7 1403
05ffdd7b
JC		 1404 /* auto-neg, insert timer to re-config phy */
1405 if (!adapter->phy_timer_pending) {
1406 adapter->phy_timer_pending = true;
e053b628
SH		 1407 mod_timer(&adapter->phy_config_timer,
1408 round_jiffies(jiffies + 3 * HZ));
f3cc28c7 1409 }
f3cc28c7 1410
05ffdd7b
JC		 1411 return 0;
1412}
f3cc28c7 1413
05ffdd7b
JC		 1414static void set_flow_ctrl_old(struct atl1_adapter *adapter)
1415{
1416 u32 hi, lo, value;
f3cc28c7 1417
05ffdd7b
JC		 1418 /* RFD Flow Control */
1419 value = adapter->rfd_ring.count;
1420 hi = value / 16;
1421 if (hi < 2)
1422 hi = 2;
1423 lo = value * 7 / 8;
f3cc28c7 1424
05ffdd7b
JC		 1425 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1426 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1427 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
f3cc28c7 1428
05ffdd7b
JC		 1429 /* RRD Flow Control */
1430 value = adapter->rrd_ring.count;
1431 lo = value / 16;
1432 hi = value * 7 / 8;
1433 if (lo < 2)
1434 lo = 2;
1435 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1436 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1437 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1438}
f3cc28c7 1439
05ffdd7b
JC		 1440static void set_flow_ctrl_new(struct atl1_hw *hw)
1441{
1442 u32 hi, lo, value;
1443
1444 /* RXF Flow Control */
1445 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1446 lo = value / 16;
1447 if (lo < 192)
1448 lo = 192;
1449 hi = value * 7 / 8;
1450 if (hi < lo)
1451 hi = lo + 16;
1452 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1453 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1454 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1455
1456 /* RRD Flow Control */
1457 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1458 lo = value / 8;
1459 hi = value * 7 / 8;
1460 if (lo < 2)
1461 lo = 2;
1462 if (hi < lo)
1463 hi = lo + 3;
1464 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1465 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1466 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1467}
1468
1469/*
1470 * atl1_configure - Configure Transmit&Receive Unit after Reset
1471 * @adapter: board private structure
1472 *
1473 * Configure the Tx /Rx unit of the MAC after a reset.
1474 */
1475static u32 atl1_configure(struct atl1_adapter *adapter)
1476{
1477 struct atl1_hw *hw = &adapter->hw;
1478 u32 value;
1479
1480 /* clear interrupt status */
1481 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1482
1483 /* set MAC Address */
1484 value = (((u32) hw->mac_addr[2]) << 24) |
1485 (((u32) hw->mac_addr[3]) << 16) |
1486 (((u32) hw->mac_addr[4]) << 8) |
1487 (((u32) hw->mac_addr[5]));
1488 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1489 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1490 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1491
1492 /* tx / rx ring */
f3cc28c7 1493
05ffdd7b
JC		 1494 /* HI base address */
1495 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
1496 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1497 /* LO base address */
1498 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
1499 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1500 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
1501 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1502 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
1503 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1504 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
1505 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1506 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
1507 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
f3cc28c7 1508
05ffdd7b
JC		 1509 /* element count */
1510 value = adapter->rrd_ring.count;
1511 value <<= 16;
1512 value += adapter->rfd_ring.count;
1513 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1514 iowrite32(adapter->tpd_ring.count, hw->hw_addr +
1515 REG_DESC_TPD_RING_SIZE);
f3cc28c7 1516
05ffdd7b
JC		 1517 /* Load Ptr */
1518 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
f3cc28c7 1519
05ffdd7b
JC		 1520 /* config Mailbox */
1521 value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1522 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
1523 ((atomic_read(&adapter->rrd_ring.next_to_clean)
1524 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
1525 ((atomic_read(&adapter->rfd_ring.next_to_use)
1526 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
1527 iowrite32(value, hw->hw_addr + REG_MAILBOX);
f3cc28c7 1528
05ffdd7b
JC		 1529 /* config IPG/IFG */
1530 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1531 << MAC_IPG_IFG_IPGT_SHIFT) |
1532 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1533 << MAC_IPG_IFG_MIFG_SHIFT) |
1534 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1535 << MAC_IPG_IFG_IPGR1_SHIFT) |
1536 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1537 << MAC_IPG_IFG_IPGR2_SHIFT);
1538 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
f3cc28c7 1539
05ffdd7b
JC		 1540 /* config Half-Duplex Control */
1541 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1542 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1543 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
1544 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
1545 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
1546 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1547 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
1548 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
f3cc28c7 1549
05ffdd7b
JC		 1550 /* set Interrupt Moderator Timer */
1551 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1552 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
f3cc28c7 1553
05ffdd7b
JC		 1554 /* set Interrupt Clear Timer */
1555 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
f3cc28c7 1556
2a49128f
JC		 1557 /* set max frame size hw will accept */
1558 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
f3cc28c7 1559
05ffdd7b
JC		 1560 /* jumbo size & rrd retirement timer */
1561 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1562 << RXQ_JMBOSZ_TH_SHIFT) |
1563 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1564 << RXQ_JMBO_LKAH_SHIFT) |
1565 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1566 << RXQ_RRD_TIMER_SHIFT);
1567 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
f3cc28c7 1568
05ffdd7b
JC		 1569 /* Flow Control */
1570 switch (hw->dev_rev) {
1571 case 0x8001:
1572 case 0x9001:
1573 case 0x9002:
1574 case 0x9003:
1575 set_flow_ctrl_old(adapter);
1576 break;
1577 default:
1578 set_flow_ctrl_new(hw);
1579 break;
f3cc28c7 1580 }
f3cc28c7 1581
05ffdd7b
JC		 1582 /* config TXQ */
1583 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1584 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
1585 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1586 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
1587 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1588 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
1589 TXQ_CTRL_EN;
1590 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
f3cc28c7 1591
05ffdd7b
JC		 1592 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1593 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1594 << TX_JUMBO_TASK_TH_SHIFT) |
1595 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1596 << TX_TPD_MIN_IPG_SHIFT);
1597 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
f3cc28c7 1598
05ffdd7b
JC		 1599 /* config RXQ */
1600 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1601 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
1602 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1603 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
1604 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1605 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
1606 RXQ_CTRL_EN;
1607 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
f3cc28c7 1608
05ffdd7b
JC		 1609 /* config DMA Engine */
1610 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1611 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
3f516c00
JC		 1612 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1613 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
05ffdd7b
JC		 1614 DMA_CTRL_DMAW_EN;
1615 value |= (u32) hw->dma_ord;
1616 if (atl1_rcb_128 == hw->rcb_value)
1617 value |= DMA_CTRL_RCB_VALUE;
1618 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
f3cc28c7 1619
05ffdd7b 1620 /* config CMB / SMB */
91a500ac
JC		 1621 value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1622 hw->cmb_tpd : adapter->tpd_ring.count;
1623 value <<= 16;
1624 value |= hw->cmb_rrd;
05ffdd7b
JC		 1625 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1626 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1627 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1628 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
f3cc28c7 1629
05ffdd7b
JC		 1630 /* --- enable CMB / SMB */
1631 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1632 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
f3cc28c7 1633
05ffdd7b
JC		 1634 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1635 if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1636 value = 1; /* config failed */
1637 else
1638 value = 0;
f3cc28c7 1639
05ffdd7b
JC		 1640 /* clear all interrupt status */
1641 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1642 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1643 return value;
f3cc28c7 1644}
f3cc28c7 1645
05ffdd7b
JC		 1646/*
1647 * atl1_pcie_patch - Patch for PCIE module
1648 */
1649static void atl1_pcie_patch(struct atl1_adapter *adapter)
f3cc28c7 1650{
05ffdd7b 1651 u32 value;
f3cc28c7 1652
05ffdd7b
JC		 1653 /* much vendor magic here */
1654 value = 0x6500;
1655 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1656 /* pcie flow control mode change */
1657 value = ioread32(adapter->hw.hw_addr + 0x1008);
1658 value |= 0x8000;
1659 iowrite32(value, adapter->hw.hw_addr + 0x1008);
f3cc28c7 1660}
f3cc28c7 1661
f3cc28c7 1662/*
05ffdd7b
JC		 1663 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
1664 * on PCI Command register is disable.
1665 * The function enable this bit.
1666 * Brackett, 2006/03/15
f3cc28c7 1667 */
05ffdd7b 1668static void atl1_via_workaround(struct atl1_adapter *adapter)
f3cc28c7 1669{
05ffdd7b 1670 unsigned long value;
f3cc28c7 1671
05ffdd7b
JC		 1672 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1673 if (value & PCI_COMMAND_INTX_DISABLE)
1674 value &= ~PCI_COMMAND_INTX_DISABLE;
1675 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
f3cc28c7
JC		 1676}
1677
05ffdd7b
JC		 1678static void atl1_inc_smb(struct atl1_adapter *adapter)
1679{
02e71731 1680 struct net_device *netdev = adapter->netdev;
05ffdd7b 1681 struct stats_msg_block *smb = adapter->smb.smb;
f3cc28c7 1682
05ffdd7b
JC		 1683 /* Fill out the OS statistics structure */
1684 adapter->soft_stats.rx_packets += smb->rx_ok;
1685 adapter->soft_stats.tx_packets += smb->tx_ok;
1686 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
1687 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
1688 adapter->soft_stats.multicast += smb->rx_mcast;
1689 adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
1690 smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
f3cc28c7 1691
05ffdd7b
JC		 1692 /* Rx Errors */
1693 adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
1694 smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
1695 smb->rx_rrd_ov + smb->rx_align_err);
1696 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
1697 adapter->soft_stats.rx_length_errors += smb->rx_len_err;
1698 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
1699 adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
1700 adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
1701 smb->rx_rxf_ov);
f3cc28c7 1702
05ffdd7b
JC		 1703 adapter->soft_stats.rx_pause += smb->rx_pause;
1704 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
1705 adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
f3cc28c7 1706
05ffdd7b
JC		 1707 /* Tx Errors */
1708 adapter->soft_stats.tx_errors += (smb->tx_late_col +
1709 smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
1710 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
1711 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
1712 adapter->soft_stats.tx_window_errors += smb->tx_late_col;
f3cc28c7 1713
05ffdd7b
JC		 1714 adapter->soft_stats.excecol += smb->tx_abort_col;
1715 adapter->soft_stats.deffer += smb->tx_defer;
1716 adapter->soft_stats.scc += smb->tx_1_col;
1717 adapter->soft_stats.mcc += smb->tx_2_col;
1718 adapter->soft_stats.latecol += smb->tx_late_col;
1719 adapter->soft_stats.tx_underun += smb->tx_underrun;
1720 adapter->soft_stats.tx_trunc += smb->tx_trunc;
1721 adapter->soft_stats.tx_pause += smb->tx_pause;
f3cc28c7 1722
02e71731
SH		 1723 netdev->stats.rx_packets = adapter->soft_stats.rx_packets;
1724 netdev->stats.tx_packets = adapter->soft_stats.tx_packets;
1725 netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes;
1726 netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes;
1727 netdev->stats.multicast = adapter->soft_stats.multicast;
1728 netdev->stats.collisions = adapter->soft_stats.collisions;
1729 netdev->stats.rx_errors = adapter->soft_stats.rx_errors;
1730 netdev->stats.rx_over_errors =
05ffdd7b 1731 adapter->soft_stats.rx_missed_errors;
02e71731 1732 netdev->stats.rx_length_errors =
05ffdd7b 1733 adapter->soft_stats.rx_length_errors;
02e71731
SH		 1734 netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
1735 netdev->stats.rx_frame_errors =
05ffdd7b 1736 adapter->soft_stats.rx_frame_errors;
02e71731
SH		 1737 netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
1738 netdev->stats.rx_missed_errors =
05ffdd7b 1739 adapter->soft_stats.rx_missed_errors;
02e71731
SH		 1740 netdev->stats.tx_errors = adapter->soft_stats.tx_errors;
1741 netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
1742 netdev->stats.tx_aborted_errors =
05ffdd7b 1743 adapter->soft_stats.tx_aborted_errors;
02e71731 1744 netdev->stats.tx_window_errors =
05ffdd7b 1745 adapter->soft_stats.tx_window_errors;
02e71731 1746 netdev->stats.tx_carrier_errors =
05ffdd7b 1747 adapter->soft_stats.tx_carrier_errors;
f3cc28c7
JC		 1748}
1749
05ffdd7b 1750static void atl1_update_mailbox(struct atl1_adapter *adapter)
f3cc28c7 1751{
05ffdd7b
JC		 1752 unsigned long flags;
1753 u32 tpd_next_to_use;
1754 u32 rfd_next_to_use;
1755 u32 rrd_next_to_clean;
f3cc28c7 1756 u32 value;
f3cc28c7 1757
05ffdd7b 1758 spin_lock_irqsave(&adapter->mb_lock, flags);
f3cc28c7 1759
05ffdd7b
JC		 1760 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1761 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1762 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
f3cc28c7 1763
05ffdd7b
JC		 1764 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1765 MB_RFD_PROD_INDX_SHIFT) |
1766 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1767 MB_RRD_CONS_INDX_SHIFT) |
1768 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1769 MB_TPD_PROD_INDX_SHIFT);
1770 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
f3cc28c7 1771
05ffdd7b 1772 spin_unlock_irqrestore(&adapter->mb_lock, flags);
f3cc28c7
JC		 1773}
1774
05ffdd7b
JC		 1775static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
1776 struct rx_return_desc *rrd, u16 offset)
f3cc28c7 1777{
05ffdd7b 1778 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
f3cc28c7 1779
05ffdd7b
JC		 1780 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
1781 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
1782 if (++rfd_ring->next_to_clean == rfd_ring->count) {
1783 rfd_ring->next_to_clean = 0;
f3cc28c7 1784 }
f3cc28c7 1785 }
05ffdd7b 1786}
f3cc28c7 1787
05ffdd7b
JC		 1788static void atl1_update_rfd_index(struct atl1_adapter *adapter,
1789 struct rx_return_desc *rrd)
1790{
1791 u16 num_buf;
f3cc28c7 1792
05ffdd7b
JC		 1793 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
1794 adapter->rx_buffer_len;
1795 if (rrd->num_buf == num_buf)
1796 /* clean alloc flag for bad rrd */
1797 atl1_clean_alloc_flag(adapter, rrd, num_buf);
1798}
f3cc28c7 1799
05ffdd7b
JC		 1800static void atl1_rx_checksum(struct atl1_adapter *adapter,
1801 struct rx_return_desc *rrd, struct sk_buff *skb)
1802{
1803 struct pci_dev *pdev = adapter->pdev;
f3cc28c7 1804
c2ac3ef3
JC		 1805 /*
1806 * The L1 hardware contains a bug that erroneously sets the
1807 * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a
1808 * fragmented IP packet is received, even though the packet
1809 * is perfectly valid and its checksum is correct. There's
1810 * no way to distinguish between one of these good packets
1811 * and a packet that actually contains a TCP/UDP checksum
1812 * error, so all we can do is allow it to be handed up to
1813 * the higher layers and let it be sorted out there.
1814 */
1815
bc8acf2c 1816 skb_checksum_none_assert(skb);
f3cc28c7 1817
05ffdd7b
JC		 1818 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1819 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
1820 ERR_FLAG_CODE | ERR_FLAG_OV)) {
1821 adapter->hw_csum_err++;
6446a860
JC		 1822 if (netif_msg_rx_err(adapter))
1823 dev_printk(KERN_DEBUG, &pdev->dev,
1824 "rx checksum error\n");
05ffdd7b 1825 return;
f3cc28c7 1826 }
f3cc28c7
JC		 1827 }
1828
05ffdd7b
JC		 1829 /* not IPv4 */
1830 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
1831 /* checksum is invalid, but it's not an IPv4 pkt, so ok */
1832 return;
1833
1834 /* IPv4 packet */
1835 if (likely(!(rrd->err_flg &
1836 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
1837 skb->ip_summed = CHECKSUM_UNNECESSARY;
1838 adapter->hw_csum_good++;
1839 return;
f3cc28c7 1840 }
f3cc28c7
JC		 1841}
1842
05ffdd7b
JC		 1843/*
1844 * atl1_alloc_rx_buffers - Replace used receive buffers
1845 * @adapter: address of board private structure
1846 */
1847static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
f3cc28c7 1848{
05ffdd7b
JC		 1849 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1850 struct pci_dev *pdev = adapter->pdev;
1851 struct page *page;
1852 unsigned long offset;
1853 struct atl1_buffer *buffer_info, *next_info;
1854 struct sk_buff *skb;
1855 u16 num_alloc = 0;
1856 u16 rfd_next_to_use, next_next;
1857 struct rx_free_desc *rfd_desc;
f3cc28c7 1858
05ffdd7b
JC		 1859 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
1860 if (++next_next == rfd_ring->count)
1861 next_next = 0;
1862 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1863 next_info = &rfd_ring->buffer_info[next_next];
f3cc28c7 1864
05ffdd7b
JC		 1865 while (!buffer_info->alloced && !next_info->alloced) {
1866 if (buffer_info->skb) {
1867 buffer_info->alloced = 1;
1868 goto next;
1869 }
f3cc28c7 1870
05ffdd7b 1871 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
f3cc28c7 1872
89d71a66
ED		 1873 skb = netdev_alloc_skb_ip_align(adapter->netdev,
1874 adapter->rx_buffer_len);
6446a860
JC		 1875 if (unlikely(!skb)) {
1876 /* Better luck next round */
02e71731 1877 adapter->netdev->stats.rx_dropped++;
05ffdd7b
JC		 1878 break;
1879 }
f3cc28c7 1880
05ffdd7b
JC		 1881 buffer_info->alloced = 1;
1882 buffer_info->skb = skb;
1883 buffer_info->length = (u16) adapter->rx_buffer_len;
1884 page = virt_to_page(skb->data);
1885 offset = (unsigned long)skb->data & ~PAGE_MASK;
1886 buffer_info->dma = pci_map_page(pdev, page, offset,
1887 adapter->rx_buffer_len,
1888 PCI_DMA_FROMDEVICE);
1889 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1890 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
1891 rfd_desc->coalese = 0;
f3cc28c7 1892
05ffdd7b
JC		 1893next:
1894 rfd_next_to_use = next_next;
1895 if (unlikely(++next_next == rfd_ring->count))
1896 next_next = 0;
f3cc28c7 1897
05ffdd7b
JC		 1898 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1899 next_info = &rfd_ring->buffer_info[next_next];
1900 num_alloc++;
1901 }
f3cc28c7 1902
05ffdd7b
JC		 1903 if (num_alloc) {
1904 /*
1905 * Force memory writes to complete before letting h/w
1906 * know there are new descriptors to fetch. (Only
1907 * applicable for weak-ordered memory model archs,
1908 * such as IA-64).
1909 */
1910 wmb();
1911 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
1912 }
1913 return num_alloc;
f3cc28c7
JC		 1914}
1915
05ffdd7b 1916static void atl1_intr_rx(struct atl1_adapter *adapter)
f3cc28c7 1917{
05ffdd7b
JC		 1918 int i, count;
1919 u16 length;
1920 u16 rrd_next_to_clean;
f3cc28c7 1921 u32 value;
05ffdd7b
JC		 1922 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1923 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1924 struct atl1_buffer *buffer_info;
1925 struct rx_return_desc *rrd;
1926 struct sk_buff *skb;
f3cc28c7 1927
05ffdd7b 1928 count = 0;
f3cc28c7 1929
05ffdd7b 1930 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
f3cc28c7 1931
05ffdd7b
JC		 1932 while (1) {
1933 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
1934 i = 1;
1935 if (likely(rrd->xsz.valid)) { /* packet valid */
1936chk_rrd:
1937 /* check rrd status */
1938 if (likely(rrd->num_buf == 1))
1939 goto rrd_ok;
6446a860
JC		 1940 else if (netif_msg_rx_err(adapter)) {
1941 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1942 "unexpected RRD buffer count\n");
1943 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1944 "rx_buf_len = %d\n",
1945 adapter->rx_buffer_len);
1946 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1947 "RRD num_buf = %d\n",
1948 rrd->num_buf);
1949 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1950 "RRD pkt_len = %d\n",
1951 rrd->xsz.xsum_sz.pkt_size);
1952 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1953 "RRD pkt_flg = 0x%08X\n",
1954 rrd->pkt_flg);
1955 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1956 "RRD err_flg = 0x%08X\n",
1957 rrd->err_flg);
1958 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1959 "RRD vlan_tag = 0x%08X\n",
1960 rrd->vlan_tag);
1961 }
f3cc28c7 1962
05ffdd7b
JC		 1963 /* rrd seems to be bad */
1964 if (unlikely(i-- > 0)) {
1965 /* rrd may not be DMAed completely */
05ffdd7b
JC		 1966 udelay(1);
1967 goto chk_rrd;
1968 }
1969 /* bad rrd */
6446a860
JC		 1970 if (netif_msg_rx_err(adapter))
1971 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1972 "bad RRD\n");
05ffdd7b
JC		 1973 /* see if update RFD index */
1974 if (rrd->num_buf > 1)
1975 atl1_update_rfd_index(adapter, rrd);
f3cc28c7 1976
05ffdd7b
JC		 1977 /* update rrd */
1978 rrd->xsz.valid = 0;
1979 if (++rrd_next_to_clean == rrd_ring->count)
1980 rrd_next_to_clean = 0;
1981 count++;
1982 continue;
1983 } else { /* current rrd still not be updated */
f3cc28c7 1984
05ffdd7b
JC		 1985 break;
1986 }
1987rrd_ok:
1988 /* clean alloc flag for bad rrd */
1989 atl1_clean_alloc_flag(adapter, rrd, 0);
f3cc28c7 1990
05ffdd7b
JC		 1991 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
1992 if (++rfd_ring->next_to_clean == rfd_ring->count)
1993 rfd_ring->next_to_clean = 0;
f3cc28c7 1994
05ffdd7b
JC		 1995 /* update rrd next to clean */
1996 if (++rrd_next_to_clean == rrd_ring->count)
1997 rrd_next_to_clean = 0;
1998 count++;
f3cc28c7 1999
05ffdd7b
JC		 2000 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
2001 if (!(rrd->err_flg &
2002 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
2003 | ERR_FLAG_LEN))) {
2004 /* packet error, don't need upstream */
2005 buffer_info->alloced = 0;
2006 rrd->xsz.valid = 0;
2007 continue;
2008 }
2009 }
f3cc28c7 2010
05ffdd7b
JC		 2011 /* Good Receive */
2012 pci_unmap_page(adapter->pdev, buffer_info->dma,
2013 buffer_info->length, PCI_DMA_FROMDEVICE);
aefdbf1a 2014 buffer_info->dma = 0;
05ffdd7b
JC		 2015 skb = buffer_info->skb;
2016 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
f3cc28c7 2017
a3093d9b 2018 skb_put(skb, length - ETH_FCS_LEN);
f3cc28c7 2019
05ffdd7b
JC		 2020 /* Receive Checksum Offload */
2021 atl1_rx_checksum(adapter, rrd, skb);
2022 skb->protocol = eth_type_trans(skb, adapter->netdev);
f3cc28c7 2023
05ffdd7b
JC		 2024 if (adapter->vlgrp && (rrd->pkt_flg & PACKET_FLAG_VLAN_INS)) {
2025 u16 vlan_tag = (rrd->vlan_tag >> 4) |
2026 ((rrd->vlan_tag & 7) << 13) |
2027 ((rrd->vlan_tag & 8) << 9);
2028 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
2029 } else
2030 netif_rx(skb);
f3cc28c7 2031
05ffdd7b
JC		 2032 /* let protocol layer free skb */
2033 buffer_info->skb = NULL;
2034 buffer_info->alloced = 0;
2035 rrd->xsz.valid = 0;
05ffdd7b 2036 }
f3cc28c7 2037
05ffdd7b 2038 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
f3cc28c7 2039
05ffdd7b 2040 atl1_alloc_rx_buffers(adapter);
f3cc28c7 2041
05ffdd7b
JC		 2042 /* update mailbox ? */
2043 if (count) {
2044 u32 tpd_next_to_use;
2045 u32 rfd_next_to_use;
f3cc28c7 2046
05ffdd7b 2047 spin_lock(&adapter->mb_lock);
f3cc28c7 2048
05ffdd7b
JC		 2049 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
2050 rfd_next_to_use =
2051 atomic_read(&adapter->rfd_ring.next_to_use);
2052 rrd_next_to_clean =
2053 atomic_read(&adapter->rrd_ring.next_to_clean);
2054 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
2055 MB_RFD_PROD_INDX_SHIFT) |
2056 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
2057 MB_RRD_CONS_INDX_SHIFT) |
2058 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
2059 MB_TPD_PROD_INDX_SHIFT);
2060 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2061 spin_unlock(&adapter->mb_lock);
2062 }
f3cc28c7
JC		 2063}
2064
05ffdd7b 2065static void atl1_intr_tx(struct atl1_adapter *adapter)
f3cc28c7 2066{
05ffdd7b
JC		 2067 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2068 struct atl1_buffer *buffer_info;
2069 u16 sw_tpd_next_to_clean;
2070 u16 cmb_tpd_next_to_clean;
f3cc28c7 2071
05ffdd7b
JC		 2072 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2073 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
f3cc28c7 2074
05ffdd7b
JC		 2075 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
2076 struct tx_packet_desc *tpd;
f3cc28c7 2077
05ffdd7b
JC		 2078 tpd = ATL1_TPD_DESC(tpd_ring, sw_tpd_next_to_clean);
2079 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
2080 if (buffer_info->dma) {
2081 pci_unmap_page(adapter->pdev, buffer_info->dma,
2082 buffer_info->length, PCI_DMA_TODEVICE);
2083 buffer_info->dma = 0;
2084 }
f3cc28c7 2085
05ffdd7b
JC		 2086 if (buffer_info->skb) {
2087 dev_kfree_skb_irq(buffer_info->skb);
2088 buffer_info->skb = NULL;
2089 }
f3cc28c7 2090
05ffdd7b
JC		 2091 if (++sw_tpd_next_to_clean == tpd_ring->count)
2092 sw_tpd_next_to_clean = 0;
2093 }
2094 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
2095
8e95a202
JP		 2096 if (netif_queue_stopped(adapter->netdev) &&
2097 netif_carrier_ok(adapter->netdev))
05ffdd7b 2098 netif_wake_queue(adapter->netdev);
f3cc28c7
JC		 2099}
2100
e6a7ff4a 2101static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
f3cc28c7
JC		 2102{
2103 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2104 u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
807540ba 2105 return (next_to_clean > next_to_use) ?
53ffb42c 2106 next_to_clean - next_to_use - 1 :
807540ba 2107 tpd_ring->count + next_to_clean - next_to_use - 1;
f3cc28c7
JC		 2108}
2109
2110static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
6446a860 2111 struct tx_packet_desc *ptpd)
f3cc28c7 2112{
6446a860
JC		 2113 u8 hdr_len, ip_off;
2114 u32 real_len;
f3cc28c7
JC		 2115 int err;
2116
2117 if (skb_shinfo(skb)->gso_size) {
2118 if (skb_header_cloned(skb)) {
2119 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2120 if (unlikely(err))
6446a860 2121 return -1;
f3cc28c7
JC		 2122 }
2123
d63ddcec 2124 if (skb->protocol == htons(ETH_P_IP)) {
eddc9ec5
ACM		 2125 struct iphdr *iph = ip_hdr(skb);
2126
6446a860
JC		 2127 real_len = (((unsigned char *)iph - skb->data) +
2128 ntohs(iph->tot_len));
2129 if (real_len < skb->len)
2130 pskb_trim(skb, real_len);
2131 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2132 if (skb->len == hdr_len) {
2133 iph->check = 0;
2134 tcp_hdr(skb)->check =
2135 ~csum_tcpudp_magic(iph->saddr,
2136 iph->daddr, tcp_hdrlen(skb),
2137 IPPROTO_TCP, 0);
2138 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2139 TPD_IPHL_SHIFT;
2140 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2141 TPD_TCPHDRLEN_MASK) <<
2142 TPD_TCPHDRLEN_SHIFT;
2143 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT;
2144 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT;
2145 return 1;
2146 }
2147
eddc9ec5 2148 iph->check = 0;
aa8223c7 2149 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6446a860
JC		 2150 iph->daddr, 0, IPPROTO_TCP, 0);
2151 ip_off = (unsigned char *)iph -
2152 (unsigned char *) skb_network_header(skb);
2153 if (ip_off == 8) /* 802.3-SNAP frame */
2154 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT;
2155 else if (ip_off != 0)
2156 return -2;
2157
2158 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2159 TPD_IPHL_SHIFT;
2160 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2161 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT;
2162 ptpd->word3 |= (skb_shinfo(skb)->gso_size &
2163 TPD_MSS_MASK) << TPD_MSS_SHIFT;
2164 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
2165 return 3;
f3cc28c7
JC		 2166 }
2167 }
2168 return false;
2169}
2170
2171static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
6446a860 2172 struct tx_packet_desc *ptpd)
f3cc28c7
JC		 2173{
2174 u8 css, cso;
2175
2176 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
6446a860
JC		 2177 css = (u8) (skb->csum_start - skb_headroom(skb));
2178 cso = css + (u8) skb->csum_offset;
2179 if (unlikely(css & 0x1)) {
2180 /* L1 hardware requires an even number here */
2181 if (netif_msg_tx_err(adapter))
2182 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2183 "payload offset not an even number\n");
f3cc28c7
JC		 2184 return -1;
2185 }
6446a860
JC		 2186 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) <<
2187 TPD_PLOADOFFSET_SHIFT;
2188 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) <<
2189 TPD_CCSUMOFFSET_SHIFT;
2190 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
f3cc28c7
JC		 2191 return true;
2192 }
6446a860 2193 return 0;
f3cc28c7
JC		 2194}
2195
53ffb42c 2196static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
6446a860 2197 struct tx_packet_desc *ptpd)
f3cc28c7 2198{
f3cc28c7
JC		 2199 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2200 struct atl1_buffer *buffer_info;
6446a860 2201 u16 buf_len = skb->len;
f3cc28c7 2202 struct page *page;
f3cc28c7
JC		 2203 unsigned long offset;
2204 unsigned int nr_frags;
2205 unsigned int f;
6446a860
JC		 2206 int retval;
2207 u16 next_to_use;
2208 u16 data_len;
2209 u8 hdr_len;
f3cc28c7 2210
6446a860 2211 buf_len -= skb->data_len;
f3cc28c7 2212 nr_frags = skb_shinfo(skb)->nr_frags;
6446a860
JC		 2213 next_to_use = atomic_read(&tpd_ring->next_to_use);
2214 buffer_info = &tpd_ring->buffer_info[next_to_use];
0ee904c3 2215 BUG_ON(buffer_info->skb);
6446a860
JC		 2216 /* put skb in last TPD */
2217 buffer_info->skb = NULL;
f3cc28c7 2218
6446a860
JC		 2219 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
2220 if (retval) {
2221 /* TSO */
2222 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2223 buffer_info->length = hdr_len;
f3cc28c7
JC		 2224 page = virt_to_page(skb->data);
2225 offset = (unsigned long)skb->data & ~PAGE_MASK;
2226 buffer_info->dma = pci_map_page(adapter->pdev, page,
6446a860 2227 offset, hdr_len,
f3cc28c7
JC		 2228 PCI_DMA_TODEVICE);
2229
6446a860
JC		 2230 if (++next_to_use == tpd_ring->count)
2231 next_to_use = 0;
f3cc28c7 2232
6446a860
JC		 2233 if (buf_len > hdr_len) {
2234 int i, nseg;
ddfce6bb 2235
6446a860
JC		 2236 data_len = buf_len - hdr_len;
2237 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) /
53ffb42c 2238 ATL1_MAX_TX_BUF_LEN;
6446a860 2239 for (i = 0; i < nseg; i++) {
f3cc28c7 2240 buffer_info =
6446a860 2241 &tpd_ring->buffer_info[next_to_use];
f3cc28c7
JC		 2242 buffer_info->skb = NULL;
2243 buffer_info->length =
2b116145 2244 (ATL1_MAX_TX_BUF_LEN >=
6446a860
JC		 2245 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len;
2246 data_len -= buffer_info->length;
f3cc28c7 2247 page = virt_to_page(skb->data +
6446a860 2248 (hdr_len + i * ATL1_MAX_TX_BUF_LEN));
f3cc28c7 2249 offset = (unsigned long)(skb->data +
6446a860
JC		 2250 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) &
2251 ~PAGE_MASK;
53ffb42c
JC		 2252 buffer_info->dma = pci_map_page(adapter->pdev,
2253 page, offset, buffer_info->length,
2254 PCI_DMA_TODEVICE);
6446a860
JC		 2255 if (++next_to_use == tpd_ring->count)
2256 next_to_use = 0;
f3cc28c7
JC		 2257 }
2258 }
2259 } else {
6446a860
JC		 2260 /* not TSO */
2261 buffer_info->length = buf_len;
f3cc28c7
JC		 2262 page = virt_to_page(skb->data);
2263 offset = (unsigned long)skb->data & ~PAGE_MASK;
2264 buffer_info->dma = pci_map_page(adapter->pdev, page,
6446a860
JC		 2265 offset, buf_len, PCI_DMA_TODEVICE);
2266 if (++next_to_use == tpd_ring->count)
2267 next_to_use = 0;
f3cc28c7
JC		 2268 }
2269
2270 for (f = 0; f < nr_frags; f++) {
2271 struct skb_frag_struct *frag;
6446a860 2272 u16 i, nseg;
f3cc28c7
JC		 2273
2274 frag = &skb_shinfo(skb)->frags[f];
6446a860 2275 buf_len = frag->size;
f3cc28c7 2276
6446a860
JC		 2277 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) /
2278 ATL1_MAX_TX_BUF_LEN;
2279 for (i = 0; i < nseg; i++) {
2280 buffer_info = &tpd_ring->buffer_info[next_to_use];
0ee904c3
AB		 2281 BUG_ON(buffer_info->skb);
2282
f3cc28c7 2283 buffer_info->skb = NULL;
6446a860
JC		 2284 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
2285 ATL1_MAX_TX_BUF_LEN : buf_len;
2286 buf_len -= buffer_info->length;
53ffb42c
JC		 2287 buffer_info->dma = pci_map_page(adapter->pdev,
2288 frag->page,
2289 frag->page_offset + (i * ATL1_MAX_TX_BUF_LEN),
2290 buffer_info->length, PCI_DMA_TODEVICE);
f3cc28c7 2291
6446a860
JC		 2292 if (++next_to_use == tpd_ring->count)
2293 next_to_use = 0;
f3cc28c7
JC		 2294 }
2295 }
2296
2297 /* last tpd's buffer-info */
2298 buffer_info->skb = skb;
2299}
2300
6446a860
JC		 2301static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count,
2302 struct tx_packet_desc *ptpd)
f3cc28c7 2303{
f3cc28c7 2304 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
f3cc28c7
JC		 2305 struct atl1_buffer *buffer_info;
2306 struct tx_packet_desc *tpd;
6446a860
JC		 2307 u16 j;
2308 u32 val;
2309 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use);
f3cc28c7
JC		 2310
2311 for (j = 0; j < count; j++) {
6446a860
JC		 2312 buffer_info = &tpd_ring->buffer_info[next_to_use];
2313 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use);
2314 if (tpd != ptpd)
2315 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc));
f3cc28c7 2316 tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
dc5596d9
JC		 2317 tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT);
2318 tpd->word2 |= (cpu_to_le16(buffer_info->length) &
6446a860 2319 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT;
f3cc28c7 2320
6446a860
JC		 2321 /*
2322 * if this is the first packet in a TSO chain, set
2323 * TPD_HDRFLAG, otherwise, clear it.
2324 */
2325 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) &
2326 TPD_SEGMENT_EN_MASK;
2327 if (val) {
2328 if (!j)
2329 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
2330 else
2331 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT);
2332 }
f3cc28c7
JC		 2333
2334 if (j == (count - 1))
6446a860 2335 tpd->word3 |= 1 << TPD_EOP_SHIFT;
f3cc28c7 2336
6446a860
JC		 2337 if (++next_to_use == tpd_ring->count)
2338 next_to_use = 0;
f3cc28c7
JC		 2339 }
2340 /*
2341 * Force memory writes to complete before letting h/w
2342 * know there are new descriptors to fetch. (Only
2343 * applicable for weak-ordered memory model archs,
2344 * such as IA-64).
2345 */
2346 wmb();
2347
6446a860 2348 atomic_set(&tpd_ring->next_to_use, next_to_use);
f3cc28c7
JC		 2349}
2350
61357325
SH		 2351static netdev_tx_t atl1_xmit_frame(struct sk_buff *skb,
2352 struct net_device *netdev)
f3cc28c7
JC		 2353{
2354 struct atl1_adapter *adapter = netdev_priv(netdev);
6446a860 2355 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
e743d313 2356 int len;
f3cc28c7
JC		 2357 int tso;
2358 int count = 1;
2359 int ret_val;
6446a860 2360 struct tx_packet_desc *ptpd;
f3cc28c7
JC		 2361 u16 frag_size;
2362 u16 vlan_tag;
f3cc28c7
JC		 2363 unsigned int nr_frags = 0;
2364 unsigned int mss = 0;
2365 unsigned int f;
2366 unsigned int proto_hdr_len;
2367
e743d313 2368 len = skb_headlen(skb);
f3cc28c7 2369
6446a860 2370 if (unlikely(skb->len <= 0)) {
f3cc28c7
JC		 2371 dev_kfree_skb_any(skb);
2372 return NETDEV_TX_OK;
2373 }
2374
f3cc28c7
JC		 2375 nr_frags = skb_shinfo(skb)->nr_frags;
2376 for (f = 0; f < nr_frags; f++) {
2377 frag_size = skb_shinfo(skb)->frags[f].size;
2378 if (frag_size)
53ffb42c
JC		 2379 count += (frag_size + ATL1_MAX_TX_BUF_LEN - 1) /
2380 ATL1_MAX_TX_BUF_LEN;
f3cc28c7
JC		 2381 }
2382
f3cc28c7
JC		 2383 mss = skb_shinfo(skb)->gso_size;
2384 if (mss) {
17d0cdfa 2385 if (skb->protocol == htons(ETH_P_IP)) {
ea2ae17d 2386 proto_hdr_len = (skb_transport_offset(skb) +
ab6a5bb6 2387 tcp_hdrlen(skb));
f3cc28c7
JC		 2388 if (unlikely(proto_hdr_len > len)) {
2389 dev_kfree_skb_any(skb);
2390 return NETDEV_TX_OK;
2391 }
2392 /* need additional TPD ? */
2393 if (proto_hdr_len != len)
2394 count += (len - proto_hdr_len +
53ffb42c
JC		 2395 ATL1_MAX_TX_BUF_LEN - 1) /
2396 ATL1_MAX_TX_BUF_LEN;
f3cc28c7
JC		 2397 }
2398 }
2399
e6a7ff4a 2400 if (atl1_tpd_avail(&adapter->tpd_ring) < count) {
f3cc28c7
JC		 2401 /* not enough descriptors */
2402 netif_stop_queue(netdev);
6446a860
JC		 2403 if (netif_msg_tx_queued(adapter))
2404 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2405 "tx busy\n");
f3cc28c7
JC		 2406 return NETDEV_TX_BUSY;
2407 }
2408
6446a860
JC		 2409 ptpd = ATL1_TPD_DESC(tpd_ring,
2410 (u16) atomic_read(&tpd_ring->next_to_use));
2411 memset(ptpd, 0, sizeof(struct tx_packet_desc));
f3cc28c7 2412
eab6d18d 2413 if (vlan_tx_tag_present(skb)) {
f3cc28c7
JC		 2414 vlan_tag = vlan_tx_tag_get(skb);
2415 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
2416 ((vlan_tag >> 9) & 0x8);
6446a860 2417 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
dc5596d9
JC		 2418 ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) <<
2419 TPD_VLANTAG_SHIFT;
f3cc28c7
JC		 2420 }
2421
6446a860 2422 tso = atl1_tso(adapter, skb, ptpd);
f3cc28c7 2423 if (tso < 0) {
f3cc28c7
JC		 2424 dev_kfree_skb_any(skb);
2425 return NETDEV_TX_OK;
2426 }
2427
2428 if (!tso) {
6446a860 2429 ret_val = atl1_tx_csum(adapter, skb, ptpd);
f3cc28c7 2430 if (ret_val < 0) {
f3cc28c7
JC		 2431 dev_kfree_skb_any(skb);
2432 return NETDEV_TX_OK;
2433 }
2434 }
2435
6446a860
JC		 2436 atl1_tx_map(adapter, skb, ptpd);
2437 atl1_tx_queue(adapter, count, ptpd);
f3cc28c7 2438 atl1_update_mailbox(adapter);
e1098328 2439 mmiowb();
f3cc28c7
JC		 2440 return NETDEV_TX_OK;
2441}
2442
2443/*
05ffdd7b
JC		 2444 * atl1_intr - Interrupt Handler
2445 * @irq: interrupt number
2446 * @data: pointer to a network interface device structure
2447 * @pt_regs: CPU registers structure
f3cc28c7 2448 */
05ffdd7b 2449static irqreturn_t atl1_intr(int irq, void *data)
f3cc28c7 2450{
05ffdd7b
JC		 2451 struct atl1_adapter *adapter = netdev_priv(data);
2452 u32 status;
05ffdd7b 2453 int max_ints = 10;
f3cc28c7 2454
05ffdd7b
JC		 2455 status = adapter->cmb.cmb->int_stats;
2456 if (!status)
2457 return IRQ_NONE;
f3cc28c7 2458
05ffdd7b
JC		 2459 do {
2460 /* clear CMB interrupt status at once */
2461 adapter->cmb.cmb->int_stats = 0;
2462
2463 if (status & ISR_GPHY) /* clear phy status */
6446a860 2464 atlx_clear_phy_int(adapter);
05ffdd7b
JC		 2465
2466 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
2467 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
2468
2469 /* check if SMB intr */
2470 if (status & ISR_SMB)
2471 atl1_inc_smb(adapter);
2472
2473 /* check if PCIE PHY Link down */
2474 if (status & ISR_PHY_LINKDOWN) {
6446a860
JC		 2475 if (netif_msg_intr(adapter))
2476 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2477 "pcie phy link down %x\n", status);
05ffdd7b
JC		 2478 if (netif_running(adapter->netdev)) { /* reset MAC */
2479 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2480 schedule_work(&adapter->pcie_dma_to_rst_task);
2481 return IRQ_HANDLED;
2482 }
f3cc28c7 2483 }
05ffdd7b
JC		 2484
2485 /* check if DMA read/write error ? */
2486 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
6446a860
JC		 2487 if (netif_msg_intr(adapter))
2488 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2489 "pcie DMA r/w error (status = 0x%x)\n",
2490 status);
05ffdd7b
JC		 2491 iowrite32(0, adapter->hw.hw_addr + REG_IMR);
2492 schedule_work(&adapter->pcie_dma_to_rst_task);
2493 return IRQ_HANDLED;
f3cc28c7 2494 }
f3cc28c7 2495
05ffdd7b
JC		 2496 /* link event */
2497 if (status & ISR_GPHY) {
2498 adapter->soft_stats.tx_carrier_errors++;
2499 atl1_check_for_link(adapter);
2500 }
f3cc28c7 2501
05ffdd7b
JC		 2502 /* transmit event */
2503 if (status & ISR_CMB_TX)
2504 atl1_intr_tx(adapter);
f3cc28c7 2505
05ffdd7b
JC		 2506 /* rx exception */
2507 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2508 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2509 ISR_HOST_RRD_OV | ISR_CMB_RX))) {
2510 if (status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2511 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2512 ISR_HOST_RRD_OV))
6446a860
JC		 2513 if (netif_msg_intr(adapter))
2514 dev_printk(KERN_DEBUG,
2515 &adapter->pdev->dev,
2516 "rx exception, ISR = 0x%x\n",
2517 status);
05ffdd7b
JC		 2518 atl1_intr_rx(adapter);
2519 }
f3cc28c7 2520
05ffdd7b
JC		 2521 if (--max_ints < 0)
2522 break;
2523
2524 } while ((status = adapter->cmb.cmb->int_stats));
2525
2526 /* re-enable Interrupt */
2527 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
2528 return IRQ_HANDLED;
f3cc28c7
JC		 2529}
2530
f3cc28c7 2531
05ffdd7b
JC		 2532/*
2533 * atl1_phy_config - Timer Call-back
2534 * @data: pointer to netdev cast into an unsigned long
2535 */
2536static void atl1_phy_config(unsigned long data)
2537{
6446a860
JC		 2538 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2539 struct atl1_hw *hw = &adapter->hw;
05ffdd7b 2540 unsigned long flags;
f3cc28c7 2541
05ffdd7b 2542 spin_lock_irqsave(&adapter->lock, flags);
6446a860
JC		 2543 adapter->phy_timer_pending = false;
2544 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
2545 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
2546 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
05ffdd7b
JC		 2547 spin_unlock_irqrestore(&adapter->lock, flags);
2548}
2549
6446a860
JC		 2550/*
2551 * Orphaned vendor comment left intact here:
2552 * <vendor comment>
2553 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
2554 * will assert. We do soft reset <0x1400=1> according
2555 * with the SPEC. BUT, it seemes that PCIE or DMA
2556 * state-machine will not be reset. DMAR_TO_INT will
2557 * assert again and again.
2558 * </vendor comment>
2559 */
05ffdd7b 2560
6446a860 2561static int atl1_reset(struct atl1_adapter *adapter)
05ffdd7b
JC		 2562{
2563 int ret;
05ffdd7b 2564 ret = atl1_reset_hw(&adapter->hw);
6446a860 2565 if (ret)
05ffdd7b
JC		 2566 return ret;
2567 return atl1_init_hw(&adapter->hw);
f3cc28c7
JC		 2568}
2569
6446a860 2570static s32 atl1_up(struct atl1_adapter *adapter)
f3cc28c7
JC		 2571{
2572 struct net_device *netdev = adapter->netdev;
2573 int err;
2574 int irq_flags = IRQF_SAMPLE_RANDOM;
2575
2576 /* hardware has been reset, we need to reload some things */
6446a860 2577 atlx_set_multi(netdev);
2ca13da7 2578 atl1_init_ring_ptrs(adapter);
6446a860 2579 atlx_restore_vlan(adapter);
f3cc28c7 2580 err = atl1_alloc_rx_buffers(adapter);
6446a860
JC		 2581 if (unlikely(!err))
2582 /* no RX BUFFER allocated */
f3cc28c7
JC		 2583 return -ENOMEM;
2584
2585 if (unlikely(atl1_configure(adapter))) {
2586 err = -EIO;
2587 goto err_up;
2588 }
2589
2590 err = pci_enable_msi(adapter->pdev);
2591 if (err) {
6446a860
JC		 2592 if (netif_msg_ifup(adapter))
2593 dev_info(&adapter->pdev->dev,
2594 "Unable to enable MSI: %d\n", err);
f3cc28c7
JC		 2595 irq_flags |= IRQF_SHARED;
2596 }
2597
a0607fd3 2598 err = request_irq(adapter->pdev->irq, atl1_intr, irq_flags,
f3cc28c7
JC		 2599 netdev->name, netdev);
2600 if (unlikely(err))
2601 goto err_up;
2602
6446a860 2603 atlx_irq_enable(adapter);
f3cc28c7 2604 atl1_check_link(adapter);
39d48157 2605 netif_start_queue(netdev);
f3cc28c7
JC		 2606 return 0;
2607
f3cc28c7
JC		 2608err_up:
2609 pci_disable_msi(adapter->pdev);
2610 /* free rx_buffers */
2611 atl1_clean_rx_ring(adapter);
2612 return err;
2613}
2614
6446a860 2615static void atl1_down(struct atl1_adapter *adapter)
f3cc28c7
JC		 2616{
2617 struct net_device *netdev = adapter->netdev;
2618
b29be6d3 2619 netif_stop_queue(netdev);
f3cc28c7
JC		 2620 del_timer_sync(&adapter->phy_config_timer);
2621 adapter->phy_timer_pending = false;
2622
6446a860 2623 atlx_irq_disable(adapter);
f3cc28c7
JC		 2624 free_irq(adapter->pdev->irq, netdev);
2625 pci_disable_msi(adapter->pdev);
2626 atl1_reset_hw(&adapter->hw);
2627 adapter->cmb.cmb->int_stats = 0;
2628
2629 adapter->link_speed = SPEED_0;
2630 adapter->link_duplex = -1;
2631 netif_carrier_off(netdev);
f3cc28c7 2632
f3cc28c7
JC		 2633 atl1_clean_tx_ring(adapter);
2634 atl1_clean_rx_ring(adapter);
f3cc28c7
JC		 2635}
2636
6446a860
JC		 2637static void atl1_tx_timeout_task(struct work_struct *work)
2638{
2639 struct atl1_adapter *adapter =
2640 container_of(work, struct atl1_adapter, tx_timeout_task);
2641 struct net_device *netdev = adapter->netdev;
2642
2643 netif_device_detach(netdev);
2644 atl1_down(adapter);
305282ba 2645 atl1_up(adapter);
6446a860 2646 netif_device_attach(netdev);
305282ba
JC		 2647}
2648
6446a860
JC		 2649/*
2650 * atl1_change_mtu - Change the Maximum Transfer Unit
2651 * @netdev: network interface device structure
2652 * @new_mtu: new value for maximum frame size
2653 *
2654 * Returns 0 on success, negative on failure
2655 */
2656static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
305282ba
JC		 2657{
2658 struct atl1_adapter *adapter = netdev_priv(netdev);
6446a860
JC		 2659 int old_mtu = netdev->mtu;
2660 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
305282ba 2661
6446a860
JC		 2662 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2663 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2664 if (netif_msg_link(adapter))
2665 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
2666 return -EINVAL;
305282ba 2667 }
6446a860
JC		 2668
2669 adapter->hw.max_frame_size = max_frame;
2670 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
2671 adapter->rx_buffer_len = (max_frame + 7) & ~7;
2672 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
2673
2674 netdev->mtu = new_mtu;
2675 if ((old_mtu != new_mtu) && netif_running(netdev)) {
2676 atl1_down(adapter);
2677 atl1_up(adapter);
2678 }
2679
2680 return 0;
305282ba
JC		 2681}
2682
f3cc28c7
JC		 2683/*
2684 * atl1_open - Called when a network interface is made active
2685 * @netdev: network interface device structure
2686 *
2687 * Returns 0 on success, negative value on failure
2688 *
2689 * The open entry point is called when a network interface is made
2690 * active by the system (IFF_UP). At this point all resources needed
2691 * for transmit and receive operations are allocated, the interrupt
2692 * handler is registered with the OS, the watchdog timer is started,
2693 * and the stack is notified that the interface is ready.
2694 */
2695static int atl1_open(struct net_device *netdev)
2696{
2697 struct atl1_adapter *adapter = netdev_priv(netdev);
2698 int err;
2699
b29be6d3
JC		 2700 netif_carrier_off(netdev);
2701
f3cc28c7
JC		 2702 /* allocate transmit descriptors */
2703 err = atl1_setup_ring_resources(adapter);
2704 if (err)
2705 return err;
2706
2707 err = atl1_up(adapter);
2708 if (err)
2709 goto err_up;
2710
2711 return 0;
2712
2713err_up:
2714 atl1_reset(adapter);
2715 return err;
2716}
2717
2718/*
2719 * atl1_close - Disables a network interface
2720 * @netdev: network interface device structure
2721 *
2722 * Returns 0, this is not allowed to fail
2723 *
2724 * The close entry point is called when an interface is de-activated
2725 * by the OS. The hardware is still under the drivers control, but
2726 * needs to be disabled. A global MAC reset is issued to stop the
2727 * hardware, and all transmit and receive resources are freed.
2728 */
2729static int atl1_close(struct net_device *netdev)
2730{
2731 struct atl1_adapter *adapter = netdev_priv(netdev);
2732 atl1_down(adapter);
2733 atl1_free_ring_resources(adapter);
2734 return 0;
2735}
2736
05ffdd7b
JC		 2737#ifdef CONFIG_PM
2738static int atl1_suspend(struct pci_dev *pdev, pm_message_t state)
f3cc28c7 2739{
05ffdd7b
JC		 2740 struct net_device *netdev = pci_get_drvdata(pdev);
2741 struct atl1_adapter *adapter = netdev_priv(netdev);
2742 struct atl1_hw *hw = &adapter->hw;
2743 u32 ctrl = 0;
2744 u32 wufc = adapter->wol;
08e0f1dc
JC		 2745 u32 val;
2746 int retval;
2747 u16 speed;
2748 u16 duplex;
f3cc28c7
JC		 2749
2750 netif_device_detach(netdev);
05ffdd7b
JC		 2751 if (netif_running(netdev))
2752 atl1_down(adapter);
f3cc28c7 2753
08e0f1dc
JC		 2754 retval = pci_save_state(pdev);
2755 if (retval)
2756 return retval;
2757
05ffdd7b
JC		 2758 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2759 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
08e0f1dc
JC		 2760 val = ctrl & BMSR_LSTATUS;
2761 if (val)
6446a860 2762 wufc &= ~ATLX_WUFC_LNKC;
f3cc28c7 2763
08e0f1dc
JC		 2764 if (val && wufc) {
2765 val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
2766 if (val) {
2767 if (netif_msg_ifdown(adapter))
2768 dev_printk(KERN_DEBUG, &pdev->dev,
2769 "error getting speed/duplex\n");
2770 goto disable_wol;
2771 }
05ffdd7b
JC		 2772
2773 ctrl = 0;
05ffdd7b 2774
08e0f1dc
JC		 2775 /* enable magic packet WOL */
2776 if (wufc & ATLX_WUFC_MAG)
2777 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
05ffdd7b 2778 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
08e0f1dc
JC		 2779 ioread32(hw->hw_addr + REG_WOL_CTRL);
2780
2781 /* configure the mac */
2782 ctrl = MAC_CTRL_RX_EN;
2783 ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 :
2784 MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT);
2785 if (duplex == FULL_DUPLEX)
2786 ctrl |= MAC_CTRL_DUPLX;
2787 ctrl |= (((u32)adapter->hw.preamble_len &
2788 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
2789 if (adapter->vlgrp)
2790 ctrl |= MAC_CTRL_RMV_VLAN;
2791 if (wufc & ATLX_WUFC_MAG)
05ffdd7b 2792 ctrl |= MAC_CTRL_BC_EN;
05ffdd7b 2793 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
08e0f1dc
JC		 2794 ioread32(hw->hw_addr + REG_MAC_CTRL);
2795
2796 /* poke the PHY */
2797 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2798 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2799 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2800 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2801
2802 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2803 goto exit;
05ffdd7b
JC		 2804 }
2805
08e0f1dc
JC		 2806 if (!val && wufc) {
2807 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2808 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2809 ioread32(hw->hw_addr + REG_WOL_CTRL);
2810 iowrite32(0, hw->hw_addr + REG_MAC_CTRL);
2811 ioread32(hw->hw_addr + REG_MAC_CTRL);
2812 hw->phy_configured = false;
2813 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2814 goto exit;
2815 }
05ffdd7b 2816
08e0f1dc
JC		 2817disable_wol:
2818 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2819 ioread32(hw->hw_addr + REG_WOL_CTRL);
2820 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2821 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2822 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2823 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
08e0f1dc
JC		 2824 hw->phy_configured = false;
2825 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
2826exit:
2827 if (netif_running(netdev))
2828 pci_disable_msi(adapter->pdev);
2829 pci_disable_device(pdev);
2830 pci_set_power_state(pdev, pci_choose_state(pdev, state));
05ffdd7b
JC		 2831
2832 return 0;
f3cc28c7
JC		 2833}
2834
05ffdd7b 2835static int atl1_resume(struct pci_dev *pdev)
f3cc28c7 2836{
05ffdd7b
JC		 2837 struct net_device *netdev = pci_get_drvdata(pdev);
2838 struct atl1_adapter *adapter = netdev_priv(netdev);
6446a860 2839 u32 err;
53ffb42c 2840
6446a860 2841 pci_set_power_state(pdev, PCI_D0);
05ffdd7b
JC		 2842 pci_restore_state(pdev);
2843
6446a860 2844 err = pci_enable_device(pdev);
08e0f1dc
JC		 2845 if (err) {
2846 if (netif_msg_ifup(adapter))
2847 dev_printk(KERN_DEBUG, &pdev->dev,
2848 "error enabling pci device\n");
2849 return err;
2850 }
2851
2852 pci_set_master(pdev);
2853 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
05ffdd7b
JC		 2854 pci_enable_wake(pdev, PCI_D3hot, 0);
2855 pci_enable_wake(pdev, PCI_D3cold, 0);
2856
08e0f1dc 2857 atl1_reset_hw(&adapter->hw);
05ffdd7b 2858
ec5a32f6
LT		 2859 if (netif_running(netdev)) {
2860 adapter->cmb.cmb->int_stats = 0;
05ffdd7b 2861 atl1_up(adapter);
ec5a32f6 2862 }
05ffdd7b 2863 netif_device_attach(netdev);
05ffdd7b
JC		 2864
2865 return 0;
f3cc28c7 2866}
05ffdd7b
JC		 2867#else
2868#define atl1_suspend NULL
2869#define atl1_resume NULL
2870#endif
f3cc28c7 2871
bf455a22
JC		 2872static void atl1_shutdown(struct pci_dev *pdev)
2873{
2874#ifdef CONFIG_PM
2875 atl1_suspend(pdev, PMSG_SUSPEND);
2876#endif
2877}
2878
05ffdd7b
JC		 2879#ifdef CONFIG_NET_POLL_CONTROLLER
2880static void atl1_poll_controller(struct net_device *netdev)
f3cc28c7 2881{
05ffdd7b
JC		 2882 disable_irq(netdev->irq);
2883 atl1_intr(netdev->irq, netdev);
2884 enable_irq(netdev->irq);
f3cc28c7 2885}
05ffdd7b 2886#endif
f3cc28c7 2887
825a84d1
SH		 2888static const struct net_device_ops atl1_netdev_ops = {
2889 .ndo_open = atl1_open,
2890 .ndo_stop = atl1_close,
00829823 2891 .ndo_start_xmit = atl1_xmit_frame,
825a84d1
SH		 2892 .ndo_set_multicast_list = atlx_set_multi,
2893 .ndo_validate_addr = eth_validate_addr,
2894 .ndo_set_mac_address = atl1_set_mac,
2895 .ndo_change_mtu = atl1_change_mtu,
2896 .ndo_do_ioctl = atlx_ioctl,
00829823 2897 .ndo_tx_timeout = atlx_tx_timeout,
825a84d1
SH		 2898 .ndo_vlan_rx_register = atlx_vlan_rx_register,
2899#ifdef CONFIG_NET_POLL_CONTROLLER
2900 .ndo_poll_controller = atl1_poll_controller,
2901#endif
2902};
2903
f3cc28c7
JC		 2904/*
2905 * atl1_probe - Device Initialization Routine
2906 * @pdev: PCI device information struct
2907 * @ent: entry in atl1_pci_tbl
2908 *
2909 * Returns 0 on success, negative on failure
2910 *
2911 * atl1_probe initializes an adapter identified by a pci_dev structure.
2912 * The OS initialization, configuring of the adapter private structure,
2913 * and a hardware reset occur.
2914 */
2915static int __devinit atl1_probe(struct pci_dev *pdev,
53ffb42c 2916 const struct pci_device_id *ent)
f3cc28c7
JC		 2917{
2918 struct net_device *netdev;
2919 struct atl1_adapter *adapter;
2920 static int cards_found = 0;
f3cc28c7
JC		 2921 int err;
2922
2923 err = pci_enable_device(pdev);
2924 if (err)
2925 return err;
2926
5f08e46b 2927 /*
cdcc520d
CS		 2928 * The atl1 chip can DMA to 64-bit addresses, but it uses a single
2929 * shared register for the high 32 bits, so only a single, aligned,
2930 * 4 GB physical address range can be used at a time.
2931 *
2932 * Supporting 64-bit DMA on this hardware is more trouble than it's
2933 * worth. It is far easier to limit to 32-bit DMA than update
2934 * various kernel subsystems to support the mechanics required by a
2935 * fixed-high-32-bit system.
5f08e46b 2936 */
284901a9 2937 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
f3cc28c7 2938 if (err) {
5f08e46b
LT		 2939 dev_err(&pdev->dev, "no usable DMA configuration\n");
2940 goto err_dma;
f3cc28c7 2941 }
6446a860
JC		 2942 /*
2943 * Mark all PCI regions associated with PCI device
f3cc28c7
JC		 2944 * pdev as being reserved by owner atl1_driver_name
2945 */
6446a860 2946 err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
f3cc28c7
JC		 2947 if (err)
2948 goto err_request_regions;
2949
6446a860
JC		 2950 /*
2951 * Enables bus-mastering on the device and calls
f3cc28c7
JC		 2952 * pcibios_set_master to do the needed arch specific settings
2953 */
2954 pci_set_master(pdev);
2955
2956 netdev = alloc_etherdev(sizeof(struct atl1_adapter));
2957 if (!netdev) {
2958 err = -ENOMEM;
2959 goto err_alloc_etherdev;
2960 }
f3cc28c7
JC		 2961 SET_NETDEV_DEV(netdev, &pdev->dev);
2962
2963 pci_set_drvdata(pdev, netdev);
2964 adapter = netdev_priv(netdev);
2965 adapter->netdev = netdev;
2966 adapter->pdev = pdev;
2967 adapter->hw.back = adapter;
6446a860 2968 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg);
f3cc28c7
JC		 2969
2970 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
2971 if (!adapter->hw.hw_addr) {
2972 err = -EIO;
2973 goto err_pci_iomap;
2974 }
2975 /* get device revision number */
1e006364 2976 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
53ffb42c 2977 (REG_MASTER_CTRL + 2));
6446a860
JC		 2978 if (netif_msg_probe(adapter))
2979 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
f3cc28c7
JC		 2980
2981 /* set default ring resource counts */
2982 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
2983 adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
2984
2985 adapter->mii.dev = netdev;
2986 adapter->mii.mdio_read = mdio_read;
2987 adapter->mii.mdio_write = mdio_write;
2988 adapter->mii.phy_id_mask = 0x1f;
2989 adapter->mii.reg_num_mask = 0x1f;
2990
825a84d1 2991 netdev->netdev_ops = &atl1_netdev_ops;
f3cc28c7 2992 netdev->watchdog_timeo = 5 * HZ;
cb434e38 2993
f3cc28c7
JC		 2994 netdev->ethtool_ops = &atl1_ethtool_ops;
2995 adapter->bd_number = cards_found;
f3cc28c7
JC		 2996
2997 /* setup the private structure */
2998 err = atl1_sw_init(adapter);
2999 if (err)
3000 goto err_common;
3001
3002 netdev->features = NETIF_F_HW_CSUM;
3003 netdev->features |= NETIF_F_SG;
3004 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
f3cc28c7
JC		 3005
3006 /*
3007 * patch for some L1 of old version,
3008 * the final version of L1 may not need these
3009 * patches
3010 */
3011 /* atl1_pcie_patch(adapter); */
3012
3013 /* really reset GPHY core */
6446a860 3014 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
f3cc28c7
JC		 3015
3016 /*
3017 * reset the controller to
3018 * put the device in a known good starting state
3019 */
3020 if (atl1_reset_hw(&adapter->hw)) {
3021 err = -EIO;
3022 goto err_common;
3023 }
3024
3025 /* copy the MAC address out of the EEPROM */
3026 atl1_read_mac_addr(&adapter->hw);
3027 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
3028
3029 if (!is_valid_ether_addr(netdev->dev_addr)) {
3030 err = -EIO;
3031 goto err_common;
3032 }
3033
3034 atl1_check_options(adapter);
3035
3036 /* pre-init the MAC, and setup link */
3037 err = atl1_init_hw(&adapter->hw);
3038 if (err) {
3039 err = -EIO;
3040 goto err_common;
3041 }
3042
3043 atl1_pcie_patch(adapter);
3044 /* assume we have no link for now */
3045 netif_carrier_off(netdev);
f3cc28c7 3046
c061b18d 3047 setup_timer(&adapter->phy_config_timer, atl1_phy_config,
e053b628 3048 (unsigned long)adapter);
f3cc28c7
JC		 3049 adapter->phy_timer_pending = false;
3050
3051 INIT_WORK(&adapter->tx_timeout_task, atl1_tx_timeout_task);
3052
6446a860 3053 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
f3cc28c7
JC		 3054
3055 INIT_WORK(&adapter->pcie_dma_to_rst_task, atl1_tx_timeout_task);
3056
3057 err = register_netdev(netdev);
3058 if (err)
3059 goto err_common;
3060
3061 cards_found++;
3062 atl1_via_workaround(adapter);
3063 return 0;
3064
3065err_common:
3066 pci_iounmap(pdev, adapter->hw.hw_addr);
3067err_pci_iomap:
3068 free_netdev(netdev);
3069err_alloc_etherdev:
3070 pci_release_regions(pdev);
3071err_dma:
3072err_request_regions:
3073 pci_disable_device(pdev);
3074 return err;
3075}
3076
3077/*
3078 * atl1_remove - Device Removal Routine
3079 * @pdev: PCI device information struct
3080 *
3081 * atl1_remove is called by the PCI subsystem to alert the driver
3082 * that it should release a PCI device. The could be caused by a
3083 * Hot-Plug event, or because the driver is going to be removed from
3084 * memory.
3085 */
3086static void __devexit atl1_remove(struct pci_dev *pdev)
3087{
3088 struct net_device *netdev = pci_get_drvdata(pdev);
3089 struct atl1_adapter *adapter;
3090 /* Device not available. Return. */
3091 if (!netdev)
3092 return;
3093
3094 adapter = netdev_priv(netdev);
8c754a04 3095
6446a860
JC		 3096 /*
3097 * Some atl1 boards lack persistent storage for their MAC, and get it
8c754a04
CS		 3098 * from the BIOS during POST. If we've been messing with the MAC
3099 * address, we need to save the permanent one.
3100 */
3101 if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) {
53ffb42c
JC		 3102 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
3103 ETH_ALEN);
8c754a04
CS		 3104 atl1_set_mac_addr(&adapter->hw);
3105 }
3106
6446a860 3107 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
f3cc28c7
JC		 3108 unregister_netdev(netdev);
3109 pci_iounmap(pdev, adapter->hw.hw_addr);
3110 pci_release_regions(pdev);
3111 free_netdev(netdev);
3112 pci_disable_device(pdev);
3113}
3114
f3cc28c7 3115static struct pci_driver atl1_driver = {
6446a860 3116 .name = ATLX_DRIVER_NAME,
f3cc28c7
JC		 3117 .id_table = atl1_pci_tbl,
3118 .probe = atl1_probe,
3119 .remove = __devexit_p(atl1_remove),
f3cc28c7 3120 .suspend = atl1_suspend,
bf455a22
JC		 3121 .resume = atl1_resume,
3122 .shutdown = atl1_shutdown
f3cc28c7
JC		 3123};
3124
3125/*
3126 * atl1_exit_module - Driver Exit Cleanup Routine
3127 *
3128 * atl1_exit_module is called just before the driver is removed
3129 * from memory.
3130 */
3131static void __exit atl1_exit_module(void)
3132{
3133 pci_unregister_driver(&atl1_driver);
3134}
3135
3136/*
3137 * atl1_init_module - Driver Registration Routine
3138 *
3139 * atl1_init_module is the first routine called when the driver is
3140 * loaded. All it does is register with the PCI subsystem.
3141 */
3142static int __init atl1_init_module(void)
3143{
f3cc28c7
JC		 3144 return pci_register_driver(&atl1_driver);
3145}
3146
3147module_init(atl1_init_module);
3148module_exit(atl1_exit_module);
6446a860
JC		 3149
3150struct atl1_stats {
3151 char stat_string[ETH_GSTRING_LEN];
3152 int sizeof_stat;
3153 int stat_offset;
3154};
3155
3156#define ATL1_STAT(m) \
3157 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
3158
3159static struct atl1_stats atl1_gstrings_stats[] = {
3160 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
3161 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
3162 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
3163 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
3164 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
3165 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
6446a860
JC		 3166 {"multicast", ATL1_STAT(soft_stats.multicast)},
3167 {"collisions", ATL1_STAT(soft_stats.collisions)},
3168 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
3169 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3170 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
3171 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
3172 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
3173 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3174 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
3175 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
3176 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
3177 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
3178 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
3179 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
3180 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
3181 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
3182 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
3183 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
3184 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
3185 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
3186 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
3187 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
3188 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
3189};
3190
3191static void atl1_get_ethtool_stats(struct net_device *netdev,
3192 struct ethtool_stats *stats, u64 *data)
305282ba 3193{
6446a860 3194 struct atl1_adapter *adapter = netdev_priv(netdev);
305282ba 3195 int i;
6446a860 3196 char *p;
305282ba 3197
6446a860
JC		 3198 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3199 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
3200 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
3201 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
305282ba
JC		 3202 }
3203
305282ba
JC		 3204}
3205
6446a860 3206static int atl1_get_sset_count(struct net_device *netdev, int sset)
305282ba 3207{
6446a860
JC		 3208 switch (sset) {
3209 case ETH_SS_STATS:
3210 return ARRAY_SIZE(atl1_gstrings_stats);
3211 default:
3212 return -EOPNOTSUPP;
3213 }
305282ba
JC		 3214}
3215
6446a860
JC		 3216static int atl1_get_settings(struct net_device *netdev,
3217 struct ethtool_cmd *ecmd)
305282ba 3218{
6446a860
JC		 3219 struct atl1_adapter *adapter = netdev_priv(netdev);
3220 struct atl1_hw *hw = &adapter->hw;
3221
3222 ecmd->supported = (SUPPORTED_10baseT_Half |
3223 SUPPORTED_10baseT_Full |
3224 SUPPORTED_100baseT_Half |
3225 SUPPORTED_100baseT_Full |
3226 SUPPORTED_1000baseT_Full |
3227 SUPPORTED_Autoneg | SUPPORTED_TP);
3228 ecmd->advertising = ADVERTISED_TP;
3229 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3230 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3231 ecmd->advertising |= ADVERTISED_Autoneg;
3232 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
3233 ecmd->advertising |= ADVERTISED_Autoneg;
3234 ecmd->advertising |=
3235 (ADVERTISED_10baseT_Half |
3236 ADVERTISED_10baseT_Full |
3237 ADVERTISED_100baseT_Half |
3238 ADVERTISED_100baseT_Full |
3239 ADVERTISED_1000baseT_Full);
3240 } else
3241 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
3242 }
3243 ecmd->port = PORT_TP;
3244 ecmd->phy_address = 0;
3245 ecmd->transceiver = XCVR_INTERNAL;
3246
3247 if (netif_carrier_ok(adapter->netdev)) {
3248 u16 link_speed, link_duplex;
3249 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
3250 ecmd->speed = link_speed;
3251 if (link_duplex == FULL_DUPLEX)
3252 ecmd->duplex = DUPLEX_FULL;
3253 else
3254 ecmd->duplex = DUPLEX_HALF;
3255 } else {
3256 ecmd->speed = -1;
3257 ecmd->duplex = -1;
3258 }
3259 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3260 hw->media_type == MEDIA_TYPE_1000M_FULL)
3261 ecmd->autoneg = AUTONEG_ENABLE;
3262 else
3263 ecmd->autoneg = AUTONEG_DISABLE;
305282ba 3264
305282ba
JC		 3265 return 0;
3266}
3267
6446a860
JC		 3268static int atl1_set_settings(struct net_device *netdev,
3269 struct ethtool_cmd *ecmd)
305282ba 3270{
6446a860
JC		 3271 struct atl1_adapter *adapter = netdev_priv(netdev);
3272 struct atl1_hw *hw = &adapter->hw;
305282ba 3273 u16 phy_data;
6446a860
JC		 3274 int ret_val = 0;
3275 u16 old_media_type = hw->media_type;
305282ba 3276
6446a860
JC		 3277 if (netif_running(adapter->netdev)) {
3278 if (netif_msg_link(adapter))
3279 dev_dbg(&adapter->pdev->dev,
3280 "ethtool shutting down adapter\n");
3281 atl1_down(adapter);
3282 }
3283
3284 if (ecmd->autoneg == AUTONEG_ENABLE)
3285 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
3286 else {
3287 if (ecmd->speed == SPEED_1000) {
3288 if (ecmd->duplex != DUPLEX_FULL) {
3289 if (netif_msg_link(adapter))
3290 dev_warn(&adapter->pdev->dev,
3291 "1000M half is invalid\n");
3292 ret_val = -EINVAL;
3293 goto exit_sset;
3294 }
3295 hw->media_type = MEDIA_TYPE_1000M_FULL;
3296 } else if (ecmd->speed == SPEED_100) {
3297 if (ecmd->duplex == DUPLEX_FULL)
3298 hw->media_type = MEDIA_TYPE_100M_FULL;
3299 else
3300 hw->media_type = MEDIA_TYPE_100M_HALF;
3301 } else {
3302 if (ecmd->duplex == DUPLEX_FULL)
3303 hw->media_type = MEDIA_TYPE_10M_FULL;
3304 else
3305 hw->media_type = MEDIA_TYPE_10M_HALF;
3306 }
3307 }
3308 switch (hw->media_type) {
3309 case MEDIA_TYPE_AUTO_SENSOR:
3310 ecmd->advertising =
3311 ADVERTISED_10baseT_Half |
3312 ADVERTISED_10baseT_Full |
3313 ADVERTISED_100baseT_Half |
3314 ADVERTISED_100baseT_Full |
3315 ADVERTISED_1000baseT_Full |
3316 ADVERTISED_Autoneg | ADVERTISED_TP;
3317 break;
3318 case MEDIA_TYPE_1000M_FULL:
3319 ecmd->advertising =
3320 ADVERTISED_1000baseT_Full |
3321 ADVERTISED_Autoneg | ADVERTISED_TP;
3322 break;
3323 default:
3324 ecmd->advertising = 0;
3325 break;
3326 }
3327 if (atl1_phy_setup_autoneg_adv(hw)) {
3328 ret_val = -EINVAL;
3329 if (netif_msg_link(adapter))
3330 dev_warn(&adapter->pdev->dev,
3331 "invalid ethtool speed/duplex setting\n");
3332 goto exit_sset;
3333 }
305282ba
JC		 3334 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3335 hw->media_type == MEDIA_TYPE_1000M_FULL)
3336 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3337 else {
3338 switch (hw->media_type) {
3339 case MEDIA_TYPE_100M_FULL:
3340 phy_data =
3341 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
3342 MII_CR_RESET;
3343 break;
3344 case MEDIA_TYPE_100M_HALF:
3345 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3346 break;
3347 case MEDIA_TYPE_10M_FULL:
3348 phy_data =
3349 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
3350 break;
3351 default:
3352 /* MEDIA_TYPE_10M_HALF: */
3353 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3354 break;
3355 }
3356 }
6446a860
JC		 3357 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3358exit_sset:
3359 if (ret_val)
3360 hw->media_type = old_media_type;
305282ba 3361
6446a860
JC		 3362 if (netif_running(adapter->netdev)) {
3363 if (netif_msg_link(adapter))
3364 dev_dbg(&adapter->pdev->dev,
3365 "ethtool starting adapter\n");
3366 atl1_up(adapter);
3367 } else if (!ret_val) {
3368 if (netif_msg_link(adapter))
3369 dev_dbg(&adapter->pdev->dev,
3370 "ethtool resetting adapter\n");
3371 atl1_reset(adapter);
3372 }
3373 return ret_val;
3374}
305282ba 3375
6446a860
JC		 3376static void atl1_get_drvinfo(struct net_device *netdev,
3377 struct ethtool_drvinfo *drvinfo)
3378{
3379 struct atl1_adapter *adapter = netdev_priv(netdev);
305282ba 3380
082ba88a
RK		 3381 strlcpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
3382 strlcpy(drvinfo->version, ATLX_DRIVER_VERSION,
6446a860 3383 sizeof(drvinfo->version));
082ba88a
RK		 3384 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
3385 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
6446a860
JC		 3386 sizeof(drvinfo->bus_info));
3387 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
3388}
3389
3390static void atl1_get_wol(struct net_device *netdev,
3391 struct ethtool_wolinfo *wol)
3392{
3393 struct atl1_adapter *adapter = netdev_priv(netdev);
3394
3b259e36 3395 wol->supported = WAKE_MAGIC;
6446a860 3396 wol->wolopts = 0;
6446a860
JC		 3397 if (adapter->wol & ATLX_WUFC_MAG)
3398 wol->wolopts |= WAKE_MAGIC;
6446a860
JC		 3399}
3400
3401static int atl1_set_wol(struct net_device *netdev,
3402 struct ethtool_wolinfo *wol)
3403{
3404 struct atl1_adapter *adapter = netdev_priv(netdev);
3405
3b259e36
C		 3406 if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
3407 WAKE_ARP | WAKE_MAGICSECURE))
6446a860
JC		 3408 return -EOPNOTSUPP;
3409 adapter->wol = 0;
6446a860
JC		 3410 if (wol->wolopts & WAKE_MAGIC)
3411 adapter->wol |= ATLX_WUFC_MAG;
305282ba
JC		 3412 return 0;
3413}
3414
6446a860 3415static u32 atl1_get_msglevel(struct net_device *netdev)
305282ba 3416{
6446a860
JC		 3417 struct atl1_adapter *adapter = netdev_priv(netdev);
3418 return adapter->msg_enable;
3419}
305282ba 3420
6446a860
JC		 3421static void atl1_set_msglevel(struct net_device *netdev, u32 value)
3422{
3423 struct atl1_adapter *adapter = netdev_priv(netdev);
3424 adapter->msg_enable = value;
3425}
305282ba 3426
6446a860
JC		 3427static int atl1_get_regs_len(struct net_device *netdev)
3428{
3429 return ATL1_REG_COUNT * sizeof(u32);
3430}
305282ba 3431
6446a860
JC		 3432static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
3433 void *p)
3434{
3435 struct atl1_adapter *adapter = netdev_priv(netdev);
3436 struct atl1_hw *hw = &adapter->hw;
3437 unsigned int i;
3438 u32 *regbuf = p;
305282ba 3439
6446a860
JC		 3440 for (i = 0; i < ATL1_REG_COUNT; i++) {
3441 /*
3442 * This switch statement avoids reserved regions
3443 * of register space.
3444 */
3445 switch (i) {
3446 case 6 ... 9:
3447 case 14:
3448 case 29 ... 31:
3449 case 34 ... 63:
3450 case 75 ... 127:
3451 case 136 ... 1023:
3452 case 1027 ... 1087:
3453 case 1091 ... 1151:
3454 case 1194 ... 1195:
3455 case 1200 ... 1201:
3456 case 1206 ... 1213:
3457 case 1216 ... 1279:
3458 case 1290 ... 1311:
3459 case 1323 ... 1343:
3460 case 1358 ... 1359:
3461 case 1368 ... 1375:
3462 case 1378 ... 1383:
3463 case 1388 ... 1391:
3464 case 1393 ... 1395:
3465 case 1402 ... 1403:
3466 case 1410 ... 1471:
3467 case 1522 ... 1535:
3468 /* reserved region; don't read it */
3469 regbuf[i] = 0;
3470 break;
3471 default:
3472 /* unreserved region */
3473 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
3474 }
3475 }
3476}
305282ba 3477
6446a860
JC		 3478static void atl1_get_ringparam(struct net_device *netdev,
3479 struct ethtool_ringparam *ring)
3480{
3481 struct atl1_adapter *adapter = netdev_priv(netdev);
3482 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
3483 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
305282ba 3484
6446a860
JC		 3485 ring->rx_max_pending = ATL1_MAX_RFD;
3486 ring->tx_max_pending = ATL1_MAX_TPD;
3487 ring->rx_mini_max_pending = 0;
3488 ring->rx_jumbo_max_pending = 0;
3489 ring->rx_pending = rxdr->count;
3490 ring->tx_pending = txdr->count;
3491 ring->rx_mini_pending = 0;
3492 ring->rx_jumbo_pending = 0;
3493}
305282ba 3494
6446a860
JC		 3495static int atl1_set_ringparam(struct net_device *netdev,
3496 struct ethtool_ringparam *ring)
3497{
3498 struct atl1_adapter *adapter = netdev_priv(netdev);
3499 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
3500 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
3501 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
305282ba 3502
6446a860
JC		 3503 struct atl1_tpd_ring tpd_old, tpd_new;
3504 struct atl1_rfd_ring rfd_old, rfd_new;
3505 struct atl1_rrd_ring rrd_old, rrd_new;
3506 struct atl1_ring_header rhdr_old, rhdr_new;
3507 int err;
305282ba 3508
6446a860
JC		 3509 tpd_old = adapter->tpd_ring;
3510 rfd_old = adapter->rfd_ring;
3511 rrd_old = adapter->rrd_ring;
3512 rhdr_old = adapter->ring_header;
305282ba 3513
6446a860
JC		 3514 if (netif_running(adapter->netdev))
3515 atl1_down(adapter);
305282ba 3516
6446a860
JC		 3517 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
3518 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
3519 rfdr->count;
3520 rfdr->count = (rfdr->count + 3) & ~3;
3521 rrdr->count = rfdr->count;
305282ba 3522
6446a860
JC		 3523 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
3524 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
3525 tpdr->count;
3526 tpdr->count = (tpdr->count + 3) & ~3;
3527
3528 if (netif_running(adapter->netdev)) {
3529 /* try to get new resources before deleting old */
3530 err = atl1_setup_ring_resources(adapter);
3531 if (err)
3532 goto err_setup_ring;
3533
3534 /*
3535 * save the new, restore the old in order to free it,
3536 * then restore the new back again
3537 */
305282ba 3538
6446a860
JC		 3539 rfd_new = adapter->rfd_ring;
3540 rrd_new = adapter->rrd_ring;
3541 tpd_new = adapter->tpd_ring;
3542 rhdr_new = adapter->ring_header;
3543 adapter->rfd_ring = rfd_old;
3544 adapter->rrd_ring = rrd_old;
3545 adapter->tpd_ring = tpd_old;
3546 adapter->ring_header = rhdr_old;
3547 atl1_free_ring_resources(adapter);
3548 adapter->rfd_ring = rfd_new;
3549 adapter->rrd_ring = rrd_new;
3550 adapter->tpd_ring = tpd_new;
3551 adapter->ring_header = rhdr_new;
305282ba 3552
6446a860
JC		 3553 err = atl1_up(adapter);
3554 if (err)
3555 return err;
3556 }
305282ba 3557 return 0;
6446a860
JC		 3558
3559err_setup_ring:
3560 adapter->rfd_ring = rfd_old;
3561 adapter->rrd_ring = rrd_old;
3562 adapter->tpd_ring = tpd_old;
3563 adapter->ring_header = rhdr_old;
3564 atl1_up(adapter);
3565 return err;
305282ba
JC		 3566}
3567
6446a860
JC		 3568static void atl1_get_pauseparam(struct net_device *netdev,
3569 struct ethtool_pauseparam *epause)
305282ba 3570{
6446a860
JC		 3571 struct atl1_adapter *adapter = netdev_priv(netdev);
3572 struct atl1_hw *hw = &adapter->hw;
305282ba 3573
6446a860
JC		 3574 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3575 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3576 epause->autoneg = AUTONEG_ENABLE;
3577 } else {
3578 epause->autoneg = AUTONEG_DISABLE;
305282ba 3579 }
6446a860
JC		 3580 epause->rx_pause = 1;
3581 epause->tx_pause = 1;
305282ba
JC		 3582}
3583
6446a860
JC		 3584static int atl1_set_pauseparam(struct net_device *netdev,
3585 struct ethtool_pauseparam *epause)
305282ba 3586{
6446a860
JC		 3587 struct atl1_adapter *adapter = netdev_priv(netdev);
3588 struct atl1_hw *hw = &adapter->hw;
305282ba 3589
6446a860
JC		 3590 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3591 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3592 epause->autoneg = AUTONEG_ENABLE;
3593 } else {
3594 epause->autoneg = AUTONEG_DISABLE;
3595 }
3596
3597 epause->rx_pause = 1;
3598 epause->tx_pause = 1;
3599
3600 return 0;
305282ba
JC		 3601}
3602
6446a860
JC		 3603/* FIXME: is this right? -- CHS */
3604static u32 atl1_get_rx_csum(struct net_device *netdev)
305282ba 3605{
6446a860
JC		 3606 return 1;
3607}
305282ba 3608
6446a860
JC		 3609static void atl1_get_strings(struct net_device *netdev, u32 stringset,
3610 u8 *data)
3611{
3612 u8 *p = data;
3613 int i;
305282ba 3614
6446a860
JC		 3615 switch (stringset) {
3616 case ETH_SS_STATS:
3617 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3618 memcpy(p, atl1_gstrings_stats[i].stat_string,
3619 ETH_GSTRING_LEN);
3620 p += ETH_GSTRING_LEN;
3621 }
3622 break;
305282ba 3623 }
305282ba
JC		 3624}
3625
6446a860 3626static int atl1_nway_reset(struct net_device *netdev)
305282ba 3627{
6446a860
JC		 3628 struct atl1_adapter *adapter = netdev_priv(netdev);
3629 struct atl1_hw *hw = &adapter->hw;
305282ba 3630
6446a860
JC		 3631 if (netif_running(netdev)) {
3632 u16 phy_data;
3633 atl1_down(adapter);
305282ba 3634
6446a860
JC		 3635 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3636 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3637 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3638 } else {
3639 switch (hw->media_type) {
3640 case MEDIA_TYPE_100M_FULL:
3641 phy_data = MII_CR_FULL_DUPLEX |
3642 MII_CR_SPEED_100 | MII_CR_RESET;
3643 break;
3644 case MEDIA_TYPE_100M_HALF:
3645 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3646 break;
3647 case MEDIA_TYPE_10M_FULL:
3648 phy_data = MII_CR_FULL_DUPLEX |
3649 MII_CR_SPEED_10 | MII_CR_RESET;
3650 break;
3651 default:
3652 /* MEDIA_TYPE_10M_HALF */
3653 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3654 }
3655 }
3656 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3657 atl1_up(adapter);
305282ba 3658 }
305282ba
JC		 3659 return 0;
3660}
3661
ff2d8d6c 3662static const struct ethtool_ops atl1_ethtool_ops = {
6446a860
JC		 3663 .get_settings = atl1_get_settings,
3664 .set_settings = atl1_set_settings,
3665 .get_drvinfo = atl1_get_drvinfo,
3666 .get_wol = atl1_get_wol,
3667 .set_wol = atl1_set_wol,
3668 .get_msglevel = atl1_get_msglevel,
3669 .set_msglevel = atl1_set_msglevel,
3670 .get_regs_len = atl1_get_regs_len,
3671 .get_regs = atl1_get_regs,
3672 .get_ringparam = atl1_get_ringparam,
3673 .set_ringparam = atl1_set_ringparam,
3674 .get_pauseparam = atl1_get_pauseparam,
3675 .set_pauseparam = atl1_set_pauseparam,
3676 .get_rx_csum = atl1_get_rx_csum,
3677 .set_tx_csum = ethtool_op_set_tx_hw_csum,
3678 .get_link = ethtool_op_get_link,
3679 .set_sg = ethtool_op_set_sg,
3680 .get_strings = atl1_get_strings,
3681 .nway_reset = atl1_nway_reset,
3682 .get_ethtool_stats = atl1_get_ethtool_stats,
3683 .get_sset_count = atl1_get_sset_count,
3684 .set_tso = ethtool_op_set_tso,
3685};
Clone of davem's net-next-2.6 tree