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netdev: add more functions to netdevice ops
[net-next-2.6.git] / drivers / net / atl1e / atl1e_main.c
CommitLineData
a6a53252
JY		 1/*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "atl1e.h"
23
24#define DRV_VERSION "1.0.0.7-NAPI"
25
26char atl1e_driver_name[] = "ATL1E";
27char atl1e_driver_version[] = DRV_VERSION;
28#define PCI_DEVICE_ID_ATTANSIC_L1E 0x1026
29/*
30 * atl1e_pci_tbl - PCI Device ID Table
31 *
32 * Wildcard entries (PCI_ANY_ID) should come last
33 * Last entry must be all 0s
34 *
35 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
36 * Class, Class Mask, private data (not used) }
37 */
38static struct pci_device_id atl1e_pci_tbl[] = {
39 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1E)},
40 /* required last entry */
41 { 0 }
42};
43MODULE_DEVICE_TABLE(pci, atl1e_pci_tbl);
44
45MODULE_AUTHOR("Atheros Corporation, <xiong.huang@atheros.com>, Jie Yang <jie.yang@atheros.com>");
46MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
47MODULE_LICENSE("GPL");
48MODULE_VERSION(DRV_VERSION);
49
e6ca2328 50static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter);
a6a53252
JY		 51
52static const u16
53atl1e_rx_page_vld_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
54{
55 {REG_HOST_RXF0_PAGE0_VLD, REG_HOST_RXF0_PAGE1_VLD},
56 {REG_HOST_RXF1_PAGE0_VLD, REG_HOST_RXF1_PAGE1_VLD},
57 {REG_HOST_RXF2_PAGE0_VLD, REG_HOST_RXF2_PAGE1_VLD},
58 {REG_HOST_RXF3_PAGE0_VLD, REG_HOST_RXF3_PAGE1_VLD}
59};
60
61static const u16 atl1e_rx_page_hi_addr_regs[AT_MAX_RECEIVE_QUEUE] =
62{
63 REG_RXF0_BASE_ADDR_HI,
64 REG_RXF1_BASE_ADDR_HI,
65 REG_RXF2_BASE_ADDR_HI,
66 REG_RXF3_BASE_ADDR_HI
67};
68
69static const u16
70atl1e_rx_page_lo_addr_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
71{
72 {REG_HOST_RXF0_PAGE0_LO, REG_HOST_RXF0_PAGE1_LO},
73 {REG_HOST_RXF1_PAGE0_LO, REG_HOST_RXF1_PAGE1_LO},
74 {REG_HOST_RXF2_PAGE0_LO, REG_HOST_RXF2_PAGE1_LO},
75 {REG_HOST_RXF3_PAGE0_LO, REG_HOST_RXF3_PAGE1_LO}
76};
77
78static const u16
79atl1e_rx_page_write_offset_regs[AT_MAX_RECEIVE_QUEUE][AT_PAGE_NUM_PER_QUEUE] =
80{
81 {REG_HOST_RXF0_MB0_LO, REG_HOST_RXF0_MB1_LO},
82 {REG_HOST_RXF1_MB0_LO, REG_HOST_RXF1_MB1_LO},
83 {REG_HOST_RXF2_MB0_LO, REG_HOST_RXF2_MB1_LO},
84 {REG_HOST_RXF3_MB0_LO, REG_HOST_RXF3_MB1_LO}
85};
86
87static const u16 atl1e_pay_load_size[] = {
88 128, 256, 512, 1024, 2048, 4096,
89};
90
91/*
92 * atl1e_irq_enable - Enable default interrupt generation settings
93 * @adapter: board private structure
94 */
95static inline void atl1e_irq_enable(struct atl1e_adapter *adapter)
96{
97 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
98 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
99 AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
100 AT_WRITE_FLUSH(&adapter->hw);
101 }
102}
103
104/*
105 * atl1e_irq_disable - Mask off interrupt generation on the NIC
106 * @adapter: board private structure
107 */
108static inline void atl1e_irq_disable(struct atl1e_adapter *adapter)
109{
110 atomic_inc(&adapter->irq_sem);
111 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
112 AT_WRITE_FLUSH(&adapter->hw);
113 synchronize_irq(adapter->pdev->irq);
114}
115
116/*
117 * atl1e_irq_reset - reset interrupt confiure on the NIC
118 * @adapter: board private structure
119 */
120static inline void atl1e_irq_reset(struct atl1e_adapter *adapter)
121{
122 atomic_set(&adapter->irq_sem, 0);
123 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
124 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
125 AT_WRITE_FLUSH(&adapter->hw);
126}
127
128/*
129 * atl1e_phy_config - Timer Call-back
130 * @data: pointer to netdev cast into an unsigned long
131 */
132static void atl1e_phy_config(unsigned long data)
133{
134 struct atl1e_adapter *adapter = (struct atl1e_adapter *) data;
135 struct atl1e_hw *hw = &adapter->hw;
136 unsigned long flags;
137
138 spin_lock_irqsave(&adapter->mdio_lock, flags);
139 atl1e_restart_autoneg(hw);
140 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
141}
142
143void atl1e_reinit_locked(struct atl1e_adapter *adapter)
144{
145
146 WARN_ON(in_interrupt());
147 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
148 msleep(1);
149 atl1e_down(adapter);
150 atl1e_up(adapter);
151 clear_bit(__AT_RESETTING, &adapter->flags);
152}
153
154static void atl1e_reset_task(struct work_struct *work)
155{
156 struct atl1e_adapter *adapter;
157 adapter = container_of(work, struct atl1e_adapter, reset_task);
158
159 atl1e_reinit_locked(adapter);
160}
161
162static int atl1e_check_link(struct atl1e_adapter *adapter)
163{
164 struct atl1e_hw *hw = &adapter->hw;
165 struct net_device *netdev = adapter->netdev;
166 struct pci_dev *pdev = adapter->pdev;
167 int err = 0;
168 u16 speed, duplex, phy_data;
169
170 /* MII_BMSR must read twise */
171 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
172 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
173 if ((phy_data & BMSR_LSTATUS) == 0) {
174 /* link down */
175 if (netif_carrier_ok(netdev)) { /* old link state: Up */
176 u32 value;
177 /* disable rx */
178 value = AT_READ_REG(hw, REG_MAC_CTRL);
179 value &= ~MAC_CTRL_RX_EN;
180 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
181 adapter->link_speed = SPEED_0;
182 netif_carrier_off(netdev);
183 netif_stop_queue(netdev);
184 }
185 } else {
186 /* Link Up */
187 err = atl1e_get_speed_and_duplex(hw, &speed, &duplex);
188 if (unlikely(err))
189 return err;
190
191 /* link result is our setting */
192 if (adapter->link_speed != speed ||
193 adapter->link_duplex != duplex) {
194 adapter->link_speed = speed;
195 adapter->link_duplex = duplex;
196 atl1e_setup_mac_ctrl(adapter);
197 dev_info(&pdev->dev,
198 "%s: %s NIC Link is Up<%d Mbps %s>\n",
199 atl1e_driver_name, netdev->name,
200 adapter->link_speed,
201 adapter->link_duplex == FULL_DUPLEX ?
202 "Full Duplex" : "Half Duplex");
203 }
204
205 if (!netif_carrier_ok(netdev)) {
206 /* Link down -> Up */
207 netif_carrier_on(netdev);
208 netif_wake_queue(netdev);
209 }
210 }
211 return 0;
212}
213
214/*
215 * atl1e_link_chg_task - deal with link change event Out of interrupt context
216 * @netdev: network interface device structure
217 */
218static void atl1e_link_chg_task(struct work_struct *work)
219{
220 struct atl1e_adapter *adapter;
221 unsigned long flags;
222
223 adapter = container_of(work, struct atl1e_adapter, link_chg_task);
224 spin_lock_irqsave(&adapter->mdio_lock, flags);
225 atl1e_check_link(adapter);
226 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
227}
228
229static void atl1e_link_chg_event(struct atl1e_adapter *adapter)
230{
231 struct net_device *netdev = adapter->netdev;
232 struct pci_dev *pdev = adapter->pdev;
233 u16 phy_data = 0;
234 u16 link_up = 0;
235
236 spin_lock(&adapter->mdio_lock);
237 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
238 atl1e_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
239 spin_unlock(&adapter->mdio_lock);
240 link_up = phy_data & BMSR_LSTATUS;
241 /* notify upper layer link down ASAP */
242 if (!link_up) {
243 if (netif_carrier_ok(netdev)) {
244 /* old link state: Up */
245 dev_info(&pdev->dev, "%s: %s NIC Link is Down\n",
246 atl1e_driver_name, netdev->name);
247 adapter->link_speed = SPEED_0;
248 netif_stop_queue(netdev);
249 }
250 }
251 schedule_work(&adapter->link_chg_task);
252}
253
254static void atl1e_del_timer(struct atl1e_adapter *adapter)
255{
256 del_timer_sync(&adapter->phy_config_timer);
257}
258
259static void atl1e_cancel_work(struct atl1e_adapter *adapter)
260{
261 cancel_work_sync(&adapter->reset_task);
262 cancel_work_sync(&adapter->link_chg_task);
263}
264
265/*
266 * atl1e_tx_timeout - Respond to a Tx Hang
267 * @netdev: network interface device structure
268 */
269static void atl1e_tx_timeout(struct net_device *netdev)
270{
271 struct atl1e_adapter *adapter = netdev_priv(netdev);
272
273 /* Do the reset outside of interrupt context */
274 schedule_work(&adapter->reset_task);
275}
276
277/*
278 * atl1e_set_multi - Multicast and Promiscuous mode set
279 * @netdev: network interface device structure
280 *
281 * The set_multi entry point is called whenever the multicast address
282 * list or the network interface flags are updated. This routine is
283 * responsible for configuring the hardware for proper multicast,
284 * promiscuous mode, and all-multi behavior.
285 */
286static void atl1e_set_multi(struct net_device *netdev)
287{
288 struct atl1e_adapter *adapter = netdev_priv(netdev);
289 struct atl1e_hw *hw = &adapter->hw;
290 struct dev_mc_list *mc_ptr;
291 u32 mac_ctrl_data = 0;
292 u32 hash_value;
293
294 /* Check for Promiscuous and All Multicast modes */
295 mac_ctrl_data = AT_READ_REG(hw, REG_MAC_CTRL);
296
297 if (netdev->flags & IFF_PROMISC) {
298 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
299 } else if (netdev->flags & IFF_ALLMULTI) {
300 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
301 mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
302 } else {
303 mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
304 }
305
306 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
307
308 /* clear the old settings from the multicast hash table */
309 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
310 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
311
312 /* comoute mc addresses' hash value ,and put it into hash table */
313 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
314 hash_value = atl1e_hash_mc_addr(hw, mc_ptr->dmi_addr);
315 atl1e_hash_set(hw, hash_value);
316 }
317}
318
319static void atl1e_vlan_rx_register(struct net_device *netdev,
320 struct vlan_group *grp)
321{
322 struct atl1e_adapter *adapter = netdev_priv(netdev);
323 struct pci_dev *pdev = adapter->pdev;
324 u32 mac_ctrl_data = 0;
325
326 dev_dbg(&pdev->dev, "atl1e_vlan_rx_register\n");
327
328 atl1e_irq_disable(adapter);
329
330 adapter->vlgrp = grp;
331 mac_ctrl_data = AT_READ_REG(&adapter->hw, REG_MAC_CTRL);
332
333 if (grp) {
334 /* enable VLAN tag insert/strip */
335 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
336 } else {
337 /* disable VLAN tag insert/strip */
338 mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
339 }
340
341 AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
342 atl1e_irq_enable(adapter);
343}
344
345static void atl1e_restore_vlan(struct atl1e_adapter *adapter)
346{
347 struct pci_dev *pdev = adapter->pdev;
348
349 dev_dbg(&pdev->dev, "atl1e_restore_vlan !");
350 atl1e_vlan_rx_register(adapter->netdev, adapter->vlgrp);
351}
352/*
353 * atl1e_set_mac - Change the Ethernet Address of the NIC
354 * @netdev: network interface device structure
355 * @p: pointer to an address structure
356 *
357 * Returns 0 on success, negative on failure
358 */
359static int atl1e_set_mac_addr(struct net_device *netdev, void *p)
360{
361 struct atl1e_adapter *adapter = netdev_priv(netdev);
362 struct sockaddr *addr = p;
363
364 if (!is_valid_ether_addr(addr->sa_data))
365 return -EADDRNOTAVAIL;
366
367 if (netif_running(netdev))
368 return -EBUSY;
369
370 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
371 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
372
373 atl1e_hw_set_mac_addr(&adapter->hw);
374
375 return 0;
376}
377
378/*
379 * atl1e_change_mtu - Change the Maximum Transfer Unit
380 * @netdev: network interface device structure
381 * @new_mtu: new value for maximum frame size
382 *
383 * Returns 0 on success, negative on failure
384 */
385static int atl1e_change_mtu(struct net_device *netdev, int new_mtu)
386{
387 struct atl1e_adapter *adapter = netdev_priv(netdev);
388 int old_mtu = netdev->mtu;
389 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
390
391 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
392 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
393 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
394 return -EINVAL;
395 }
396 /* set MTU */
397 if (old_mtu != new_mtu && netif_running(netdev)) {
398 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
399 msleep(1);
400 netdev->mtu = new_mtu;
401 adapter->hw.max_frame_size = new_mtu;
402 adapter->hw.rx_jumbo_th = (max_frame + 7) >> 3;
403 atl1e_down(adapter);
404 atl1e_up(adapter);
405 clear_bit(__AT_RESETTING, &adapter->flags);
406 }
407 return 0;
408}
409
410/*
411 * caller should hold mdio_lock
412 */
413static int atl1e_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
414{
415 struct atl1e_adapter *adapter = netdev_priv(netdev);
416 u16 result;
417
418 atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
419 return result;
420}
421
422static void atl1e_mdio_write(struct net_device *netdev, int phy_id,
423 int reg_num, int val)
424{
425 struct atl1e_adapter *adapter = netdev_priv(netdev);
426
427 atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
428}
429
430/*
431 * atl1e_mii_ioctl -
432 * @netdev:
433 * @ifreq:
434 * @cmd:
435 */
436static int atl1e_mii_ioctl(struct net_device *netdev,
437 struct ifreq *ifr, int cmd)
438{
439 struct atl1e_adapter *adapter = netdev_priv(netdev);
440 struct pci_dev *pdev = adapter->pdev;
441 struct mii_ioctl_data *data = if_mii(ifr);
442 unsigned long flags;
443 int retval = 0;
444
445 if (!netif_running(netdev))
446 return -EINVAL;
447
448 spin_lock_irqsave(&adapter->mdio_lock, flags);
449 switch (cmd) {
450 case SIOCGMIIPHY:
451 data->phy_id = 0;
452 break;
453
454 case SIOCGMIIREG:
455 if (!capable(CAP_NET_ADMIN)) {
456 retval = -EPERM;
457 goto out;
458 }
459 if (atl1e_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
460 &data->val_out)) {
461 retval = -EIO;
462 goto out;
463 }
464 break;
465
466 case SIOCSMIIREG:
467 if (!capable(CAP_NET_ADMIN)) {
468 retval = -EPERM;
469 goto out;
470 }
471 if (data->reg_num & ~(0x1F)) {
472 retval = -EFAULT;
473 goto out;
474 }
475
476 dev_dbg(&pdev->dev, "<atl1e_mii_ioctl> write %x %x",
477 data->reg_num, data->val_in);
478 if (atl1e_write_phy_reg(&adapter->hw,
479 data->reg_num, data->val_in)) {
480 retval = -EIO;
481 goto out;
482 }
483 break;
484
485 default:
486 retval = -EOPNOTSUPP;
487 break;
488 }
489out:
490 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
491 return retval;
492
493}
494
495/*
496 * atl1e_ioctl -
497 * @netdev:
498 * @ifreq:
499 * @cmd:
500 */
501static int atl1e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
502{
503 switch (cmd) {
504 case SIOCGMIIPHY:
505 case SIOCGMIIREG:
506 case SIOCSMIIREG:
507 return atl1e_mii_ioctl(netdev, ifr, cmd);
508 default:
509 return -EOPNOTSUPP;
510 }
511}
512
513static void atl1e_setup_pcicmd(struct pci_dev *pdev)
514{
515 u16 cmd;
516
517 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
518 cmd &= ~(PCI_COMMAND_INTX_DISABLE | PCI_COMMAND_IO);
519 cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
520 pci_write_config_word(pdev, PCI_COMMAND, cmd);
521
522 /*
523 * some motherboards BIOS(PXE/EFI) driver may set PME
524 * while they transfer control to OS (Windows/Linux)
525 * so we should clear this bit before NIC work normally
526 */
527 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
528 msleep(1);
529}
530
531/*
532 * atl1e_alloc_queues - Allocate memory for all rings
533 * @adapter: board private structure to initialize
534 *
535 */
536static int __devinit atl1e_alloc_queues(struct atl1e_adapter *adapter)
537{
538 return 0;
539}
540
541/*
542 * atl1e_sw_init - Initialize general software structures (struct atl1e_adapter)
543 * @adapter: board private structure to initialize
544 *
545 * atl1e_sw_init initializes the Adapter private data structure.
546 * Fields are initialized based on PCI device information and
547 * OS network device settings (MTU size).
548 */
549static int __devinit atl1e_sw_init(struct atl1e_adapter *adapter)
550{
551 struct atl1e_hw *hw = &adapter->hw;
552 struct pci_dev *pdev = adapter->pdev;
553 u32 phy_status_data = 0;
554
555 adapter->wol = 0;
556 adapter->link_speed = SPEED_0; /* hardware init */
557 adapter->link_duplex = FULL_DUPLEX;
558 adapter->num_rx_queues = 1;
559
560 /* PCI config space info */
561 hw->vendor_id = pdev->vendor;
562 hw->device_id = pdev->device;
563 hw->subsystem_vendor_id = pdev->subsystem_vendor;
564 hw->subsystem_id = pdev->subsystem_device;
565
566 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
567 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
568
569 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
570 /* nic type */
571 if (hw->revision_id >= 0xF0) {
572 hw->nic_type = athr_l2e_revB;
573 } else {
574 if (phy_status_data & PHY_STATUS_100M)
575 hw->nic_type = athr_l1e;
576 else
577 hw->nic_type = athr_l2e_revA;
578 }
579
580 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
581
582 if (phy_status_data & PHY_STATUS_EMI_CA)
583 hw->emi_ca = true;
584 else
585 hw->emi_ca = false;
586
587 hw->phy_configured = false;
588 hw->preamble_len = 7;
589 hw->max_frame_size = adapter->netdev->mtu;
590 hw->rx_jumbo_th = (hw->max_frame_size + ETH_HLEN +
591 VLAN_HLEN + ETH_FCS_LEN + 7) >> 3;
592
593 hw->rrs_type = atl1e_rrs_disable;
594 hw->indirect_tab = 0;
595 hw->base_cpu = 0;
596
597 /* need confirm */
598
599 hw->ict = 50000; /* 100ms */
600 hw->smb_timer = 200000; /* 200ms */
601 hw->tpd_burst = 5;
602 hw->rrd_thresh = 1;
603 hw->tpd_thresh = adapter->tx_ring.count / 2;
604 hw->rx_count_down = 4; /* 2us resolution */
605 hw->tx_count_down = hw->imt * 4 / 3;
606 hw->dmar_block = atl1e_dma_req_1024;
607 hw->dmaw_block = atl1e_dma_req_1024;
608 hw->dmar_dly_cnt = 15;
609 hw->dmaw_dly_cnt = 4;
610
611 if (atl1e_alloc_queues(adapter)) {
612 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
613 return -ENOMEM;
614 }
615
616 atomic_set(&adapter->irq_sem, 1);
617 spin_lock_init(&adapter->mdio_lock);
618 spin_lock_init(&adapter->tx_lock);
619
620 set_bit(__AT_DOWN, &adapter->flags);
621
622 return 0;
623}
624
625/*
626 * atl1e_clean_tx_ring - Free Tx-skb
627 * @adapter: board private structure
628 */
629static void atl1e_clean_tx_ring(struct atl1e_adapter *adapter)
630{
631 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
632 &adapter->tx_ring;
633 struct atl1e_tx_buffer *tx_buffer = NULL;
634 struct pci_dev *pdev = adapter->pdev;
635 u16 index, ring_count;
636
637 if (tx_ring->desc == NULL || tx_ring->tx_buffer == NULL)
638 return;
639
640 ring_count = tx_ring->count;
641 /* first unmmap dma */
642 for (index = 0; index < ring_count; index++) {
643 tx_buffer = &tx_ring->tx_buffer[index];
644 if (tx_buffer->dma) {
645 pci_unmap_page(pdev, tx_buffer->dma,
646 tx_buffer->length, PCI_DMA_TODEVICE);
647 tx_buffer->dma = 0;
648 }
649 }
650 /* second free skb */
651 for (index = 0; index < ring_count; index++) {
652 tx_buffer = &tx_ring->tx_buffer[index];
653 if (tx_buffer->skb) {
654 dev_kfree_skb_any(tx_buffer->skb);
655 tx_buffer->skb = NULL;
656 }
657 }
658 /* Zero out Tx-buffers */
659 memset(tx_ring->desc, 0, sizeof(struct atl1e_tpd_desc) *
660 ring_count);
661 memset(tx_ring->tx_buffer, 0, sizeof(struct atl1e_tx_buffer) *
662 ring_count);
663}
664
665/*
666 * atl1e_clean_rx_ring - Free rx-reservation skbs
667 * @adapter: board private structure
668 */
669static void atl1e_clean_rx_ring(struct atl1e_adapter *adapter)
670{
671 struct atl1e_rx_ring *rx_ring =
672 (struct atl1e_rx_ring *)&adapter->rx_ring;
673 struct atl1e_rx_page_desc *rx_page_desc = rx_ring->rx_page_desc;
674 u16 i, j;
675
676
677 if (adapter->ring_vir_addr == NULL)
678 return;
679 /* Zero out the descriptor ring */
680 for (i = 0; i < adapter->num_rx_queues; i++) {
681 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
682 if (rx_page_desc[i].rx_page[j].addr != NULL) {
683 memset(rx_page_desc[i].rx_page[j].addr, 0,
684 rx_ring->real_page_size);
685 }
686 }
687 }
688}
689
690static void atl1e_cal_ring_size(struct atl1e_adapter *adapter, u32 *ring_size)
691{
692 *ring_size = ((u32)(adapter->tx_ring.count *
693 sizeof(struct atl1e_tpd_desc) + 7
694 /* tx ring, qword align */
695 + adapter->rx_ring.real_page_size * AT_PAGE_NUM_PER_QUEUE *
696 adapter->num_rx_queues + 31
697 /* rx ring, 32 bytes align */
698 + (1 + AT_PAGE_NUM_PER_QUEUE * adapter->num_rx_queues) *
699 sizeof(u32) + 3));
700 /* tx, rx cmd, dword align */
701}
702
703static void atl1e_init_ring_resources(struct atl1e_adapter *adapter)
704{
705 struct atl1e_tx_ring *tx_ring = NULL;
706 struct atl1e_rx_ring *rx_ring = NULL;
707
708 tx_ring = &adapter->tx_ring;
709 rx_ring = &adapter->rx_ring;
710
711 rx_ring->real_page_size = adapter->rx_ring.page_size
712 + adapter->hw.max_frame_size
713 + ETH_HLEN + VLAN_HLEN
714 + ETH_FCS_LEN;
715 rx_ring->real_page_size = roundup(rx_ring->real_page_size, 32);
716 atl1e_cal_ring_size(adapter, &adapter->ring_size);
717
718 adapter->ring_vir_addr = NULL;
719 adapter->rx_ring.desc = NULL;
720 rwlock_init(&adapter->tx_ring.tx_lock);
721
722 return;
723}
724
725/*
726 * Read / Write Ptr Initialize:
727 */
728static void atl1e_init_ring_ptrs(struct atl1e_adapter *adapter)
729{
730 struct atl1e_tx_ring *tx_ring = NULL;
731 struct atl1e_rx_ring *rx_ring = NULL;
732 struct atl1e_rx_page_desc *rx_page_desc = NULL;
733 int i, j;
734
735 tx_ring = &adapter->tx_ring;
736 rx_ring = &adapter->rx_ring;
737 rx_page_desc = rx_ring->rx_page_desc;
738
739 tx_ring->next_to_use = 0;
740 atomic_set(&tx_ring->next_to_clean, 0);
741
742 for (i = 0; i < adapter->num_rx_queues; i++) {
743 rx_page_desc[i].rx_using = 0;
744 rx_page_desc[i].rx_nxseq = 0;
745 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
746 *rx_page_desc[i].rx_page[j].write_offset_addr = 0;
747 rx_page_desc[i].rx_page[j].read_offset = 0;
748 }
749 }
750}
751
752/*
753 * atl1e_free_ring_resources - Free Tx / RX descriptor Resources
754 * @adapter: board private structure
755 *
756 * Free all transmit software resources
757 */
758static void atl1e_free_ring_resources(struct atl1e_adapter *adapter)
759{
760 struct pci_dev *pdev = adapter->pdev;
761
762 atl1e_clean_tx_ring(adapter);
763 atl1e_clean_rx_ring(adapter);
764
765 if (adapter->ring_vir_addr) {
766 pci_free_consistent(pdev, adapter->ring_size,
767 adapter->ring_vir_addr, adapter->ring_dma);
768 adapter->ring_vir_addr = NULL;
769 }
770
771 if (adapter->tx_ring.tx_buffer) {
772 kfree(adapter->tx_ring.tx_buffer);
773 adapter->tx_ring.tx_buffer = NULL;
774 }
775}
776
777/*
778 * atl1e_setup_mem_resources - allocate Tx / RX descriptor resources
779 * @adapter: board private structure
780 *
781 * Return 0 on success, negative on failure
782 */
783static int atl1e_setup_ring_resources(struct atl1e_adapter *adapter)
784{
785 struct pci_dev *pdev = adapter->pdev;
786 struct atl1e_tx_ring *tx_ring;
787 struct atl1e_rx_ring *rx_ring;
788 struct atl1e_rx_page_desc *rx_page_desc;
789 int size, i, j;
790 u32 offset = 0;
791 int err = 0;
792
793 if (adapter->ring_vir_addr != NULL)
794 return 0; /* alloced already */
795
796 tx_ring = &adapter->tx_ring;
797 rx_ring = &adapter->rx_ring;
798
799 /* real ring DMA buffer */
800
801 size = adapter->ring_size;
802 adapter->ring_vir_addr = pci_alloc_consistent(pdev,
803 adapter->ring_size, &adapter->ring_dma);
804
805 if (adapter->ring_vir_addr == NULL) {
806 dev_err(&pdev->dev, "pci_alloc_consistent failed, "
807 "size = D%d", size);
808 return -ENOMEM;
809 }
810
811 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
812
813 rx_page_desc = rx_ring->rx_page_desc;
814
815 /* Init TPD Ring */
816 tx_ring->dma = roundup(adapter->ring_dma, 8);
817 offset = tx_ring->dma - adapter->ring_dma;
818 tx_ring->desc = (struct atl1e_tpd_desc *)
819 (adapter->ring_vir_addr + offset);
820 size = sizeof(struct atl1e_tx_buffer) * (tx_ring->count);
821 tx_ring->tx_buffer = kzalloc(size, GFP_KERNEL);
822 if (tx_ring->tx_buffer == NULL) {
823 dev_err(&pdev->dev, "kzalloc failed , size = D%d", size);
824 err = -ENOMEM;
825 goto failed;
826 }
827
828 /* Init RXF-Pages */
829 offset += (sizeof(struct atl1e_tpd_desc) * tx_ring->count);
830 offset = roundup(offset, 32);
831
832 for (i = 0; i < adapter->num_rx_queues; i++) {
833 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
834 rx_page_desc[i].rx_page[j].dma =
835 adapter->ring_dma + offset;
836 rx_page_desc[i].rx_page[j].addr =
837 adapter->ring_vir_addr + offset;
838 offset += rx_ring->real_page_size;
839 }
840 }
841
842 /* Init CMB dma address */
843 tx_ring->cmb_dma = adapter->ring_dma + offset;
844 tx_ring->cmb = (u32 *)(adapter->ring_vir_addr + offset);
845 offset += sizeof(u32);
846
847 for (i = 0; i < adapter->num_rx_queues; i++) {
848 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
849 rx_page_desc[i].rx_page[j].write_offset_dma =
850 adapter->ring_dma + offset;
851 rx_page_desc[i].rx_page[j].write_offset_addr =
852 adapter->ring_vir_addr + offset;
853 offset += sizeof(u32);
854 }
855 }
856
857 if (unlikely(offset > adapter->ring_size)) {
858 dev_err(&pdev->dev, "offset(%d) > ring size(%d) !!\n",
859 offset, adapter->ring_size);
860 err = -1;
861 goto failed;
862 }
863
864 return 0;
865failed:
866 if (adapter->ring_vir_addr != NULL) {
867 pci_free_consistent(pdev, adapter->ring_size,
868 adapter->ring_vir_addr, adapter->ring_dma);
869 adapter->ring_vir_addr = NULL;
870 }
871 return err;
872}
873
874static inline void atl1e_configure_des_ring(const struct atl1e_adapter *adapter)
875{
876
877 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
878 struct atl1e_rx_ring *rx_ring =
879 (struct atl1e_rx_ring *)&adapter->rx_ring;
880 struct atl1e_tx_ring *tx_ring =
881 (struct atl1e_tx_ring *)&adapter->tx_ring;
882 struct atl1e_rx_page_desc *rx_page_desc = NULL;
883 int i, j;
884
885 AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
886 (u32)((adapter->ring_dma & AT_DMA_HI_ADDR_MASK) >> 32));
887 AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO,
888 (u32)((tx_ring->dma) & AT_DMA_LO_ADDR_MASK));
889 AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count));
890 AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO,
891 (u32)((tx_ring->cmb_dma) & AT_DMA_LO_ADDR_MASK));
892
893 rx_page_desc = rx_ring->rx_page_desc;
894 /* RXF Page Physical address / Page Length */
895 for (i = 0; i < AT_MAX_RECEIVE_QUEUE; i++) {
896 AT_WRITE_REG(hw, atl1e_rx_page_hi_addr_regs[i],
897 (u32)((adapter->ring_dma &
898 AT_DMA_HI_ADDR_MASK) >> 32));
899 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
900 u32 page_phy_addr;
901 u32 offset_phy_addr;
902
903 page_phy_addr = rx_page_desc[i].rx_page[j].dma;
904 offset_phy_addr =
905 rx_page_desc[i].rx_page[j].write_offset_dma;
906
907 AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[i][j],
908 page_phy_addr & AT_DMA_LO_ADDR_MASK);
909 AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[i][j],
910 offset_phy_addr & AT_DMA_LO_ADDR_MASK);
911 AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[i][j], 1);
912 }
913 }
914 /* Page Length */
915 AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size);
916 /* Load all of base address above */
917 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
918
919 return;
920}
921
922static inline void atl1e_configure_tx(struct atl1e_adapter *adapter)
923{
924 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
925 u32 dev_ctrl_data = 0;
926 u32 max_pay_load = 0;
927 u32 jumbo_thresh = 0;
928 u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
929
930 /* configure TXQ param */
931 if (hw->nic_type != athr_l2e_revB) {
932 extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
933 if (hw->max_frame_size <= 1500) {
934 jumbo_thresh = hw->max_frame_size + extra_size;
935 } else if (hw->max_frame_size < 6*1024) {
936 jumbo_thresh =
937 (hw->max_frame_size + extra_size) * 2 / 3;
938 } else {
939 jumbo_thresh = (hw->max_frame_size + extra_size) / 2;
940 }
941 AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3);
942 }
943
944 dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL);
945
946 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT)) &
947 DEVICE_CTRL_MAX_PAYLOAD_MASK;
948
949 hw->dmaw_block = min(max_pay_load, hw->dmaw_block);
950
951 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT)) &
952 DEVICE_CTRL_MAX_RREQ_SZ_MASK;
953 hw->dmar_block = min(max_pay_load, hw->dmar_block);
954
955 if (hw->nic_type != athr_l2e_revB)
956 AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2,
957 atl1e_pay_load_size[hw->dmar_block]);
958 /* enable TXQ */
959 AT_WRITE_REGW(hw, REG_TXQ_CTRL,
960 (((u16)hw->tpd_burst & TXQ_CTRL_NUM_TPD_BURST_MASK)
961 << TXQ_CTRL_NUM_TPD_BURST_SHIFT)
962 | TXQ_CTRL_ENH_MODE | TXQ_CTRL_EN);
963 return;
964}
965
966static inline void atl1e_configure_rx(struct atl1e_adapter *adapter)
967{
968 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
969 u32 rxf_len = 0;
970 u32 rxf_low = 0;
971 u32 rxf_high = 0;
972 u32 rxf_thresh_data = 0;
973 u32 rxq_ctrl_data = 0;
974
975 if (hw->nic_type != athr_l2e_revB) {
976 AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM,
977 (u16)((hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) <<
978 RXQ_JMBOSZ_TH_SHIFT |
979 (1 & RXQ_JMBO_LKAH_MASK) <<
980 RXQ_JMBO_LKAH_SHIFT));
981
982 rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
983 rxf_high = rxf_len * 4 / 5;
984 rxf_low = rxf_len / 5;
985 rxf_thresh_data = ((rxf_high & RXQ_RXF_PAUSE_TH_HI_MASK)
986 << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
987 ((rxf_low & RXQ_RXF_PAUSE_TH_LO_MASK)
988 << RXQ_RXF_PAUSE_TH_LO_SHIFT);
989
990 AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data);
991 }
992
993 /* RRS */
994 AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
995 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
996
997 if (hw->rrs_type & atl1e_rrs_ipv4)
998 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4;
999
1000 if (hw->rrs_type & atl1e_rrs_ipv4_tcp)
1001 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV4_TCP;
1002
1003 if (hw->rrs_type & atl1e_rrs_ipv6)
1004 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6;
1005
1006 if (hw->rrs_type & atl1e_rrs_ipv6_tcp)
1007 rxq_ctrl_data |= RXQ_CTRL_HASH_TYPE_IPV6_TCP;
1008
1009 if (hw->rrs_type != atl1e_rrs_disable)
1010 rxq_ctrl_data |=
1011 (RXQ_CTRL_HASH_ENABLE | RXQ_CTRL_RSS_MODE_MQUESINT);
1012
1013 rxq_ctrl_data |= RXQ_CTRL_IPV6_XSUM_VERIFY_EN | RXQ_CTRL_PBA_ALIGN_32 |
1014 RXQ_CTRL_CUT_THRU_EN | RXQ_CTRL_EN;
1015
1016 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1017 return;
1018}
1019
1020static inline void atl1e_configure_dma(struct atl1e_adapter *adapter)
1021{
1022 struct atl1e_hw *hw = &adapter->hw;
1023 u32 dma_ctrl_data = 0;
1024
1025 dma_ctrl_data = DMA_CTRL_RXCMB_EN;
1026 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1027 << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
1028 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1029 << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
1030 dma_ctrl_data |= DMA_CTRL_DMAR_REQ_PRI | DMA_CTRL_DMAR_OUT_ORDER;
1031 dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
1032 << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
1033 dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
1034 << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
1035
1036 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1037 return;
1038}
1039
e6ca2328 1040static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter)
a6a53252
JY		 1041{
1042 u32 value;
1043 struct atl1e_hw *hw = &adapter->hw;
1044 struct net_device *netdev = adapter->netdev;
1045
1046 /* Config MAC CTRL Register */
1047 value = MAC_CTRL_TX_EN |
1048 MAC_CTRL_RX_EN ;
1049
1050 if (FULL_DUPLEX == adapter->link_duplex)
1051 value |= MAC_CTRL_DUPLX;
1052
1053 value |= ((u32)((SPEED_1000 == adapter->link_speed) ?
1054 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1055 MAC_CTRL_SPEED_SHIFT);
1056 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1057
1058 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1059 value |= (((u32)adapter->hw.preamble_len &
1060 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1061
1062 if (adapter->vlgrp)
1063 value |= MAC_CTRL_RMV_VLAN;
1064
1065 value |= MAC_CTRL_BC_EN;
1066 if (netdev->flags & IFF_PROMISC)
1067 value |= MAC_CTRL_PROMIS_EN;
1068 if (netdev->flags & IFF_ALLMULTI)
1069 value |= MAC_CTRL_MC_ALL_EN;
1070
1071 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
1072}
1073
1074/*
1075 * atl1e_configure - Configure Transmit&Receive Unit after Reset
1076 * @adapter: board private structure
1077 *
1078 * Configure the Tx /Rx unit of the MAC after a reset.
1079 */
1080static int atl1e_configure(struct atl1e_adapter *adapter)
1081{
1082 struct atl1e_hw *hw = &adapter->hw;
1083 struct pci_dev *pdev = adapter->pdev;
1084
1085 u32 intr_status_data = 0;
1086
1087 /* clear interrupt status */
1088 AT_WRITE_REG(hw, REG_ISR, ~0);
1089
1090 /* 1. set MAC Address */
1091 atl1e_hw_set_mac_addr(hw);
1092
1093 /* 2. Init the Multicast HASH table done by set_muti */
1094
1095 /* 3. Clear any WOL status */
1096 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1097
1098 /* 4. Descripter Ring BaseMem/Length/Read ptr/Write ptr
1099 * TPD Ring/SMB/RXF0 Page CMBs, they use the same
1100 * High 32bits memory */
1101 atl1e_configure_des_ring(adapter);
1102
1103 /* 5. set Interrupt Moderator Timer */
1104 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, hw->imt);
1105 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, hw->imt);
1106 AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE |
1107 MASTER_CTRL_ITIMER_EN | MASTER_CTRL_ITIMER2_EN);
1108
1109 /* 6. rx/tx threshold to trig interrupt */
1110 AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, hw->rrd_thresh);
1111 AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, hw->tpd_thresh);
1112 AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, hw->rx_count_down);
1113 AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, hw->tx_count_down);
1114
1115 /* 7. set Interrupt Clear Timer */
1116 AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, hw->ict);
1117
1118 /* 8. set MTU */
1119 AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1120 VLAN_HLEN + ETH_FCS_LEN);
1121
1122 /* 9. config TXQ early tx threshold */
1123 atl1e_configure_tx(adapter);
1124
1125 /* 10. config RXQ */
1126 atl1e_configure_rx(adapter);
1127
1128 /* 11. config DMA Engine */
1129 atl1e_configure_dma(adapter);
1130
1131 /* 12. smb timer to trig interrupt */
1132 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, hw->smb_timer);
1133
1134 intr_status_data = AT_READ_REG(hw, REG_ISR);
1135 if (unlikely((intr_status_data & ISR_PHY_LINKDOWN) != 0)) {
1136 dev_err(&pdev->dev, "atl1e_configure failed,"
1137 "PCIE phy link down\n");
1138 return -1;
1139 }
1140
1141 AT_WRITE_REG(hw, REG_ISR, 0x7fffffff);
1142 return 0;
1143}
1144
1145/*
1146 * atl1e_get_stats - Get System Network Statistics
1147 * @netdev: network interface device structure
1148 *
1149 * Returns the address of the device statistics structure.
1150 * The statistics are actually updated from the timer callback.
1151 */
1152static struct net_device_stats *atl1e_get_stats(struct net_device *netdev)
1153{
1154 struct atl1e_adapter *adapter = netdev_priv(netdev);
1155 struct atl1e_hw_stats *hw_stats = &adapter->hw_stats;
1156 struct net_device_stats *net_stats = &adapter->net_stats;
1157
1158 net_stats->rx_packets = hw_stats->rx_ok;
1159 net_stats->tx_packets = hw_stats->tx_ok;
1160 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1161 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1162 net_stats->multicast = hw_stats->rx_mcast;
1163 net_stats->collisions = hw_stats->tx_1_col +
1164 hw_stats->tx_2_col * 2 +
1165 hw_stats->tx_late_col + hw_stats->tx_abort_col;
1166
1167 net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
1168 hw_stats->rx_len_err + hw_stats->rx_sz_ov +
1169 hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
1170 net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
1171 net_stats->rx_length_errors = hw_stats->rx_len_err;
1172 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1173 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1174 net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1175
1176 net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1177
1178 net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
1179 hw_stats->tx_underrun + hw_stats->tx_trunc;
1180 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1181 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1182 net_stats->tx_window_errors = hw_stats->tx_late_col;
1183
1184 return &adapter->net_stats;
1185}
1186
1187static void atl1e_update_hw_stats(struct atl1e_adapter *adapter)
1188{
1189 u16 hw_reg_addr = 0;
1190 unsigned long *stats_item = NULL;
1191
1192 /* update rx status */
1193 hw_reg_addr = REG_MAC_RX_STATUS_BIN;
1194 stats_item = &adapter->hw_stats.rx_ok;
1195 while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
1196 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1197 stats_item++;
1198 hw_reg_addr += 4;
1199 }
1200 /* update tx status */
1201 hw_reg_addr = REG_MAC_TX_STATUS_BIN;
1202 stats_item = &adapter->hw_stats.tx_ok;
1203 while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
1204 *stats_item += AT_READ_REG(&adapter->hw, hw_reg_addr);
1205 stats_item++;
1206 hw_reg_addr += 4;
1207 }
1208}
1209
1210static inline void atl1e_clear_phy_int(struct atl1e_adapter *adapter)
1211{
1212 u16 phy_data;
1213
1214 spin_lock(&adapter->mdio_lock);
1215 atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data);
1216 spin_unlock(&adapter->mdio_lock);
1217}
1218
1219static bool atl1e_clean_tx_irq(struct atl1e_adapter *adapter)
1220{
1221 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
1222 &adapter->tx_ring;
1223 struct atl1e_tx_buffer *tx_buffer = NULL;
1224 u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX);
1225 u16 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1226
1227 while (next_to_clean != hw_next_to_clean) {
1228 tx_buffer = &tx_ring->tx_buffer[next_to_clean];
1229 if (tx_buffer->dma) {
1230 pci_unmap_page(adapter->pdev, tx_buffer->dma,
1231 tx_buffer->length, PCI_DMA_TODEVICE);
1232 tx_buffer->dma = 0;
1233 }
1234
1235 if (tx_buffer->skb) {
1236 dev_kfree_skb_irq(tx_buffer->skb);
1237 tx_buffer->skb = NULL;
1238 }
1239
1240 if (++next_to_clean == tx_ring->count)
1241 next_to_clean = 0;
1242 }
1243
1244 atomic_set(&tx_ring->next_to_clean, next_to_clean);
1245
1246 if (netif_queue_stopped(adapter->netdev) &&
1247 netif_carrier_ok(adapter->netdev)) {
1248 netif_wake_queue(adapter->netdev);
1249 }
1250
1251 return true;
1252}
1253
1254/*
1255 * atl1e_intr - Interrupt Handler
1256 * @irq: interrupt number
1257 * @data: pointer to a network interface device structure
1258 * @pt_regs: CPU registers structure
1259 */
1260static irqreturn_t atl1e_intr(int irq, void *data)
1261{
1262 struct net_device *netdev = data;
1263 struct atl1e_adapter *adapter = netdev_priv(netdev);
1264 struct pci_dev *pdev = adapter->pdev;
1265 struct atl1e_hw *hw = &adapter->hw;
1266 int max_ints = AT_MAX_INT_WORK;
1267 int handled = IRQ_NONE;
1268 u32 status;
1269
1270 do {
1271 status = AT_READ_REG(hw, REG_ISR);
1272 if ((status & IMR_NORMAL_MASK) == 0 ||
1273 (status & ISR_DIS_INT) != 0) {
1274 if (max_ints != AT_MAX_INT_WORK)
1275 handled = IRQ_HANDLED;
1276 break;
1277 }
1278 /* link event */
1279 if (status & ISR_GPHY)
1280 atl1e_clear_phy_int(adapter);
1281 /* Ack ISR */
1282 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1283
1284 handled = IRQ_HANDLED;
1285 /* check if PCIE PHY Link down */
1286 if (status & ISR_PHY_LINKDOWN) {
1287 dev_err(&pdev->dev,
1288 "pcie phy linkdown %x\n", status);
1289 if (netif_running(adapter->netdev)) {
1290 /* reset MAC */
1291 atl1e_irq_reset(adapter);
1292 schedule_work(&adapter->reset_task);
1293 break;
1294 }
1295 }
1296
1297 /* check if DMA read/write error */
1298 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
1299 dev_err(&pdev->dev,
1300 "PCIE DMA RW error (status = 0x%x)\n",
1301 status);
1302 atl1e_irq_reset(adapter);
1303 schedule_work(&adapter->reset_task);
1304 break;
1305 }
1306
1307 if (status & ISR_SMB)
1308 atl1e_update_hw_stats(adapter);
1309
1310 /* link event */
1311 if (status & (ISR_GPHY | ISR_MANUAL)) {
1312 adapter->net_stats.tx_carrier_errors++;
1313 atl1e_link_chg_event(adapter);
1314 break;
1315 }
1316
1317 /* transmit event */
1318 if (status & ISR_TX_EVENT)
1319 atl1e_clean_tx_irq(adapter);
1320
1321 if (status & ISR_RX_EVENT) {
1322 /*
1323 * disable rx interrupts, without
1324 * the synchronize_irq bit
1325 */
1326 AT_WRITE_REG(hw, REG_IMR,
1327 IMR_NORMAL_MASK & ~ISR_RX_EVENT);
1328 AT_WRITE_FLUSH(hw);
1329 if (likely(netif_rx_schedule_prep(netdev,
1330 &adapter->napi)))
1331 __netif_rx_schedule(netdev, &adapter->napi);
1332 }
1333 } while (--max_ints > 0);
1334 /* re-enable Interrupt*/
1335 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1336
1337 return handled;
1338}
1339
1340static inline void atl1e_rx_checksum(struct atl1e_adapter *adapter,
1341 struct sk_buff *skb, struct atl1e_recv_ret_status *prrs)
1342{
1343 u8 *packet = (u8 *)(prrs + 1);
1344 struct iphdr *iph;
1345 u16 head_len = ETH_HLEN;
1346 u16 pkt_flags;
1347 u16 err_flags;
1348
1349 skb->ip_summed = CHECKSUM_NONE;
1350 pkt_flags = prrs->pkt_flag;
1351 err_flags = prrs->err_flag;
1352 if (((pkt_flags & RRS_IS_IPV4) || (pkt_flags & RRS_IS_IPV6)) &&
1353 ((pkt_flags & RRS_IS_TCP) || (pkt_flags & RRS_IS_UDP))) {
1354 if (pkt_flags & RRS_IS_IPV4) {
1355 if (pkt_flags & RRS_IS_802_3)
1356 head_len += 8;
1357 iph = (struct iphdr *) (packet + head_len);
1358 if (iph->frag_off != 0 && !(pkt_flags & RRS_IS_IP_DF))
1359 goto hw_xsum;
1360 }
1361 if (!(err_flags & (RRS_ERR_IP_CSUM | RRS_ERR_L4_CSUM))) {
1362 skb->ip_summed = CHECKSUM_UNNECESSARY;
1363 return;
1364 }
1365 }
1366
1367hw_xsum :
1368 return;
1369}
1370
1371static struct atl1e_rx_page *atl1e_get_rx_page(struct atl1e_adapter *adapter,
1372 u8 que)
1373{
1374 struct atl1e_rx_page_desc *rx_page_desc =
1375 (struct atl1e_rx_page_desc *) adapter->rx_ring.rx_page_desc;
1376 u8 rx_using = rx_page_desc[que].rx_using;
1377
1378 return (struct atl1e_rx_page *)&(rx_page_desc[que].rx_page[rx_using]);
1379}
1380
1381static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter, u8 que,
1382 int *work_done, int work_to_do)
1383{
1384 struct pci_dev *pdev = adapter->pdev;
1385 struct net_device *netdev = adapter->netdev;
1386 struct atl1e_rx_ring *rx_ring = (struct atl1e_rx_ring *)
1387 &adapter->rx_ring;
1388 struct atl1e_rx_page_desc *rx_page_desc =
1389 (struct atl1e_rx_page_desc *) rx_ring->rx_page_desc;
1390 struct sk_buff *skb = NULL;
1391 struct atl1e_rx_page *rx_page = atl1e_get_rx_page(adapter, que);
1392 u32 packet_size, write_offset;
1393 struct atl1e_recv_ret_status *prrs;
1394
1395 write_offset = *(rx_page->write_offset_addr);
1396 if (likely(rx_page->read_offset < write_offset)) {
1397 do {
1398 if (*work_done >= work_to_do)
1399 break;
1400 (*work_done)++;
1401 /* get new packet's rrs */
1402 prrs = (struct atl1e_recv_ret_status *) (rx_page->addr +
1403 rx_page->read_offset);
1404 /* check sequence number */
1405 if (prrs->seq_num != rx_page_desc[que].rx_nxseq) {
1406 dev_err(&pdev->dev,
1407 "rx sequence number"
1408 " error (rx=%d) (expect=%d)\n",
1409 prrs->seq_num,
1410 rx_page_desc[que].rx_nxseq);
1411 rx_page_desc[que].rx_nxseq++;
1412 /* just for debug use */
1413 AT_WRITE_REG(&adapter->hw, REG_DEBUG_DATA0,
1414 (((u32)prrs->seq_num) << 16) |
1415 rx_page_desc[que].rx_nxseq);
1416 goto fatal_err;
1417 }
1418 rx_page_desc[que].rx_nxseq++;
1419
1420 /* error packet */
1421 if (prrs->pkt_flag & RRS_IS_ERR_FRAME) {
1422 if (prrs->err_flag & (RRS_ERR_BAD_CRC |
1423 RRS_ERR_DRIBBLE | RRS_ERR_CODE |
1424 RRS_ERR_TRUNC)) {
1425 /* hardware error, discard this packet*/
1426 dev_err(&pdev->dev,
1427 "rx packet desc error %x\n",
1428 *((u32 *)prrs + 1));
1429 goto skip_pkt;
1430 }
1431 }
1432
1433 packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1434 RRS_PKT_SIZE_MASK) - 4; /* CRC */
1435 skb = netdev_alloc_skb(netdev,
1436 packet_size + NET_IP_ALIGN);
1437 if (skb == NULL) {
1438 dev_warn(&pdev->dev, "%s: Memory squeeze,"
1439 "deferring packet.\n", netdev->name);
1440 goto skip_pkt;
1441 }
1442 skb_reserve(skb, NET_IP_ALIGN);
1443 skb->dev = netdev;
1444 memcpy(skb->data, (u8 *)(prrs + 1), packet_size);
1445 skb_put(skb, packet_size);
1446 skb->protocol = eth_type_trans(skb, netdev);
1447 atl1e_rx_checksum(adapter, skb, prrs);
1448
1449 if (unlikely(adapter->vlgrp &&
1450 (prrs->pkt_flag & RRS_IS_VLAN_TAG))) {
1451 u16 vlan_tag = (prrs->vtag >> 4) |
1452 ((prrs->vtag & 7) << 13) |
1453 ((prrs->vtag & 8) << 9);
1454 dev_dbg(&pdev->dev,
1455 "RXD VLAN TAG<RRD>=0x%04x\n",
1456 prrs->vtag);
1457 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
1458 vlan_tag);
1459 } else {
1460 netif_receive_skb(skb);
1461 }
1462
a6a53252
JY		 1463skip_pkt:
1464 /* skip current packet whether it's ok or not. */
1465 rx_page->read_offset +=
1466 (((u32)((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
1467 RRS_PKT_SIZE_MASK) +
1468 sizeof(struct atl1e_recv_ret_status) + 31) &
1469 0xFFFFFFE0);
1470
1471 if (rx_page->read_offset >= rx_ring->page_size) {
1472 /* mark this page clean */
1473 u16 reg_addr;
1474 u8 rx_using;
1475
1476 rx_page->read_offset =
1477 *(rx_page->write_offset_addr) = 0;
1478 rx_using = rx_page_desc[que].rx_using;
1479 reg_addr =
1480 atl1e_rx_page_vld_regs[que][rx_using];
1481 AT_WRITE_REGB(&adapter->hw, reg_addr, 1);
1482 rx_page_desc[que].rx_using ^= 1;
1483 rx_page = atl1e_get_rx_page(adapter, que);
1484 }
1485 write_offset = *(rx_page->write_offset_addr);
1486 } while (rx_page->read_offset < write_offset);
1487 }
1488
1489 return;
1490
1491fatal_err:
1492 if (!test_bit(__AT_DOWN, &adapter->flags))
1493 schedule_work(&adapter->reset_task);
1494}
1495
1496/*
1497 * atl1e_clean - NAPI Rx polling callback
1498 * @adapter: board private structure
1499 */
1500static int atl1e_clean(struct napi_struct *napi, int budget)
1501{
1502 struct atl1e_adapter *adapter =
1503 container_of(napi, struct atl1e_adapter, napi);
1504 struct net_device *netdev = adapter->netdev;
1505 struct pci_dev *pdev = adapter->pdev;
1506 u32 imr_data;
1507 int work_done = 0;
1508
1509 /* Keep link state information with original netdev */
1510 if (!netif_carrier_ok(adapter->netdev))
1511 goto quit_polling;
1512
1513 atl1e_clean_rx_irq(adapter, 0, &work_done, budget);
1514
1515 /* If no Tx and not enough Rx work done, exit the polling mode */
1516 if (work_done < budget) {
1517quit_polling:
1518 netif_rx_complete(netdev, napi);
1519 imr_data = AT_READ_REG(&adapter->hw, REG_IMR);
1520 AT_WRITE_REG(&adapter->hw, REG_IMR, imr_data | ISR_RX_EVENT);
1521 /* test debug */
1522 if (test_bit(__AT_DOWN, &adapter->flags)) {
1523 atomic_dec(&adapter->irq_sem);
1524 dev_err(&pdev->dev,
1525 "atl1e_clean is called when AT_DOWN\n");
1526 }
1527 /* reenable RX intr */
1528 /*atl1e_irq_enable(adapter); */
1529
1530 }
1531 return work_done;
1532}
1533
1534#ifdef CONFIG_NET_POLL_CONTROLLER
1535
1536/*
1537 * Polling 'interrupt' - used by things like netconsole to send skbs
1538 * without having to re-enable interrupts. It's not called while
1539 * the interrupt routine is executing.
1540 */
1541static void atl1e_netpoll(struct net_device *netdev)
1542{
1543 struct atl1e_adapter *adapter = netdev_priv(netdev);
1544
1545 disable_irq(adapter->pdev->irq);
1546 atl1e_intr(adapter->pdev->irq, netdev);
1547 enable_irq(adapter->pdev->irq);
1548}
1549#endif
1550
1551static inline u16 atl1e_tpd_avail(struct atl1e_adapter *adapter)
1552{
1553 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1554 u16 next_to_use = 0;
1555 u16 next_to_clean = 0;
1556
1557 next_to_clean = atomic_read(&tx_ring->next_to_clean);
1558 next_to_use = tx_ring->next_to_use;
1559
1560 return (u16)(next_to_clean > next_to_use) ?
1561 (next_to_clean - next_to_use - 1) :
1562 (tx_ring->count + next_to_clean - next_to_use - 1);
1563}
1564
1565/*
1566 * get next usable tpd
1567 * Note: should call atl1e_tdp_avail to make sure
1568 * there is enough tpd to use
1569 */
1570static struct atl1e_tpd_desc *atl1e_get_tpd(struct atl1e_adapter *adapter)
1571{
1572 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1573 u16 next_to_use = 0;
1574
1575 next_to_use = tx_ring->next_to_use;
1576 if (++tx_ring->next_to_use == tx_ring->count)
1577 tx_ring->next_to_use = 0;
1578
1579 memset(&tx_ring->desc[next_to_use], 0, sizeof(struct atl1e_tpd_desc));
1580 return (struct atl1e_tpd_desc *)&tx_ring->desc[next_to_use];
1581}
1582
1583static struct atl1e_tx_buffer *
1584atl1e_get_tx_buffer(struct atl1e_adapter *adapter, struct atl1e_tpd_desc *tpd)
1585{
1586 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1587
1588 return &tx_ring->tx_buffer[tpd - tx_ring->desc];
1589}
1590
1591/* Calculate the transmit packet descript needed*/
1592static u16 atl1e_cal_tdp_req(const struct sk_buff *skb)
1593{
1594 int i = 0;
1595 u16 tpd_req = 1;
1596 u16 fg_size = 0;
1597 u16 proto_hdr_len = 0;
1598
1599 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1600 fg_size = skb_shinfo(skb)->frags[i].size;
1601 tpd_req += ((fg_size + MAX_TX_BUF_LEN - 1) >> MAX_TX_BUF_SHIFT);
1602 }
1603
1604 if (skb_is_gso(skb)) {
1605 if (skb->protocol == ntohs(ETH_P_IP) ||
1606 (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6)) {
1607 proto_hdr_len = skb_transport_offset(skb) +
1608 tcp_hdrlen(skb);
1609 if (proto_hdr_len < skb_headlen(skb)) {
1610 tpd_req += ((skb_headlen(skb) - proto_hdr_len +
1611 MAX_TX_BUF_LEN - 1) >>
1612 MAX_TX_BUF_SHIFT);
1613 }
1614 }
1615
1616 }
1617 return tpd_req;
1618}
1619
1620static int atl1e_tso_csum(struct atl1e_adapter *adapter,
1621 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1622{
1623 struct pci_dev *pdev = adapter->pdev;
1624 u8 hdr_len;
1625 u32 real_len;
1626 unsigned short offload_type;
1627 int err;
1628
1629 if (skb_is_gso(skb)) {
1630 if (skb_header_cloned(skb)) {
1631 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1632 if (unlikely(err))
1633 return -1;
1634 }
1635 offload_type = skb_shinfo(skb)->gso_type;
1636
1637 if (offload_type & SKB_GSO_TCPV4) {
1638 real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
1639 + ntohs(ip_hdr(skb)->tot_len));
1640
1641 if (real_len < skb->len)
1642 pskb_trim(skb, real_len);
1643
1644 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
1645 if (unlikely(skb->len == hdr_len)) {
1646 /* only xsum need */
1647 dev_warn(&pdev->dev,
1648 "IPV4 tso with zero data??\n");
1649 goto check_sum;
1650 } else {
1651 ip_hdr(skb)->check = 0;
1652 ip_hdr(skb)->tot_len = 0;
1653 tcp_hdr(skb)->check = ~csum_tcpudp_magic(
1654 ip_hdr(skb)->saddr,
1655 ip_hdr(skb)->daddr,
1656 0, IPPROTO_TCP, 0);
1657 tpd->word3 |= (ip_hdr(skb)->ihl &
1658 TDP_V4_IPHL_MASK) <<
1659 TPD_V4_IPHL_SHIFT;
1660 tpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
1661 TPD_TCPHDRLEN_MASK) <<
1662 TPD_TCPHDRLEN_SHIFT;
1663 tpd->word3 |= ((skb_shinfo(skb)->gso_size) &
1664 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1665 tpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
1666 }
1667 return 0;
1668 }
1669
1670 if (offload_type & SKB_GSO_TCPV6) {
1671 real_len = (((unsigned char *)ipv6_hdr(skb) - skb->data)
1672 + ntohs(ipv6_hdr(skb)->payload_len));
1673 if (real_len < skb->len)
1674 pskb_trim(skb, real_len);
1675
1676 /* check payload == 0 byte ? */
1677 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
1678 if (unlikely(skb->len == hdr_len)) {
1679 /* only xsum need */
1680 dev_warn(&pdev->dev,
1681 "IPV6 tso with zero data??\n");
1682 goto check_sum;
1683 } else {
1684 tcp_hdr(skb)->check = ~csum_ipv6_magic(
1685 &ipv6_hdr(skb)->saddr,
1686 &ipv6_hdr(skb)->daddr,
1687 0, IPPROTO_TCP, 0);
1688 tpd->word3 |= 1 << TPD_IP_VERSION_SHIFT;
1689 hdr_len >>= 1;
1690 tpd->word3 |= (hdr_len & TPD_V6_IPHLLO_MASK) <<
1691 TPD_V6_IPHLLO_SHIFT;
1692 tpd->word3 |= ((hdr_len >> 3) &
1693 TPD_V6_IPHLHI_MASK) <<
1694 TPD_V6_IPHLHI_SHIFT;
1695 tpd->word3 |= (tcp_hdrlen(skb) >> 2 &
1696 TPD_TCPHDRLEN_MASK) <<
1697 TPD_TCPHDRLEN_SHIFT;
1698 tpd->word3 |= ((skb_shinfo(skb)->gso_size) &
1699 TPD_MSS_MASK) << TPD_MSS_SHIFT;
1700 tpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
1701 }
1702 }
1703 return 0;
1704 }
1705
1706check_sum:
1707 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1708 u8 css, cso;
1709
1710 cso = skb_transport_offset(skb);
1711 if (unlikely(cso & 0x1)) {
1712 dev_err(&adapter->pdev->dev,
1713 "pay load offset should not ant event number\n");
1714 return -1;
1715 } else {
1716 css = cso + skb->csum_offset;
1717 tpd->word3 |= (cso & TPD_PLOADOFFSET_MASK) <<
1718 TPD_PLOADOFFSET_SHIFT;
1719 tpd->word3 |= (css & TPD_CCSUMOFFSET_MASK) <<
1720 TPD_CCSUMOFFSET_SHIFT;
1721 tpd->word3 |= 1 << TPD_CC_SEGMENT_EN_SHIFT;
1722 }
1723 }
1724
1725 return 0;
1726}
1727
1728static void atl1e_tx_map(struct atl1e_adapter *adapter,
1729 struct sk_buff *skb, struct atl1e_tpd_desc *tpd)
1730{
1731 struct atl1e_tpd_desc *use_tpd = NULL;
1732 struct atl1e_tx_buffer *tx_buffer = NULL;
1733 u16 buf_len = skb->len - skb->data_len;
1734 u16 map_len = 0;
1735 u16 mapped_len = 0;
1736 u16 hdr_len = 0;
1737 u16 nr_frags;
1738 u16 f;
1739 int segment;
1740
1741 nr_frags = skb_shinfo(skb)->nr_frags;
1742 segment = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
1743 if (segment) {
1744 /* TSO */
1745 map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1746 use_tpd = tpd;
1747
1748 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1749 tx_buffer->length = map_len;
1750 tx_buffer->dma = pci_map_single(adapter->pdev,
1751 skb->data, hdr_len, PCI_DMA_TODEVICE);
1752 mapped_len += map_len;
1753 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1754 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1755 ((cpu_to_le32(tx_buffer->length) &
1756 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1757 }
1758
1759 while (mapped_len < buf_len) {
1760 /* mapped_len == 0, means we should use the first tpd,
1761 which is given by caller */
1762 if (mapped_len == 0) {
1763 use_tpd = tpd;
1764 } else {
1765 use_tpd = atl1e_get_tpd(adapter);
1766 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1767 }
1768 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1769 tx_buffer->skb = NULL;
1770
1771 tx_buffer->length = map_len =
1772 ((buf_len - mapped_len) >= MAX_TX_BUF_LEN) ?
1773 MAX_TX_BUF_LEN : (buf_len - mapped_len);
1774 tx_buffer->dma =
1775 pci_map_single(adapter->pdev, skb->data + mapped_len,
1776 map_len, PCI_DMA_TODEVICE);
1777 mapped_len += map_len;
1778 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1779 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1780 ((cpu_to_le32(tx_buffer->length) &
1781 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1782 }
1783
1784 for (f = 0; f < nr_frags; f++) {
1785 struct skb_frag_struct *frag;
1786 u16 i;
1787 u16 seg_num;
1788
1789 frag = &skb_shinfo(skb)->frags[f];
1790 buf_len = frag->size;
1791
1792 seg_num = (buf_len + MAX_TX_BUF_LEN - 1) / MAX_TX_BUF_LEN;
1793 for (i = 0; i < seg_num; i++) {
1794 use_tpd = atl1e_get_tpd(adapter);
1795 memcpy(use_tpd, tpd, sizeof(struct atl1e_tpd_desc));
1796
1797 tx_buffer = atl1e_get_tx_buffer(adapter, use_tpd);
1798 if (tx_buffer->skb)
1799 BUG();
1800
1801 tx_buffer->skb = NULL;
1802 tx_buffer->length =
1803 (buf_len > MAX_TX_BUF_LEN) ?
1804 MAX_TX_BUF_LEN : buf_len;
1805 buf_len -= tx_buffer->length;
1806
1807 tx_buffer->dma =
1808 pci_map_page(adapter->pdev, frag->page,
1809 frag->page_offset +
1810 (i * MAX_TX_BUF_LEN),
1811 tx_buffer->length,
1812 PCI_DMA_TODEVICE);
1813 use_tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
1814 use_tpd->word2 = (use_tpd->word2 & (~TPD_BUFLEN_MASK)) |
1815 ((cpu_to_le32(tx_buffer->length) &
1816 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT);
1817 }
1818 }
1819
1820 if ((tpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK)
1821 /* note this one is a tcp header */
1822 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
1823 /* The last tpd */
1824
1825 use_tpd->word3 |= 1 << TPD_EOP_SHIFT;
1826 /* The last buffer info contain the skb address,
1827 so it will be free after unmap */
1828 tx_buffer->skb = skb;
1829}
1830
1831static void atl1e_tx_queue(struct atl1e_adapter *adapter, u16 count,
1832 struct atl1e_tpd_desc *tpd)
1833{
1834 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
1835 /* Force memory writes to complete before letting h/w
1836 * know there are new descriptors to fetch. (Only
1837 * applicable for weak-ordered memory model archs,
1838 * such as IA-64). */
1839 wmb();
1840 AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use);
1841}
1842
1843static int atl1e_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1844{
1845 struct atl1e_adapter *adapter = netdev_priv(netdev);
1846 unsigned long flags;
1847 u16 tpd_req = 1;
1848 struct atl1e_tpd_desc *tpd;
1849
1850 if (test_bit(__AT_DOWN, &adapter->flags)) {
1851 dev_kfree_skb_any(skb);
1852 return NETDEV_TX_OK;
1853 }
1854
1855 if (unlikely(skb->len <= 0)) {
1856 dev_kfree_skb_any(skb);
1857 return NETDEV_TX_OK;
1858 }
1859 tpd_req = atl1e_cal_tdp_req(skb);
1860 if (!spin_trylock_irqsave(&adapter->tx_lock, flags))
1861 return NETDEV_TX_LOCKED;
1862
1863 if (atl1e_tpd_avail(adapter) < tpd_req) {
1864 /* no enough descriptor, just stop queue */
1865 netif_stop_queue(netdev);
1866 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1867 return NETDEV_TX_BUSY;
1868 }
1869
1870 tpd = atl1e_get_tpd(adapter);
1871
1872 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1873 u16 vlan_tag = vlan_tx_tag_get(skb);
1874 u16 atl1e_vlan_tag;
1875
1876 tpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
1877 AT_VLAN_TAG_TO_TPD_TAG(vlan_tag, atl1e_vlan_tag);
1878 tpd->word2 |= (atl1e_vlan_tag & TPD_VLANTAG_MASK) <<
1879 TPD_VLAN_SHIFT;
1880 }
1881
1882 if (skb->protocol == ntohs(ETH_P_8021Q))
1883 tpd->word3 |= 1 << TPD_VL_TAGGED_SHIFT;
1884
1885 if (skb_network_offset(skb) != ETH_HLEN)
1886 tpd->word3 |= 1 << TPD_ETHTYPE_SHIFT; /* 802.3 frame */
1887
1888 /* do TSO and check sum */
1889 if (atl1e_tso_csum(adapter, skb, tpd) != 0) {
1890 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1891 dev_kfree_skb_any(skb);
1892 return NETDEV_TX_OK;
1893 }
1894
1895 atl1e_tx_map(adapter, skb, tpd);
1896 atl1e_tx_queue(adapter, tpd_req, tpd);
1897
1898 netdev->trans_start = jiffies;
1899 spin_unlock_irqrestore(&adapter->tx_lock, flags);
1900 return NETDEV_TX_OK;
1901}
1902
1903static void atl1e_free_irq(struct atl1e_adapter *adapter)
1904{
1905 struct net_device *netdev = adapter->netdev;
1906
1907 free_irq(adapter->pdev->irq, netdev);
1908
1909 if (adapter->have_msi)
1910 pci_disable_msi(adapter->pdev);
1911}
1912
1913static int atl1e_request_irq(struct atl1e_adapter *adapter)
1914{
1915 struct pci_dev *pdev = adapter->pdev;
1916 struct net_device *netdev = adapter->netdev;
1917 int flags = 0;
1918 int err = 0;
1919
1920 adapter->have_msi = true;
1921 err = pci_enable_msi(adapter->pdev);
1922 if (err) {
1923 dev_dbg(&pdev->dev,
1924 "Unable to allocate MSI interrupt Error: %d\n", err);
1925 adapter->have_msi = false;
1926 } else
1927 netdev->irq = pdev->irq;
1928
1929
1930 if (!adapter->have_msi)
1931 flags |= IRQF_SHARED;
1932 err = request_irq(adapter->pdev->irq, &atl1e_intr, flags,
1933 netdev->name, netdev);
1934 if (err) {
1935 dev_dbg(&pdev->dev,
1936 "Unable to allocate interrupt Error: %d\n", err);
1937 if (adapter->have_msi)
1938 pci_disable_msi(adapter->pdev);
1939 return err;
1940 }
1941 dev_dbg(&pdev->dev, "atl1e_request_irq OK\n");
1942 return err;
1943}
1944
1945int atl1e_up(struct atl1e_adapter *adapter)
1946{
1947 struct net_device *netdev = adapter->netdev;
1948 int err = 0;
1949 u32 val;
1950
1951 /* hardware has been reset, we need to reload some things */
1952 err = atl1e_init_hw(&adapter->hw);
1953 if (err) {
1954 err = -EIO;
1955 return err;
1956 }
1957 atl1e_init_ring_ptrs(adapter);
1958 atl1e_set_multi(netdev);
1959 atl1e_restore_vlan(adapter);
1960
1961 if (atl1e_configure(adapter)) {
1962 err = -EIO;
1963 goto err_up;
1964 }
1965
1966 clear_bit(__AT_DOWN, &adapter->flags);
1967 napi_enable(&adapter->napi);
1968 atl1e_irq_enable(adapter);
1969 val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1970 AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
1971 val | MASTER_CTRL_MANUAL_INT);
1972
1973err_up:
1974 return err;
1975}
1976
1977void atl1e_down(struct atl1e_adapter *adapter)
1978{
1979 struct net_device *netdev = adapter->netdev;
1980
1981 /* signal that we're down so the interrupt handler does not
1982 * reschedule our watchdog timer */
1983 set_bit(__AT_DOWN, &adapter->flags);
1984
1985#ifdef NETIF_F_LLTX
1986 netif_stop_queue(netdev);
1987#else
1988 netif_tx_disable(netdev);
1989#endif
1990
1991 /* reset MAC to disable all RX/TX */
1992 atl1e_reset_hw(&adapter->hw);
1993 msleep(1);
1994
1995 napi_disable(&adapter->napi);
1996 atl1e_del_timer(adapter);
1997 atl1e_irq_disable(adapter);
1998
1999 netif_carrier_off(netdev);
2000 adapter->link_speed = SPEED_0;
2001 adapter->link_duplex = -1;
2002 atl1e_clean_tx_ring(adapter);
2003 atl1e_clean_rx_ring(adapter);
2004}
2005
2006/*
2007 * atl1e_open - Called when a network interface is made active
2008 * @netdev: network interface device structure
2009 *
2010 * Returns 0 on success, negative value on failure
2011 *
2012 * The open entry point is called when a network interface is made
2013 * active by the system (IFF_UP). At this point all resources needed
2014 * for transmit and receive operations are allocated, the interrupt
2015 * handler is registered with the OS, the watchdog timer is started,
2016 * and the stack is notified that the interface is ready.
2017 */
2018static int atl1e_open(struct net_device *netdev)
2019{
2020 struct atl1e_adapter *adapter = netdev_priv(netdev);
2021 int err;
2022
2023 /* disallow open during test */
2024 if (test_bit(__AT_TESTING, &adapter->flags))
2025 return -EBUSY;
2026
2027 /* allocate rx/tx dma buffer & descriptors */
2028 atl1e_init_ring_resources(adapter);
2029 err = atl1e_setup_ring_resources(adapter);
2030 if (unlikely(err))
2031 return err;
2032
2033 err = atl1e_request_irq(adapter);
2034 if (unlikely(err))
2035 goto err_req_irq;
2036
2037 err = atl1e_up(adapter);
2038 if (unlikely(err))
2039 goto err_up;
2040
2041 return 0;
2042
2043err_up:
2044 atl1e_free_irq(adapter);
2045err_req_irq:
2046 atl1e_free_ring_resources(adapter);
2047 atl1e_reset_hw(&adapter->hw);
2048
2049 return err;
2050}
2051
2052/*
2053 * atl1e_close - Disables a network interface
2054 * @netdev: network interface device structure
2055 *
2056 * Returns 0, this is not allowed to fail
2057 *
2058 * The close entry point is called when an interface is de-activated
2059 * by the OS. The hardware is still under the drivers control, but
2060 * needs to be disabled. A global MAC reset is issued to stop the
2061 * hardware, and all transmit and receive resources are freed.
2062 */
2063static int atl1e_close(struct net_device *netdev)
2064{
2065 struct atl1e_adapter *adapter = netdev_priv(netdev);
2066
2067 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2068 atl1e_down(adapter);
2069 atl1e_free_irq(adapter);
2070 atl1e_free_ring_resources(adapter);
2071
2072 return 0;
2073}
2074
a6a53252
JY		 2075static int atl1e_suspend(struct pci_dev *pdev, pm_message_t state)
2076{
2077 struct net_device *netdev = pci_get_drvdata(pdev);
2078 struct atl1e_adapter *adapter = netdev_priv(netdev);
2079 struct atl1e_hw *hw = &adapter->hw;
2080 u32 ctrl = 0;
2081 u32 mac_ctrl_data = 0;
2082 u32 wol_ctrl_data = 0;
2083 u16 mii_advertise_data = 0;
2084 u16 mii_bmsr_data = 0;
2085 u16 mii_intr_status_data = 0;
2086 u32 wufc = adapter->wol;
2087 u32 i;
2088#ifdef CONFIG_PM
2089 int retval = 0;
2090#endif
2091
2092 if (netif_running(netdev)) {
2093 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2094 atl1e_down(adapter);
2095 }
2096 netif_device_detach(netdev);
2097
2098#ifdef CONFIG_PM
2099 retval = pci_save_state(pdev);
2100 if (retval)
2101 return retval;
2102#endif
2103
2104 if (wufc) {
2105 /* get link status */
2106 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2107 atl1e_read_phy_reg(hw, MII_BMSR, (u16 *)&mii_bmsr_data);
2108
2109 mii_advertise_data = MII_AR_10T_HD_CAPS;
2110
2111 if ((atl1e_write_phy_reg(hw, MII_AT001_CR, 0) != 0) ||
2112 (atl1e_write_phy_reg(hw,
2113 MII_ADVERTISE, mii_advertise_data) != 0) ||
2114 (atl1e_phy_commit(hw)) != 0) {
2115 dev_dbg(&pdev->dev, "set phy register failed\n");
2116 goto wol_dis;
2117 }
2118
2119 hw->phy_configured = false; /* re-init PHY when resume */
2120
2121 /* turn on magic packet wol */
2122 if (wufc & AT_WUFC_MAG)
2123 wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
2124
2125 if (wufc & AT_WUFC_LNKC) {
2126 /* if orignal link status is link, just wait for retrive link */
2127 if (mii_bmsr_data & BMSR_LSTATUS) {
2128 for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) {
2129 msleep(100);
2130 atl1e_read_phy_reg(hw, MII_BMSR,
2131 (u16 *)&mii_bmsr_data);
2132 if (mii_bmsr_data & BMSR_LSTATUS)
2133 break;
2134 }
2135
2136 if ((mii_bmsr_data & BMSR_LSTATUS) == 0)
2137 dev_dbg(&pdev->dev,
2138 "%s: Link may change"
2139 "when suspend\n",
2140 atl1e_driver_name);
2141 }
2142 wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
2143 /* only link up can wake up */
2144 if (atl1e_write_phy_reg(hw, MII_INT_CTRL, 0x400) != 0) {
2145 dev_dbg(&pdev->dev, "%s: read write phy "
2146 "register failed.\n",
2147 atl1e_driver_name);
2148 goto wol_dis;
2149 }
2150 }
2151 /* clear phy interrupt */
2152 atl1e_read_phy_reg(hw, MII_INT_STATUS, &mii_intr_status_data);
2153 /* Config MAC Ctrl register */
2154 mac_ctrl_data = MAC_CTRL_RX_EN;
2155 /* set to 10/100M halt duplex */
2156 mac_ctrl_data |= MAC_CTRL_SPEED_10_100 << MAC_CTRL_SPEED_SHIFT;
2157 mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
2158 MAC_CTRL_PRMLEN_MASK) <<
2159 MAC_CTRL_PRMLEN_SHIFT);
2160
2161 if (adapter->vlgrp)
2162 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
2163
2164 /* magic packet maybe Broadcast&multicast&Unicast frame */
2165 if (wufc & AT_WUFC_MAG)
2166 mac_ctrl_data |= MAC_CTRL_BC_EN;
2167
2168 dev_dbg(&pdev->dev,
2169 "%s: suspend MAC=0x%x\n",
2170 atl1e_driver_name, mac_ctrl_data);
2171
2172 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
2173 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2174 /* pcie patch */
2175 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2176 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2177 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2178 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
2179 goto suspend_exit;
2180 }
2181wol_dis:
2182
2183 /* WOL disabled */
2184 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
2185
2186 /* pcie patch */
2187 ctrl = AT_READ_REG(hw, REG_PCIE_PHYMISC);
2188 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2189 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
2190
2191 atl1e_force_ps(hw);
2192 hw->phy_configured = false; /* re-init PHY when resume */
2193
2194 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
2195
2196suspend_exit:
2197
2198 if (netif_running(netdev))
2199 atl1e_free_irq(adapter);
2200
2201 pci_disable_device(pdev);
2202
2203 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2204
2205 return 0;
2206}
2207
d6f8aa85 2208#ifdef CONFIG_PM
a6a53252
JY		 2209static int atl1e_resume(struct pci_dev *pdev)
2210{
2211 struct net_device *netdev = pci_get_drvdata(pdev);
2212 struct atl1e_adapter *adapter = netdev_priv(netdev);
2213 u32 err;
2214
2215 pci_set_power_state(pdev, PCI_D0);
2216 pci_restore_state(pdev);
2217
2218 err = pci_enable_device(pdev);
2219 if (err) {
2220 dev_err(&pdev->dev, "ATL1e: Cannot enable PCI"
2221 " device from suspend\n");
2222 return err;
2223 }
2224
2225 pci_set_master(pdev);
2226
2227 AT_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
2228
2229 pci_enable_wake(pdev, PCI_D3hot, 0);
2230 pci_enable_wake(pdev, PCI_D3cold, 0);
2231
2232 AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
2233
50f684b9 2234 if (netif_running(netdev)) {
a6a53252
JY		 2235 err = atl1e_request_irq(adapter);
2236 if (err)
2237 return err;
50f684b9 2238 }
a6a53252
JY		 2239
2240 atl1e_reset_hw(&adapter->hw);
2241
2242 if (netif_running(netdev))
2243 atl1e_up(adapter);
2244
2245 netif_device_attach(netdev);
2246
2247 return 0;
2248}
2249#endif
2250
2251static void atl1e_shutdown(struct pci_dev *pdev)
2252{
2253 atl1e_suspend(pdev, PMSG_SUSPEND);
2254}
2255
1e058ab5
SH		 2256static const struct net_device_ops atl1e_netdev_ops = {
2257 .ndo_open = atl1e_open,
2258 .ndo_stop = atl1e_close,
00829823 2259 .ndo_start_xmit = atl1e_xmit_frame,
1e058ab5
SH		 2260 .ndo_get_stats = atl1e_get_stats,
2261 .ndo_set_multicast_list = atl1e_set_multi,
2262 .ndo_validate_addr = eth_validate_addr,
2263 .ndo_set_mac_address = atl1e_set_mac_addr,
2264 .ndo_change_mtu = atl1e_change_mtu,
2265 .ndo_do_ioctl = atl1e_ioctl,
2266 .ndo_tx_timeout = atl1e_tx_timeout,
2267 .ndo_vlan_rx_register = atl1e_vlan_rx_register,
2268#ifdef CONFIG_NET_POLL_CONTROLLER
2269 .ndo_poll_controller = atl1e_netpoll,
2270#endif
2271
2272};
2273
a6a53252
JY		 2274static int atl1e_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
2275{
2276 SET_NETDEV_DEV(netdev, &pdev->dev);
2277 pci_set_drvdata(pdev, netdev);
2278
2279 netdev->irq = pdev->irq;
1e058ab5 2280 netdev->netdev_ops = &atl1e_netdev_ops;
00829823 2281
a6a53252 2282 netdev->watchdog_timeo = AT_TX_WATCHDOG;
a6a53252
JY		 2283 atl1e_set_ethtool_ops(netdev);
2284
2285 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM |
2286 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2287 netdev->features |= NETIF_F_LLTX;
2288 netdev->features |= NETIF_F_TSO;
2289 netdev->features |= NETIF_F_TSO6;
2290
2291 return 0;
2292}
2293
2294/*
2295 * atl1e_probe - Device Initialization Routine
2296 * @pdev: PCI device information struct
2297 * @ent: entry in atl1e_pci_tbl
2298 *
2299 * Returns 0 on success, negative on failure
2300 *
2301 * atl1e_probe initializes an adapter identified by a pci_dev structure.
2302 * The OS initialization, configuring of the adapter private structure,
2303 * and a hardware reset occur.
2304 */
2305static int __devinit atl1e_probe(struct pci_dev *pdev,
2306 const struct pci_device_id *ent)
2307{
2308 struct net_device *netdev;
2309 struct atl1e_adapter *adapter = NULL;
2310 static int cards_found;
2311
2312 int err = 0;
2313
2314 err = pci_enable_device(pdev);
2315 if (err) {
2316 dev_err(&pdev->dev, "cannot enable PCI device\n");
2317 return err;
2318 }
2319
2320 /*
2321 * The atl1e chip can DMA to 64-bit addresses, but it uses a single
2322 * shared register for the high 32 bits, so only a single, aligned,
2323 * 4 GB physical address range can be used at a time.
2324 *
2325 * Supporting 64-bit DMA on this hardware is more trouble than it's
2326 * worth. It is far easier to limit to 32-bit DMA than update
2327 * various kernel subsystems to support the mechanics required by a
2328 * fixed-high-32-bit system.
2329 */
2330 if ((pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) ||
2331 (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK) != 0)) {
2332 dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
2333 goto err_dma;
2334 }
2335
2336 err = pci_request_regions(pdev, atl1e_driver_name);
2337 if (err) {
2338 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
2339 goto err_pci_reg;
2340 }
2341
2342 pci_set_master(pdev);
2343
2344 netdev = alloc_etherdev(sizeof(struct atl1e_adapter));
2345 if (netdev == NULL) {
2346 err = -ENOMEM;
2347 dev_err(&pdev->dev, "etherdev alloc failed\n");
2348 goto err_alloc_etherdev;
2349 }
2350
2351 err = atl1e_init_netdev(netdev, pdev);
2352 if (err) {
2353 dev_err(&pdev->dev, "init netdevice failed\n");
2354 goto err_init_netdev;
2355 }
2356 adapter = netdev_priv(netdev);
2357 adapter->bd_number = cards_found;
2358 adapter->netdev = netdev;
2359 adapter->pdev = pdev;
2360 adapter->hw.adapter = adapter;
2361 adapter->hw.hw_addr = pci_iomap(pdev, BAR_0, 0);
2362 if (!adapter->hw.hw_addr) {
2363 err = -EIO;
2364 dev_err(&pdev->dev, "cannot map device registers\n");
2365 goto err_ioremap;
2366 }
2367 netdev->base_addr = (unsigned long)adapter->hw.hw_addr;
2368
2369 /* init mii data */
2370 adapter->mii.dev = netdev;
2371 adapter->mii.mdio_read = atl1e_mdio_read;
2372 adapter->mii.mdio_write = atl1e_mdio_write;
2373 adapter->mii.phy_id_mask = 0x1f;
2374 adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
2375
2376 netif_napi_add(netdev, &adapter->napi, atl1e_clean, 64);
2377
2378 init_timer(&adapter->phy_config_timer);
2379 adapter->phy_config_timer.function = &atl1e_phy_config;
2380 adapter->phy_config_timer.data = (unsigned long) adapter;
2381
2382 /* get user settings */
2383 atl1e_check_options(adapter);
2384 /*
2385 * Mark all PCI regions associated with PCI device
2386 * pdev as being reserved by owner atl1e_driver_name
2387 * Enables bus-mastering on the device and calls
2388 * pcibios_set_master to do the needed arch specific settings
2389 */
2390 atl1e_setup_pcicmd(pdev);
2391 /* setup the private structure */
2392 err = atl1e_sw_init(adapter);
2393 if (err) {
2394 dev_err(&pdev->dev, "net device private data init failed\n");
2395 goto err_sw_init;
2396 }
2397
2398 /* Init GPHY as early as possible due to power saving issue */
a6a53252 2399 atl1e_phy_init(&adapter->hw);
a6a53252
JY		 2400 /* reset the controller to
2401 * put the device in a known good starting state */
2402 err = atl1e_reset_hw(&adapter->hw);
2403 if (err) {
2404 err = -EIO;
2405 goto err_reset;
2406 }
2407
2408 if (atl1e_read_mac_addr(&adapter->hw) != 0) {
2409 err = -EIO;
2410 dev_err(&pdev->dev, "get mac address failed\n");
2411 goto err_eeprom;
2412 }
2413
2414 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2415 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
2416 dev_dbg(&pdev->dev, "mac address : %02x-%02x-%02x-%02x-%02x-%02x\n",
2417 adapter->hw.mac_addr[0], adapter->hw.mac_addr[1],
2418 adapter->hw.mac_addr[2], adapter->hw.mac_addr[3],
2419 adapter->hw.mac_addr[4], adapter->hw.mac_addr[5]);
2420
2421 INIT_WORK(&adapter->reset_task, atl1e_reset_task);
2422 INIT_WORK(&adapter->link_chg_task, atl1e_link_chg_task);
2423 err = register_netdev(netdev);
2424 if (err) {
2425 dev_err(&pdev->dev, "register netdevice failed\n");
2426 goto err_register;
2427 }
2428
2429 /* assume we have no link for now */
2430 netif_stop_queue(netdev);
2431 netif_carrier_off(netdev);
2432
2433 cards_found++;
2434
2435 return 0;
2436
2437err_reset:
2438err_register:
2439err_sw_init:
2440err_eeprom:
2441 iounmap(adapter->hw.hw_addr);
2442err_init_netdev:
2443err_ioremap:
2444 free_netdev(netdev);
2445err_alloc_etherdev:
2446 pci_release_regions(pdev);
2447err_pci_reg:
2448err_dma:
2449 pci_disable_device(pdev);
2450 return err;
2451}
2452
2453/*
2454 * atl1e_remove - Device Removal Routine
2455 * @pdev: PCI device information struct
2456 *
2457 * atl1e_remove is called by the PCI subsystem to alert the driver
2458 * that it should release a PCI device. The could be caused by a
2459 * Hot-Plug event, or because the driver is going to be removed from
2460 * memory.
2461 */
2462static void __devexit atl1e_remove(struct pci_dev *pdev)
2463{
2464 struct net_device *netdev = pci_get_drvdata(pdev);
2465 struct atl1e_adapter *adapter = netdev_priv(netdev);
2466
2467 /*
2468 * flush_scheduled work may reschedule our watchdog task, so
2469 * explicitly disable watchdog tasks from being rescheduled
2470 */
2471 set_bit(__AT_DOWN, &adapter->flags);
2472
2473 atl1e_del_timer(adapter);
2474 atl1e_cancel_work(adapter);
2475
2476 unregister_netdev(netdev);
2477 atl1e_free_ring_resources(adapter);
2478 atl1e_force_ps(&adapter->hw);
2479 iounmap(adapter->hw.hw_addr);
2480 pci_release_regions(pdev);
2481 free_netdev(netdev);
2482 pci_disable_device(pdev);
2483}
2484
2485/*
2486 * atl1e_io_error_detected - called when PCI error is detected
2487 * @pdev: Pointer to PCI device
2488 * @state: The current pci connection state
2489 *
2490 * This function is called after a PCI bus error affecting
2491 * this device has been detected.
2492 */
2493static pci_ers_result_t
2494atl1e_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2495{
2496 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 2497 struct atl1e_adapter *adapter = netdev_priv(netdev);
a6a53252
JY		 2498
2499 netif_device_detach(netdev);
2500
2501 if (netif_running(netdev))
2502 atl1e_down(adapter);
2503
2504 pci_disable_device(pdev);
2505
2506 /* Request a slot slot reset. */
2507 return PCI_ERS_RESULT_NEED_RESET;
2508}
2509
2510/*
2511 * atl1e_io_slot_reset - called after the pci bus has been reset.
2512 * @pdev: Pointer to PCI device
2513 *
2514 * Restart the card from scratch, as if from a cold-boot. Implementation
2515 * resembles the first-half of the e1000_resume routine.
2516 */
2517static pci_ers_result_t atl1e_io_slot_reset(struct pci_dev *pdev)
2518{
2519 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 2520 struct atl1e_adapter *adapter = netdev_priv(netdev);
a6a53252
JY		 2521
2522 if (pci_enable_device(pdev)) {
2523 dev_err(&pdev->dev,
2524 "ATL1e: Cannot re-enable PCI device after reset.\n");
2525 return PCI_ERS_RESULT_DISCONNECT;
2526 }
2527 pci_set_master(pdev);
2528
2529 pci_enable_wake(pdev, PCI_D3hot, 0);
2530 pci_enable_wake(pdev, PCI_D3cold, 0);
2531
2532 atl1e_reset_hw(&adapter->hw);
2533
2534 return PCI_ERS_RESULT_RECOVERED;
2535}
2536
2537/*
2538 * atl1e_io_resume - called when traffic can start flowing again.
2539 * @pdev: Pointer to PCI device
2540 *
2541 * This callback is called when the error recovery driver tells us that
2542 * its OK to resume normal operation. Implementation resembles the
2543 * second-half of the atl1e_resume routine.
2544 */
2545static void atl1e_io_resume(struct pci_dev *pdev)
2546{
2547 struct net_device *netdev = pci_get_drvdata(pdev);
454d7c9b 2548 struct atl1e_adapter *adapter = netdev_priv(netdev);
a6a53252
JY		 2549
2550 if (netif_running(netdev)) {
2551 if (atl1e_up(adapter)) {
2552 dev_err(&pdev->dev,
2553 "ATL1e: can't bring device back up after reset\n");
2554 return;
2555 }
2556 }
2557
2558 netif_device_attach(netdev);
2559}
2560
2561static struct pci_error_handlers atl1e_err_handler = {
2562 .error_detected = atl1e_io_error_detected,
2563 .slot_reset = atl1e_io_slot_reset,
2564 .resume = atl1e_io_resume,
2565};
2566
2567static struct pci_driver atl1e_driver = {
2568 .name = atl1e_driver_name,
2569 .id_table = atl1e_pci_tbl,
2570 .probe = atl1e_probe,
2571 .remove = __devexit_p(atl1e_remove),
2572 /* Power Managment Hooks */
2573#ifdef CONFIG_PM
2574 .suspend = atl1e_suspend,
2575 .resume = atl1e_resume,
2576#endif
2577 .shutdown = atl1e_shutdown,
2578 .err_handler = &atl1e_err_handler
2579};
2580
2581/*
2582 * atl1e_init_module - Driver Registration Routine
2583 *
2584 * atl1e_init_module is the first routine called when the driver is
2585 * loaded. All it does is register with the PCI subsystem.
2586 */
2587static int __init atl1e_init_module(void)
2588{
2589 return pci_register_driver(&atl1e_driver);
2590}
2591
2592/*
2593 * atl1e_exit_module - Driver Exit Cleanup Routine
2594 *
2595 * atl1e_exit_module is called just before the driver is removed
2596 * from memory.
2597 */
2598static void __exit atl1e_exit_module(void)
2599{
2600 pci_unregister_driver(&atl1e_driver);
2601}
2602
2603module_init(atl1e_init_module);
2604module_exit(atl1e_exit_module);
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