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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[net-next-2.6.git] / drivers / net / atl1c / atl1c_main.c
CommitLineData
43250ddd
JY		 1/*
2 * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "atl1c.h"
23
8f574b35 24#define ATL1C_DRV_VERSION "1.0.1.0-NAPI"
43250ddd
JY		 25char atl1c_driver_name[] = "atl1c";
26char atl1c_driver_version[] = ATL1C_DRV_VERSION;
27#define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
28#define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
496c185c
LR		 29#define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
30#define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
31#define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
8f574b35 32#define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
496c185c
LR		 33#define L2CB_V10 0xc0
34#define L2CB_V11 0xc1
35
43250ddd
JY		 36/*
37 * atl1c_pci_tbl - PCI Device ID Table
38 *
39 * Wildcard entries (PCI_ANY_ID) should come last
40 * Last entry must be all 0s
41 *
42 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
43 * Class, Class Mask, private data (not used) }
44 */
a3aa1884 45static DEFINE_PCI_DEVICE_TABLE(atl1c_pci_tbl) = {
43250ddd
JY		 46 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
47 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
496c185c
LR		 48 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
49 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
50 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
43250ddd
JY		 51 /* required last entry */
52 { 0 }
53};
54MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
55
56MODULE_AUTHOR("Jie Yang <jie.yang@atheros.com>");
57MODULE_DESCRIPTION("Atheros 1000M Ethernet Network Driver");
58MODULE_LICENSE("GPL");
59MODULE_VERSION(ATL1C_DRV_VERSION);
60
61static int atl1c_stop_mac(struct atl1c_hw *hw);
62static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw);
63static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw);
64static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
65static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup);
66static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter);
67static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
68 int *work_done, int work_to_do);
0fb1e54e 69static int atl1c_up(struct atl1c_adapter *adapter);
70static void atl1c_down(struct atl1c_adapter *adapter);
43250ddd
JY		 71
72static const u16 atl1c_pay_load_size[] = {
73 128, 256, 512, 1024, 2048, 4096,
74};
75
76static const u16 atl1c_rfd_prod_idx_regs[AT_MAX_RECEIVE_QUEUE] =
77{
78 REG_MB_RFD0_PROD_IDX,
79 REG_MB_RFD1_PROD_IDX,
80 REG_MB_RFD2_PROD_IDX,
81 REG_MB_RFD3_PROD_IDX
82};
83
84static const u16 atl1c_rfd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
85{
86 REG_RFD0_HEAD_ADDR_LO,
87 REG_RFD1_HEAD_ADDR_LO,
88 REG_RFD2_HEAD_ADDR_LO,
89 REG_RFD3_HEAD_ADDR_LO
90};
91
92static const u16 atl1c_rrd_addr_lo_regs[AT_MAX_RECEIVE_QUEUE] =
93{
94 REG_RRD0_HEAD_ADDR_LO,
95 REG_RRD1_HEAD_ADDR_LO,
96 REG_RRD2_HEAD_ADDR_LO,
97 REG_RRD3_HEAD_ADDR_LO
98};
99
100static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
101 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
8f574b35
JY		 102static void atl1c_pcie_patch(struct atl1c_hw *hw)
103{
104 u32 data;
43250ddd 105
8f574b35
JY		 106 AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
107 data |= PCIE_PHYMISC_FORCE_RCV_DET;
108 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
109
110 if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
111 AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
112
113 data &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK <<
114 PCIE_PHYMISC2_SERDES_CDR_SHIFT);
115 data |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT;
116 data &= ~(PCIE_PHYMISC2_SERDES_TH_MASK <<
117 PCIE_PHYMISC2_SERDES_TH_SHIFT);
118 data |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT;
119 AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
120 }
121}
122
123/* FIXME: no need any more ? */
43250ddd
JY		 124/*
125 * atl1c_init_pcie - init PCIE module
126 */
127static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
128{
129 u32 data;
130 u32 pci_cmd;
131 struct pci_dev *pdev = hw->adapter->pdev;
132
133 AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
134 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
135 pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
136 PCI_COMMAND_IO);
137 AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
138
139 /*
140 * Clear any PowerSaveing Settings
141 */
142 pci_enable_wake(pdev, PCI_D3hot, 0);
143 pci_enable_wake(pdev, PCI_D3cold, 0);
144
145 /*
146 * Mask some pcie error bits
147 */
148 AT_READ_REG(hw, REG_PCIE_UC_SEVERITY, &data);
149 data &= ~PCIE_UC_SERVRITY_DLP;
150 data &= ~PCIE_UC_SERVRITY_FCP;
151 AT_WRITE_REG(hw, REG_PCIE_UC_SEVERITY, data);
152
8f574b35
JY		 153 AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
154 data &= ~LTSSM_ID_EN_WRO;
155 AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
156
157 atl1c_pcie_patch(hw);
43250ddd
JY		 158 if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
159 atl1c_disable_l0s_l1(hw);
160 if (flag & ATL1C_PCIE_PHY_RESET)
161 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
162 else
163 AT_WRITE_REG(hw, REG_GPHY_CTRL,
164 GPHY_CTRL_DEFAULT | GPHY_CTRL_EXT_RESET);
165
8f574b35 166 msleep(5);
43250ddd
JY		 167}
168
169/*
170 * atl1c_irq_enable - Enable default interrupt generation settings
171 * @adapter: board private structure
172 */
173static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
174{
175 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
176 AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
177 AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
178 AT_WRITE_FLUSH(&adapter->hw);
179 }
180}
181
182/*
183 * atl1c_irq_disable - Mask off interrupt generation on the NIC
184 * @adapter: board private structure
185 */
186static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
187{
188 atomic_inc(&adapter->irq_sem);
189 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
8f574b35 190 AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
43250ddd
JY		 191 AT_WRITE_FLUSH(&adapter->hw);
192 synchronize_irq(adapter->pdev->irq);
193}
194
195/*
196 * atl1c_irq_reset - reset interrupt confiure on the NIC
197 * @adapter: board private structure
198 */
199static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
200{
201 atomic_set(&adapter->irq_sem, 1);
202 atl1c_irq_enable(adapter);
203}
204
c930a662
JP		 205/*
206 * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
207 * of the idle status register until the device is actually idle
208 */
209static u32 atl1c_wait_until_idle(struct atl1c_hw *hw)
210{
211 int timeout;
212 u32 data;
213
214 for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
215 AT_READ_REG(hw, REG_IDLE_STATUS, &data);
216 if ((data & IDLE_STATUS_MASK) == 0)
217 return 0;
218 msleep(1);
219 }
220 return data;
221}
222
43250ddd
JY		 223/*
224 * atl1c_phy_config - Timer Call-back
225 * @data: pointer to netdev cast into an unsigned long
226 */
227static void atl1c_phy_config(unsigned long data)
228{
229 struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
230 struct atl1c_hw *hw = &adapter->hw;
231 unsigned long flags;
232
233 spin_lock_irqsave(&adapter->mdio_lock, flags);
234 atl1c_restart_autoneg(hw);
235 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
236}
237
238void atl1c_reinit_locked(struct atl1c_adapter *adapter)
239{
43250ddd
JY		 240 WARN_ON(in_interrupt());
241 atl1c_down(adapter);
242 atl1c_up(adapter);
243 clear_bit(__AT_RESETTING, &adapter->flags);
244}
245
43250ddd
JY		 246static void atl1c_check_link_status(struct atl1c_adapter *adapter)
247{
248 struct atl1c_hw *hw = &adapter->hw;
249 struct net_device *netdev = adapter->netdev;
250 struct pci_dev *pdev = adapter->pdev;
251 int err;
252 unsigned long flags;
253 u16 speed, duplex, phy_data;
254
255 spin_lock_irqsave(&adapter->mdio_lock, flags);
256 /* MII_BMSR must read twise */
257 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
258 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
259 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
260
261 if ((phy_data & BMSR_LSTATUS) == 0) {
262 /* link down */
8f574b35
JY		 263 hw->hibernate = true;
264 if (atl1c_stop_mac(hw) != 0)
265 if (netif_msg_hw(adapter))
266 dev_warn(&pdev->dev, "stop mac failed\n");
267 atl1c_set_aspm(hw, false);
43250ddd 268 netif_carrier_off(netdev);
8f574b35
JY		 269 netif_stop_queue(netdev);
270 atl1c_phy_reset(hw);
271 atl1c_phy_init(&adapter->hw);
43250ddd
JY		 272 } else {
273 /* Link Up */
274 hw->hibernate = false;
275 spin_lock_irqsave(&adapter->mdio_lock, flags);
276 err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
277 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
278 if (unlikely(err))
279 return;
280 /* link result is our setting */
281 if (adapter->link_speed != speed ||
282 adapter->link_duplex != duplex) {
283 adapter->link_speed = speed;
284 adapter->link_duplex = duplex;
52fbc100 285 atl1c_set_aspm(hw, true);
43250ddd
JY		 286 atl1c_enable_tx_ctrl(hw);
287 atl1c_enable_rx_ctrl(hw);
288 atl1c_setup_mac_ctrl(adapter);
43250ddd
JY		 289 if (netif_msg_link(adapter))
290 dev_info(&pdev->dev,
291 "%s: %s NIC Link is Up<%d Mbps %s>\n",
292 atl1c_driver_name, netdev->name,
293 adapter->link_speed,
294 adapter->link_duplex == FULL_DUPLEX ?
295 "Full Duplex" : "Half Duplex");
296 }
297 if (!netif_carrier_ok(netdev))
298 netif_carrier_on(netdev);
299 }
300}
301
43250ddd
JY		 302static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
303{
304 struct net_device *netdev = adapter->netdev;
305 struct pci_dev *pdev = adapter->pdev;
306 u16 phy_data;
307 u16 link_up;
308
309 spin_lock(&adapter->mdio_lock);
310 atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
311 atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
312 spin_unlock(&adapter->mdio_lock);
313 link_up = phy_data & BMSR_LSTATUS;
314 /* notify upper layer link down ASAP */
315 if (!link_up) {
316 if (netif_carrier_ok(netdev)) {
317 /* old link state: Up */
318 netif_carrier_off(netdev);
319 if (netif_msg_link(adapter))
320 dev_info(&pdev->dev,
321 "%s: %s NIC Link is Down\n",
322 atl1c_driver_name, netdev->name);
323 adapter->link_speed = SPEED_0;
324 }
325 }
cb190546
JY		 326
327 adapter->work_event |= ATL1C_WORK_EVENT_LINK_CHANGE;
328 schedule_work(&adapter->common_task);
43250ddd
JY		 329}
330
cb190546 331static void atl1c_common_task(struct work_struct *work)
43250ddd 332{
cb190546
JY		 333 struct atl1c_adapter *adapter;
334 struct net_device *netdev;
335
336 adapter = container_of(work, struct atl1c_adapter, common_task);
337 netdev = adapter->netdev;
338
339 if (adapter->work_event & ATL1C_WORK_EVENT_RESET) {
8f574b35 340 adapter->work_event &= ~ATL1C_WORK_EVENT_RESET;
cb190546
JY		 341 netif_device_detach(netdev);
342 atl1c_down(adapter);
343 atl1c_up(adapter);
344 netif_device_attach(netdev);
345 return;
346 }
347
8f574b35
JY		 348 if (adapter->work_event & ATL1C_WORK_EVENT_LINK_CHANGE) {
349 adapter->work_event &= ~ATL1C_WORK_EVENT_LINK_CHANGE;
cb190546 350 atl1c_check_link_status(adapter);
8f574b35
JY		 351 }
352 return;
43250ddd
JY		 353}
354
cb190546
JY		 355
356static void atl1c_del_timer(struct atl1c_adapter *adapter)
43250ddd 357{
cb190546 358 del_timer_sync(&adapter->phy_config_timer);
43250ddd
JY		 359}
360
cb190546 361
43250ddd
JY		 362/*
363 * atl1c_tx_timeout - Respond to a Tx Hang
364 * @netdev: network interface device structure
365 */
366static void atl1c_tx_timeout(struct net_device *netdev)
367{
368 struct atl1c_adapter *adapter = netdev_priv(netdev);
369
370 /* Do the reset outside of interrupt context */
cb190546
JY		 371 adapter->work_event |= ATL1C_WORK_EVENT_RESET;
372 schedule_work(&adapter->common_task);
43250ddd
JY		 373}
374
375/*
376 * atl1c_set_multi - Multicast and Promiscuous mode set
377 * @netdev: network interface device structure
378 *
379 * The set_multi entry point is called whenever the multicast address
380 * list or the network interface flags are updated. This routine is
381 * responsible for configuring the hardware for proper multicast,
382 * promiscuous mode, and all-multi behavior.
383 */
384static void atl1c_set_multi(struct net_device *netdev)
385{
386 struct atl1c_adapter *adapter = netdev_priv(netdev);
387 struct atl1c_hw *hw = &adapter->hw;
22bedad3 388 struct netdev_hw_addr *ha;
43250ddd
JY		 389 u32 mac_ctrl_data;
390 u32 hash_value;
391
392 /* Check for Promiscuous and All Multicast modes */
393 AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
394
395 if (netdev->flags & IFF_PROMISC) {
396 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
397 } else if (netdev->flags & IFF_ALLMULTI) {
398 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
399 mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
400 } else {
401 mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
402 }
403
404 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
405
406 /* clear the old settings from the multicast hash table */
407 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
408 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
409
410 /* comoute mc addresses' hash value ,and put it into hash table */
22bedad3
JP		 411 netdev_for_each_mc_addr(ha, netdev) {
412 hash_value = atl1c_hash_mc_addr(hw, ha->addr);
43250ddd
JY		 413 atl1c_hash_set(hw, hash_value);
414 }
415}
416
417static void atl1c_vlan_rx_register(struct net_device *netdev,
418 struct vlan_group *grp)
419{
420 struct atl1c_adapter *adapter = netdev_priv(netdev);
421 struct pci_dev *pdev = adapter->pdev;
422 u32 mac_ctrl_data = 0;
423
424 if (netif_msg_pktdata(adapter))
425 dev_dbg(&pdev->dev, "atl1c_vlan_rx_register\n");
426
427 atl1c_irq_disable(adapter);
428
429 adapter->vlgrp = grp;
430 AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
431
432 if (grp) {
433 /* enable VLAN tag insert/strip */
434 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
435 } else {
436 /* disable VLAN tag insert/strip */
437 mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
438 }
439
440 AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
441 atl1c_irq_enable(adapter);
442}
443
444static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
445{
446 struct pci_dev *pdev = adapter->pdev;
447
448 if (netif_msg_pktdata(adapter))
449 dev_dbg(&pdev->dev, "atl1c_restore_vlan !");
450 atl1c_vlan_rx_register(adapter->netdev, adapter->vlgrp);
451}
452/*
453 * atl1c_set_mac - Change the Ethernet Address of the NIC
454 * @netdev: network interface device structure
455 * @p: pointer to an address structure
456 *
457 * Returns 0 on success, negative on failure
458 */
459static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
460{
461 struct atl1c_adapter *adapter = netdev_priv(netdev);
462 struct sockaddr *addr = p;
463
464 if (!is_valid_ether_addr(addr->sa_data))
465 return -EADDRNOTAVAIL;
466
467 if (netif_running(netdev))
468 return -EBUSY;
469
470 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
471 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
472
473 atl1c_hw_set_mac_addr(&adapter->hw);
474
475 return 0;
476}
477
478static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
479 struct net_device *dev)
480{
481 int mtu = dev->mtu;
482
483 adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
484 roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
485}
486/*
487 * atl1c_change_mtu - Change the Maximum Transfer Unit
488 * @netdev: network interface device structure
489 * @new_mtu: new value for maximum frame size
490 *
491 * Returns 0 on success, negative on failure
492 */
493static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
494{
495 struct atl1c_adapter *adapter = netdev_priv(netdev);
496 int old_mtu = netdev->mtu;
497 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
498
499 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
500 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
501 if (netif_msg_link(adapter))
502 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
503 return -EINVAL;
504 }
505 /* set MTU */
506 if (old_mtu != new_mtu && netif_running(netdev)) {
507 while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
508 msleep(1);
509 netdev->mtu = new_mtu;
510 adapter->hw.max_frame_size = new_mtu;
511 atl1c_set_rxbufsize(adapter, netdev);
8f574b35
JY		 512 if (new_mtu > MAX_TSO_FRAME_SIZE) {
513 adapter->netdev->features &= ~NETIF_F_TSO;
514 adapter->netdev->features &= ~NETIF_F_TSO6;
515 } else {
516 adapter->netdev->features |= NETIF_F_TSO;
517 adapter->netdev->features |= NETIF_F_TSO6;
518 }
43250ddd
JY		 519 atl1c_down(adapter);
520 atl1c_up(adapter);
521 clear_bit(__AT_RESETTING, &adapter->flags);
522 if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
523 u32 phy_data;
524
525 AT_READ_REG(&adapter->hw, 0x1414, &phy_data);
526 phy_data |= 0x10000000;
527 AT_WRITE_REG(&adapter->hw, 0x1414, phy_data);
528 }
529
530 }
531 return 0;
532}
533
534/*
535 * caller should hold mdio_lock
536 */
537static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
538{
539 struct atl1c_adapter *adapter = netdev_priv(netdev);
540 u16 result;
541
542 atl1c_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
543 return result;
544}
545
546static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
547 int reg_num, int val)
548{
549 struct atl1c_adapter *adapter = netdev_priv(netdev);
550
551 atl1c_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
552}
553
554/*
555 * atl1c_mii_ioctl -
556 * @netdev:
557 * @ifreq:
558 * @cmd:
559 */
560static int atl1c_mii_ioctl(struct net_device *netdev,
561 struct ifreq *ifr, int cmd)
562{
563 struct atl1c_adapter *adapter = netdev_priv(netdev);
564 struct pci_dev *pdev = adapter->pdev;
565 struct mii_ioctl_data *data = if_mii(ifr);
566 unsigned long flags;
567 int retval = 0;
568
569 if (!netif_running(netdev))
570 return -EINVAL;
571
572 spin_lock_irqsave(&adapter->mdio_lock, flags);
573 switch (cmd) {
574 case SIOCGMIIPHY:
575 data->phy_id = 0;
576 break;
577
578 case SIOCGMIIREG:
43250ddd
JY		 579 if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
580 &data->val_out)) {
581 retval = -EIO;
582 goto out;
583 }
584 break;
585
586 case SIOCSMIIREG:
43250ddd
JY		 587 if (data->reg_num & ~(0x1F)) {
588 retval = -EFAULT;
589 goto out;
590 }
591
592 dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
593 data->reg_num, data->val_in);
594 if (atl1c_write_phy_reg(&adapter->hw,
595 data->reg_num, data->val_in)) {
596 retval = -EIO;
597 goto out;
598 }
599 break;
600
601 default:
602 retval = -EOPNOTSUPP;
603 break;
604 }
605out:
606 spin_unlock_irqrestore(&adapter->mdio_lock, flags);
607 return retval;
608}
609
610/*
611 * atl1c_ioctl -
612 * @netdev:
613 * @ifreq:
614 * @cmd:
615 */
616static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
617{
618 switch (cmd) {
619 case SIOCGMIIPHY:
620 case SIOCGMIIREG:
621 case SIOCSMIIREG:
622 return atl1c_mii_ioctl(netdev, ifr, cmd);
623 default:
624 return -EOPNOTSUPP;
625 }
626}
627
628/*
629 * atl1c_alloc_queues - Allocate memory for all rings
630 * @adapter: board private structure to initialize
631 *
632 */
633static int __devinit atl1c_alloc_queues(struct atl1c_adapter *adapter)
634{
635 return 0;
636}
637
638static void atl1c_set_mac_type(struct atl1c_hw *hw)
639{
640 switch (hw->device_id) {
641 case PCI_DEVICE_ID_ATTANSIC_L2C:
642 hw->nic_type = athr_l2c;
643 break;
43250ddd
JY		 644 case PCI_DEVICE_ID_ATTANSIC_L1C:
645 hw->nic_type = athr_l1c;
646 break;
496c185c
LR		 647 case PCI_DEVICE_ID_ATHEROS_L2C_B:
648 hw->nic_type = athr_l2c_b;
649 break;
650 case PCI_DEVICE_ID_ATHEROS_L2C_B2:
651 hw->nic_type = athr_l2c_b2;
652 break;
653 case PCI_DEVICE_ID_ATHEROS_L1D:
654 hw->nic_type = athr_l1d;
655 break;
8f574b35
JY		 656 case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
657 hw->nic_type = athr_l1d_2;
658 break;
43250ddd
JY		 659 default:
660 break;
661 }
662}
663
664static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
665{
666 u32 phy_status_data;
667 u32 link_ctrl_data;
668
669 atl1c_set_mac_type(hw);
670 AT_READ_REG(hw, REG_PHY_STATUS, &phy_status_data);
671 AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
672
8f574b35 673 hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
43250ddd
JY		 674 ATL1C_TXQ_MODE_ENHANCE;
675 if (link_ctrl_data & LINK_CTRL_L0S_EN)
676 hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT;
677 if (link_ctrl_data & LINK_CTRL_L1_EN)
678 hw->ctrl_flags |= ATL1C_ASPM_L1_SUPPORT;
496c185c
LR		 679 if (link_ctrl_data & LINK_CTRL_EXT_SYNC)
680 hw->ctrl_flags |= ATL1C_LINK_EXT_SYNC;
8f574b35 681 hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
43250ddd 682
496c185c 683 if (hw->nic_type == athr_l1c ||
8f574b35
JY		 684 hw->nic_type == athr_l1d ||
685 hw->nic_type == athr_l1d_2)
496c185c 686 hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
43250ddd
JY		 687 return 0;
688}
689/*
690 * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
691 * @adapter: board private structure to initialize
692 *
693 * atl1c_sw_init initializes the Adapter private data structure.
694 * Fields are initialized based on PCI device information and
695 * OS network device settings (MTU size).
696 */
697static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
698{
699 struct atl1c_hw *hw = &adapter->hw;
700 struct pci_dev *pdev = adapter->pdev;
8f574b35
JY		 701 u32 revision;
702
43250ddd
JY		 703
704 adapter->wol = 0;
705 adapter->link_speed = SPEED_0;
706 adapter->link_duplex = FULL_DUPLEX;
707 adapter->num_rx_queues = AT_DEF_RECEIVE_QUEUE;
708 adapter->tpd_ring[0].count = 1024;
709 adapter->rfd_ring[0].count = 512;
710
711 hw->vendor_id = pdev->vendor;
712 hw->device_id = pdev->device;
713 hw->subsystem_vendor_id = pdev->subsystem_vendor;
714 hw->subsystem_id = pdev->subsystem_device;
8f574b35
JY		 715 AT_READ_REG(hw, PCI_CLASS_REVISION, &revision);
716 hw->revision_id = revision & 0xFF;
43250ddd
JY		 717 /* before link up, we assume hibernate is true */
718 hw->hibernate = true;
719 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
720 if (atl1c_setup_mac_funcs(hw) != 0) {
721 dev_err(&pdev->dev, "set mac function pointers failed\n");
722 return -1;
723 }
724 hw->intr_mask = IMR_NORMAL_MASK;
725 hw->phy_configured = false;
726 hw->preamble_len = 7;
727 hw->max_frame_size = adapter->netdev->mtu;
728 if (adapter->num_rx_queues < 2) {
729 hw->rss_type = atl1c_rss_disable;
730 hw->rss_mode = atl1c_rss_mode_disable;
731 } else {
732 hw->rss_type = atl1c_rss_ipv4;
733 hw->rss_mode = atl1c_rss_mul_que_mul_int;
734 hw->rss_hash_bits = 16;
735 }
736 hw->autoneg_advertised = ADVERTISED_Autoneg;
737 hw->indirect_tab = 0xE4E4E4E4;
738 hw->base_cpu = 0;
739
740 hw->ict = 50000; /* 100ms */
741 hw->smb_timer = 200000; /* 400ms */
742 hw->cmb_tpd = 4;
743 hw->cmb_tx_timer = 1; /* 2 us */
744 hw->rx_imt = 200;
745 hw->tx_imt = 1000;
746
747 hw->tpd_burst = 5;
748 hw->rfd_burst = 8;
749 hw->dma_order = atl1c_dma_ord_out;
750 hw->dmar_block = atl1c_dma_req_1024;
751 hw->dmaw_block = atl1c_dma_req_1024;
752 hw->dmar_dly_cnt = 15;
753 hw->dmaw_dly_cnt = 4;
754
755 if (atl1c_alloc_queues(adapter)) {
756 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
757 return -ENOMEM;
758 }
759 /* TODO */
760 atl1c_set_rxbufsize(adapter, adapter->netdev);
761 atomic_set(&adapter->irq_sem, 1);
762 spin_lock_init(&adapter->mdio_lock);
763 spin_lock_init(&adapter->tx_lock);
764 set_bit(__AT_DOWN, &adapter->flags);
765
766 return 0;
767}
768
c6060be4
JY		 769static inline void atl1c_clean_buffer(struct pci_dev *pdev,
770 struct atl1c_buffer *buffer_info, int in_irq)
771{
4b45e342 772 u16 pci_driection;
c6060be4
JY		 773 if (buffer_info->flags & ATL1C_BUFFER_FREE)
774 return;
775 if (buffer_info->dma) {
4b45e342
JY		 776 if (buffer_info->flags & ATL1C_PCIMAP_FROMDEVICE)
777 pci_driection = PCI_DMA_FROMDEVICE;
778 else
779 pci_driection = PCI_DMA_TODEVICE;
780
c6060be4
JY		 781 if (buffer_info->flags & ATL1C_PCIMAP_SINGLE)
782 pci_unmap_single(pdev, buffer_info->dma,
4b45e342 783 buffer_info->length, pci_driection);
c6060be4
JY		 784 else if (buffer_info->flags & ATL1C_PCIMAP_PAGE)
785 pci_unmap_page(pdev, buffer_info->dma,
4b45e342 786 buffer_info->length, pci_driection);
c6060be4
JY		 787 }
788 if (buffer_info->skb) {
789 if (in_irq)
790 dev_kfree_skb_irq(buffer_info->skb);
791 else
792 dev_kfree_skb(buffer_info->skb);
793 }
794 buffer_info->dma = 0;
795 buffer_info->skb = NULL;
796 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
797}
43250ddd
JY		 798/*
799 * atl1c_clean_tx_ring - Free Tx-skb
800 * @adapter: board private structure
801 */
802static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
803 enum atl1c_trans_queue type)
804{
805 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
806 struct atl1c_buffer *buffer_info;
807 struct pci_dev *pdev = adapter->pdev;
808 u16 index, ring_count;
809
810 ring_count = tpd_ring->count;
811 for (index = 0; index < ring_count; index++) {
812 buffer_info = &tpd_ring->buffer_info[index];
c6060be4 813 atl1c_clean_buffer(pdev, buffer_info, 0);
43250ddd
JY		 814 }
815
816 /* Zero out Tx-buffers */
817 memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
c6060be4 818 ring_count);
43250ddd
JY		 819 atomic_set(&tpd_ring->next_to_clean, 0);
820 tpd_ring->next_to_use = 0;
821}
822
823/*
824 * atl1c_clean_rx_ring - Free rx-reservation skbs
825 * @adapter: board private structure
826 */
827static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
828{
829 struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
830 struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
831 struct atl1c_buffer *buffer_info;
832 struct pci_dev *pdev = adapter->pdev;
833 int i, j;
834
835 for (i = 0; i < adapter->num_rx_queues; i++) {
836 for (j = 0; j < rfd_ring[i].count; j++) {
837 buffer_info = &rfd_ring[i].buffer_info[j];
c6060be4 838 atl1c_clean_buffer(pdev, buffer_info, 0);
43250ddd
JY		 839 }
840 /* zero out the descriptor ring */
841 memset(rfd_ring[i].desc, 0, rfd_ring[i].size);
842 rfd_ring[i].next_to_clean = 0;
843 rfd_ring[i].next_to_use = 0;
844 rrd_ring[i].next_to_use = 0;
845 rrd_ring[i].next_to_clean = 0;
846 }
847}
848
849/*
850 * Read / Write Ptr Initialize:
851 */
852static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
853{
854 struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
855 struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
856 struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
857 struct atl1c_buffer *buffer_info;
858 int i, j;
859
860 for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
861 tpd_ring[i].next_to_use = 0;
862 atomic_set(&tpd_ring[i].next_to_clean, 0);
863 buffer_info = tpd_ring[i].buffer_info;
864 for (j = 0; j < tpd_ring->count; j++)
c6060be4
JY		 865 ATL1C_SET_BUFFER_STATE(&buffer_info[i],
866 ATL1C_BUFFER_FREE);
43250ddd
JY		 867 }
868 for (i = 0; i < adapter->num_rx_queues; i++) {
869 rfd_ring[i].next_to_use = 0;
870 rfd_ring[i].next_to_clean = 0;
871 rrd_ring[i].next_to_use = 0;
872 rrd_ring[i].next_to_clean = 0;
873 for (j = 0; j < rfd_ring[i].count; j++) {
874 buffer_info = &rfd_ring[i].buffer_info[j];
c6060be4 875 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
43250ddd
JY		 876 }
877 }
878}
879
880/*
881 * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
882 * @adapter: board private structure
883 *
884 * Free all transmit software resources
885 */
886static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
887{
888 struct pci_dev *pdev = adapter->pdev;
889
890 pci_free_consistent(pdev, adapter->ring_header.size,
891 adapter->ring_header.desc,
892 adapter->ring_header.dma);
893 adapter->ring_header.desc = NULL;
894
895 /* Note: just free tdp_ring.buffer_info,
896 * it contain rfd_ring.buffer_info, do not double free */
897 if (adapter->tpd_ring[0].buffer_info) {
898 kfree(adapter->tpd_ring[0].buffer_info);
899 adapter->tpd_ring[0].buffer_info = NULL;
900 }
901}
902
903/*
904 * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
905 * @adapter: board private structure
906 *
907 * Return 0 on success, negative on failure
908 */
909static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
910{
911 struct pci_dev *pdev = adapter->pdev;
912 struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
913 struct atl1c_rfd_ring *rfd_ring = adapter->rfd_ring;
914 struct atl1c_rrd_ring *rrd_ring = adapter->rrd_ring;
915 struct atl1c_ring_header *ring_header = &adapter->ring_header;
916 int num_rx_queues = adapter->num_rx_queues;
917 int size;
918 int i;
919 int count = 0;
920 int rx_desc_count = 0;
921 u32 offset = 0;
922
923 rrd_ring[0].count = rfd_ring[0].count;
924 for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
925 tpd_ring[i].count = tpd_ring[0].count;
926
927 for (i = 1; i < adapter->num_rx_queues; i++)
928 rfd_ring[i].count = rrd_ring[i].count = rfd_ring[0].count;
929
930 /* 2 tpd queue, one high priority queue,
931 * another normal priority queue */
932 size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
933 rfd_ring->count * num_rx_queues);
934 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
935 if (unlikely(!tpd_ring->buffer_info)) {
936 dev_err(&pdev->dev, "kzalloc failed, size = %d\n",
937 size);
938 goto err_nomem;
939 }
940 for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
941 tpd_ring[i].buffer_info =
942 (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
943 count += tpd_ring[i].count;
944 }
945
946 for (i = 0; i < num_rx_queues; i++) {
947 rfd_ring[i].buffer_info =
948 (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
949 count += rfd_ring[i].count;
950 rx_desc_count += rfd_ring[i].count;
951 }
952 /*
953 * real ring DMA buffer
954 * each ring/block may need up to 8 bytes for alignment, hence the
955 * additional bytes tacked onto the end.
956 */
957 ring_header->size = size =
958 sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
959 sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
960 sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
961 sizeof(struct atl1c_hw_stats) +
962 8 * 4 + 8 * 2 * num_rx_queues;
963
964 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
965 &ring_header->dma);
966 if (unlikely(!ring_header->desc)) {
967 dev_err(&pdev->dev, "pci_alloc_consistend failed\n");
968 goto err_nomem;
969 }
970 memset(ring_header->desc, 0, ring_header->size);
971 /* init TPD ring */
972
973 tpd_ring[0].dma = roundup(ring_header->dma, 8);
974 offset = tpd_ring[0].dma - ring_header->dma;
975 for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
976 tpd_ring[i].dma = ring_header->dma + offset;
977 tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
978 tpd_ring[i].size =
979 sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
980 offset += roundup(tpd_ring[i].size, 8);
981 }
982 /* init RFD ring */
983 for (i = 0; i < num_rx_queues; i++) {
984 rfd_ring[i].dma = ring_header->dma + offset;
985 rfd_ring[i].desc = (u8 *) ring_header->desc + offset;
986 rfd_ring[i].size = sizeof(struct atl1c_rx_free_desc) *
987 rfd_ring[i].count;
988 offset += roundup(rfd_ring[i].size, 8);
989 }
990
991 /* init RRD ring */
992 for (i = 0; i < num_rx_queues; i++) {
993 rrd_ring[i].dma = ring_header->dma + offset;
994 rrd_ring[i].desc = (u8 *) ring_header->desc + offset;
995 rrd_ring[i].size = sizeof(struct atl1c_recv_ret_status) *
996 rrd_ring[i].count;
997 offset += roundup(rrd_ring[i].size, 8);
998 }
999
1000 adapter->smb.dma = ring_header->dma + offset;
1001 adapter->smb.smb = (u8 *)ring_header->desc + offset;
1002 return 0;
1003
1004err_nomem:
1005 kfree(tpd_ring->buffer_info);
1006 return -ENOMEM;
1007}
1008
1009static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
1010{
1011 struct atl1c_hw *hw = &adapter->hw;
1012 struct atl1c_rfd_ring *rfd_ring = (struct atl1c_rfd_ring *)
1013 adapter->rfd_ring;
1014 struct atl1c_rrd_ring *rrd_ring = (struct atl1c_rrd_ring *)
1015 adapter->rrd_ring;
1016 struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
1017 adapter->tpd_ring;
1018 struct atl1c_cmb *cmb = (struct atl1c_cmb *) &adapter->cmb;
1019 struct atl1c_smb *smb = (struct atl1c_smb *) &adapter->smb;
1020 int i;
8f574b35 1021 u32 data;
43250ddd
JY		 1022
1023 /* TPD */
1024 AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
1025 (u32)((tpd_ring[atl1c_trans_normal].dma &
1026 AT_DMA_HI_ADDR_MASK) >> 32));
1027 /* just enable normal priority TX queue */
1028 AT_WRITE_REG(hw, REG_NTPD_HEAD_ADDR_LO,
1029 (u32)(tpd_ring[atl1c_trans_normal].dma &
1030 AT_DMA_LO_ADDR_MASK));
1031 AT_WRITE_REG(hw, REG_HTPD_HEAD_ADDR_LO,
1032 (u32)(tpd_ring[atl1c_trans_high].dma &
1033 AT_DMA_LO_ADDR_MASK));
1034 AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
1035 (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
1036
1037
1038 /* RFD */
1039 AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
1040 (u32)((rfd_ring[0].dma & AT_DMA_HI_ADDR_MASK) >> 32));
1041 for (i = 0; i < adapter->num_rx_queues; i++)
1042 AT_WRITE_REG(hw, atl1c_rfd_addr_lo_regs[i],
1043 (u32)(rfd_ring[i].dma & AT_DMA_LO_ADDR_MASK));
1044
1045 AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
1046 rfd_ring[0].count & RFD_RING_SIZE_MASK);
1047 AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
1048 adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
1049
1050 /* RRD */
1051 for (i = 0; i < adapter->num_rx_queues; i++)
1052 AT_WRITE_REG(hw, atl1c_rrd_addr_lo_regs[i],
1053 (u32)(rrd_ring[i].dma & AT_DMA_LO_ADDR_MASK));
1054 AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
1055 (rrd_ring[0].count & RRD_RING_SIZE_MASK));
1056
1057 /* CMB */
1058 AT_WRITE_REG(hw, REG_CMB_BASE_ADDR_LO, cmb->dma & AT_DMA_LO_ADDR_MASK);
1059
1060 /* SMB */
1061 AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_HI,
1062 (u32)((smb->dma & AT_DMA_HI_ADDR_MASK) >> 32));
1063 AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_LO,
1064 (u32)(smb->dma & AT_DMA_LO_ADDR_MASK));
8f574b35
JY		 1065 if (hw->nic_type == athr_l2c_b) {
1066 AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
1067 AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
1068 AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
1069 AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
1070 AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
1071 AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
1072 AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
1073 AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
1074 }
1075 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d_2) {
1076 /* Power Saving for L2c_B */
1077 AT_READ_REG(hw, REG_SERDES_LOCK, &data);
1078 data |= SERDES_MAC_CLK_SLOWDOWN;
1079 data |= SERDES_PYH_CLK_SLOWDOWN;
1080 AT_WRITE_REG(hw, REG_SERDES_LOCK, data);
1081 }
43250ddd
JY		 1082 /* Load all of base address above */
1083 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
1084}
1085
1086static void atl1c_configure_tx(struct atl1c_adapter *adapter)
1087{
1088 struct atl1c_hw *hw = &adapter->hw;
1089 u32 dev_ctrl_data;
1090 u32 max_pay_load;
1091 u16 tx_offload_thresh;
1092 u32 txq_ctrl_data;
1093 u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
8f574b35 1094 u32 max_pay_load_data;
43250ddd
JY		 1095
1096 extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
1097 tx_offload_thresh = MAX_TX_OFFLOAD_THRESH;
1098 AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
1099 (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
1100 AT_READ_REG(hw, REG_DEVICE_CTRL, &dev_ctrl_data);
1101 max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT) &
1102 DEVICE_CTRL_MAX_PAYLOAD_MASK;
1103 hw->dmaw_block = min(max_pay_load, hw->dmaw_block);
1104 max_pay_load = (dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT) &
1105 DEVICE_CTRL_MAX_RREQ_SZ_MASK;
1106 hw->dmar_block = min(max_pay_load, hw->dmar_block);
1107
1108 txq_ctrl_data = (hw->tpd_burst & TXQ_NUM_TPD_BURST_MASK) <<
1109 TXQ_NUM_TPD_BURST_SHIFT;
1110 if (hw->ctrl_flags & ATL1C_TXQ_MODE_ENHANCE)
1111 txq_ctrl_data |= TXQ_CTRL_ENH_MODE;
8f574b35 1112 max_pay_load_data = (atl1c_pay_load_size[hw->dmar_block] &
43250ddd 1113 TXQ_TXF_BURST_NUM_MASK) << TXQ_TXF_BURST_NUM_SHIFT;
8f574b35
JY		 1114 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2)
1115 max_pay_load_data >>= 1;
1116 txq_ctrl_data |= max_pay_load_data;
43250ddd
JY		 1117
1118 AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
1119}
1120
1121static void atl1c_configure_rx(struct atl1c_adapter *adapter)
1122{
1123 struct atl1c_hw *hw = &adapter->hw;
1124 u32 rxq_ctrl_data;
1125
1126 rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
1127 RXQ_RFD_BURST_NUM_SHIFT;
1128
1129 if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
1130 rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
1131 if (hw->rss_type == atl1c_rss_ipv4)
1132 rxq_ctrl_data |= RSS_HASH_IPV4;
1133 if (hw->rss_type == atl1c_rss_ipv4_tcp)
1134 rxq_ctrl_data |= RSS_HASH_IPV4_TCP;
1135 if (hw->rss_type == atl1c_rss_ipv6)
1136 rxq_ctrl_data |= RSS_HASH_IPV6;
1137 if (hw->rss_type == atl1c_rss_ipv6_tcp)
1138 rxq_ctrl_data |= RSS_HASH_IPV6_TCP;
1139 if (hw->rss_type != atl1c_rss_disable)
1140 rxq_ctrl_data |= RRS_HASH_CTRL_EN;
1141
1142 rxq_ctrl_data |= (hw->rss_mode & RSS_MODE_MASK) <<
1143 RSS_MODE_SHIFT;
1144 rxq_ctrl_data |= (hw->rss_hash_bits & RSS_HASH_BITS_MASK) <<
1145 RSS_HASH_BITS_SHIFT;
1146 if (hw->ctrl_flags & ATL1C_ASPM_CTRL_MON)
8f574b35 1147 rxq_ctrl_data |= (ASPM_THRUPUT_LIMIT_1M &
43250ddd
JY		 1148 ASPM_THRUPUT_LIMIT_MASK) << ASPM_THRUPUT_LIMIT_SHIFT;
1149
1150 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1151}
1152
1153static void atl1c_configure_rss(struct atl1c_adapter *adapter)
1154{
1155 struct atl1c_hw *hw = &adapter->hw;
1156
1157 AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
1158 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
1159}
1160
1161static void atl1c_configure_dma(struct atl1c_adapter *adapter)
1162{
1163 struct atl1c_hw *hw = &adapter->hw;
1164 u32 dma_ctrl_data;
1165
1166 dma_ctrl_data = DMA_CTRL_DMAR_REQ_PRI;
1167 if (hw->ctrl_flags & ATL1C_CMB_ENABLE)
1168 dma_ctrl_data |= DMA_CTRL_CMB_EN;
1169 if (hw->ctrl_flags & ATL1C_SMB_ENABLE)
1170 dma_ctrl_data |= DMA_CTRL_SMB_EN;
1171 else
1172 dma_ctrl_data |= MAC_CTRL_SMB_DIS;
1173
1174 switch (hw->dma_order) {
1175 case atl1c_dma_ord_in:
1176 dma_ctrl_data |= DMA_CTRL_DMAR_IN_ORDER;
1177 break;
1178 case atl1c_dma_ord_enh:
1179 dma_ctrl_data |= DMA_CTRL_DMAR_ENH_ORDER;
1180 break;
1181 case atl1c_dma_ord_out:
1182 dma_ctrl_data |= DMA_CTRL_DMAR_OUT_ORDER;
1183 break;
1184 default:
1185 break;
1186 }
1187
1188 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1189 << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
1190 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1191 << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
1192 dma_ctrl_data |= (((u32)hw->dmar_dly_cnt) & DMA_CTRL_DMAR_DLY_CNT_MASK)
1193 << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
1194 dma_ctrl_data |= (((u32)hw->dmaw_dly_cnt) & DMA_CTRL_DMAW_DLY_CNT_MASK)
1195 << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
1196
1197 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1198}
1199
1200/*
1201 * Stop the mac, transmit and receive units
1202 * hw - Struct containing variables accessed by shared code
1203 * return : 0 or idle status (if error)
1204 */
1205static int atl1c_stop_mac(struct atl1c_hw *hw)
1206{
1207 u32 data;
43250ddd
JY		 1208
1209 AT_READ_REG(hw, REG_RXQ_CTRL, &data);
1210 data &= ~(RXQ1_CTRL_EN | RXQ2_CTRL_EN |
1211 RXQ3_CTRL_EN | RXQ_CTRL_EN);
1212 AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
1213
1214 AT_READ_REG(hw, REG_TXQ_CTRL, &data);
1215 data &= ~TXQ_CTRL_EN;
1216 AT_WRITE_REG(hw, REG_TWSI_CTRL, data);
1217
c930a662 1218 atl1c_wait_until_idle(hw);
43250ddd
JY		 1219
1220 AT_READ_REG(hw, REG_MAC_CTRL, &data);
1221 data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
1222 AT_WRITE_REG(hw, REG_MAC_CTRL, data);
1223
c930a662 1224 return (int)atl1c_wait_until_idle(hw);
43250ddd
JY		 1225}
1226
1227static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw)
1228{
1229 u32 data;
1230
1231 AT_READ_REG(hw, REG_RXQ_CTRL, &data);
1232 switch (hw->adapter->num_rx_queues) {
1233 case 4:
1234 data |= (RXQ3_CTRL_EN | RXQ2_CTRL_EN | RXQ1_CTRL_EN);
1235 break;
1236 case 3:
1237 data |= (RXQ2_CTRL_EN | RXQ1_CTRL_EN);
1238 break;
1239 case 2:
1240 data |= RXQ1_CTRL_EN;
1241 break;
1242 default:
1243 break;
1244 }
1245 data |= RXQ_CTRL_EN;
1246 AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
1247}
1248
1249static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw)
1250{
1251 u32 data;
1252
1253 AT_READ_REG(hw, REG_TXQ_CTRL, &data);
1254 data |= TXQ_CTRL_EN;
1255 AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
1256}
1257
1258/*
1259 * Reset the transmit and receive units; mask and clear all interrupts.
1260 * hw - Struct containing variables accessed by shared code
1261 * return : 0 or idle status (if error)
1262 */
1263static int atl1c_reset_mac(struct atl1c_hw *hw)
1264{
1265 struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
1266 struct pci_dev *pdev = adapter->pdev;
8f574b35 1267 u32 master_ctrl_data = 0;
43250ddd
JY		 1268
1269 AT_WRITE_REG(hw, REG_IMR, 0);
1270 AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT);
1271
8f574b35 1272 atl1c_stop_mac(hw);
43250ddd
JY		 1273 /*
1274 * Issue Soft Reset to the MAC. This will reset the chip's
1275 * transmit, receive, DMA. It will not effect
1276 * the current PCI configuration. The global reset bit is self-
1277 * clearing, and should clear within a microsecond.
1278 */
8f574b35
JY		 1279 AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
1280 master_ctrl_data |= MASTER_CTRL_OOB_DIS_OFF;
1281 AT_WRITE_REGW(hw, REG_MASTER_CTRL, ((master_ctrl_data | MASTER_CTRL_SOFT_RST)
1282 & 0xFFFF));
1283
43250ddd
JY		 1284 AT_WRITE_FLUSH(hw);
1285 msleep(10);
1286 /* Wait at least 10ms for All module to be Idle */
c930a662
JP		 1287
1288 if (atl1c_wait_until_idle(hw)) {
43250ddd 1289 dev_err(&pdev->dev,
c930a662 1290 "MAC state machine can't be idle since"
43250ddd
JY		 1291 " disabled for 10ms second\n");
1292 return -1;
1293 }
1294 return 0;
1295}
1296
1297static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
1298{
1299 u32 pm_ctrl_data;
1300
1301 AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
1302 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
1303 PM_CTRL_L1_ENTRY_TIMER_SHIFT);
1304 pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
1305 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1306 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1307 pm_ctrl_data &= ~PM_CTRL_MAC_ASPM_CHK;
1308 pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
1309
1310 pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
1311 pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
1312 pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
1313 AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
1314}
1315
1316/*
1317 * Set ASPM state.
1318 * Enable/disable L0s/L1 depend on link state.
1319 */
1320static void atl1c_set_aspm(struct atl1c_hw *hw, bool linkup)
1321{
1322 u32 pm_ctrl_data;
496c185c 1323 u32 link_ctrl_data;
8f574b35 1324 u32 link_l1_timer = 0xF;
43250ddd
JY		 1325
1326 AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
496c185c 1327 AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
496c185c 1328
8f574b35 1329 pm_ctrl_data &= ~PM_CTRL_SERDES_PD_EX_L1;
43250ddd
JY		 1330 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
1331 PM_CTRL_L1_ENTRY_TIMER_SHIFT);
496c185c 1332 pm_ctrl_data &= ~(PM_CTRL_LCKDET_TIMER_MASK <<
8f574b35
JY		 1333 PM_CTRL_LCKDET_TIMER_SHIFT);
1334 pm_ctrl_data |= AT_LCKDET_TIMER << PM_CTRL_LCKDET_TIMER_SHIFT;
496c185c 1335
8f574b35
JY		 1336 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
1337 hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
496c185c
LR		 1338 link_ctrl_data &= ~LINK_CTRL_EXT_SYNC;
1339 if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE)) {
8f574b35 1340 if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10)
496c185c
LR		 1341 link_ctrl_data |= LINK_CTRL_EXT_SYNC;
1342 }
1343
1344 AT_WRITE_REG(hw, REG_LINK_CTRL, link_ctrl_data);
1345
8f574b35
JY		 1346 pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER;
1347 pm_ctrl_data &= ~(PM_CTRL_PM_REQ_TIMER_MASK <<
1348 PM_CTRL_PM_REQ_TIMER_SHIFT);
1349 pm_ctrl_data |= AT_ASPM_L1_TIMER <<
1350 PM_CTRL_PM_REQ_TIMER_SHIFT;
496c185c
LR		 1351 pm_ctrl_data &= ~PM_CTRL_SA_DLY_EN;
1352 pm_ctrl_data &= ~PM_CTRL_HOTRST;
1353 pm_ctrl_data |= 1 << PM_CTRL_L1_ENTRY_TIMER_SHIFT;
1354 pm_ctrl_data |= PM_CTRL_SERDES_PD_EX_L1;
1355 }
8f574b35 1356 pm_ctrl_data |= PM_CTRL_MAC_ASPM_CHK;
43250ddd 1357 if (linkup) {
496c185c
LR		 1358 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1359 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1360 if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
1361 pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
1362 if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT)
1363 pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN;
1364
8f574b35
JY		 1365 if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
1366 hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
496c185c
LR		 1367 if (hw->nic_type == athr_l2c_b)
1368 if (!(hw->ctrl_flags & ATL1C_APS_MODE_ENABLE))
8f574b35 1369 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
496c185c
LR		 1370 pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
1371 pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
1372 pm_ctrl_data &= ~PM_CTRL_SERDES_BUDS_RX_L1_EN;
1373 pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
8f574b35
JY		 1374 if (hw->adapter->link_speed == SPEED_100 ||
1375 hw->adapter->link_speed == SPEED_1000) {
1376 pm_ctrl_data &= ~(PM_CTRL_L1_ENTRY_TIMER_MASK <<
1377 PM_CTRL_L1_ENTRY_TIMER_SHIFT);
1378 if (hw->nic_type == athr_l2c_b)
1379 link_l1_timer = 7;
1380 else if (hw->nic_type == athr_l2c_b2 ||
1381 hw->nic_type == athr_l1d_2)
1382 link_l1_timer = 4;
1383 pm_ctrl_data |= link_l1_timer <<
1384 PM_CTRL_L1_ENTRY_TIMER_SHIFT;
496c185c
LR		 1385 }
1386 } else {
1387 pm_ctrl_data |= PM_CTRL_SERDES_L1_EN;
1388 pm_ctrl_data |= PM_CTRL_SERDES_PLL_L1_EN;
1389 pm_ctrl_data |= PM_CTRL_SERDES_BUDS_RX_L1_EN;
1390 pm_ctrl_data &= ~PM_CTRL_CLK_SWH_L1;
1391 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1392 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
43250ddd 1393
8f574b35 1394 }
43250ddd 1395 } else {
52fbc100 1396 pm_ctrl_data &= ~PM_CTRL_SERDES_L1_EN;
43250ddd
JY		 1397 pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
1398 pm_ctrl_data &= ~PM_CTRL_SERDES_PLL_L1_EN;
43250ddd
JY		 1399 pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
1400
1401 if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
1402 pm_ctrl_data |= PM_CTRL_ASPM_L1_EN;
1403 else
1404 pm_ctrl_data &= ~PM_CTRL_ASPM_L1_EN;
1405 }
43250ddd 1406 AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
8f574b35
JY		 1407
1408 return;
43250ddd
JY		 1409}
1410
1411static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter)
1412{
1413 struct atl1c_hw *hw = &adapter->hw;
1414 struct net_device *netdev = adapter->netdev;
1415 u32 mac_ctrl_data;
1416
1417 mac_ctrl_data = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1418 mac_ctrl_data |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1419
1420 if (adapter->link_duplex == FULL_DUPLEX) {
1421 hw->mac_duplex = true;
1422 mac_ctrl_data |= MAC_CTRL_DUPLX;
1423 }
1424
1425 if (adapter->link_speed == SPEED_1000)
1426 hw->mac_speed = atl1c_mac_speed_1000;
1427 else
1428 hw->mac_speed = atl1c_mac_speed_10_100;
1429
1430 mac_ctrl_data |= (hw->mac_speed & MAC_CTRL_SPEED_MASK) <<
1431 MAC_CTRL_SPEED_SHIFT;
1432
1433 mac_ctrl_data |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1434 mac_ctrl_data |= ((hw->preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1435 MAC_CTRL_PRMLEN_SHIFT);
1436
1437 if (adapter->vlgrp)
1438 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
1439
1440 mac_ctrl_data |= MAC_CTRL_BC_EN;
1441 if (netdev->flags & IFF_PROMISC)
1442 mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
1443 if (netdev->flags & IFF_ALLMULTI)
1444 mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
1445
1446 mac_ctrl_data |= MAC_CTRL_SINGLE_PAUSE_EN;
8f574b35
JY		 1447 if (hw->nic_type == athr_l1d || hw->nic_type == athr_l2c_b2 ||
1448 hw->nic_type == athr_l1d_2) {
496c185c
LR		 1449 mac_ctrl_data |= MAC_CTRL_SPEED_MODE_SW;
1450 mac_ctrl_data |= MAC_CTRL_HASH_ALG_CRC32;
1451 }
43250ddd
JY		 1452 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
1453}
1454
1455/*
1456 * atl1c_configure - Configure Transmit&Receive Unit after Reset
1457 * @adapter: board private structure
1458 *
1459 * Configure the Tx /Rx unit of the MAC after a reset.
1460 */
1461static int atl1c_configure(struct atl1c_adapter *adapter)
1462{
1463 struct atl1c_hw *hw = &adapter->hw;
1464 u32 master_ctrl_data = 0;
1465 u32 intr_modrt_data;
8f574b35 1466 u32 data;
43250ddd
JY		 1467
1468 /* clear interrupt status */
1469 AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
1470 /* Clear any WOL status */
1471 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1472 /* set Interrupt Clear Timer
1473 * HW will enable self to assert interrupt event to system after
1474 * waiting x-time for software to notify it accept interrupt.
1475 */
8f574b35
JY		 1476
1477 data = CLK_GATING_EN_ALL;
1478 if (hw->ctrl_flags & ATL1C_CLK_GATING_EN) {
1479 if (hw->nic_type == athr_l2c_b)
1480 data &= ~CLK_GATING_RXMAC_EN;
1481 } else
1482 data = 0;
1483 AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
1484
43250ddd
JY		 1485 AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
1486 hw->ict & INT_RETRIG_TIMER_MASK);
1487
1488 atl1c_configure_des_ring(adapter);
1489
1490 if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
1491 intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
1492 IRQ_MODRT_TX_TIMER_SHIFT;
1493 intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
1494 IRQ_MODRT_RX_TIMER_SHIFT;
1495 AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
1496 master_ctrl_data |=
1497 MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
1498 }
1499
1500 if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
1501 master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
1502
8f574b35 1503 master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
43250ddd
JY		 1504 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
1505
1506 if (hw->ctrl_flags & ATL1C_CMB_ENABLE) {
1507 AT_WRITE_REG(hw, REG_CMB_TPD_THRESH,
1508 hw->cmb_tpd & CMB_TPD_THRESH_MASK);
1509 AT_WRITE_REG(hw, REG_CMB_TX_TIMER,
1510 hw->cmb_tx_timer & CMB_TX_TIMER_MASK);
1511 }
1512
1513 if (hw->ctrl_flags & ATL1C_SMB_ENABLE)
1514 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
1515 hw->smb_timer & SMB_STAT_TIMER_MASK);
1516 /* set MTU */
1517 AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1518 VLAN_HLEN + ETH_FCS_LEN);
1519 /* HDS, disable */
1520 AT_WRITE_REG(hw, REG_HDS_CTRL, 0);
1521
1522 atl1c_configure_tx(adapter);
1523 atl1c_configure_rx(adapter);
1524 atl1c_configure_rss(adapter);
1525 atl1c_configure_dma(adapter);
1526
1527 return 0;
1528}
1529
1530static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
1531{
1532 u16 hw_reg_addr = 0;
1533 unsigned long *stats_item = NULL;
1534 u32 data;
1535
1536 /* update rx status */
1537 hw_reg_addr = REG_MAC_RX_STATUS_BIN;
1538 stats_item = &adapter->hw_stats.rx_ok;
1539 while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
1540 AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
1541 *stats_item += data;
1542 stats_item++;
1543 hw_reg_addr += 4;
1544 }
1545/* update tx status */
1546 hw_reg_addr = REG_MAC_TX_STATUS_BIN;
1547 stats_item = &adapter->hw_stats.tx_ok;
1548 while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
1549 AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
1550 *stats_item += data;
1551 stats_item++;
1552 hw_reg_addr += 4;
1553 }
1554}
1555
1556/*
1557 * atl1c_get_stats - Get System Network Statistics
1558 * @netdev: network interface device structure
1559 *
1560 * Returns the address of the device statistics structure.
1561 * The statistics are actually updated from the timer callback.
1562 */
1563static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
1564{
1565 struct atl1c_adapter *adapter = netdev_priv(netdev);
1566 struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
a2c483a1 1567 struct net_device_stats *net_stats = &netdev->stats;
43250ddd
JY		 1568
1569 atl1c_update_hw_stats(adapter);
1570 net_stats->rx_packets = hw_stats->rx_ok;
1571 net_stats->tx_packets = hw_stats->tx_ok;
1572 net_stats->rx_bytes = hw_stats->rx_byte_cnt;
1573 net_stats->tx_bytes = hw_stats->tx_byte_cnt;
1574 net_stats->multicast = hw_stats->rx_mcast;
1575 net_stats->collisions = hw_stats->tx_1_col +
1576 hw_stats->tx_2_col * 2 +
1577 hw_stats->tx_late_col + hw_stats->tx_abort_col;
1578 net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
1579 hw_stats->rx_len_err + hw_stats->rx_sz_ov +
1580 hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
1581 net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
1582 net_stats->rx_length_errors = hw_stats->rx_len_err;
1583 net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
1584 net_stats->rx_frame_errors = hw_stats->rx_align_err;
1585 net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1586
1587 net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
1588
1589 net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
1590 hw_stats->tx_underrun + hw_stats->tx_trunc;
1591 net_stats->tx_fifo_errors = hw_stats->tx_underrun;
1592 net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
1593 net_stats->tx_window_errors = hw_stats->tx_late_col;
1594
a2c483a1 1595 return net_stats;
43250ddd
JY		 1596}
1597
1598static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
1599{
1600 u16 phy_data;
1601
1602 spin_lock(&adapter->mdio_lock);
1603 atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
1604 spin_unlock(&adapter->mdio_lock);
1605}
1606
1607static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
1608 enum atl1c_trans_queue type)
1609{
1610 struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
1611 &adapter->tpd_ring[type];
1612 struct atl1c_buffer *buffer_info;
c6060be4 1613 struct pci_dev *pdev = adapter->pdev;
43250ddd
JY		 1614 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
1615 u16 hw_next_to_clean;
1616 u16 shift;
1617 u32 data;
1618
1619 if (type == atl1c_trans_high)
1620 shift = MB_HTPD_CONS_IDX_SHIFT;
1621 else
1622 shift = MB_NTPD_CONS_IDX_SHIFT;
1623
1624 AT_READ_REG(&adapter->hw, REG_MB_PRIO_CONS_IDX, &data);
1625 hw_next_to_clean = (data >> shift) & MB_PRIO_PROD_IDX_MASK;
1626
1627 while (next_to_clean != hw_next_to_clean) {
1628 buffer_info = &tpd_ring->buffer_info[next_to_clean];
c6060be4 1629 atl1c_clean_buffer(pdev, buffer_info, 1);
43250ddd
JY		 1630 if (++next_to_clean == tpd_ring->count)
1631 next_to_clean = 0;
1632 atomic_set(&tpd_ring->next_to_clean, next_to_clean);
1633 }
1634
1635 if (netif_queue_stopped(adapter->netdev) &&
1636 netif_carrier_ok(adapter->netdev)) {
1637 netif_wake_queue(adapter->netdev);
1638 }
1639
1640 return true;
1641}
1642
1643/*
1644 * atl1c_intr - Interrupt Handler
1645 * @irq: interrupt number
1646 * @data: pointer to a network interface device structure
1647 * @pt_regs: CPU registers structure
1648 */
1649static irqreturn_t atl1c_intr(int irq, void *data)
1650{
1651 struct net_device *netdev = data;
1652 struct atl1c_adapter *adapter = netdev_priv(netdev);
1653 struct pci_dev *pdev = adapter->pdev;
1654 struct atl1c_hw *hw = &adapter->hw;
1655 int max_ints = AT_MAX_INT_WORK;
1656 int handled = IRQ_NONE;
1657 u32 status;
1658 u32 reg_data;
1659
1660 do {
1661 AT_READ_REG(hw, REG_ISR, &reg_data);
1662 status = reg_data & hw->intr_mask;
1663
1664 if (status == 0 || (status & ISR_DIS_INT) != 0) {
1665 if (max_ints != AT_MAX_INT_WORK)
1666 handled = IRQ_HANDLED;
1667 break;
1668 }
1669 /* link event */
1670 if (status & ISR_GPHY)
1671 atl1c_clear_phy_int(adapter);
1672 /* Ack ISR */
1673 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1674 if (status & ISR_RX_PKT) {
1675 if (likely(napi_schedule_prep(&adapter->napi))) {
1676 hw->intr_mask &= ~ISR_RX_PKT;
1677 AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
1678 __napi_schedule(&adapter->napi);
1679 }
1680 }
1681 if (status & ISR_TX_PKT)
1682 atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
1683
1684 handled = IRQ_HANDLED;
1685 /* check if PCIE PHY Link down */
1686 if (status & ISR_ERROR) {
1687 if (netif_msg_hw(adapter))
1688 dev_err(&pdev->dev,
1689 "atl1c hardware error (status = 0x%x)\n",
1690 status & ISR_ERROR);
1691 /* reset MAC */
cb190546
JY		 1692 adapter->work_event |= ATL1C_WORK_EVENT_RESET;
1693 schedule_work(&adapter->common_task);
8f574b35 1694 return IRQ_HANDLED;
43250ddd
JY		 1695 }
1696
1697 if (status & ISR_OVER)
1698 if (netif_msg_intr(adapter))
1699 dev_warn(&pdev->dev,
af901ca1 1700 "TX/RX overflow (status = 0x%x)\n",
43250ddd
JY		 1701 status & ISR_OVER);
1702
1703 /* link event */
1704 if (status & (ISR_GPHY | ISR_MANUAL)) {
a2c483a1 1705 netdev->stats.tx_carrier_errors++;
43250ddd
JY		 1706 atl1c_link_chg_event(adapter);
1707 break;
1708 }
1709
1710 } while (--max_ints > 0);
1711 /* re-enable Interrupt*/
1712 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1713 return handled;
1714}
1715
1716static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
1717 struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
1718{
1719 /*
1720 * The pid field in RRS in not correct sometimes, so we
1721 * cannot figure out if the packet is fragmented or not,
1722 * so we tell the KERNEL CHECKSUM_NONE
1723 */
bc8acf2c 1724 skb_checksum_none_assert(skb);
43250ddd
JY		 1725}
1726
1727static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter, const int ringid)
1728{
1729 struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[ringid];
1730 struct pci_dev *pdev = adapter->pdev;
1731 struct atl1c_buffer *buffer_info, *next_info;
1732 struct sk_buff *skb;
1733 void *vir_addr = NULL;
1734 u16 num_alloc = 0;
1735 u16 rfd_next_to_use, next_next;
1736 struct atl1c_rx_free_desc *rfd_desc;
1737
1738 next_next = rfd_next_to_use = rfd_ring->next_to_use;
1739 if (++next_next == rfd_ring->count)
1740 next_next = 0;
1741 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1742 next_info = &rfd_ring->buffer_info[next_next];
1743
c6060be4 1744 while (next_info->flags & ATL1C_BUFFER_FREE) {
43250ddd
JY		 1745 rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
1746
1747 skb = dev_alloc_skb(adapter->rx_buffer_len);
1748 if (unlikely(!skb)) {
1749 if (netif_msg_rx_err(adapter))
1750 dev_warn(&pdev->dev, "alloc rx buffer failed\n");
1751 break;
1752 }
1753
1754 /*
1755 * Make buffer alignment 2 beyond a 16 byte boundary
1756 * this will result in a 16 byte aligned IP header after
1757 * the 14 byte MAC header is removed
1758 */
1759 vir_addr = skb->data;
c6060be4 1760 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
43250ddd
JY		 1761 buffer_info->skb = skb;
1762 buffer_info->length = adapter->rx_buffer_len;
1763 buffer_info->dma = pci_map_single(pdev, vir_addr,
1764 buffer_info->length,
1765 PCI_DMA_FROMDEVICE);
4b45e342
JY		 1766 ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
1767 ATL1C_PCIMAP_FROMDEVICE);
43250ddd
JY		 1768 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1769 rfd_next_to_use = next_next;
1770 if (++next_next == rfd_ring->count)
1771 next_next = 0;
1772 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1773 next_info = &rfd_ring->buffer_info[next_next];
1774 num_alloc++;
1775 }
1776
1777 if (num_alloc) {
1778 /* TODO: update mailbox here */
1779 wmb();
1780 rfd_ring->next_to_use = rfd_next_to_use;
1781 AT_WRITE_REG(&adapter->hw, atl1c_rfd_prod_idx_regs[ringid],
1782 rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
1783 }
1784
1785 return num_alloc;
1786}
1787
1788static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
1789 struct atl1c_recv_ret_status *rrs, u16 num)
1790{
1791 u16 i;
1792 /* the relationship between rrd and rfd is one map one */
1793 for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
1794 rrd_ring->next_to_clean)) {
1795 rrs->word3 &= ~RRS_RXD_UPDATED;
1796 if (++rrd_ring->next_to_clean == rrd_ring->count)
1797 rrd_ring->next_to_clean = 0;
1798 }
1799}
1800
1801static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
1802 struct atl1c_recv_ret_status *rrs, u16 num)
1803{
1804 u16 i;
1805 u16 rfd_index;
1806 struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
1807
1808 rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
1809 RRS_RX_RFD_INDEX_MASK;
1810 for (i = 0; i < num; i++) {
1811 buffer_info[rfd_index].skb = NULL;
c6060be4
JY		 1812 ATL1C_SET_BUFFER_STATE(&buffer_info[rfd_index],
1813 ATL1C_BUFFER_FREE);
43250ddd
JY		 1814 if (++rfd_index == rfd_ring->count)
1815 rfd_index = 0;
1816 }
1817 rfd_ring->next_to_clean = rfd_index;
1818}
1819
1820static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter, u8 que,
1821 int *work_done, int work_to_do)
1822{
1823 u16 rfd_num, rfd_index;
1824 u16 count = 0;
1825 u16 length;
1826 struct pci_dev *pdev = adapter->pdev;
1827 struct net_device *netdev = adapter->netdev;
1828 struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring[que];
1829 struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring[que];
1830 struct sk_buff *skb;
1831 struct atl1c_recv_ret_status *rrs;
1832 struct atl1c_buffer *buffer_info;
1833
1834 while (1) {
1835 if (*work_done >= work_to_do)
1836 break;
1837 rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
1838 if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
1839 rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
1840 RRS_RX_RFD_CNT_MASK;
37b76c69 1841 if (unlikely(rfd_num != 1))
43250ddd
JY		 1842 /* TODO support mul rfd*/
1843 if (netif_msg_rx_err(adapter))
1844 dev_warn(&pdev->dev,
1845 "Multi rfd not support yet!\n");
1846 goto rrs_checked;
1847 } else {
1848 break;
1849 }
1850rrs_checked:
1851 atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
1852 if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
1853 atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
1854 if (netif_msg_rx_err(adapter))
1855 dev_warn(&pdev->dev,
1856 "wrong packet! rrs word3 is %x\n",
1857 rrs->word3);
1858 continue;
1859 }
1860
1861 length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
1862 RRS_PKT_SIZE_MASK);
1863 /* Good Receive */
1864 if (likely(rfd_num == 1)) {
1865 rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
1866 RRS_RX_RFD_INDEX_MASK;
1867 buffer_info = &rfd_ring->buffer_info[rfd_index];
1868 pci_unmap_single(pdev, buffer_info->dma,
1869 buffer_info->length, PCI_DMA_FROMDEVICE);
1870 skb = buffer_info->skb;
1871 } else {
1872 /* TODO */
1873 if (netif_msg_rx_err(adapter))
1874 dev_warn(&pdev->dev,
1875 "Multi rfd not support yet!\n");
1876 break;
1877 }
1878 atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
1879 skb_put(skb, length - ETH_FCS_LEN);
1880 skb->protocol = eth_type_trans(skb, netdev);
43250ddd
JY		 1881 atl1c_rx_checksum(adapter, skb, rrs);
1882 if (unlikely(adapter->vlgrp) && rrs->word3 & RRS_VLAN_INS) {
1883 u16 vlan;
1884
1885 AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
1886 vlan = le16_to_cpu(vlan);
1887 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, vlan);
1888 } else
1889 netif_receive_skb(skb);
1890
43250ddd
JY		 1891 (*work_done)++;
1892 count++;
1893 }
1894 if (count)
1895 atl1c_alloc_rx_buffer(adapter, que);
1896}
1897
1898/*
1899 * atl1c_clean - NAPI Rx polling callback
1900 * @adapter: board private structure
1901 */
1902static int atl1c_clean(struct napi_struct *napi, int budget)
1903{
1904 struct atl1c_adapter *adapter =
1905 container_of(napi, struct atl1c_adapter, napi);
1906 int work_done = 0;
1907
1908 /* Keep link state information with original netdev */
1909 if (!netif_carrier_ok(adapter->netdev))
1910 goto quit_polling;
1911 /* just enable one RXQ */
1912 atl1c_clean_rx_irq(adapter, 0, &work_done, budget);
1913
1914 if (work_done < budget) {
1915quit_polling:
1916 napi_complete(napi);
1917 adapter->hw.intr_mask |= ISR_RX_PKT;
1918 AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
1919 }
1920 return work_done;
1921}
1922
1923#ifdef CONFIG_NET_POLL_CONTROLLER
1924
1925/*
1926 * Polling 'interrupt' - used by things like netconsole to send skbs
1927 * without having to re-enable interrupts. It's not called while
1928 * the interrupt routine is executing.
1929 */
1930static void atl1c_netpoll(struct net_device *netdev)
1931{
1932 struct atl1c_adapter *adapter = netdev_priv(netdev);
1933
1934 disable_irq(adapter->pdev->irq);
1935 atl1c_intr(adapter->pdev->irq, netdev);
1936 enable_irq(adapter->pdev->irq);
1937}
1938#endif
1939
1940static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
1941{
1942 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
1943 u16 next_to_use = 0;
1944 u16 next_to_clean = 0;
1945
1946 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
1947 next_to_use = tpd_ring->next_to_use;
1948
1949 return (u16)(next_to_clean > next_to_use) ?
1950 (next_to_clean - next_to_use - 1) :
1951 (tpd_ring->count + next_to_clean - next_to_use - 1);
1952}
1953
1954/*
1955 * get next usable tpd
1956 * Note: should call atl1c_tdp_avail to make sure
1957 * there is enough tpd to use
1958 */
1959static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
1960 enum atl1c_trans_queue type)
1961{
1962 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
1963 struct atl1c_tpd_desc *tpd_desc;
1964 u16 next_to_use = 0;
1965
1966 next_to_use = tpd_ring->next_to_use;
1967 if (++tpd_ring->next_to_use == tpd_ring->count)
1968 tpd_ring->next_to_use = 0;
1969 tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
1970 memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
1971 return tpd_desc;
1972}
1973
1974static struct atl1c_buffer *
1975atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
1976{
1977 struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
1978
1979 return &tpd_ring->buffer_info[tpd -
1980 (struct atl1c_tpd_desc *)tpd_ring->desc];
1981}
1982
1983/* Calculate the transmit packet descript needed*/
1984static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
1985{
1986 u16 tpd_req;
1987 u16 proto_hdr_len = 0;
1988
1989 tpd_req = skb_shinfo(skb)->nr_frags + 1;
1990
1991 if (skb_is_gso(skb)) {
1992 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1993 if (proto_hdr_len < skb_headlen(skb))
1994 tpd_req++;
1995 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
1996 tpd_req++;
1997 }
1998 return tpd_req;
1999}
2000
2001static int atl1c_tso_csum(struct atl1c_adapter *adapter,
2002 struct sk_buff *skb,
2003 struct atl1c_tpd_desc **tpd,
2004 enum atl1c_trans_queue type)
2005{
2006 struct pci_dev *pdev = adapter->pdev;
2007 u8 hdr_len;
2008 u32 real_len;
2009 unsigned short offload_type;
2010 int err;
2011
2012 if (skb_is_gso(skb)) {
2013 if (skb_header_cloned(skb)) {
2014 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2015 if (unlikely(err))
2016 return -1;
2017 }
2018 offload_type = skb_shinfo(skb)->gso_type;
2019
2020 if (offload_type & SKB_GSO_TCPV4) {
2021 real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
2022 + ntohs(ip_hdr(skb)->tot_len));
2023
2024 if (real_len < skb->len)
2025 pskb_trim(skb, real_len);
2026
2027 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2028 if (unlikely(skb->len == hdr_len)) {
2029 /* only xsum need */
2030 if (netif_msg_tx_queued(adapter))
2031 dev_warn(&pdev->dev,
2032 "IPV4 tso with zero data??\n");
2033 goto check_sum;
2034 } else {
2035 ip_hdr(skb)->check = 0;
2036 tcp_hdr(skb)->check = ~csum_tcpudp_magic(
2037 ip_hdr(skb)->saddr,
2038 ip_hdr(skb)->daddr,
2039 0, IPPROTO_TCP, 0);
2040 (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
2041 }
2042 }
2043
2044 if (offload_type & SKB_GSO_TCPV6) {
2045 struct atl1c_tpd_ext_desc *etpd =
2046 *(struct atl1c_tpd_ext_desc **)(tpd);
2047
2048 memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
2049 *tpd = atl1c_get_tpd(adapter, type);
2050 ipv6_hdr(skb)->payload_len = 0;
2051 /* check payload == 0 byte ? */
2052 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2053 if (unlikely(skb->len == hdr_len)) {
2054 /* only xsum need */
2055 if (netif_msg_tx_queued(adapter))
2056 dev_warn(&pdev->dev,
2057 "IPV6 tso with zero data??\n");
2058 goto check_sum;
2059 } else
2060 tcp_hdr(skb)->check = ~csum_ipv6_magic(
2061 &ipv6_hdr(skb)->saddr,
2062 &ipv6_hdr(skb)->daddr,
2063 0, IPPROTO_TCP, 0);
2064 etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
2065 etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
2066 etpd->pkt_len = cpu_to_le32(skb->len);
2067 (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
2068 }
2069
2070 (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
2071 (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
2072 TPD_TCPHDR_OFFSET_SHIFT;
2073 (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
2074 TPD_MSS_SHIFT;
2075 return 0;
2076 }
2077
2078check_sum:
2079 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2080 u8 css, cso;
2081 cso = skb_transport_offset(skb);
2082
2083 if (unlikely(cso & 0x1)) {
2084 if (netif_msg_tx_err(adapter))
2085 dev_err(&adapter->pdev->dev,
2086 "payload offset should not an event number\n");
2087 return -1;
2088 } else {
2089 css = cso + skb->csum_offset;
2090
2091 (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
2092 TPD_PLOADOFFSET_SHIFT;
2093 (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
2094 TPD_CCSUM_OFFSET_SHIFT;
2095 (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
2096 }
2097 }
2098 return 0;
2099}
2100
2101static void atl1c_tx_map(struct atl1c_adapter *adapter,
2102 struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
2103 enum atl1c_trans_queue type)
2104{
2105 struct atl1c_tpd_desc *use_tpd = NULL;
2106 struct atl1c_buffer *buffer_info = NULL;
2107 u16 buf_len = skb_headlen(skb);
2108 u16 map_len = 0;
2109 u16 mapped_len = 0;
2110 u16 hdr_len = 0;
2111 u16 nr_frags;
2112 u16 f;
2113 int tso;
2114
2115 nr_frags = skb_shinfo(skb)->nr_frags;
2116 tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
2117 if (tso) {
2118 /* TSO */
2119 map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2120 use_tpd = tpd;
2121
2122 buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
2123 buffer_info->length = map_len;
2124 buffer_info->dma = pci_map_single(adapter->pdev,
2125 skb->data, hdr_len, PCI_DMA_TODEVICE);
c6060be4 2126 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
4b45e342
JY		 2127 ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
2128 ATL1C_PCIMAP_TODEVICE);
43250ddd
JY		 2129 mapped_len += map_len;
2130 use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2131 use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
2132 }
2133
2134 if (mapped_len < buf_len) {
2135 /* mapped_len == 0, means we should use the first tpd,
2136 which is given by caller */
2137 if (mapped_len == 0)
2138 use_tpd = tpd;
2139 else {
2140 use_tpd = atl1c_get_tpd(adapter, type);
43250ddd
JY		 2141 memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
2142 }
2143 buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
2144 buffer_info->length = buf_len - mapped_len;
2145 buffer_info->dma =
2146 pci_map_single(adapter->pdev, skb->data + mapped_len,
2147 buffer_info->length, PCI_DMA_TODEVICE);
c6060be4 2148 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
4b45e342
JY		 2149 ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
2150 ATL1C_PCIMAP_TODEVICE);
43250ddd
JY		 2151 use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2152 use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
2153 }
2154
2155 for (f = 0; f < nr_frags; f++) {
2156 struct skb_frag_struct *frag;
2157
2158 frag = &skb_shinfo(skb)->frags[f];
2159
2160 use_tpd = atl1c_get_tpd(adapter, type);
2161 memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
2162
2163 buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
2164 buffer_info->length = frag->size;
2165 buffer_info->dma =
2166 pci_map_page(adapter->pdev, frag->page,
2167 frag->page_offset,
2168 buffer_info->length,
2169 PCI_DMA_TODEVICE);
c6060be4 2170 ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
4b45e342
JY		 2171 ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_PAGE,
2172 ATL1C_PCIMAP_TODEVICE);
43250ddd
JY		 2173 use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2174 use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
2175 }
2176
2177 /* The last tpd */
2178 use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
2179 /* The last buffer info contain the skb address,
2180 so it will be free after unmap */
2181 buffer_info->skb = skb;
2182}
2183
2184static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
2185 struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
2186{
2187 struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
2188 u32 prod_data;
2189
2190 AT_READ_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, &prod_data);
2191 switch (type) {
2192 case atl1c_trans_high:
2193 prod_data &= 0xFFFF0000;
2194 prod_data |= tpd_ring->next_to_use & 0xFFFF;
2195 break;
2196 case atl1c_trans_normal:
2197 prod_data &= 0x0000FFFF;
2198 prod_data |= (tpd_ring->next_to_use & 0xFFFF) << 16;
2199 break;
2200 default:
2201 break;
2202 }
2203 wmb();
2204 AT_WRITE_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, prod_data);
2205}
2206
61357325
SH		 2207static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
2208 struct net_device *netdev)
43250ddd
JY		 2209{
2210 struct atl1c_adapter *adapter = netdev_priv(netdev);
2211 unsigned long flags;
2212 u16 tpd_req = 1;
2213 struct atl1c_tpd_desc *tpd;
2214 enum atl1c_trans_queue type = atl1c_trans_normal;
2215
2216 if (test_bit(__AT_DOWN, &adapter->flags)) {
2217 dev_kfree_skb_any(skb);
2218 return NETDEV_TX_OK;
2219 }
2220
2221 tpd_req = atl1c_cal_tpd_req(skb);
2222 if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
2223 if (netif_msg_pktdata(adapter))
2224 dev_info(&adapter->pdev->dev, "tx locked\n");
2225 return NETDEV_TX_LOCKED;
2226 }
2227 if (skb->mark == 0x01)
2228 type = atl1c_trans_high;
2229 else
2230 type = atl1c_trans_normal;
2231
2232 if (atl1c_tpd_avail(adapter, type) < tpd_req) {
2233 /* no enough descriptor, just stop queue */
2234 netif_stop_queue(netdev);
2235 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2236 return NETDEV_TX_BUSY;
2237 }
2238
2239 tpd = atl1c_get_tpd(adapter, type);
2240
2241 /* do TSO and check sum */
2242 if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
2243 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2244 dev_kfree_skb_any(skb);
2245 return NETDEV_TX_OK;
2246 }
2247
eab6d18d 2248 if (unlikely(vlan_tx_tag_present(skb))) {
43250ddd
JY		 2249 u16 vlan = vlan_tx_tag_get(skb);
2250 __le16 tag;
2251
2252 vlan = cpu_to_le16(vlan);
2253 AT_VLAN_TO_TAG(vlan, tag);
2254 tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
2255 tpd->vlan_tag = tag;
2256 }
2257
2258 if (skb_network_offset(skb) != ETH_HLEN)
2259 tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
2260
2261 atl1c_tx_map(adapter, skb, tpd, type);
2262 atl1c_tx_queue(adapter, skb, tpd, type);
2263
43250ddd
JY		 2264 spin_unlock_irqrestore(&adapter->tx_lock, flags);
2265 return NETDEV_TX_OK;
2266}
2267
2268static void atl1c_free_irq(struct atl1c_adapter *adapter)
2269{
2270 struct net_device *netdev = adapter->netdev;
2271
2272 free_irq(adapter->pdev->irq, netdev);
2273
2274 if (adapter->have_msi)
2275 pci_disable_msi(adapter->pdev);
2276}
2277
2278static int atl1c_request_irq(struct atl1c_adapter *adapter)
2279{
2280 struct pci_dev *pdev = adapter->pdev;
2281 struct net_device *netdev = adapter->netdev;
2282 int flags = 0;
2283 int err = 0;
2284
2285 adapter->have_msi = true;
2286 err = pci_enable_msi(adapter->pdev);
2287 if (err) {
2288 if (netif_msg_ifup(adapter))
2289 dev_err(&pdev->dev,
2290 "Unable to allocate MSI interrupt Error: %d\n",
2291 err);
2292 adapter->have_msi = false;
2293 } else
2294 netdev->irq = pdev->irq;
2295
2296 if (!adapter->have_msi)
2297 flags |= IRQF_SHARED;
9aff7e92 2298 err = request_irq(adapter->pdev->irq, atl1c_intr, flags,
43250ddd
JY		 2299 netdev->name, netdev);
2300 if (err) {
2301 if (netif_msg_ifup(adapter))
2302 dev_err(&pdev->dev,
2303 "Unable to allocate interrupt Error: %d\n",
2304 err);
2305 if (adapter->have_msi)
2306 pci_disable_msi(adapter->pdev);
2307 return err;
2308 }
2309 if (netif_msg_ifup(adapter))
2310 dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
2311 return err;
2312}
2313
0fb1e54e 2314static int atl1c_up(struct atl1c_adapter *adapter)
43250ddd
JY		 2315{
2316 struct net_device *netdev = adapter->netdev;
2317 int num;
2318 int err;
2319 int i;
2320
2321 netif_carrier_off(netdev);
2322 atl1c_init_ring_ptrs(adapter);
2323 atl1c_set_multi(netdev);
2324 atl1c_restore_vlan(adapter);
2325
2326 for (i = 0; i < adapter->num_rx_queues; i++) {
2327 num = atl1c_alloc_rx_buffer(adapter, i);
2328 if (unlikely(num == 0)) {
2329 err = -ENOMEM;
2330 goto err_alloc_rx;
2331 }
2332 }
2333
2334 if (atl1c_configure(adapter)) {
2335 err = -EIO;
2336 goto err_up;
2337 }
2338
2339 err = atl1c_request_irq(adapter);
2340 if (unlikely(err))
2341 goto err_up;
2342
2343 clear_bit(__AT_DOWN, &adapter->flags);
2344 napi_enable(&adapter->napi);
2345 atl1c_irq_enable(adapter);
2346 atl1c_check_link_status(adapter);
2347 netif_start_queue(netdev);
2348 return err;
2349
2350err_up:
2351err_alloc_rx:
2352 atl1c_clean_rx_ring(adapter);
2353 return err;
2354}
2355
0fb1e54e 2356static void atl1c_down(struct atl1c_adapter *adapter)
43250ddd
JY		 2357{
2358 struct net_device *netdev = adapter->netdev;
2359
2360 atl1c_del_timer(adapter);
cb190546 2361 adapter->work_event = 0; /* clear all event */
43250ddd
JY		 2362 /* signal that we're down so the interrupt handler does not
2363 * reschedule our watchdog timer */
2364 set_bit(__AT_DOWN, &adapter->flags);
2365 netif_carrier_off(netdev);
2366 napi_disable(&adapter->napi);
2367 atl1c_irq_disable(adapter);
2368 atl1c_free_irq(adapter);
43250ddd
JY		 2369 /* reset MAC to disable all RX/TX */
2370 atl1c_reset_mac(&adapter->hw);
2371 msleep(1);
2372
2373 adapter->link_speed = SPEED_0;
2374 adapter->link_duplex = -1;
2375 atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
2376 atl1c_clean_tx_ring(adapter, atl1c_trans_high);
2377 atl1c_clean_rx_ring(adapter);
2378}
2379
2380/*
2381 * atl1c_open - Called when a network interface is made active
2382 * @netdev: network interface device structure
2383 *
2384 * Returns 0 on success, negative value on failure
2385 *
2386 * The open entry point is called when a network interface is made
2387 * active by the system (IFF_UP). At this point all resources needed
2388 * for transmit and receive operations are allocated, the interrupt
2389 * handler is registered with the OS, the watchdog timer is started,
2390 * and the stack is notified that the interface is ready.
2391 */
2392static int atl1c_open(struct net_device *netdev)
2393{
2394 struct atl1c_adapter *adapter = netdev_priv(netdev);
2395 int err;
2396
2397 /* disallow open during test */
2398 if (test_bit(__AT_TESTING, &adapter->flags))
2399 return -EBUSY;
2400
2401 /* allocate rx/tx dma buffer & descriptors */
2402 err = atl1c_setup_ring_resources(adapter);
2403 if (unlikely(err))
2404 return err;
2405
2406 err = atl1c_up(adapter);
2407 if (unlikely(err))
2408 goto err_up;
2409
2410 if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
2411 u32 phy_data;
2412
2413 AT_READ_REG(&adapter->hw, REG_MDIO_CTRL, &phy_data);
2414 phy_data |= MDIO_AP_EN;
2415 AT_WRITE_REG(&adapter->hw, REG_MDIO_CTRL, phy_data);
2416 }
2417 return 0;
2418
2419err_up:
2420 atl1c_free_irq(adapter);
2421 atl1c_free_ring_resources(adapter);
2422 atl1c_reset_mac(&adapter->hw);
2423 return err;
2424}
2425
2426/*
2427 * atl1c_close - Disables a network interface
2428 * @netdev: network interface device structure
2429 *
2430 * Returns 0, this is not allowed to fail
2431 *
2432 * The close entry point is called when an interface is de-activated
2433 * by the OS. The hardware is still under the drivers control, but
2434 * needs to be disabled. A global MAC reset is issued to stop the
2435 * hardware, and all transmit and receive resources are freed.
2436 */
2437static int atl1c_close(struct net_device *netdev)
2438{
2439 struct atl1c_adapter *adapter = netdev_priv(netdev);
2440
2441 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2442 atl1c_down(adapter);
2443 atl1c_free_ring_resources(adapter);
2444 return 0;
2445}
2446
2447static int atl1c_suspend(struct pci_dev *pdev, pm_message_t state)
2448{
2449 struct net_device *netdev = pci_get_drvdata(pdev);
2450 struct atl1c_adapter *adapter = netdev_priv(netdev);
2451 struct atl1c_hw *hw = &adapter->hw;
8f574b35
JY		 2452 u32 mac_ctrl_data = 0;
2453 u32 master_ctrl_data = 0;
55865c66 2454 u32 wol_ctrl_data = 0;
8f574b35 2455 u16 mii_intr_status_data = 0;
43250ddd 2456 u32 wufc = adapter->wol;
43250ddd
JY		 2457 int retval = 0;
2458
8f574b35 2459 atl1c_disable_l0s_l1(hw);
43250ddd
JY		 2460 if (netif_running(netdev)) {
2461 WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
2462 atl1c_down(adapter);
2463 }
2464 netif_device_detach(netdev);
43250ddd
JY		 2465 retval = pci_save_state(pdev);
2466 if (retval)
2467 return retval;
8f574b35
JY		 2468
2469 if (wufc)
2470 if (atl1c_phy_power_saving(hw) != 0)
2471 dev_dbg(&pdev->dev, "phy power saving failed");
2472
2473 AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
2474 AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
2475
2476 master_ctrl_data &= ~MASTER_CTRL_CLK_SEL_DIS;
2477 mac_ctrl_data &= ~(MAC_CTRL_PRMLEN_MASK << MAC_CTRL_PRMLEN_SHIFT);
2478 mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
2479 MAC_CTRL_PRMLEN_MASK) <<
2480 MAC_CTRL_PRMLEN_SHIFT);
2481 mac_ctrl_data &= ~(MAC_CTRL_SPEED_MASK << MAC_CTRL_SPEED_SHIFT);
2482 mac_ctrl_data &= ~MAC_CTRL_DUPLX;
2483
43250ddd 2484 if (wufc) {
8f574b35
JY		 2485 mac_ctrl_data |= MAC_CTRL_RX_EN;
2486 if (adapter->link_speed == SPEED_1000 ||
2487 adapter->link_speed == SPEED_0) {
2488 mac_ctrl_data |= atl1c_mac_speed_1000 <<
2489 MAC_CTRL_SPEED_SHIFT;
2490 mac_ctrl_data |= MAC_CTRL_DUPLX;
2491 } else
2492 mac_ctrl_data |= atl1c_mac_speed_10_100 <<
2493 MAC_CTRL_SPEED_SHIFT;
2494
2495 if (adapter->link_duplex == DUPLEX_FULL)
2496 mac_ctrl_data |= MAC_CTRL_DUPLX;
2497
43250ddd
JY		 2498 /* turn on magic packet wol */
2499 if (wufc & AT_WUFC_MAG)
8f574b35 2500 wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
43250ddd
JY		 2501
2502 if (wufc & AT_WUFC_LNKC) {
43250ddd
JY		 2503 wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
2504 /* only link up can wake up */
2505 if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) {
8f574b35
JY		 2506 dev_dbg(&pdev->dev, "%s: read write phy "
2507 "register failed.\n",
2508 atl1c_driver_name);
43250ddd
JY		 2509 }
2510 }
2511 /* clear phy interrupt */
2512 atl1c_read_phy_reg(hw, MII_ISR, &mii_intr_status_data);
2513 /* Config MAC Ctrl register */
43250ddd
JY		 2514 if (adapter->vlgrp)
2515 mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
2516
2517 /* magic packet maybe Broadcast&multicast&Unicast frame */
2518 if (wufc & AT_WUFC_MAG)
2519 mac_ctrl_data |= MAC_CTRL_BC_EN;
2520
8f574b35
JY		 2521 dev_dbg(&pdev->dev,
2522 "%s: suspend MAC=0x%x\n",
2523 atl1c_driver_name, mac_ctrl_data);
43250ddd
JY		 2524 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
2525 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
2526 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2527
2528 /* pcie patch */
8f574b35 2529 device_set_wakeup_enable(&pdev->dev, 1);
43250ddd 2530
8f574b35
JY		 2531 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
2532 GPHY_CTRL_EXT_RESET);
2533 pci_prepare_to_sleep(pdev);
2534 } else {
2535 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_POWER_SAVING);
2536 master_ctrl_data |= MASTER_CTRL_CLK_SEL_DIS;
2537 mac_ctrl_data |= atl1c_mac_speed_10_100 << MAC_CTRL_SPEED_SHIFT;
2538 mac_ctrl_data |= MAC_CTRL_DUPLX;
2539 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
2540 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2541 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
2542 hw->phy_configured = false; /* re-init PHY when resume */
2543 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
43250ddd 2544 }
43250ddd
JY		 2545
2546 pci_disable_device(pdev);
2547 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2548
2549 return 0;
2550}
2551
2552static int atl1c_resume(struct pci_dev *pdev)
2553{
2554 struct net_device *netdev = pci_get_drvdata(pdev);
2555 struct atl1c_adapter *adapter = netdev_priv(netdev);
2556
2557 pci_set_power_state(pdev, PCI_D0);
2558 pci_restore_state(pdev);
2559 pci_enable_wake(pdev, PCI_D3hot, 0);
2560 pci_enable_wake(pdev, PCI_D3cold, 0);
2561
2562 AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
8f574b35
JY		 2563 atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
2564 ATL1C_PCIE_PHY_RESET);
43250ddd
JY		 2565
2566 atl1c_phy_reset(&adapter->hw);
2567 atl1c_reset_mac(&adapter->hw);
8f574b35
JY		 2568 atl1c_phy_init(&adapter->hw);
2569
2570#if 0
2571 AT_READ_REG(&adapter->hw, REG_PM_CTRLSTAT, &pm_data);
2572 pm_data &= ~PM_CTRLSTAT_PME_EN;
2573 AT_WRITE_REG(&adapter->hw, REG_PM_CTRLSTAT, pm_data);
2574#endif
2575
43250ddd
JY		 2576 netif_device_attach(netdev);
2577 if (netif_running(netdev))
2578 atl1c_up(adapter);
2579
2580 return 0;
2581}
2582
2583static void atl1c_shutdown(struct pci_dev *pdev)
2584{
2585 atl1c_suspend(pdev, PMSG_SUSPEND);
2586}
2587
2588static const struct net_device_ops atl1c_netdev_ops = {
2589 .ndo_open = atl1c_open,
2590 .ndo_stop = atl1c_close,
2591 .ndo_validate_addr = eth_validate_addr,
2592 .ndo_start_xmit = atl1c_xmit_frame,
2593 .ndo_set_mac_address = atl1c_set_mac_addr,
2594 .ndo_set_multicast_list = atl1c_set_multi,
2595 .ndo_change_mtu = atl1c_change_mtu,
2596 .ndo_do_ioctl = atl1c_ioctl,
2597 .ndo_tx_timeout = atl1c_tx_timeout,
2598 .ndo_get_stats = atl1c_get_stats,
2599 .ndo_vlan_rx_register = atl1c_vlan_rx_register,
2600#ifdef CONFIG_NET_POLL_CONTROLLER
2601 .ndo_poll_controller = atl1c_netpoll,
2602#endif
2603};
2604
2605static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
2606{
2607 SET_NETDEV_DEV(netdev, &pdev->dev);
2608 pci_set_drvdata(pdev, netdev);
2609
2610 netdev->irq = pdev->irq;
2611 netdev->netdev_ops = &atl1c_netdev_ops;
2612 netdev->watchdog_timeo = AT_TX_WATCHDOG;
2613 atl1c_set_ethtool_ops(netdev);
2614
2615 /* TODO: add when ready */
2616 netdev->features = NETIF_F_SG |
2617 NETIF_F_HW_CSUM |
2618 NETIF_F_HW_VLAN_TX |
2619 NETIF_F_HW_VLAN_RX |
2620 NETIF_F_TSO |
2621 NETIF_F_TSO6;
2622 return 0;
2623}
2624
2625/*
2626 * atl1c_probe - Device Initialization Routine
2627 * @pdev: PCI device information struct
2628 * @ent: entry in atl1c_pci_tbl
2629 *
2630 * Returns 0 on success, negative on failure
2631 *
2632 * atl1c_probe initializes an adapter identified by a pci_dev structure.
2633 * The OS initialization, configuring of the adapter private structure,
2634 * and a hardware reset occur.
2635 */
2636static int __devinit atl1c_probe(struct pci_dev *pdev,
2637 const struct pci_device_id *ent)
2638{
2639 struct net_device *netdev;
2640 struct atl1c_adapter *adapter;
2641 static int cards_found;
2642
2643 int err = 0;
2644
2645 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2646 err = pci_enable_device_mem(pdev);
2647 if (err) {
2648 dev_err(&pdev->dev, "cannot enable PCI device\n");
2649 return err;
2650 }
2651
2652 /*
2653 * The atl1c chip can DMA to 64-bit addresses, but it uses a single
2654 * shared register for the high 32 bits, so only a single, aligned,
2655 * 4 GB physical address range can be used at a time.
2656 *
2657 * Supporting 64-bit DMA on this hardware is more trouble than it's
2658 * worth. It is far easier to limit to 32-bit DMA than update
2659 * various kernel subsystems to support the mechanics required by a
2660 * fixed-high-32-bit system.
2661 */
e930438c
YH		 2662 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
2663 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
43250ddd
JY		 2664 dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
2665 goto err_dma;
2666 }
2667
2668 err = pci_request_regions(pdev, atl1c_driver_name);
2669 if (err) {
2670 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
2671 goto err_pci_reg;
2672 }
2673
2674 pci_set_master(pdev);
2675
2676 netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
2677 if (netdev == NULL) {
2678 err = -ENOMEM;
2679 dev_err(&pdev->dev, "etherdev alloc failed\n");
2680 goto err_alloc_etherdev;
2681 }
2682
2683 err = atl1c_init_netdev(netdev, pdev);
2684 if (err) {
2685 dev_err(&pdev->dev, "init netdevice failed\n");
2686 goto err_init_netdev;
2687 }
2688 adapter = netdev_priv(netdev);
2689 adapter->bd_number = cards_found;
2690 adapter->netdev = netdev;
2691 adapter->pdev = pdev;
2692 adapter->hw.adapter = adapter;
2693 adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
2694 adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
2695 if (!adapter->hw.hw_addr) {
2696 err = -EIO;
2697 dev_err(&pdev->dev, "cannot map device registers\n");
2698 goto err_ioremap;
2699 }
2700 netdev->base_addr = (unsigned long)adapter->hw.hw_addr;
2701
2702 /* init mii data */
2703 adapter->mii.dev = netdev;
2704 adapter->mii.mdio_read = atl1c_mdio_read;
2705 adapter->mii.mdio_write = atl1c_mdio_write;
2706 adapter->mii.phy_id_mask = 0x1f;
2707 adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
2708 netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
2709 setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
2710 (unsigned long)adapter);
2711 /* setup the private structure */
2712 err = atl1c_sw_init(adapter);
2713 if (err) {
2714 dev_err(&pdev->dev, "net device private data init failed\n");
2715 goto err_sw_init;
2716 }
2717 atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
2718 ATL1C_PCIE_PHY_RESET);
2719
2720 /* Init GPHY as early as possible due to power saving issue */
2721 atl1c_phy_reset(&adapter->hw);
2722
2723 err = atl1c_reset_mac(&adapter->hw);
2724 if (err) {
2725 err = -EIO;
2726 goto err_reset;
2727 }
2728
2729 device_init_wakeup(&pdev->dev, 1);
2730 /* reset the controller to
2731 * put the device in a known good starting state */
2732 err = atl1c_phy_init(&adapter->hw);
2733 if (err) {
2734 err = -EIO;
2735 goto err_reset;
2736 }
2737 if (atl1c_read_mac_addr(&adapter->hw) != 0) {
2738 err = -EIO;
2739 dev_err(&pdev->dev, "get mac address failed\n");
2740 goto err_eeprom;
2741 }
2742 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
2743 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
2744 if (netif_msg_probe(adapter))
82991172 2745 dev_dbg(&pdev->dev, "mac address : %pM\n",
2746 adapter->hw.mac_addr);
43250ddd
JY		 2747
2748 atl1c_hw_set_mac_addr(&adapter->hw);
cb190546
JY		 2749 INIT_WORK(&adapter->common_task, atl1c_common_task);
2750 adapter->work_event = 0;
43250ddd
JY		 2751 err = register_netdev(netdev);
2752 if (err) {
2753 dev_err(&pdev->dev, "register netdevice failed\n");
2754 goto err_register;
2755 }
2756
2757 if (netif_msg_probe(adapter))
2758 dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
2759 cards_found++;
2760 return 0;
2761
2762err_reset:
2763err_register:
2764err_sw_init:
2765err_eeprom:
2766 iounmap(adapter->hw.hw_addr);
2767err_init_netdev:
2768err_ioremap:
2769 free_netdev(netdev);
2770err_alloc_etherdev:
2771 pci_release_regions(pdev);
2772err_pci_reg:
2773err_dma:
2774 pci_disable_device(pdev);
2775 return err;
2776}
2777
2778/*
2779 * atl1c_remove - Device Removal Routine
2780 * @pdev: PCI device information struct
2781 *
2782 * atl1c_remove is called by the PCI subsystem to alert the driver
2783 * that it should release a PCI device. The could be caused by a
2784 * Hot-Plug event, or because the driver is going to be removed from
2785 * memory.
2786 */
2787static void __devexit atl1c_remove(struct pci_dev *pdev)
2788{
2789 struct net_device *netdev = pci_get_drvdata(pdev);
2790 struct atl1c_adapter *adapter = netdev_priv(netdev);
2791
2792 unregister_netdev(netdev);
2793 atl1c_phy_disable(&adapter->hw);
2794
2795 iounmap(adapter->hw.hw_addr);
2796
2797 pci_release_regions(pdev);
2798 pci_disable_device(pdev);
2799 free_netdev(netdev);
2800}
2801
2802/*
2803 * atl1c_io_error_detected - called when PCI error is detected
2804 * @pdev: Pointer to PCI device
2805 * @state: The current pci connection state
2806 *
2807 * This function is called after a PCI bus error affecting
2808 * this device has been detected.
2809 */
2810static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
2811 pci_channel_state_t state)
2812{
2813 struct net_device *netdev = pci_get_drvdata(pdev);
2814 struct atl1c_adapter *adapter = netdev_priv(netdev);
2815
2816 netif_device_detach(netdev);
2817
005fb4f0
DN		 2818 if (state == pci_channel_io_perm_failure)
2819 return PCI_ERS_RESULT_DISCONNECT;
2820
43250ddd
JY		 2821 if (netif_running(netdev))
2822 atl1c_down(adapter);
2823
2824 pci_disable_device(pdev);
2825
2826 /* Request a slot slot reset. */
2827 return PCI_ERS_RESULT_NEED_RESET;
2828}
2829
2830/*
2831 * atl1c_io_slot_reset - called after the pci bus has been reset.
2832 * @pdev: Pointer to PCI device
2833 *
2834 * Restart the card from scratch, as if from a cold-boot. Implementation
2835 * resembles the first-half of the e1000_resume routine.
2836 */
2837static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
2838{
2839 struct net_device *netdev = pci_get_drvdata(pdev);
2840 struct atl1c_adapter *adapter = netdev_priv(netdev);
2841
2842 if (pci_enable_device(pdev)) {
2843 if (netif_msg_hw(adapter))
2844 dev_err(&pdev->dev,
2845 "Cannot re-enable PCI device after reset\n");
2846 return PCI_ERS_RESULT_DISCONNECT;
2847 }
2848 pci_set_master(pdev);
2849
2850 pci_enable_wake(pdev, PCI_D3hot, 0);
2851 pci_enable_wake(pdev, PCI_D3cold, 0);
2852
2853 atl1c_reset_mac(&adapter->hw);
2854
2855 return PCI_ERS_RESULT_RECOVERED;
2856}
2857
2858/*
2859 * atl1c_io_resume - called when traffic can start flowing again.
2860 * @pdev: Pointer to PCI device
2861 *
2862 * This callback is called when the error recovery driver tells us that
2863 * its OK to resume normal operation. Implementation resembles the
2864 * second-half of the atl1c_resume routine.
2865 */
2866static void atl1c_io_resume(struct pci_dev *pdev)
2867{
2868 struct net_device *netdev = pci_get_drvdata(pdev);
2869 struct atl1c_adapter *adapter = netdev_priv(netdev);
2870
2871 if (netif_running(netdev)) {
2872 if (atl1c_up(adapter)) {
2873 if (netif_msg_hw(adapter))
2874 dev_err(&pdev->dev,
2875 "Cannot bring device back up after reset\n");
2876 return;
2877 }
2878 }
2879
2880 netif_device_attach(netdev);
2881}
2882
2883static struct pci_error_handlers atl1c_err_handler = {
2884 .error_detected = atl1c_io_error_detected,
2885 .slot_reset = atl1c_io_slot_reset,
2886 .resume = atl1c_io_resume,
2887};
2888
2889static struct pci_driver atl1c_driver = {
2890 .name = atl1c_driver_name,
2891 .id_table = atl1c_pci_tbl,
2892 .probe = atl1c_probe,
2893 .remove = __devexit_p(atl1c_remove),
2894 /* Power Managment Hooks */
2895 .suspend = atl1c_suspend,
2896 .resume = atl1c_resume,
2897 .shutdown = atl1c_shutdown,
2898 .err_handler = &atl1c_err_handler
2899};
2900
2901/*
2902 * atl1c_init_module - Driver Registration Routine
2903 *
2904 * atl1c_init_module is the first routine called when the driver is
2905 * loaded. All it does is register with the PCI subsystem.
2906 */
2907static int __init atl1c_init_module(void)
2908{
2909 return pci_register_driver(&atl1c_driver);
2910}
2911
2912/*
2913 * atl1c_exit_module - Driver Exit Cleanup Routine
2914 *
2915 * atl1c_exit_module is called just before the driver is removed
2916 * from memory.
2917 */
2918static void __exit atl1c_exit_module(void)
2919{
2920 pci_unregister_driver(&atl1c_driver);
2921}
2922
2923module_init(atl1c_init_module);
2924module_exit(atl1c_exit_module);
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