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drivers/net/: use DEFINE_PCI_DEVICE_TABLE()
[net-next-2.6.git] / drivers / net / acenic.c
CommitLineData
1da177e4
LT		 1/*
2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
4 *
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
6 *
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
9 *
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Additional credits:
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
44 * endian systems.
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
49 * driver init path.
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
51 */
52
1da177e4
LT		 53#include <linux/module.h>
54#include <linux/moduleparam.h>
1da177e4
LT		 55#include <linux/types.h>
56#include <linux/errno.h>
57#include <linux/ioport.h>
58#include <linux/pci.h>
1e7f0bd8 59#include <linux/dma-mapping.h>
1da177e4
LT		 60#include <linux/kernel.h>
61#include <linux/netdevice.h>
62#include <linux/etherdevice.h>
63#include <linux/skbuff.h>
64#include <linux/init.h>
65#include <linux/delay.h>
66#include <linux/mm.h>
67#include <linux/highmem.h>
68#include <linux/sockios.h>
949b4254 69#include <linux/firmware.h>
1da177e4
LT		 70
71#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
72#include <linux/if_vlan.h>
73#endif
74
75#ifdef SIOCETHTOOL
76#include <linux/ethtool.h>
77#endif
78
79#include <net/sock.h>
80#include <net/ip.h>
81
82#include <asm/system.h>
83#include <asm/io.h>
84#include <asm/irq.h>
85#include <asm/byteorder.h>
86#include <asm/uaccess.h>
87
88
89#define DRV_NAME "acenic"
90
91#undef INDEX_DEBUG
92
93#ifdef CONFIG_ACENIC_OMIT_TIGON_I
94#define ACE_IS_TIGON_I(ap) 0
95#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
96#else
97#define ACE_IS_TIGON_I(ap) (ap->version == 1)
98#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
99#endif
100
101#ifndef PCI_VENDOR_ID_ALTEON
6aa20a22 102#define PCI_VENDOR_ID_ALTEON 0x12ae
1da177e4
LT		 103#endif
104#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
105#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
106#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
107#endif
108#ifndef PCI_DEVICE_ID_3COM_3C985
109#define PCI_DEVICE_ID_3COM_3C985 0x0001
110#endif
111#ifndef PCI_VENDOR_ID_NETGEAR
112#define PCI_VENDOR_ID_NETGEAR 0x1385
113#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
114#endif
115#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
116#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
117#endif
118
119
120/*
121 * Farallon used the DEC vendor ID by mistake and they seem not
122 * to care - stinky!
123 */
124#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
125#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
126#endif
127#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
128#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
129#endif
130#ifndef PCI_VENDOR_ID_SGI
131#define PCI_VENDOR_ID_SGI 0x10a9
132#endif
133#ifndef PCI_DEVICE_ID_SGI_ACENIC
134#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
135#endif
136
a3aa1884 137static DEFINE_PCI_DEVICE_TABLE(acenic_pci_tbl) = {
1da177e4
LT		 138 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
139 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
140 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
141 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
142 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
143 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
144 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
145 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
146 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
147 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
148 /*
149 * Farallon used the DEC vendor ID on their cards incorrectly,
150 * then later Alteon's ID.
151 */
152 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
153 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
154 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
155 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
156 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
157 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
158 { }
159};
160MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
161
1da177e4 162#define ace_sync_irq(irq) synchronize_irq(irq)
1da177e4
LT		 163
164#ifndef offset_in_page
165#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
166#endif
167
168#define ACE_MAX_MOD_PARMS 8
169#define BOARD_IDX_STATIC 0
170#define BOARD_IDX_OVERFLOW -1
171
172#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
173 defined(NETIF_F_HW_VLAN_RX)
174#define ACENIC_DO_VLAN 1
175#define ACE_RCB_VLAN_FLAG RCB_FLG_VLAN_ASSIST
176#else
177#define ACENIC_DO_VLAN 0
178#define ACE_RCB_VLAN_FLAG 0
179#endif
180
181#include "acenic.h"
182
183/*
184 * These must be defined before the firmware is included.
185 */
186#define MAX_TEXT_LEN 96*1024
187#define MAX_RODATA_LEN 8*1024
188#define MAX_DATA_LEN 2*1024
189
1da177e4
LT		 190#ifndef tigon2FwReleaseLocal
191#define tigon2FwReleaseLocal 0
192#endif
193
194/*
195 * This driver currently supports Tigon I and Tigon II based cards
196 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
197 * GA620. The driver should also work on the SGI, DEC and Farallon
198 * versions of the card, however I have not been able to test that
199 * myself.
200 *
201 * This card is really neat, it supports receive hardware checksumming
202 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
203 * firmware. Also the programming interface is quite neat, except for
204 * the parts dealing with the i2c eeprom on the card ;-)
205 *
206 * Using jumbo frames:
207 *
208 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
209 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
210 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
211 * interface number and <MTU> being the MTU value.
212 *
213 * Module parameters:
214 *
215 * When compiled as a loadable module, the driver allows for a number
216 * of module parameters to be specified. The driver supports the
217 * following module parameters:
218 *
219 * trace=<val> - Firmware trace level. This requires special traced
220 * firmware to replace the firmware supplied with
221 * the driver - for debugging purposes only.
222 *
223 * link=<val> - Link state. Normally you want to use the default link
224 * parameters set by the driver. This can be used to
225 * override these in case your switch doesn't negotiate
226 * the link properly. Valid values are:
227 * 0x0001 - Force half duplex link.
228 * 0x0002 - Do not negotiate line speed with the other end.
229 * 0x0010 - 10Mbit/sec link.
230 * 0x0020 - 100Mbit/sec link.
231 * 0x0040 - 1000Mbit/sec link.
232 * 0x0100 - Do not negotiate flow control.
233 * 0x0200 - Enable RX flow control Y
234 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
235 * Default value is 0x0270, ie. enable link+flow
236 * control negotiation. Negotiating the highest
237 * possible link speed with RX flow control enabled.
238 *
239 * When disabling link speed negotiation, only one link
240 * speed is allowed to be specified!
241 *
242 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
243 * to wait for more packets to arive before
244 * interrupting the host, from the time the first
245 * packet arrives.
246 *
247 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
248 * to wait for more packets to arive in the transmit ring,
249 * before interrupting the host, after transmitting the
250 * first packet in the ring.
251 *
252 * max_tx_desc=<val> - maximum number of transmit descriptors
253 * (packets) transmitted before interrupting the host.
254 *
255 * max_rx_desc=<val> - maximum number of receive descriptors
256 * (packets) received before interrupting the host.
257 *
258 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
259 * increments of the NIC's on board memory to be used for
260 * transmit and receive buffers. For the 1MB NIC app. 800KB
261 * is available, on the 1/2MB NIC app. 300KB is available.
262 * 68KB will always be available as a minimum for both
263 * directions. The default value is a 50/50 split.
264 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
265 * operations, default (1) is to always disable this as
266 * that is what Alteon does on NT. I have not been able
267 * to measure any real performance differences with
268 * this on my systems. Set <val>=0 if you want to
269 * enable these operations.
270 *
271 * If you use more than one NIC, specify the parameters for the
272 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
273 * run tracing on NIC #2 but not on NIC #1 and #3.
274 *
275 * TODO:
276 *
277 * - Proper multicast support.
278 * - NIC dump support.
279 * - More tuning parameters.
280 *
281 * The mini ring is not used under Linux and I am not sure it makes sense
282 * to actually use it.
283 *
284 * New interrupt handler strategy:
285 *
286 * The old interrupt handler worked using the traditional method of
287 * replacing an skbuff with a new one when a packet arrives. However
288 * the rx rings do not need to contain a static number of buffer
289 * descriptors, thus it makes sense to move the memory allocation out
290 * of the main interrupt handler and do it in a bottom half handler
291 * and only allocate new buffers when the number of buffers in the
292 * ring is below a certain threshold. In order to avoid starving the
293 * NIC under heavy load it is however necessary to force allocation
294 * when hitting a minimum threshold. The strategy for alloction is as
295 * follows:
296 *
297 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
298 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
299 * the buffers in the interrupt handler
300 * RX_RING_THRES - maximum number of buffers in the rx ring
301 * RX_MINI_THRES - maximum number of buffers in the mini ring
302 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
303 *
304 * One advantagous side effect of this allocation approach is that the
305 * entire rx processing can be done without holding any spin lock
306 * since the rx rings and registers are totally independent of the tx
307 * ring and its registers. This of course includes the kmalloc's of
308 * new skb's. Thus start_xmit can run in parallel with rx processing
309 * and the memory allocation on SMP systems.
310 *
311 * Note that running the skb reallocation in a bottom half opens up
312 * another can of races which needs to be handled properly. In
313 * particular it can happen that the interrupt handler tries to run
314 * the reallocation while the bottom half is either running on another
315 * CPU or was interrupted on the same CPU. To get around this the
316 * driver uses bitops to prevent the reallocation routines from being
317 * reentered.
318 *
319 * TX handling can also be done without holding any spin lock, wheee
320 * this is fun! since tx_ret_csm is only written to by the interrupt
321 * handler. The case to be aware of is when shutting down the device
322 * and cleaning up where it is necessary to make sure that
323 * start_xmit() is not running while this is happening. Well DaveM
324 * informs me that this case is already protected against ... bye bye
325 * Mr. Spin Lock, it was nice to know you.
326 *
327 * TX interrupts are now partly disabled so the NIC will only generate
328 * TX interrupts for the number of coal ticks, not for the number of
329 * TX packets in the queue. This should reduce the number of TX only,
330 * ie. when no RX processing is done, interrupts seen.
331 */
332
333/*
334 * Threshold values for RX buffer allocation - the low water marks for
335 * when to start refilling the rings are set to 75% of the ring
336 * sizes. It seems to make sense to refill the rings entirely from the
337 * intrrupt handler once it gets below the panic threshold, that way
338 * we don't risk that the refilling is moved to another CPU when the
339 * one running the interrupt handler just got the slab code hot in its
340 * cache.
341 */
342#define RX_RING_SIZE 72
343#define RX_MINI_SIZE 64
344#define RX_JUMBO_SIZE 48
345
346#define RX_PANIC_STD_THRES 16
347#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
348#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
349#define RX_PANIC_MINI_THRES 12
350#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
351#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
352#define RX_PANIC_JUMBO_THRES 6
353#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
354#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
355
356
357/*
358 * Size of the mini ring entries, basically these just should be big
359 * enough to take TCP ACKs
360 */
361#define ACE_MINI_SIZE 100
362
363#define ACE_MINI_BUFSIZE ACE_MINI_SIZE
364#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
365#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
366
367/*
368 * There seems to be a magic difference in the effect between 995 and 996
369 * but little difference between 900 and 995 ... no idea why.
370 *
371 * There is now a default set of tuning parameters which is set, depending
372 * on whether or not the user enables Jumbo frames. It's assumed that if
373 * Jumbo frames are enabled, the user wants optimal tuning for that case.
374 */
375#define DEF_TX_COAL 400 /* 996 */
376#define DEF_TX_MAX_DESC 60 /* was 40 */
377#define DEF_RX_COAL 120 /* 1000 */
378#define DEF_RX_MAX_DESC 25
379#define DEF_TX_RATIO 21 /* 24 */
380
381#define DEF_JUMBO_TX_COAL 20
382#define DEF_JUMBO_TX_MAX_DESC 60
383#define DEF_JUMBO_RX_COAL 30
384#define DEF_JUMBO_RX_MAX_DESC 6
385#define DEF_JUMBO_TX_RATIO 21
386
387#if tigon2FwReleaseLocal < 20001118
388/*
389 * Standard firmware and early modifications duplicate
390 * IRQ load without this flag (coal timer is never reset).
391 * Note that with this flag tx_coal should be less than
392 * time to xmit full tx ring.
393 * 400usec is not so bad for tx ring size of 128.
394 */
395#define TX_COAL_INTS_ONLY 1 /* worth it */
396#else
397/*
398 * With modified firmware, this is not necessary, but still useful.
399 */
400#define TX_COAL_INTS_ONLY 1
401#endif
402
403#define DEF_TRACE 0
404#define DEF_STAT (2 * TICKS_PER_SEC)
405
406
ddfce6bb 407static int link_state[ACE_MAX_MOD_PARMS];
1da177e4
LT		 408static int trace[ACE_MAX_MOD_PARMS];
409static int tx_coal_tick[ACE_MAX_MOD_PARMS];
410static int rx_coal_tick[ACE_MAX_MOD_PARMS];
411static int max_tx_desc[ACE_MAX_MOD_PARMS];
412static int max_rx_desc[ACE_MAX_MOD_PARMS];
413static int tx_ratio[ACE_MAX_MOD_PARMS];
414static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
415
416MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
417MODULE_LICENSE("GPL");
418MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
949b4254
JS		 419#ifndef CONFIG_ACENIC_OMIT_TIGON_I
420MODULE_FIRMWARE("acenic/tg1.bin");
421#endif
422MODULE_FIRMWARE("acenic/tg2.bin");
1da177e4 423
ddfce6bb 424module_param_array_named(link, link_state, int, NULL, 0);
1da177e4
LT		 425module_param_array(trace, int, NULL, 0);
426module_param_array(tx_coal_tick, int, NULL, 0);
427module_param_array(max_tx_desc, int, NULL, 0);
428module_param_array(rx_coal_tick, int, NULL, 0);
429module_param_array(max_rx_desc, int, NULL, 0);
430module_param_array(tx_ratio, int, NULL, 0);
431MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
432MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
433MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
434MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
435MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
436MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
437MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
438
439
da38075c 440static const char version[] __devinitconst =
1da177e4
LT		 441 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
442 " http://home.cern.ch/~jes/gige/acenic.html\n";
443
444static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
445static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
446static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
447
7282d491 448static const struct ethtool_ops ace_ethtool_ops = {
1da177e4
LT		 449 .get_settings = ace_get_settings,
450 .set_settings = ace_set_settings,
451 .get_drvinfo = ace_get_drvinfo,
452};
453
454static void ace_watchdog(struct net_device *dev);
455
d8b83c57
SH		 456static const struct net_device_ops ace_netdev_ops = {
457 .ndo_open = ace_open,
458 .ndo_stop = ace_close,
459 .ndo_tx_timeout = ace_watchdog,
460 .ndo_get_stats = ace_get_stats,
00829823 461 .ndo_start_xmit = ace_start_xmit,
d8b83c57 462 .ndo_set_multicast_list = ace_set_multicast_list,
52255bbe 463 .ndo_validate_addr = eth_validate_addr,
d8b83c57
SH		 464 .ndo_set_mac_address = ace_set_mac_addr,
465 .ndo_change_mtu = ace_change_mtu,
00829823 466#if ACENIC_DO_VLAN
d8b83c57 467 .ndo_vlan_rx_register = ace_vlan_rx_register,
00829823 468#endif
d8b83c57
SH		 469};
470
1da177e4
LT		 471static int __devinit acenic_probe_one(struct pci_dev *pdev,
472 const struct pci_device_id *id)
473{
474 struct net_device *dev;
475 struct ace_private *ap;
476 static int boards_found;
477
478 dev = alloc_etherdev(sizeof(struct ace_private));
479 if (dev == NULL) {
480 printk(KERN_ERR "acenic: Unable to allocate "
481 "net_device structure!\n");
482 return -ENOMEM;
483 }
484
1da177e4
LT		 485 SET_NETDEV_DEV(dev, &pdev->dev);
486
454d7c9b 487 ap = netdev_priv(dev);
1da177e4
LT		 488 ap->pdev = pdev;
489 ap->name = pci_name(pdev);
490
491 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
492#if ACENIC_DO_VLAN
493 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 494#endif
25805dcf 495
25805dcf 496 dev->watchdog_timeo = 5*HZ;
1da177e4 497
d8b83c57 498 dev->netdev_ops = &ace_netdev_ops;
1da177e4 499 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
1da177e4
LT		 500
501 /* we only display this string ONCE */
502 if (!boards_found)
503 printk(version);
504
505 if (pci_enable_device(pdev))
506 goto fail_free_netdev;
507
508 /*
509 * Enable master mode before we start playing with the
510 * pci_command word since pci_set_master() will modify
511 * it.
512 */
513 pci_set_master(pdev);
514
515 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
516
6aa20a22 517 /* OpenFirmware on Mac's does not set this - DOH.. */
1da177e4
LT		 518 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
519 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
520 "access - was not enabled by BIOS/Firmware\n",
521 ap->name);
522 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
523 pci_write_config_word(ap->pdev, PCI_COMMAND,
524 ap->pci_command);
525 wmb();
526 }
527
528 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
529 if (ap->pci_latency <= 0x40) {
530 ap->pci_latency = 0x40;
531 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
532 }
533
534 /*
535 * Remap the regs into kernel space - this is abuse of
536 * dev->base_addr since it was means for I/O port
537 * addresses but who gives a damn.
538 */
539 dev->base_addr = pci_resource_start(pdev, 0);
540 ap->regs = ioremap(dev->base_addr, 0x4000);
541 if (!ap->regs) {
542 printk(KERN_ERR "%s: Unable to map I/O register, "
543 "AceNIC %i will be disabled.\n",
544 ap->name, boards_found);
545 goto fail_free_netdev;
546 }
547
548 switch(pdev->vendor) {
549 case PCI_VENDOR_ID_ALTEON:
550 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
551 printk(KERN_INFO "%s: Farallon PN9100-T ",
552 ap->name);
553 } else {
554 printk(KERN_INFO "%s: Alteon AceNIC ",
555 ap->name);
556 }
557 break;
558 case PCI_VENDOR_ID_3COM:
559 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
560 break;
561 case PCI_VENDOR_ID_NETGEAR:
562 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
563 break;
564 case PCI_VENDOR_ID_DEC:
565 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
566 printk(KERN_INFO "%s: Farallon PN9000-SX ",
567 ap->name);
568 break;
569 }
570 case PCI_VENDOR_ID_SGI:
571 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
572 break;
573 default:
574 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
575 break;
576 }
577
578 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
c6387a48 579 printk("irq %d\n", pdev->irq);
1da177e4
LT		 580
581#ifdef CONFIG_ACENIC_OMIT_TIGON_I
582 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
583 printk(KERN_ERR "%s: Driver compiled without Tigon I"
584 " support - NIC disabled\n", dev->name);
585 goto fail_uninit;
586 }
587#endif
588
589 if (ace_allocate_descriptors(dev))
590 goto fail_free_netdev;
591
592#ifdef MODULE
593 if (boards_found >= ACE_MAX_MOD_PARMS)
594 ap->board_idx = BOARD_IDX_OVERFLOW;
595 else
596 ap->board_idx = boards_found;
597#else
598 ap->board_idx = BOARD_IDX_STATIC;
599#endif
600
601 if (ace_init(dev))
602 goto fail_free_netdev;
603
604 if (register_netdev(dev)) {
605 printk(KERN_ERR "acenic: device registration failed\n");
606 goto fail_uninit;
607 }
608 ap->name = dev->name;
609
610 if (ap->pci_using_dac)
611 dev->features |= NETIF_F_HIGHDMA;
612
613 pci_set_drvdata(pdev, dev);
614
615 boards_found++;
616 return 0;
617
618 fail_uninit:
619 ace_init_cleanup(dev);
620 fail_free_netdev:
621 free_netdev(dev);
622 return -ENODEV;
623}
624
625static void __devexit acenic_remove_one(struct pci_dev *pdev)
626{
627 struct net_device *dev = pci_get_drvdata(pdev);
628 struct ace_private *ap = netdev_priv(dev);
629 struct ace_regs __iomem *regs = ap->regs;
630 short i;
631
632 unregister_netdev(dev);
633
634 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
635 if (ap->version >= 2)
636 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
6aa20a22 637
1da177e4
LT		 638 /*
639 * This clears any pending interrupts
640 */
641 writel(1, &regs->Mb0Lo);
642 readl(&regs->CpuCtrl); /* flush */
643
644 /*
645 * Make sure no other CPUs are processing interrupts
646 * on the card before the buffers are being released.
647 * Otherwise one might experience some `interesting'
648 * effects.
649 *
650 * Then release the RX buffers - jumbo buffers were
651 * already released in ace_close().
652 */
653 ace_sync_irq(dev->irq);
654
655 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
656 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
657
658 if (skb) {
659 struct ring_info *ringp;
660 dma_addr_t mapping;
661
662 ringp = &ap->skb->rx_std_skbuff[i];
663 mapping = pci_unmap_addr(ringp, mapping);
664 pci_unmap_page(ap->pdev, mapping,
665 ACE_STD_BUFSIZE,
666 PCI_DMA_FROMDEVICE);
667
668 ap->rx_std_ring[i].size = 0;
669 ap->skb->rx_std_skbuff[i].skb = NULL;
670 dev_kfree_skb(skb);
671 }
672 }
673
674 if (ap->version >= 2) {
675 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
676 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
677
678 if (skb) {
679 struct ring_info *ringp;
680 dma_addr_t mapping;
681
682 ringp = &ap->skb->rx_mini_skbuff[i];
683 mapping = pci_unmap_addr(ringp,mapping);
684 pci_unmap_page(ap->pdev, mapping,
685 ACE_MINI_BUFSIZE,
686 PCI_DMA_FROMDEVICE);
687
688 ap->rx_mini_ring[i].size = 0;
689 ap->skb->rx_mini_skbuff[i].skb = NULL;
690 dev_kfree_skb(skb);
691 }
692 }
693 }
694
695 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
696 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
697 if (skb) {
698 struct ring_info *ringp;
699 dma_addr_t mapping;
700
701 ringp = &ap->skb->rx_jumbo_skbuff[i];
702 mapping = pci_unmap_addr(ringp, mapping);
703 pci_unmap_page(ap->pdev, mapping,
704 ACE_JUMBO_BUFSIZE,
705 PCI_DMA_FROMDEVICE);
706
707 ap->rx_jumbo_ring[i].size = 0;
708 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
709 dev_kfree_skb(skb);
710 }
711 }
712
713 ace_init_cleanup(dev);
714 free_netdev(dev);
715}
716
717static struct pci_driver acenic_pci_driver = {
718 .name = "acenic",
719 .id_table = acenic_pci_tbl,
720 .probe = acenic_probe_one,
721 .remove = __devexit_p(acenic_remove_one),
722};
723
724static int __init acenic_init(void)
725{
29917620 726 return pci_register_driver(&acenic_pci_driver);
1da177e4
LT		 727}
728
729static void __exit acenic_exit(void)
730{
731 pci_unregister_driver(&acenic_pci_driver);
732}
733
734module_init(acenic_init);
735module_exit(acenic_exit);
736
737static void ace_free_descriptors(struct net_device *dev)
738{
739 struct ace_private *ap = netdev_priv(dev);
740 int size;
741
742 if (ap->rx_std_ring != NULL) {
743 size = (sizeof(struct rx_desc) *
744 (RX_STD_RING_ENTRIES +
745 RX_JUMBO_RING_ENTRIES +
746 RX_MINI_RING_ENTRIES +
747 RX_RETURN_RING_ENTRIES));
748 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
749 ap->rx_ring_base_dma);
750 ap->rx_std_ring = NULL;
751 ap->rx_jumbo_ring = NULL;
752 ap->rx_mini_ring = NULL;
753 ap->rx_return_ring = NULL;
754 }
755 if (ap->evt_ring != NULL) {
756 size = (sizeof(struct event) * EVT_RING_ENTRIES);
757 pci_free_consistent(ap->pdev, size, ap->evt_ring,
758 ap->evt_ring_dma);
759 ap->evt_ring = NULL;
760 }
761 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
762 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
763 pci_free_consistent(ap->pdev, size, ap->tx_ring,
764 ap->tx_ring_dma);
765 }
766 ap->tx_ring = NULL;
767
768 if (ap->evt_prd != NULL) {
769 pci_free_consistent(ap->pdev, sizeof(u32),
770 (void *)ap->evt_prd, ap->evt_prd_dma);
771 ap->evt_prd = NULL;
772 }
773 if (ap->rx_ret_prd != NULL) {
774 pci_free_consistent(ap->pdev, sizeof(u32),
775 (void *)ap->rx_ret_prd,
776 ap->rx_ret_prd_dma);
777 ap->rx_ret_prd = NULL;
778 }
779 if (ap->tx_csm != NULL) {
780 pci_free_consistent(ap->pdev, sizeof(u32),
781 (void *)ap->tx_csm, ap->tx_csm_dma);
782 ap->tx_csm = NULL;
783 }
784}
785
786
787static int ace_allocate_descriptors(struct net_device *dev)
788{
789 struct ace_private *ap = netdev_priv(dev);
790 int size;
791
792 size = (sizeof(struct rx_desc) *
793 (RX_STD_RING_ENTRIES +
794 RX_JUMBO_RING_ENTRIES +
795 RX_MINI_RING_ENTRIES +
796 RX_RETURN_RING_ENTRIES));
797
798 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
799 &ap->rx_ring_base_dma);
800 if (ap->rx_std_ring == NULL)
801 goto fail;
802
803 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
804 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
805 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
806
807 size = (sizeof(struct event) * EVT_RING_ENTRIES);
808
809 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
810
811 if (ap->evt_ring == NULL)
812 goto fail;
813
814 /*
815 * Only allocate a host TX ring for the Tigon II, the Tigon I
816 * has to use PCI registers for this ;-(
817 */
818 if (!ACE_IS_TIGON_I(ap)) {
819 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
820
821 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
822 &ap->tx_ring_dma);
823
824 if (ap->tx_ring == NULL)
825 goto fail;
826 }
827
828 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
829 &ap->evt_prd_dma);
830 if (ap->evt_prd == NULL)
831 goto fail;
832
833 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
834 &ap->rx_ret_prd_dma);
835 if (ap->rx_ret_prd == NULL)
836 goto fail;
837
838 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
839 &ap->tx_csm_dma);
840 if (ap->tx_csm == NULL)
841 goto fail;
842
843 return 0;
844
845fail:
846 /* Clean up. */
847 ace_init_cleanup(dev);
848 return 1;
849}
850
851
852/*
853 * Generic cleanup handling data allocated during init. Used when the
854 * module is unloaded or if an error occurs during initialization
855 */
856static void ace_init_cleanup(struct net_device *dev)
857{
858 struct ace_private *ap;
859
860 ap = netdev_priv(dev);
861
862 ace_free_descriptors(dev);
863
864 if (ap->info)
865 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
866 ap->info, ap->info_dma);
b4558ea9
JJ		 867 kfree(ap->skb);
868 kfree(ap->trace_buf);
1da177e4
LT		 869
870 if (dev->irq)
871 free_irq(dev->irq, dev);
872
873 iounmap(ap->regs);
874}
875
876
877/*
878 * Commands are considered to be slow.
879 */
880static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
881{
882 u32 idx;
883
884 idx = readl(&regs->CmdPrd);
885
886 writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
887 idx = (idx + 1) % CMD_RING_ENTRIES;
888
889 writel(idx, &regs->CmdPrd);
890}
891
892
893static int __devinit ace_init(struct net_device *dev)
894{
895 struct ace_private *ap;
896 struct ace_regs __iomem *regs;
897 struct ace_info *info = NULL;
898 struct pci_dev *pdev;
899 unsigned long myjif;
900 u64 tmp_ptr;
901 u32 tig_ver, mac1, mac2, tmp, pci_state;
902 int board_idx, ecode = 0;
903 short i;
904 unsigned char cache_size;
905
906 ap = netdev_priv(dev);
907 regs = ap->regs;
908
909 board_idx = ap->board_idx;
910
911 /*
912 * aman@sgi.com - its useful to do a NIC reset here to
913 * address the `Firmware not running' problem subsequent
914 * to any crashes involving the NIC
915 */
916 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
917 readl(&regs->HostCtrl); /* PCI write posting */
918 udelay(5);
919
920 /*
921 * Don't access any other registers before this point!
922 */
923#ifdef __BIG_ENDIAN
924 /*
925 * This will most likely need BYTE_SWAP once we switch
926 * to using __raw_writel()
927 */
928 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
929 &regs->HostCtrl);
930#else
931 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
932 &regs->HostCtrl);
933#endif
934 readl(&regs->HostCtrl); /* PCI write posting */
935
936 /*
937 * Stop the NIC CPU and clear pending interrupts
938 */
939 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
940 readl(&regs->CpuCtrl); /* PCI write posting */
941 writel(0, &regs->Mb0Lo);
942
943 tig_ver = readl(&regs->HostCtrl) >> 28;
944
945 switch(tig_ver){
946#ifndef CONFIG_ACENIC_OMIT_TIGON_I
947 case 4:
948 case 5:
949 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 950 tig_ver, ap->firmware_major, ap->firmware_minor,
951 ap->firmware_fix);
1da177e4
LT		 952 writel(0, &regs->LocalCtrl);
953 ap->version = 1;
954 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
955 break;
956#endif
957 case 6:
958 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 959 tig_ver, ap->firmware_major, ap->firmware_minor,
960 ap->firmware_fix);
1da177e4
LT		 961 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
962 readl(&regs->CpuBCtrl); /* PCI write posting */
963 /*
964 * The SRAM bank size does _not_ indicate the amount
965 * of memory on the card, it controls the _bank_ size!
966 * Ie. a 1MB AceNIC will have two banks of 512KB.
967 */
968 writel(SRAM_BANK_512K, &regs->LocalCtrl);
969 writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
970 ap->version = 2;
971 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
972 break;
973 default:
974 printk(KERN_WARNING " Unsupported Tigon version detected "
975 "(%i)\n", tig_ver);
976 ecode = -ENODEV;
977 goto init_error;
978 }
979
980 /*
981 * ModeStat _must_ be set after the SRAM settings as this change
982 * seems to corrupt the ModeStat and possible other registers.
983 * The SRAM settings survive resets and setting it to the same
984 * value a second time works as well. This is what caused the
985 * `Firmware not running' problem on the Tigon II.
986 */
987#ifdef __BIG_ENDIAN
988 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
989 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
990#else
991 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
992 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
993#endif
994 readl(&regs->ModeStat); /* PCI write posting */
995
996 mac1 = 0;
997 for(i = 0; i < 4; i++) {
ddfce6bb 998 int t;
6f9d4722 999
1da177e4 1000 mac1 = mac1 << 8;
ddfce6bb
SH		 1001 t = read_eeprom_byte(dev, 0x8c+i);
1002 if (t < 0) {
1da177e4
LT		 1003 ecode = -EIO;
1004 goto init_error;
1005 } else
ddfce6bb 1006 mac1 |= (t & 0xff);
1da177e4
LT		 1007 }
1008 mac2 = 0;
1009 for(i = 4; i < 8; i++) {
ddfce6bb 1010 int t;
6f9d4722 1011
1da177e4 1012 mac2 = mac2 << 8;
ddfce6bb
SH		 1013 t = read_eeprom_byte(dev, 0x8c+i);
1014 if (t < 0) {
1da177e4
LT		 1015 ecode = -EIO;
1016 goto init_error;
1017 } else
ddfce6bb 1018 mac2 |= (t & 0xff);
1da177e4
LT		 1019 }
1020
1021 writel(mac1, &regs->MacAddrHi);
1022 writel(mac2, &regs->MacAddrLo);
1023
1da177e4
LT		 1024 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1025 dev->dev_addr[1] = mac1 & 0xff;
1026 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1027 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1028 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1029 dev->dev_addr[5] = mac2 & 0xff;
1030
e174961c 1031 printk("MAC: %pM\n", dev->dev_addr);
0795af57 1032
1da177e4
LT		 1033 /*
1034 * Looks like this is necessary to deal with on all architectures,
1035 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1036 * Ie. having two NICs in the machine, one will have the cache
1037 * line set at boot time, the other will not.
1038 */
1039 pdev = ap->pdev;
1040 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1041 cache_size <<= 2;
1042 if (cache_size != SMP_CACHE_BYTES) {
1043 printk(KERN_INFO " PCI cache line size set incorrectly "
1044 "(%i bytes) by BIOS/FW, ", cache_size);
1045 if (cache_size > SMP_CACHE_BYTES)
1046 printk("expecting %i\n", SMP_CACHE_BYTES);
1047 else {
1048 printk("correcting to %i\n", SMP_CACHE_BYTES);
1049 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1050 SMP_CACHE_BYTES >> 2);
1051 }
1052 }
1053
1054 pci_state = readl(&regs->PciState);
1055 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1056 "latency: %i clks\n",
1057 (pci_state & PCI_32BIT) ? 32 : 64,
6aa20a22 1058 (pci_state & PCI_66MHZ) ? 66 : 33,
1da177e4
LT		 1059 ap->pci_latency);
1060
1061 /*
1062 * Set the max DMA transfer size. Seems that for most systems
1063 * the performance is better when no MAX parameter is
1064 * set. However for systems enabling PCI write and invalidate,
1065 * DMA writes must be set to the L1 cache line size to get
1066 * optimal performance.
1067 *
1068 * The default is now to turn the PCI write and invalidate off
1069 * - that is what Alteon does for NT.
1070 */
1071 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1072 if (ap->version >= 2) {
1073 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1074 /*
1075 * Tuning parameters only supported for 8 cards
1076 */
1077 if (board_idx == BOARD_IDX_OVERFLOW ||
1078 dis_pci_mem_inval[board_idx]) {
1079 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1080 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1081 pci_write_config_word(pdev, PCI_COMMAND,
1082 ap->pci_command);
1083 printk(KERN_INFO " Disabling PCI memory "
1084 "write and invalidate\n");
1085 }
1086 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1087 printk(KERN_INFO " PCI memory write & invalidate "
1088 "enabled by BIOS, enabling counter measures\n");
1089
1090 switch(SMP_CACHE_BYTES) {
1091 case 16:
1092 tmp |= DMA_WRITE_MAX_16;
1093 break;
1094 case 32:
1095 tmp |= DMA_WRITE_MAX_32;
1096 break;
1097 case 64:
1098 tmp |= DMA_WRITE_MAX_64;
1099 break;
1100 case 128:
1101 tmp |= DMA_WRITE_MAX_128;
1102 break;
1103 default:
1104 printk(KERN_INFO " Cache line size %i not "
1105 "supported, PCI write and invalidate "
1106 "disabled\n", SMP_CACHE_BYTES);
1107 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1108 pci_write_config_word(pdev, PCI_COMMAND,
1109 ap->pci_command);
1110 }
1111 }
1112 }
1113
1114#ifdef __sparc__
1115 /*
1116 * On this platform, we know what the best dma settings
1117 * are. We use 64-byte maximum bursts, because if we
1118 * burst larger than the cache line size (or even cross
1119 * a 64byte boundary in a single burst) the UltraSparc
1120 * PCI controller will disconnect at 64-byte multiples.
1121 *
1122 * Read-multiple will be properly enabled above, and when
1123 * set will give the PCI controller proper hints about
1124 * prefetching.
1125 */
1126 tmp &= ~DMA_READ_WRITE_MASK;
1127 tmp |= DMA_READ_MAX_64;
1128 tmp |= DMA_WRITE_MAX_64;
1129#endif
1130#ifdef __alpha__
1131 tmp &= ~DMA_READ_WRITE_MASK;
1132 tmp |= DMA_READ_MAX_128;
1133 /*
1134 * All the docs say MUST NOT. Well, I did.
1135 * Nothing terrible happens, if we load wrong size.
1136 * Bit w&i still works better!
1137 */
1138 tmp |= DMA_WRITE_MAX_128;
1139#endif
1140 writel(tmp, &regs->PciState);
1141
1142#if 0
1143 /*
1144 * The Host PCI bus controller driver has to set FBB.
1145 * If all devices on that PCI bus support FBB, then the controller
1146 * can enable FBB support in the Host PCI Bus controller (or on
1147 * the PCI-PCI bridge if that applies).
1148 * -ggg
1149 */
1150 /*
1151 * I have received reports from people having problems when this
1152 * bit is enabled.
1153 */
1154 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1155 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1156 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1157 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1158 }
1159#endif
6aa20a22 1160
1da177e4
LT		 1161 /*
1162 * Configure DMA attributes.
1163 */
6a35528a 1164 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 1165 ap->pci_using_dac = 1;
284901a9 1166 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 1167 ap->pci_using_dac = 0;
1168 } else {
1169 ecode = -ENODEV;
1170 goto init_error;
1171 }
1172
1173 /*
1174 * Initialize the generic info block and the command+event rings
1175 * and the control blocks for the transmit and receive rings
1176 * as they need to be setup once and for all.
1177 */
1178 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1179 &ap->info_dma))) {
1180 ecode = -EAGAIN;
1181 goto init_error;
1182 }
1183 ap->info = info;
1184
1185 /*
1186 * Get the memory for the skb rings.
1187 */
1188 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1189 ecode = -EAGAIN;
1190 goto init_error;
1191 }
1192
1fb9df5d 1193 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1da177e4
LT		 1194 DRV_NAME, dev);
1195 if (ecode) {
1196 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1197 DRV_NAME, pdev->irq);
1198 goto init_error;
1199 } else
1200 dev->irq = pdev->irq;
1201
1202#ifdef INDEX_DEBUG
1203 spin_lock_init(&ap->debug_lock);
1204 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1205 ap->last_std_rx = 0;
1206 ap->last_mini_rx = 0;
1207#endif
1208
1209 memset(ap->info, 0, sizeof(struct ace_info));
1210 memset(ap->skb, 0, sizeof(struct ace_skb));
1211
6c60e0c3
BH		 1212 ecode = ace_load_firmware(dev);
1213 if (ecode)
949b4254
JS		 1214 goto init_error;
1215
1da177e4
LT		 1216 ap->fw_running = 0;
1217
1218 tmp_ptr = ap->info_dma;
1219 writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1220 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1221
1222 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1223
1224 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1225 info->evt_ctrl.flags = 0;
1226
1227 *(ap->evt_prd) = 0;
1228 wmb();
1229 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1230 writel(0, &regs->EvtCsm);
1231
1232 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1233 info->cmd_ctrl.flags = 0;
1234 info->cmd_ctrl.max_len = 0;
1235
1236 for (i = 0; i < CMD_RING_ENTRIES; i++)
1237 writel(0, &regs->CmdRng[i]);
1238
1239 writel(0, &regs->CmdPrd);
1240 writel(0, &regs->CmdCsm);
1241
1242 tmp_ptr = ap->info_dma;
1243 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1244 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1245
1246 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1247 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1248 info->rx_std_ctrl.flags =
1249 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1250
1251 memset(ap->rx_std_ring, 0,
1252 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1253
1254 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1255 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1256
1257 ap->rx_std_skbprd = 0;
1258 atomic_set(&ap->cur_rx_bufs, 0);
1259
1260 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1261 (ap->rx_ring_base_dma +
1262 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1263 info->rx_jumbo_ctrl.max_len = 0;
1264 info->rx_jumbo_ctrl.flags =
1265 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1266
1267 memset(ap->rx_jumbo_ring, 0,
1268 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1269
1270 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1271 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1272
1273 ap->rx_jumbo_skbprd = 0;
1274 atomic_set(&ap->cur_jumbo_bufs, 0);
1275
1276 memset(ap->rx_mini_ring, 0,
1277 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1278
1279 if (ap->version >= 2) {
1280 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1281 (ap->rx_ring_base_dma +
1282 (sizeof(struct rx_desc) *
1283 (RX_STD_RING_ENTRIES +
1284 RX_JUMBO_RING_ENTRIES))));
1285 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
6aa20a22 1286 info->rx_mini_ctrl.flags =
1da177e4
LT		 1287 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|ACE_RCB_VLAN_FLAG;
1288
1289 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1290 ap->rx_mini_ring[i].flags =
1291 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1292 } else {
1293 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1294 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1295 info->rx_mini_ctrl.max_len = 0;
1296 }
1297
1298 ap->rx_mini_skbprd = 0;
1299 atomic_set(&ap->cur_mini_bufs, 0);
1300
1301 set_aceaddr(&info->rx_return_ctrl.rngptr,
1302 (ap->rx_ring_base_dma +
1303 (sizeof(struct rx_desc) *
1304 (RX_STD_RING_ENTRIES +
1305 RX_JUMBO_RING_ENTRIES +
1306 RX_MINI_RING_ENTRIES))));
1307 info->rx_return_ctrl.flags = 0;
1308 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1309
1310 memset(ap->rx_return_ring, 0,
1311 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1312
1313 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1314 *(ap->rx_ret_prd) = 0;
1315
1316 writel(TX_RING_BASE, &regs->WinBase);
1317
1318 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 1319 ap->tx_ring = (__force struct tx_desc *) regs->Window;
6aa20a22 1320 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1da177e4 1321 * sizeof(struct tx_desc)) / sizeof(u32); i++)
ddfce6bb 1322 writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
1da177e4
LT		 1323
1324 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1325 } else {
1326 memset(ap->tx_ring, 0,
1327 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1328
1329 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1330 }
1331
1332 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1333 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | ACE_RCB_VLAN_FLAG;
1334
1335 /*
1336 * The Tigon I does not like having the TX ring in host memory ;-(
1337 */
1338 if (!ACE_IS_TIGON_I(ap))
1339 tmp |= RCB_FLG_TX_HOST_RING;
1340#if TX_COAL_INTS_ONLY
1341 tmp |= RCB_FLG_COAL_INT_ONLY;
1342#endif
1343 info->tx_ctrl.flags = tmp;
1344
1345 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1346
1347 /*
1348 * Potential item for tuning parameter
1349 */
1350#if 0 /* NO */
1351 writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1352 writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1353#else
1354 writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1355 writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1356#endif
1357
1358 writel(0, &regs->MaskInt);
1359 writel(1, &regs->IfIdx);
1360#if 0
1361 /*
1362 * McKinley boxes do not like us fiddling with AssistState
1363 * this early
1364 */
1365 writel(1, &regs->AssistState);
1366#endif
1367
1368 writel(DEF_STAT, &regs->TuneStatTicks);
1369 writel(DEF_TRACE, &regs->TuneTrace);
1370
1371 ace_set_rxtx_parms(dev, 0);
1372
1373 if (board_idx == BOARD_IDX_OVERFLOW) {
1374 printk(KERN_WARNING "%s: more than %i NICs detected, "
1375 "ignoring module parameters!\n",
1376 ap->name, ACE_MAX_MOD_PARMS);
1377 } else if (board_idx >= 0) {
1378 if (tx_coal_tick[board_idx])
1379 writel(tx_coal_tick[board_idx],
1380 &regs->TuneTxCoalTicks);
1381 if (max_tx_desc[board_idx])
1382 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1383
1384 if (rx_coal_tick[board_idx])
1385 writel(rx_coal_tick[board_idx],
1386 &regs->TuneRxCoalTicks);
1387 if (max_rx_desc[board_idx])
1388 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1389
1390 if (trace[board_idx])
1391 writel(trace[board_idx], &regs->TuneTrace);
1392
1393 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1394 writel(tx_ratio[board_idx], &regs->TxBufRat);
1395 }
1396
1397 /*
1398 * Default link parameters
1399 */
1400 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1401 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1402 if(ap->version >= 2)
1403 tmp |= LNK_TX_FLOW_CTL_Y;
1404
1405 /*
1406 * Override link default parameters
1407 */
ddfce6bb
SH		 1408 if ((board_idx >= 0) && link_state[board_idx]) {
1409 int option = link_state[board_idx];
1da177e4
LT		 1410
1411 tmp = LNK_ENABLE;
1412
1413 if (option & 0x01) {
1414 printk(KERN_INFO "%s: Setting half duplex link\n",
1415 ap->name);
1416 tmp &= ~LNK_FULL_DUPLEX;
1417 }
1418 if (option & 0x02)
1419 tmp &= ~LNK_NEGOTIATE;
1420 if (option & 0x10)
1421 tmp |= LNK_10MB;
1422 if (option & 0x20)
1423 tmp |= LNK_100MB;
1424 if (option & 0x40)
1425 tmp |= LNK_1000MB;
1426 if ((option & 0x70) == 0) {
1427 printk(KERN_WARNING "%s: No media speed specified, "
1428 "forcing auto negotiation\n", ap->name);
1429 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1430 LNK_100MB | LNK_10MB;
1431 }
1432 if ((option & 0x100) == 0)
1433 tmp |= LNK_NEG_FCTL;
1434 else
1435 printk(KERN_INFO "%s: Disabling flow control "
1436 "negotiation\n", ap->name);
1437 if (option & 0x200)
1438 tmp |= LNK_RX_FLOW_CTL_Y;
1439 if ((option & 0x400) && (ap->version >= 2)) {
1440 printk(KERN_INFO "%s: Enabling TX flow control\n",
1441 ap->name);
1442 tmp |= LNK_TX_FLOW_CTL_Y;
1443 }
1444 }
1445
1446 ap->link = tmp;
1447 writel(tmp, &regs->TuneLink);
1448 if (ap->version >= 2)
1449 writel(tmp, &regs->TuneFastLink);
1450
949b4254 1451 writel(ap->firmware_start, &regs->Pc);
1da177e4
LT		 1452
1453 writel(0, &regs->Mb0Lo);
1454
1455 /*
1456 * Set tx_csm before we start receiving interrupts, otherwise
1457 * the interrupt handler might think it is supposed to process
1458 * tx ints before we are up and running, which may cause a null
1459 * pointer access in the int handler.
1460 */
1461 ap->cur_rx = 0;
1462 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1463
1464 wmb();
1465 ace_set_txprd(regs, ap, 0);
1466 writel(0, &regs->RxRetCsm);
1467
1da177e4
LT		 1468 /*
1469 * Enable DMA engine now.
1470 * If we do this sooner, Mckinley box pukes.
1471 * I assume it's because Tigon II DMA engine wants to check
1472 * *something* even before the CPU is started.
1473 */
1474 writel(1, &regs->AssistState); /* enable DMA */
1475
1476 /*
1477 * Start the NIC CPU
1478 */
1479 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1480 readl(&regs->CpuCtrl);
1481
1482 /*
1483 * Wait for the firmware to spin up - max 3 seconds.
1484 */
1485 myjif = jiffies + 3 * HZ;
1486 while (time_before(jiffies, myjif) && !ap->fw_running)
1487 cpu_relax();
1488
1489 if (!ap->fw_running) {
1490 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1491
1492 ace_dump_trace(ap);
1493 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1494 readl(&regs->CpuCtrl);
1495
1496 /* aman@sgi.com - account for badly behaving firmware/NIC:
1497 * - have observed that the NIC may continue to generate
1498 * interrupts for some reason; attempt to stop it - halt
1499 * second CPU for Tigon II cards, and also clear Mb0
1500 * - if we're a module, we'll fail to load if this was
1501 * the only GbE card in the system => if the kernel does
1502 * see an interrupt from the NIC, code to handle it is
1503 * gone and OOps! - so free_irq also
1504 */
1505 if (ap->version >= 2)
1506 writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1507 &regs->CpuBCtrl);
1508 writel(0, &regs->Mb0Lo);
1509 readl(&regs->Mb0Lo);
1510
1511 ecode = -EBUSY;
1512 goto init_error;
1513 }
1514
1515 /*
1516 * We load the ring here as there seem to be no way to tell the
1517 * firmware to wipe the ring without re-initializing it.
1518 */
1519 if (!test_and_set_bit(0, &ap->std_refill_busy))
1520 ace_load_std_rx_ring(ap, RX_RING_SIZE);
1521 else
1522 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1523 ap->name);
1524 if (ap->version >= 2) {
1525 if (!test_and_set_bit(0, &ap->mini_refill_busy))
1526 ace_load_mini_rx_ring(ap, RX_MINI_SIZE);
1527 else
1528 printk(KERN_ERR "%s: Someone is busy refilling "
1529 "the RX mini ring\n", ap->name);
1530 }
1531 return 0;
1532
1533 init_error:
1534 ace_init_cleanup(dev);
1535 return ecode;
1536}
1537
1538
1539static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1540{
1541 struct ace_private *ap = netdev_priv(dev);
1542 struct ace_regs __iomem *regs = ap->regs;
1543 int board_idx = ap->board_idx;
1544
1545 if (board_idx >= 0) {
1546 if (!jumbo) {
1547 if (!tx_coal_tick[board_idx])
1548 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1549 if (!max_tx_desc[board_idx])
1550 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1551 if (!rx_coal_tick[board_idx])
1552 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1553 if (!max_rx_desc[board_idx])
1554 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1555 if (!tx_ratio[board_idx])
1556 writel(DEF_TX_RATIO, &regs->TxBufRat);
1557 } else {
1558 if (!tx_coal_tick[board_idx])
1559 writel(DEF_JUMBO_TX_COAL,
1560 &regs->TuneTxCoalTicks);
1561 if (!max_tx_desc[board_idx])
1562 writel(DEF_JUMBO_TX_MAX_DESC,
1563 &regs->TuneMaxTxDesc);
1564 if (!rx_coal_tick[board_idx])
1565 writel(DEF_JUMBO_RX_COAL,
1566 &regs->TuneRxCoalTicks);
1567 if (!max_rx_desc[board_idx])
1568 writel(DEF_JUMBO_RX_MAX_DESC,
1569 &regs->TuneMaxRxDesc);
1570 if (!tx_ratio[board_idx])
1571 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1572 }
1573 }
1574}
1575
1576
1577static void ace_watchdog(struct net_device *data)
1578{
1579 struct net_device *dev = data;
1580 struct ace_private *ap = netdev_priv(dev);
1581 struct ace_regs __iomem *regs = ap->regs;
1582
1583 /*
1584 * We haven't received a stats update event for more than 2.5
1585 * seconds and there is data in the transmit queue, thus we
1586 * asume the card is stuck.
1587 */
1588 if (*ap->tx_csm != ap->tx_ret_csm) {
1589 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1590 dev->name, (unsigned int)readl(&regs->HostCtrl));
1591 /* This can happen due to ieee flow control. */
1592 } else {
1593 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1594 dev->name);
1595#if 0
1596 netif_wake_queue(dev);
1597#endif
1598 }
1599}
1600
1601
1602static void ace_tasklet(unsigned long dev)
1603{
1604 struct ace_private *ap = netdev_priv((struct net_device *)dev);
1605 int cur_size;
1606
1607 cur_size = atomic_read(&ap->cur_rx_bufs);
1608 if ((cur_size < RX_LOW_STD_THRES) &&
1609 !test_and_set_bit(0, &ap->std_refill_busy)) {
1610#ifdef DEBUG
1611 printk("refilling buffers (current %i)\n", cur_size);
1612#endif
1613 ace_load_std_rx_ring(ap, RX_RING_SIZE - cur_size);
1614 }
1615
1616 if (ap->version >= 2) {
1617 cur_size = atomic_read(&ap->cur_mini_bufs);
1618 if ((cur_size < RX_LOW_MINI_THRES) &&
1619 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1620#ifdef DEBUG
1621 printk("refilling mini buffers (current %i)\n",
1622 cur_size);
1623#endif
1624 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
1625 }
1626 }
1627
1628 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1629 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1630 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1631#ifdef DEBUG
1632 printk("refilling jumbo buffers (current %i)\n", cur_size);
1633#endif
1634 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
1635 }
1636 ap->tasklet_pending = 0;
1637}
1638
1639
1640/*
1641 * Copy the contents of the NIC's trace buffer to kernel memory.
1642 */
1643static void ace_dump_trace(struct ace_private *ap)
1644{
1645#if 0
1646 if (!ap->trace_buf)
1647 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1648 return;
1649#endif
1650}
1651
1652
1653/*
1654 * Load the standard rx ring.
1655 *
1656 * Loading rings is safe without holding the spin lock since this is
1657 * done only before the device is enabled, thus no interrupts are
1658 * generated and by the interrupt handler/tasklet handler.
1659 */
1660static void ace_load_std_rx_ring(struct ace_private *ap, int nr_bufs)
1661{
1662 struct ace_regs __iomem *regs = ap->regs;
1663 short i, idx;
6aa20a22 1664
1da177e4
LT		 1665
1666 prefetchw(&ap->cur_rx_bufs);
1667
1668 idx = ap->rx_std_skbprd;
1669
1670 for (i = 0; i < nr_bufs; i++) {
1671 struct sk_buff *skb;
1672 struct rx_desc *rd;
1673 dma_addr_t mapping;
1674
1675 skb = alloc_skb(ACE_STD_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1676 if (!skb)
1677 break;
1678
1679 skb_reserve(skb, NET_IP_ALIGN);
1680 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1681 offset_in_page(skb->data),
1682 ACE_STD_BUFSIZE,
1683 PCI_DMA_FROMDEVICE);
1684 ap->skb->rx_std_skbuff[idx].skb = skb;
1685 pci_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1686 mapping, mapping);
1687
1688 rd = &ap->rx_std_ring[idx];
1689 set_aceaddr(&rd->addr, mapping);
1690 rd->size = ACE_STD_BUFSIZE;
1691 rd->idx = idx;
1692 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1693 }
1694
1695 if (!i)
1696 goto error_out;
1697
1698 atomic_add(i, &ap->cur_rx_bufs);
1699 ap->rx_std_skbprd = idx;
1700
1701 if (ACE_IS_TIGON_I(ap)) {
1702 struct cmd cmd;
1703 cmd.evt = C_SET_RX_PRD_IDX;
1704 cmd.code = 0;
1705 cmd.idx = ap->rx_std_skbprd;
1706 ace_issue_cmd(regs, &cmd);
1707 } else {
1708 writel(idx, &regs->RxStdPrd);
1709 wmb();
1710 }
1711
1712 out:
1713 clear_bit(0, &ap->std_refill_busy);
1714 return;
1715
1716 error_out:
1717 printk(KERN_INFO "Out of memory when allocating "
1718 "standard receive buffers\n");
1719 goto out;
1720}
1721
1722
1723static void ace_load_mini_rx_ring(struct ace_private *ap, int nr_bufs)
1724{
1725 struct ace_regs __iomem *regs = ap->regs;
1726 short i, idx;
1727
1728 prefetchw(&ap->cur_mini_bufs);
1729
1730 idx = ap->rx_mini_skbprd;
1731 for (i = 0; i < nr_bufs; i++) {
1732 struct sk_buff *skb;
1733 struct rx_desc *rd;
1734 dma_addr_t mapping;
1735
1736 skb = alloc_skb(ACE_MINI_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1737 if (!skb)
1738 break;
1739
1740 skb_reserve(skb, NET_IP_ALIGN);
1741 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1742 offset_in_page(skb->data),
1743 ACE_MINI_BUFSIZE,
1744 PCI_DMA_FROMDEVICE);
1745 ap->skb->rx_mini_skbuff[idx].skb = skb;
1746 pci_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1747 mapping, mapping);
1748
1749 rd = &ap->rx_mini_ring[idx];
1750 set_aceaddr(&rd->addr, mapping);
1751 rd->size = ACE_MINI_BUFSIZE;
1752 rd->idx = idx;
1753 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1754 }
1755
1756 if (!i)
1757 goto error_out;
1758
1759 atomic_add(i, &ap->cur_mini_bufs);
1760
1761 ap->rx_mini_skbprd = idx;
1762
1763 writel(idx, &regs->RxMiniPrd);
1764 wmb();
1765
1766 out:
1767 clear_bit(0, &ap->mini_refill_busy);
1768 return;
1769 error_out:
1770 printk(KERN_INFO "Out of memory when allocating "
1771 "mini receive buffers\n");
1772 goto out;
1773}
1774
1775
1776/*
1777 * Load the jumbo rx ring, this may happen at any time if the MTU
1778 * is changed to a value > 1500.
1779 */
1780static void ace_load_jumbo_rx_ring(struct ace_private *ap, int nr_bufs)
1781{
1782 struct ace_regs __iomem *regs = ap->regs;
1783 short i, idx;
1784
1785 idx = ap->rx_jumbo_skbprd;
1786
1787 for (i = 0; i < nr_bufs; i++) {
1788 struct sk_buff *skb;
1789 struct rx_desc *rd;
1790 dma_addr_t mapping;
1791
1792 skb = alloc_skb(ACE_JUMBO_BUFSIZE + NET_IP_ALIGN, GFP_ATOMIC);
1793 if (!skb)
1794 break;
1795
1796 skb_reserve(skb, NET_IP_ALIGN);
1797 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1798 offset_in_page(skb->data),
1799 ACE_JUMBO_BUFSIZE,
1800 PCI_DMA_FROMDEVICE);
1801 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1802 pci_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1803 mapping, mapping);
1804
1805 rd = &ap->rx_jumbo_ring[idx];
1806 set_aceaddr(&rd->addr, mapping);
1807 rd->size = ACE_JUMBO_BUFSIZE;
1808 rd->idx = idx;
1809 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1810 }
1811
1812 if (!i)
1813 goto error_out;
1814
1815 atomic_add(i, &ap->cur_jumbo_bufs);
1816 ap->rx_jumbo_skbprd = idx;
1817
1818 if (ACE_IS_TIGON_I(ap)) {
1819 struct cmd cmd;
1820 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1821 cmd.code = 0;
1822 cmd.idx = ap->rx_jumbo_skbprd;
1823 ace_issue_cmd(regs, &cmd);
1824 } else {
1825 writel(idx, &regs->RxJumboPrd);
1826 wmb();
1827 }
1828
1829 out:
1830 clear_bit(0, &ap->jumbo_refill_busy);
1831 return;
1832 error_out:
1833 if (net_ratelimit())
1834 printk(KERN_INFO "Out of memory when allocating "
1835 "jumbo receive buffers\n");
1836 goto out;
1837}
1838
1839
1840/*
1841 * All events are considered to be slow (RX/TX ints do not generate
1842 * events) and are handled here, outside the main interrupt handler,
1843 * to reduce the size of the handler.
1844 */
1845static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1846{
1847 struct ace_private *ap;
1848
1849 ap = netdev_priv(dev);
1850
1851 while (evtcsm != evtprd) {
1852 switch (ap->evt_ring[evtcsm].evt) {
1853 case E_FW_RUNNING:
1854 printk(KERN_INFO "%s: Firmware up and running\n",
1855 ap->name);
1856 ap->fw_running = 1;
1857 wmb();
1858 break;
1859 case E_STATS_UPDATED:
1860 break;
1861 case E_LNK_STATE:
1862 {
1863 u16 code = ap->evt_ring[evtcsm].code;
1864 switch (code) {
1865 case E_C_LINK_UP:
1866 {
1867 u32 state = readl(&ap->regs->GigLnkState);
1868 printk(KERN_WARNING "%s: Optical link UP "
1869 "(%s Duplex, Flow Control: %s%s)\n",
1870 ap->name,
1871 state & LNK_FULL_DUPLEX ? "Full":"Half",
1872 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1873 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1874 break;
1875 }
1876 case E_C_LINK_DOWN:
1877 printk(KERN_WARNING "%s: Optical link DOWN\n",
1878 ap->name);
1879 break;
1880 case E_C_LINK_10_100:
1881 printk(KERN_WARNING "%s: 10/100BaseT link "
1882 "UP\n", ap->name);
1883 break;
1884 default:
1885 printk(KERN_ERR "%s: Unknown optical link "
1886 "state %02x\n", ap->name, code);
1887 }
1888 break;
1889 }
1890 case E_ERROR:
1891 switch(ap->evt_ring[evtcsm].code) {
1892 case E_C_ERR_INVAL_CMD:
1893 printk(KERN_ERR "%s: invalid command error\n",
1894 ap->name);
1895 break;
1896 case E_C_ERR_UNIMP_CMD:
1897 printk(KERN_ERR "%s: unimplemented command "
1898 "error\n", ap->name);
1899 break;
1900 case E_C_ERR_BAD_CFG:
1901 printk(KERN_ERR "%s: bad config error\n",
1902 ap->name);
1903 break;
1904 default:
1905 printk(KERN_ERR "%s: unknown error %02x\n",
1906 ap->name, ap->evt_ring[evtcsm].code);
1907 }
1908 break;
1909 case E_RESET_JUMBO_RNG:
1910 {
1911 int i;
1912 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1913 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1914 ap->rx_jumbo_ring[i].size = 0;
1915 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1916 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1917 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1918 }
1919 }
1920
1921 if (ACE_IS_TIGON_I(ap)) {
1922 struct cmd cmd;
1923 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1924 cmd.code = 0;
1925 cmd.idx = 0;
1926 ace_issue_cmd(ap->regs, &cmd);
1927 } else {
1928 writel(0, &((ap->regs)->RxJumboPrd));
1929 wmb();
1930 }
1931
1932 ap->jumbo = 0;
1933 ap->rx_jumbo_skbprd = 0;
1934 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1935 ap->name);
1936 clear_bit(0, &ap->jumbo_refill_busy);
1937 break;
1938 }
1939 default:
1940 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1941 ap->name, ap->evt_ring[evtcsm].evt);
1942 }
1943 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1944 }
1945
1946 return evtcsm;
1947}
1948
1949
1950static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1951{
1952 struct ace_private *ap = netdev_priv(dev);
1953 u32 idx;
1954 int mini_count = 0, std_count = 0;
1955
1956 idx = rxretcsm;
1957
1958 prefetchw(&ap->cur_rx_bufs);
1959 prefetchw(&ap->cur_mini_bufs);
6aa20a22 1960
1da177e4
LT		 1961 while (idx != rxretprd) {
1962 struct ring_info *rip;
1963 struct sk_buff *skb;
1964 struct rx_desc *rxdesc, *retdesc;
1965 u32 skbidx;
1966 int bd_flags, desc_type, mapsize;
1967 u16 csum;
1968
1969
1970 /* make sure the rx descriptor isn't read before rxretprd */
6aa20a22 1971 if (idx == rxretcsm)
1da177e4
LT		 1972 rmb();
1973
1974 retdesc = &ap->rx_return_ring[idx];
1975 skbidx = retdesc->idx;
1976 bd_flags = retdesc->flags;
1977 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1978
1979 switch(desc_type) {
1980 /*
1981 * Normal frames do not have any flags set
1982 *
1983 * Mini and normal frames arrive frequently,
1984 * so use a local counter to avoid doing
1985 * atomic operations for each packet arriving.
1986 */
1987 case 0:
1988 rip = &ap->skb->rx_std_skbuff[skbidx];
1989 mapsize = ACE_STD_BUFSIZE;
1990 rxdesc = &ap->rx_std_ring[skbidx];
1991 std_count++;
1992 break;
1993 case BD_FLG_JUMBO:
1994 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1995 mapsize = ACE_JUMBO_BUFSIZE;
1996 rxdesc = &ap->rx_jumbo_ring[skbidx];
1997 atomic_dec(&ap->cur_jumbo_bufs);
1998 break;
1999 case BD_FLG_MINI:
2000 rip = &ap->skb->rx_mini_skbuff[skbidx];
2001 mapsize = ACE_MINI_BUFSIZE;
2002 rxdesc = &ap->rx_mini_ring[skbidx];
6aa20a22 2003 mini_count++;
1da177e4
LT		 2004 break;
2005 default:
2006 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
2007 "returned by NIC\n", dev->name,
2008 retdesc->flags);
2009 goto error;
2010 }
2011
2012 skb = rip->skb;
2013 rip->skb = NULL;
2014 pci_unmap_page(ap->pdev,
2015 pci_unmap_addr(rip, mapping),
2016 mapsize,
2017 PCI_DMA_FROMDEVICE);
2018 skb_put(skb, retdesc->size);
2019
2020 /*
2021 * Fly baby, fly!
2022 */
2023 csum = retdesc->tcp_udp_csum;
2024
1da177e4
LT		 2025 skb->protocol = eth_type_trans(skb, dev);
2026
2027 /*
2028 * Instead of forcing the poor tigon mips cpu to calculate
2029 * pseudo hdr checksum, we do this ourselves.
2030 */
2031 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2032 skb->csum = htons(csum);
84fa7933 2033 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 2034 } else {
2035 skb->ip_summed = CHECKSUM_NONE;
2036 }
2037
2038 /* send it up */
2039#if ACENIC_DO_VLAN
2040 if (ap->vlgrp && (bd_flags & BD_FLG_VLAN_TAG)) {
2041 vlan_hwaccel_rx(skb, ap->vlgrp, retdesc->vlan);
2042 } else
2043#endif
2044 netif_rx(skb);
2045
966e37bc
PZ		 2046 dev->stats.rx_packets++;
2047 dev->stats.rx_bytes += retdesc->size;
1da177e4
LT		 2048
2049 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2050 }
2051
2052 atomic_sub(std_count, &ap->cur_rx_bufs);
2053 if (!ACE_IS_TIGON_I(ap))
2054 atomic_sub(mini_count, &ap->cur_mini_bufs);
2055
2056 out:
2057 /*
2058 * According to the documentation RxRetCsm is obsolete with
2059 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2060 */
2061 if (ACE_IS_TIGON_I(ap)) {
2062 writel(idx, &ap->regs->RxRetCsm);
2063 }
2064 ap->cur_rx = idx;
2065
2066 return;
2067 error:
2068 idx = rxretprd;
2069 goto out;
2070}
2071
2072
2073static inline void ace_tx_int(struct net_device *dev,
2074 u32 txcsm, u32 idx)
2075{
2076 struct ace_private *ap = netdev_priv(dev);
2077
2078 do {
2079 struct sk_buff *skb;
2080 dma_addr_t mapping;
2081 struct tx_ring_info *info;
2082
2083 info = ap->skb->tx_skbuff + idx;
2084 skb = info->skb;
2085 mapping = pci_unmap_addr(info, mapping);
2086
2087 if (mapping) {
2088 pci_unmap_page(ap->pdev, mapping,
2089 pci_unmap_len(info, maplen),
2090 PCI_DMA_TODEVICE);
2091 pci_unmap_addr_set(info, mapping, 0);
2092 }
2093
2094 if (skb) {
966e37bc
PZ		 2095 dev->stats.tx_packets++;
2096 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 2097 dev_kfree_skb_irq(skb);
2098 info->skb = NULL;
2099 }
2100
2101 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2102 } while (idx != txcsm);
2103
2104 if (netif_queue_stopped(dev))
2105 netif_wake_queue(dev);
2106
2107 wmb();
2108 ap->tx_ret_csm = txcsm;
2109
2110 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2111 *
2112 * We could try to make it before. In this case we would get
2113 * the following race condition: hard_start_xmit on other cpu
2114 * enters after we advanced tx_ret_csm and fills space,
2115 * which we have just freed, so that we make illegal device wakeup.
2116 * There is no good way to workaround this (at entry
2117 * to ace_start_xmit detects this condition and prevents
2118 * ring corruption, but it is not a good workaround.)
2119 *
2120 * When tx_ret_csm is advanced after, we wake up device _only_
2121 * if we really have some space in ring (though the core doing
2122 * hard_start_xmit can see full ring for some period and has to
2123 * synchronize.) Superb.
2124 * BUT! We get another subtle race condition. hard_start_xmit
2125 * may think that ring is full between wakeup and advancing
2126 * tx_ret_csm and will stop device instantly! It is not so bad.
2127 * We are guaranteed that there is something in ring, so that
2128 * the next irq will resume transmission. To speedup this we could
2129 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2130 * (see ace_start_xmit).
2131 *
2132 * Well, this dilemma exists in all lock-free devices.
2133 * We, following scheme used in drivers by Donald Becker,
2134 * select the least dangerous.
2135 * --ANK
2136 */
2137}
2138
2139
7d12e780 2140static irqreturn_t ace_interrupt(int irq, void *dev_id)
1da177e4
LT		 2141{
2142 struct net_device *dev = (struct net_device *)dev_id;
2143 struct ace_private *ap = netdev_priv(dev);
2144 struct ace_regs __iomem *regs = ap->regs;
2145 u32 idx;
2146 u32 txcsm, rxretcsm, rxretprd;
2147 u32 evtcsm, evtprd;
2148
2149 /*
2150 * In case of PCI shared interrupts or spurious interrupts,
2151 * we want to make sure it is actually our interrupt before
2152 * spending any time in here.
2153 */
2154 if (!(readl(&regs->HostCtrl) & IN_INT))
2155 return IRQ_NONE;
2156
2157 /*
2158 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2159 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2160 * writel(0, &regs->Mb0Lo).
2161 *
2162 * "IRQ avoidance" recommended in docs applies to IRQs served
2163 * threads and it is wrong even for that case.
2164 */
2165 writel(0, &regs->Mb0Lo);
2166 readl(&regs->Mb0Lo);
2167
2168 /*
2169 * There is no conflict between transmit handling in
2170 * start_xmit and receive processing, thus there is no reason
2171 * to take a spin lock for RX handling. Wait until we start
2172 * working on the other stuff - hey we don't need a spin lock
2173 * anymore.
2174 */
2175 rxretprd = *ap->rx_ret_prd;
2176 rxretcsm = ap->cur_rx;
2177
2178 if (rxretprd != rxretcsm)
2179 ace_rx_int(dev, rxretprd, rxretcsm);
2180
2181 txcsm = *ap->tx_csm;
2182 idx = ap->tx_ret_csm;
2183
2184 if (txcsm != idx) {
2185 /*
2186 * If each skb takes only one descriptor this check degenerates
2187 * to identity, because new space has just been opened.
2188 * But if skbs are fragmented we must check that this index
2189 * update releases enough of space, otherwise we just
2190 * wait for device to make more work.
2191 */
2192 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2193 ace_tx_int(dev, txcsm, idx);
2194 }
2195
2196 evtcsm = readl(&regs->EvtCsm);
2197 evtprd = *ap->evt_prd;
2198
2199 if (evtcsm != evtprd) {
2200 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2201 writel(evtcsm, &regs->EvtCsm);
2202 }
2203
2204 /*
2205 * This has to go last in the interrupt handler and run with
2206 * the spin lock released ... what lock?
2207 */
2208 if (netif_running(dev)) {
2209 int cur_size;
2210 int run_tasklet = 0;
2211
2212 cur_size = atomic_read(&ap->cur_rx_bufs);
2213 if (cur_size < RX_LOW_STD_THRES) {
2214 if ((cur_size < RX_PANIC_STD_THRES) &&
2215 !test_and_set_bit(0, &ap->std_refill_busy)) {
2216#ifdef DEBUG
2217 printk("low on std buffers %i\n", cur_size);
2218#endif
2219 ace_load_std_rx_ring(ap,
2220 RX_RING_SIZE - cur_size);
2221 } else
2222 run_tasklet = 1;
2223 }
2224
2225 if (!ACE_IS_TIGON_I(ap)) {
2226 cur_size = atomic_read(&ap->cur_mini_bufs);
2227 if (cur_size < RX_LOW_MINI_THRES) {
2228 if ((cur_size < RX_PANIC_MINI_THRES) &&
2229 !test_and_set_bit(0,
2230 &ap->mini_refill_busy)) {
2231#ifdef DEBUG
2232 printk("low on mini buffers %i\n",
2233 cur_size);
2234#endif
2235 ace_load_mini_rx_ring(ap, RX_MINI_SIZE - cur_size);
2236 } else
2237 run_tasklet = 1;
2238 }
2239 }
2240
2241 if (ap->jumbo) {
2242 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2243 if (cur_size < RX_LOW_JUMBO_THRES) {
2244 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2245 !test_and_set_bit(0,
2246 &ap->jumbo_refill_busy)){
2247#ifdef DEBUG
2248 printk("low on jumbo buffers %i\n",
2249 cur_size);
2250#endif
2251 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE - cur_size);
2252 } else
2253 run_tasklet = 1;
2254 }
2255 }
2256 if (run_tasklet && !ap->tasklet_pending) {
2257 ap->tasklet_pending = 1;
2258 tasklet_schedule(&ap->ace_tasklet);
2259 }
2260 }
2261
2262 return IRQ_HANDLED;
2263}
2264
2265
2266#if ACENIC_DO_VLAN
2267static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
2268{
2269 struct ace_private *ap = netdev_priv(dev);
2270 unsigned long flags;
2271
2272 local_irq_save(flags);
2273 ace_mask_irq(dev);
2274
2275 ap->vlgrp = grp;
2276
2277 ace_unmask_irq(dev);
2278 local_irq_restore(flags);
2279}
1da177e4
LT		 2280#endif /* ACENIC_DO_VLAN */
2281
2282
2283static int ace_open(struct net_device *dev)
2284{
2285 struct ace_private *ap = netdev_priv(dev);
2286 struct ace_regs __iomem *regs = ap->regs;
2287 struct cmd cmd;
2288
2289 if (!(ap->fw_running)) {
2290 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2291 return -EBUSY;
2292 }
2293
2294 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2295
2296 cmd.evt = C_CLEAR_STATS;
2297 cmd.code = 0;
2298 cmd.idx = 0;
2299 ace_issue_cmd(regs, &cmd);
2300
2301 cmd.evt = C_HOST_STATE;
2302 cmd.code = C_C_STACK_UP;
2303 cmd.idx = 0;
2304 ace_issue_cmd(regs, &cmd);
2305
2306 if (ap->jumbo &&
2307 !test_and_set_bit(0, &ap->jumbo_refill_busy))
2308 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2309
2310 if (dev->flags & IFF_PROMISC) {
2311 cmd.evt = C_SET_PROMISC_MODE;
2312 cmd.code = C_C_PROMISC_ENABLE;
2313 cmd.idx = 0;
2314 ace_issue_cmd(regs, &cmd);
2315
2316 ap->promisc = 1;
2317 }else
2318 ap->promisc = 0;
2319 ap->mcast_all = 0;
2320
2321#if 0
2322 cmd.evt = C_LNK_NEGOTIATION;
2323 cmd.code = 0;
2324 cmd.idx = 0;
2325 ace_issue_cmd(regs, &cmd);
2326#endif
2327
2328 netif_start_queue(dev);
2329
2330 /*
2331 * Setup the bottom half rx ring refill handler
2332 */
2333 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2334 return 0;
2335}
2336
2337
2338static int ace_close(struct net_device *dev)
2339{
2340 struct ace_private *ap = netdev_priv(dev);
2341 struct ace_regs __iomem *regs = ap->regs;
2342 struct cmd cmd;
2343 unsigned long flags;
2344 short i;
2345
2346 /*
2347 * Without (or before) releasing irq and stopping hardware, this
2348 * is an absolute non-sense, by the way. It will be reset instantly
2349 * by the first irq.
2350 */
2351 netif_stop_queue(dev);
2352
6aa20a22 2353
1da177e4
LT		 2354 if (ap->promisc) {
2355 cmd.evt = C_SET_PROMISC_MODE;
2356 cmd.code = C_C_PROMISC_DISABLE;
2357 cmd.idx = 0;
2358 ace_issue_cmd(regs, &cmd);
2359 ap->promisc = 0;
2360 }
2361
2362 cmd.evt = C_HOST_STATE;
2363 cmd.code = C_C_STACK_DOWN;
2364 cmd.idx = 0;
2365 ace_issue_cmd(regs, &cmd);
2366
2367 tasklet_kill(&ap->ace_tasklet);
2368
2369 /*
2370 * Make sure one CPU is not processing packets while
2371 * buffers are being released by another.
2372 */
2373
2374 local_irq_save(flags);
2375 ace_mask_irq(dev);
2376
2377 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2378 struct sk_buff *skb;
2379 dma_addr_t mapping;
2380 struct tx_ring_info *info;
2381
2382 info = ap->skb->tx_skbuff + i;
2383 skb = info->skb;
2384 mapping = pci_unmap_addr(info, mapping);
2385
2386 if (mapping) {
2387 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb
SH		 2388 /* NB: TIGON_1 is special, tx_ring is in io space */
2389 struct tx_desc __iomem *tx;
2390 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
1da177e4
LT		 2391 writel(0, &tx->addr.addrhi);
2392 writel(0, &tx->addr.addrlo);
2393 writel(0, &tx->flagsize);
2394 } else
2395 memset(ap->tx_ring + i, 0,
2396 sizeof(struct tx_desc));
2397 pci_unmap_page(ap->pdev, mapping,
2398 pci_unmap_len(info, maplen),
2399 PCI_DMA_TODEVICE);
2400 pci_unmap_addr_set(info, mapping, 0);
2401 }
2402 if (skb) {
2403 dev_kfree_skb(skb);
2404 info->skb = NULL;
2405 }
2406 }
2407
2408 if (ap->jumbo) {
2409 cmd.evt = C_RESET_JUMBO_RNG;
2410 cmd.code = 0;
2411 cmd.idx = 0;
2412 ace_issue_cmd(regs, &cmd);
2413 }
2414
2415 ace_unmask_irq(dev);
2416 local_irq_restore(flags);
2417
2418 return 0;
2419}
2420
2421
2422static inline dma_addr_t
2423ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2424 struct sk_buff *tail, u32 idx)
2425{
2426 dma_addr_t mapping;
2427 struct tx_ring_info *info;
2428
2429 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2430 offset_in_page(skb->data),
2431 skb->len, PCI_DMA_TODEVICE);
2432
2433 info = ap->skb->tx_skbuff + idx;
2434 info->skb = tail;
2435 pci_unmap_addr_set(info, mapping, mapping);
2436 pci_unmap_len_set(info, maplen, skb->len);
2437 return mapping;
2438}
2439
2440
2441static inline void
2442ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2443 u32 flagsize, u32 vlan_tag)
2444{
2445#if !USE_TX_COAL_NOW
2446 flagsize &= ~BD_FLG_COAL_NOW;
2447#endif
2448
2449 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 2450 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
1da177e4
LT		 2451 writel(addr >> 32, &io->addr.addrhi);
2452 writel(addr & 0xffffffff, &io->addr.addrlo);
2453 writel(flagsize, &io->flagsize);
2454#if ACENIC_DO_VLAN
2455 writel(vlan_tag, &io->vlanres);
2456#endif
2457 } else {
2458 desc->addr.addrhi = addr >> 32;
2459 desc->addr.addrlo = addr;
2460 desc->flagsize = flagsize;
2461#if ACENIC_DO_VLAN
2462 desc->vlanres = vlan_tag;
2463#endif
2464 }
2465}
2466
2467
61357325
SH		 2468static netdev_tx_t ace_start_xmit(struct sk_buff *skb,
2469 struct net_device *dev)
1da177e4
LT		 2470{
2471 struct ace_private *ap = netdev_priv(dev);
2472 struct ace_regs __iomem *regs = ap->regs;
2473 struct tx_desc *desc;
2474 u32 idx, flagsize;
2475 unsigned long maxjiff = jiffies + 3*HZ;
2476
2477restart:
2478 idx = ap->tx_prd;
2479
2480 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2481 goto overflow;
2482
2483 if (!skb_shinfo(skb)->nr_frags) {
2484 dma_addr_t mapping;
2485 u32 vlan_tag = 0;
2486
2487 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2488 flagsize = (skb->len << 16) | (BD_FLG_END);
84fa7933 2489 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2490 flagsize |= BD_FLG_TCP_UDP_SUM;
2491#if ACENIC_DO_VLAN
2492 if (vlan_tx_tag_present(skb)) {
2493 flagsize |= BD_FLG_VLAN_TAG;
2494 vlan_tag = vlan_tx_tag_get(skb);
2495 }
2496#endif
2497 desc = ap->tx_ring + idx;
2498 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2499
2500 /* Look at ace_tx_int for explanations. */
2501 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2502 flagsize |= BD_FLG_COAL_NOW;
2503
2504 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2505 } else {
2506 dma_addr_t mapping;
2507 u32 vlan_tag = 0;
2508 int i, len = 0;
2509
2510 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2511 flagsize = (skb_headlen(skb) << 16);
84fa7933 2512 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2513 flagsize |= BD_FLG_TCP_UDP_SUM;
2514#if ACENIC_DO_VLAN
2515 if (vlan_tx_tag_present(skb)) {
2516 flagsize |= BD_FLG_VLAN_TAG;
2517 vlan_tag = vlan_tx_tag_get(skb);
2518 }
2519#endif
2520
2521 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2522
2523 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2524
2525 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2526 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2527 struct tx_ring_info *info;
2528
2529 len += frag->size;
2530 info = ap->skb->tx_skbuff + idx;
2531 desc = ap->tx_ring + idx;
2532
2533 mapping = pci_map_page(ap->pdev, frag->page,
2534 frag->page_offset, frag->size,
2535 PCI_DMA_TODEVICE);
2536
2537 flagsize = (frag->size << 16);
84fa7933 2538 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2539 flagsize |= BD_FLG_TCP_UDP_SUM;
2540 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2541
2542 if (i == skb_shinfo(skb)->nr_frags - 1) {
2543 flagsize |= BD_FLG_END;
2544 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2545 flagsize |= BD_FLG_COAL_NOW;
2546
2547 /*
2548 * Only the last fragment frees
2549 * the skb!
2550 */
2551 info->skb = skb;
2552 } else {
2553 info->skb = NULL;
2554 }
2555 pci_unmap_addr_set(info, mapping, mapping);
2556 pci_unmap_len_set(info, maplen, frag->size);
2557 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2558 }
2559 }
2560
2561 wmb();
2562 ap->tx_prd = idx;
2563 ace_set_txprd(regs, ap, idx);
2564
2565 if (flagsize & BD_FLG_COAL_NOW) {
2566 netif_stop_queue(dev);
2567
2568 /*
2569 * A TX-descriptor producer (an IRQ) might have gotten
2570 * inbetween, making the ring free again. Since xmit is
2571 * serialized, this is the only situation we have to
2572 * re-test.
2573 */
2574 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2575 netif_wake_queue(dev);
2576 }
2577
1da177e4
LT		 2578 return NETDEV_TX_OK;
2579
2580overflow:
2581 /*
2582 * This race condition is unavoidable with lock-free drivers.
2583 * We wake up the queue _before_ tx_prd is advanced, so that we can
2584 * enter hard_start_xmit too early, while tx ring still looks closed.
2585 * This happens ~1-4 times per 100000 packets, so that we can allow
2586 * to loop syncing to other CPU. Probably, we need an additional
2587 * wmb() in ace_tx_intr as well.
2588 *
2589 * Note that this race is relieved by reserving one more entry
2590 * in tx ring than it is necessary (see original non-SG driver).
2591 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2592 * is already overkill.
2593 *
2594 * Alternative is to return with 1 not throttling queue. In this
2595 * case loop becomes longer, no more useful effects.
2596 */
2597 if (time_before(jiffies, maxjiff)) {
2598 barrier();
2599 cpu_relax();
2600 goto restart;
2601 }
6aa20a22 2602
1da177e4
LT		 2603 /* The ring is stuck full. */
2604 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2605 return NETDEV_TX_BUSY;
2606}
2607
2608
2609static int ace_change_mtu(struct net_device *dev, int new_mtu)
2610{
2611 struct ace_private *ap = netdev_priv(dev);
2612 struct ace_regs __iomem *regs = ap->regs;
2613
2614 if (new_mtu > ACE_JUMBO_MTU)
2615 return -EINVAL;
2616
2617 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2618 dev->mtu = new_mtu;
2619
2620 if (new_mtu > ACE_STD_MTU) {
2621 if (!(ap->jumbo)) {
2622 printk(KERN_INFO "%s: Enabling Jumbo frame "
2623 "support\n", dev->name);
2624 ap->jumbo = 1;
2625 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2626 ace_load_jumbo_rx_ring(ap, RX_JUMBO_SIZE);
2627 ace_set_rxtx_parms(dev, 1);
2628 }
2629 } else {
2630 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2631 ace_sync_irq(dev->irq);
2632 ace_set_rxtx_parms(dev, 0);
2633 if (ap->jumbo) {
2634 struct cmd cmd;
2635
2636 cmd.evt = C_RESET_JUMBO_RNG;
2637 cmd.code = 0;
2638 cmd.idx = 0;
2639 ace_issue_cmd(regs, &cmd);
2640 }
2641 }
2642
2643 return 0;
2644}
2645
2646static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2647{
2648 struct ace_private *ap = netdev_priv(dev);
2649 struct ace_regs __iomem *regs = ap->regs;
2650 u32 link;
2651
2652 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2653 ecmd->supported =
2654 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2655 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2656 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2657 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2658
2659 ecmd->port = PORT_FIBRE;
2660 ecmd->transceiver = XCVR_INTERNAL;
2661
2662 link = readl(&regs->GigLnkState);
2663 if (link & LNK_1000MB)
2664 ecmd->speed = SPEED_1000;
2665 else {
2666 link = readl(&regs->FastLnkState);
2667 if (link & LNK_100MB)
2668 ecmd->speed = SPEED_100;
2669 else if (link & LNK_10MB)
2670 ecmd->speed = SPEED_10;
2671 else
2672 ecmd->speed = 0;
2673 }
2674 if (link & LNK_FULL_DUPLEX)
2675 ecmd->duplex = DUPLEX_FULL;
2676 else
2677 ecmd->duplex = DUPLEX_HALF;
2678
2679 if (link & LNK_NEGOTIATE)
2680 ecmd->autoneg = AUTONEG_ENABLE;
2681 else
2682 ecmd->autoneg = AUTONEG_DISABLE;
2683
2684#if 0
2685 /*
2686 * Current struct ethtool_cmd is insufficient
2687 */
2688 ecmd->trace = readl(&regs->TuneTrace);
2689
2690 ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2691 ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2692#endif
2693 ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
2694 ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
2695
2696 return 0;
2697}
2698
2699static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2700{
2701 struct ace_private *ap = netdev_priv(dev);
2702 struct ace_regs __iomem *regs = ap->regs;
2703 u32 link, speed;
2704
2705 link = readl(&regs->GigLnkState);
2706 if (link & LNK_1000MB)
2707 speed = SPEED_1000;
2708 else {
2709 link = readl(&regs->FastLnkState);
2710 if (link & LNK_100MB)
2711 speed = SPEED_100;
2712 else if (link & LNK_10MB)
2713 speed = SPEED_10;
2714 else
2715 speed = SPEED_100;
2716 }
2717
2718 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2719 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2720 if (!ACE_IS_TIGON_I(ap))
2721 link |= LNK_TX_FLOW_CTL_Y;
2722 if (ecmd->autoneg == AUTONEG_ENABLE)
2723 link |= LNK_NEGOTIATE;
2724 if (ecmd->speed != speed) {
2725 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2726 switch (speed) {
2727 case SPEED_1000:
2728 link |= LNK_1000MB;
2729 break;
2730 case SPEED_100:
2731 link |= LNK_100MB;
2732 break;
2733 case SPEED_10:
2734 link |= LNK_10MB;
2735 break;
2736 }
2737 }
2738
2739 if (ecmd->duplex == DUPLEX_FULL)
2740 link |= LNK_FULL_DUPLEX;
2741
2742 if (link != ap->link) {
2743 struct cmd cmd;
2744 printk(KERN_INFO "%s: Renegotiating link state\n",
2745 dev->name);
2746
2747 ap->link = link;
2748 writel(link, &regs->TuneLink);
2749 if (!ACE_IS_TIGON_I(ap))
2750 writel(link, &regs->TuneFastLink);
2751 wmb();
2752
2753 cmd.evt = C_LNK_NEGOTIATION;
2754 cmd.code = 0;
2755 cmd.idx = 0;
2756 ace_issue_cmd(regs, &cmd);
2757 }
2758 return 0;
2759}
2760
6aa20a22 2761static void ace_get_drvinfo(struct net_device *dev,
1da177e4
LT		 2762 struct ethtool_drvinfo *info)
2763{
2764 struct ace_private *ap = netdev_priv(dev);
2765
2766 strlcpy(info->driver, "acenic", sizeof(info->driver));
6aa20a22 2767 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
949b4254
JS		 2768 ap->firmware_major, ap->firmware_minor,
2769 ap->firmware_fix);
1da177e4
LT		 2770
2771 if (ap->pdev)
6aa20a22 2772 strlcpy(info->bus_info, pci_name(ap->pdev),
1da177e4
LT		 2773 sizeof(info->bus_info));
2774
2775}
2776
2777/*
2778 * Set the hardware MAC address.
2779 */
2780static int ace_set_mac_addr(struct net_device *dev, void *p)
2781{
2782 struct ace_private *ap = netdev_priv(dev);
2783 struct ace_regs __iomem *regs = ap->regs;
2784 struct sockaddr *addr=p;
2785 u8 *da;
2786 struct cmd cmd;
2787
2788 if(netif_running(dev))
2789 return -EBUSY;
2790
2791 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2792
2793 da = (u8 *)dev->dev_addr;
2794
2795 writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2796 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2797 &regs->MacAddrLo);
2798
2799 cmd.evt = C_SET_MAC_ADDR;
2800 cmd.code = 0;
2801 cmd.idx = 0;
2802 ace_issue_cmd(regs, &cmd);
2803
2804 return 0;
2805}
2806
2807
2808static void ace_set_multicast_list(struct net_device *dev)
2809{
2810 struct ace_private *ap = netdev_priv(dev);
2811 struct ace_regs __iomem *regs = ap->regs;
2812 struct cmd cmd;
2813
2814 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2815 cmd.evt = C_SET_MULTICAST_MODE;
2816 cmd.code = C_C_MCAST_ENABLE;
2817 cmd.idx = 0;
2818 ace_issue_cmd(regs, &cmd);
2819 ap->mcast_all = 1;
2820 } else if (ap->mcast_all) {
2821 cmd.evt = C_SET_MULTICAST_MODE;
2822 cmd.code = C_C_MCAST_DISABLE;
2823 cmd.idx = 0;
2824 ace_issue_cmd(regs, &cmd);
2825 ap->mcast_all = 0;
2826 }
2827
2828 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2829 cmd.evt = C_SET_PROMISC_MODE;
2830 cmd.code = C_C_PROMISC_ENABLE;
2831 cmd.idx = 0;
2832 ace_issue_cmd(regs, &cmd);
2833 ap->promisc = 1;
2834 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2835 cmd.evt = C_SET_PROMISC_MODE;
2836 cmd.code = C_C_PROMISC_DISABLE;
2837 cmd.idx = 0;
2838 ace_issue_cmd(regs, &cmd);
2839 ap->promisc = 0;
2840 }
2841
2842 /*
2843 * For the time being multicast relies on the upper layers
2844 * filtering it properly. The Firmware does not allow one to
2845 * set the entire multicast list at a time and keeping track of
2846 * it here is going to be messy.
2847 */
2848 if ((dev->mc_count) && !(ap->mcast_all)) {
2849 cmd.evt = C_SET_MULTICAST_MODE;
2850 cmd.code = C_C_MCAST_ENABLE;
2851 cmd.idx = 0;
2852 ace_issue_cmd(regs, &cmd);
2853 }else if (!ap->mcast_all) {
2854 cmd.evt = C_SET_MULTICAST_MODE;
2855 cmd.code = C_C_MCAST_DISABLE;
2856 cmd.idx = 0;
2857 ace_issue_cmd(regs, &cmd);
2858 }
2859}
2860
2861
2862static struct net_device_stats *ace_get_stats(struct net_device *dev)
2863{
2864 struct ace_private *ap = netdev_priv(dev);
2865 struct ace_mac_stats __iomem *mac_stats =
2866 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2867
966e37bc
PZ		 2868 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2869 dev->stats.multicast = readl(&mac_stats->kept_mc);
2870 dev->stats.collisions = readl(&mac_stats->coll);
1da177e4 2871
966e37bc 2872 return &dev->stats;
1da177e4
LT		 2873}
2874
2875
949b4254
JS		 2876static void __devinit ace_copy(struct ace_regs __iomem *regs, const __be32 *src,
2877 u32 dest, int size)
1da177e4
LT		 2878{
2879 void __iomem *tdest;
1da177e4
LT		 2880 short tsize, i;
2881
2882 if (size <= 0)
2883 return;
2884
2885 while (size > 0) {
2886 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2887 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2888 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2889 (dest & (ACE_WINDOW_SIZE - 1));
2890 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
1da177e4 2891 for (i = 0; i < (tsize / 4); i++) {
949b4254
JS		 2892 /* Firmware is big-endian */
2893 writel(be32_to_cpup(src), tdest);
2894 src++;
2895 tdest += 4;
2896 dest += 4;
2897 size -= 4;
1da177e4 2898 }
1da177e4 2899 }
1da177e4
LT		 2900}
2901
2902
2903static void __devinit ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2904{
2905 void __iomem *tdest;
2906 short tsize = 0, i;
2907
2908 if (size <= 0)
2909 return;
2910
2911 while (size > 0) {
2912 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2913 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2914 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2915 (dest & (ACE_WINDOW_SIZE - 1));
2916 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2917
2918 for (i = 0; i < (tsize / 4); i++) {
2919 writel(0, tdest + i*4);
2920 }
2921
2922 dest += tsize;
2923 size -= tsize;
2924 }
2925
2926 return;
2927}
2928
2929
2930/*
2931 * Download the firmware into the SRAM on the NIC
2932 *
2933 * This operation requires the NIC to be halted and is performed with
2934 * interrupts disabled and with the spinlock hold.
2935 */
ddfce6bb 2936static int __devinit ace_load_firmware(struct net_device *dev)
1da177e4 2937{
949b4254
JS		 2938 const struct firmware *fw;
2939 const char *fw_name = "acenic/tg2.bin";
1da177e4
LT		 2940 struct ace_private *ap = netdev_priv(dev);
2941 struct ace_regs __iomem *regs = ap->regs;
949b4254
JS		 2942 const __be32 *fw_data;
2943 u32 load_addr;
2944 int ret;
1da177e4
LT		 2945
2946 if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2947 printk(KERN_ERR "%s: trying to download firmware while the "
2948 "CPU is running!\n", ap->name);
2949 return -EFAULT;
2950 }
2951
949b4254
JS		 2952 if (ACE_IS_TIGON_I(ap))
2953 fw_name = "acenic/tg1.bin";
2954
2955 ret = request_firmware(&fw, fw_name, &ap->pdev->dev);
2956 if (ret) {
2957 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
2958 ap->name, fw_name);
2959 return ret;
2960 }
2961
2962 fw_data = (void *)fw->data;
2963
2964 /* Firmware blob starts with version numbers, followed by
2965 load and start address. Remainder is the blob to be loaded
2966 contiguously from load address. We don't bother to represent
2967 the BSS/SBSS sections any more, since we were clearing the
2968 whole thing anyway. */
2969 ap->firmware_major = fw->data[0];
2970 ap->firmware_minor = fw->data[1];
2971 ap->firmware_fix = fw->data[2];
2972
2973 ap->firmware_start = be32_to_cpu(fw_data[1]);
2974 if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) {
2975 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2976 ap->name, ap->firmware_start, fw_name);
2977 ret = -EINVAL;
2978 goto out;
2979 }
2980
2981 load_addr = be32_to_cpu(fw_data[2]);
2982 if (load_addr < 0x4000 || load_addr >= 0x80000) {
2983 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2984 ap->name, load_addr, fw_name);
2985 ret = -EINVAL;
2986 goto out;
2987 }
2988
1da177e4 2989 /*
949b4254
JS		 2990 * Do not try to clear more than 512KiB or we end up seeing
2991 * funny things on NICs with only 512KiB SRAM
1da177e4
LT		 2992 */
2993 ace_clear(regs, 0x2000, 0x80000-0x2000);
949b4254
JS		 2994 ace_copy(regs, &fw_data[3], load_addr, fw->size-12);
2995 out:
2996 release_firmware(fw);
2997 return ret;
1da177e4
LT		 2998}
2999
3000
3001/*
3002 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
3003 *
3004 * Accessing the EEPROM is `interesting' to say the least - don't read
3005 * this code right after dinner.
3006 *
3007 * This is all about black magic and bit-banging the device .... I
3008 * wonder in what hospital they have put the guy who designed the i2c
3009 * specs.
3010 *
3011 * Oh yes, this is only the beginning!
3012 *
3013 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
3014 * code i2c readout code by beta testing all my hacks.
3015 */
3016static void __devinit eeprom_start(struct ace_regs __iomem *regs)
3017{
3018 u32 local;
3019
3020 readl(&regs->LocalCtrl);
3021 udelay(ACE_SHORT_DELAY);
3022 local = readl(&regs->LocalCtrl);
3023 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
3024 writel(local, &regs->LocalCtrl);
3025 readl(&regs->LocalCtrl);
3026 mb();
3027 udelay(ACE_SHORT_DELAY);
3028 local |= EEPROM_CLK_OUT;
3029 writel(local, &regs->LocalCtrl);
3030 readl(&regs->LocalCtrl);
3031 mb();
3032 udelay(ACE_SHORT_DELAY);
3033 local &= ~EEPROM_DATA_OUT;
3034 writel(local, &regs->LocalCtrl);
3035 readl(&regs->LocalCtrl);
3036 mb();
3037 udelay(ACE_SHORT_DELAY);
3038 local &= ~EEPROM_CLK_OUT;
3039 writel(local, &regs->LocalCtrl);
3040 readl(&regs->LocalCtrl);
3041 mb();
3042}
3043
3044
3045static void __devinit eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
3046{
3047 short i;
3048 u32 local;
3049
3050 udelay(ACE_SHORT_DELAY);
3051 local = readl(&regs->LocalCtrl);
3052 local &= ~EEPROM_DATA_OUT;
3053 local |= EEPROM_WRITE_ENABLE;
3054 writel(local, &regs->LocalCtrl);
3055 readl(&regs->LocalCtrl);
3056 mb();
3057
3058 for (i = 0; i < 8; i++, magic <<= 1) {
3059 udelay(ACE_SHORT_DELAY);
6aa20a22 3060 if (magic & 0x80)
1da177e4
LT		 3061 local |= EEPROM_DATA_OUT;
3062 else
3063 local &= ~EEPROM_DATA_OUT;
3064 writel(local, &regs->LocalCtrl);
3065 readl(&regs->LocalCtrl);
3066 mb();
3067
3068 udelay(ACE_SHORT_DELAY);
3069 local |= EEPROM_CLK_OUT;
3070 writel(local, &regs->LocalCtrl);
3071 readl(&regs->LocalCtrl);
3072 mb();
3073 udelay(ACE_SHORT_DELAY);
3074 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3075 writel(local, &regs->LocalCtrl);
3076 readl(&regs->LocalCtrl);
3077 mb();
3078 }
3079}
3080
3081
3082static int __devinit eeprom_check_ack(struct ace_regs __iomem *regs)
3083{
3084 int state;
3085 u32 local;
3086
3087 local = readl(&regs->LocalCtrl);
3088 local &= ~EEPROM_WRITE_ENABLE;
3089 writel(local, &regs->LocalCtrl);
3090 readl(&regs->LocalCtrl);
3091 mb();
3092 udelay(ACE_LONG_DELAY);
3093 local |= EEPROM_CLK_OUT;
3094 writel(local, &regs->LocalCtrl);
3095 readl(&regs->LocalCtrl);
3096 mb();
3097 udelay(ACE_SHORT_DELAY);
3098 /* sample data in middle of high clk */
3099 state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3100 udelay(ACE_SHORT_DELAY);
3101 mb();
3102 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3103 readl(&regs->LocalCtrl);
3104 mb();
3105
3106 return state;
3107}
3108
3109
3110static void __devinit eeprom_stop(struct ace_regs __iomem *regs)
3111{
3112 u32 local;
3113
3114 udelay(ACE_SHORT_DELAY);
3115 local = readl(&regs->LocalCtrl);
3116 local |= EEPROM_WRITE_ENABLE;
3117 writel(local, &regs->LocalCtrl);
3118 readl(&regs->LocalCtrl);
3119 mb();
3120 udelay(ACE_SHORT_DELAY);
3121 local &= ~EEPROM_DATA_OUT;
3122 writel(local, &regs->LocalCtrl);
3123 readl(&regs->LocalCtrl);
3124 mb();
3125 udelay(ACE_SHORT_DELAY);
3126 local |= EEPROM_CLK_OUT;
3127 writel(local, &regs->LocalCtrl);
3128 readl(&regs->LocalCtrl);
3129 mb();
3130 udelay(ACE_SHORT_DELAY);
3131 local |= EEPROM_DATA_OUT;
3132 writel(local, &regs->LocalCtrl);
3133 readl(&regs->LocalCtrl);
3134 mb();
3135 udelay(ACE_LONG_DELAY);
3136 local &= ~EEPROM_CLK_OUT;
3137 writel(local, &regs->LocalCtrl);
3138 mb();
3139}
3140
3141
3142/*
3143 * Read a whole byte from the EEPROM.
3144 */
3145static int __devinit read_eeprom_byte(struct net_device *dev,
3146 unsigned long offset)
3147{
3148 struct ace_private *ap = netdev_priv(dev);
3149 struct ace_regs __iomem *regs = ap->regs;
3150 unsigned long flags;
3151 u32 local;
3152 int result = 0;
3153 short i;
3154
1da177e4
LT		 3155 /*
3156 * Don't take interrupts on this CPU will bit banging
3157 * the %#%#@$ I2C device
3158 */
3159 local_irq_save(flags);
3160
3161 eeprom_start(regs);
3162
3163 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3164 if (eeprom_check_ack(regs)) {
3165 local_irq_restore(flags);
3166 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3167 result = -EIO;
3168 goto eeprom_read_error;
3169 }
3170
3171 eeprom_prep(regs, (offset >> 8) & 0xff);
3172 if (eeprom_check_ack(regs)) {
3173 local_irq_restore(flags);
3174 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3175 ap->name);
3176 result = -EIO;
3177 goto eeprom_read_error;
3178 }
3179
3180 eeprom_prep(regs, offset & 0xff);
3181 if (eeprom_check_ack(regs)) {
3182 local_irq_restore(flags);
3183 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3184 ap->name);
3185 result = -EIO;
3186 goto eeprom_read_error;
3187 }
3188
3189 eeprom_start(regs);
3190 eeprom_prep(regs, EEPROM_READ_SELECT);
3191 if (eeprom_check_ack(regs)) {
3192 local_irq_restore(flags);
3193 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3194 ap->name);
3195 result = -EIO;
3196 goto eeprom_read_error;
3197 }
3198
3199 for (i = 0; i < 8; i++) {
3200 local = readl(&regs->LocalCtrl);
3201 local &= ~EEPROM_WRITE_ENABLE;
3202 writel(local, &regs->LocalCtrl);
3203 readl(&regs->LocalCtrl);
3204 udelay(ACE_LONG_DELAY);
3205 mb();
3206 local |= EEPROM_CLK_OUT;
3207 writel(local, &regs->LocalCtrl);
3208 readl(&regs->LocalCtrl);
3209 mb();
3210 udelay(ACE_SHORT_DELAY);
3211 /* sample data mid high clk */
3212 result = (result << 1) |
3213 ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3214 udelay(ACE_SHORT_DELAY);
3215 mb();
3216 local = readl(&regs->LocalCtrl);
3217 local &= ~EEPROM_CLK_OUT;
3218 writel(local, &regs->LocalCtrl);
3219 readl(&regs->LocalCtrl);
3220 udelay(ACE_SHORT_DELAY);
3221 mb();
3222 if (i == 7) {
3223 local |= EEPROM_WRITE_ENABLE;
3224 writel(local, &regs->LocalCtrl);
3225 readl(&regs->LocalCtrl);
3226 mb();
3227 udelay(ACE_SHORT_DELAY);
3228 }
3229 }
3230
3231 local |= EEPROM_DATA_OUT;
3232 writel(local, &regs->LocalCtrl);
3233 readl(&regs->LocalCtrl);
3234 mb();
3235 udelay(ACE_SHORT_DELAY);
3236 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3237 readl(&regs->LocalCtrl);
3238 udelay(ACE_LONG_DELAY);
3239 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3240 readl(&regs->LocalCtrl);
3241 mb();
3242 udelay(ACE_SHORT_DELAY);
3243 eeprom_stop(regs);
3244
3245 local_irq_restore(flags);
3246 out:
3247 return result;
3248
3249 eeprom_read_error:
3250 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3251 ap->name, offset);
3252 goto out;
3253}
Clone of davem's net-next-2.6 tree