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Massive net driver const-ification.
[net-next-2.6.git] / drivers / net / 8139cp.c
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1da177e4
LT		 1/* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2/*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
30
31 Low priority TODO:
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
39 Tx descriptor bit
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
43
44 NOTES:
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
47
48 */
49
50#define DRV_NAME "8139cp"
51#define DRV_VERSION "1.2"
52#define DRV_RELDATE "Mar 22, 2004"
53
54
55#include <linux/config.h>
56#include <linux/module.h>
e21ba282 57#include <linux/moduleparam.h>
1da177e4
LT		 58#include <linux/kernel.h>
59#include <linux/compiler.h>
60#include <linux/netdevice.h>
61#include <linux/etherdevice.h>
62#include <linux/init.h>
63#include <linux/pci.h>
8662d061 64#include <linux/dma-mapping.h>
1da177e4
LT		 65#include <linux/delay.h>
66#include <linux/ethtool.h>
67#include <linux/mii.h>
68#include <linux/if_vlan.h>
69#include <linux/crc32.h>
70#include <linux/in.h>
71#include <linux/ip.h>
72#include <linux/tcp.h>
73#include <linux/udp.h>
74#include <linux/cache.h>
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/uaccess.h>
78
79/* VLAN tagging feature enable/disable */
80#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
81#define CP_VLAN_TAG_USED 1
82#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
83 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
84#else
85#define CP_VLAN_TAG_USED 0
86#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
87 do { (tx_desc)->opts2 = 0; } while (0)
88#endif
89
90/* These identify the driver base version and may not be removed. */
91static char version[] =
92KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
93
94MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
95MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
a78d8927 96MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 97MODULE_LICENSE("GPL");
98
99static int debug = -1;
e21ba282 100module_param(debug, int, 0);
1da177e4
LT		 101MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
102
103/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
104 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
105static int multicast_filter_limit = 32;
e21ba282 106module_param(multicast_filter_limit, int, 0);
1da177e4
LT		 107MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
108
109#define PFX DRV_NAME ": "
110
111#ifndef TRUE
112#define FALSE 0
113#define TRUE (!FALSE)
114#endif
115
116#define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
117 NETIF_MSG_PROBE | \
118 NETIF_MSG_LINK)
119#define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
120#define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
121#define CP_REGS_SIZE (0xff + 1)
122#define CP_REGS_VER 1 /* version 1 */
123#define CP_RX_RING_SIZE 64
124#define CP_TX_RING_SIZE 64
125#define CP_RING_BYTES \
126 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
127 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
128 CP_STATS_SIZE)
129#define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
130#define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
131#define TX_BUFFS_AVAIL(CP) \
132 (((CP)->tx_tail <= (CP)->tx_head) ? \
133 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
134 (CP)->tx_tail - (CP)->tx_head - 1)
135
136#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
137#define RX_OFFSET 2
138#define CP_INTERNAL_PHY 32
139
140/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
141#define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
142#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
143#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
144#define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
145
146/* Time in jiffies before concluding the transmitter is hung. */
147#define TX_TIMEOUT (6*HZ)
148
149/* hardware minimum and maximum for a single frame's data payload */
150#define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
151#define CP_MAX_MTU 4096
152
153enum {
154 /* NIC register offsets */
155 MAC0 = 0x00, /* Ethernet hardware address. */
156 MAR0 = 0x08, /* Multicast filter. */
157 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
158 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
159 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
160 Cmd = 0x37, /* Command register */
161 IntrMask = 0x3C, /* Interrupt mask */
162 IntrStatus = 0x3E, /* Interrupt status */
163 TxConfig = 0x40, /* Tx configuration */
164 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
165 RxConfig = 0x44, /* Rx configuration */
166 RxMissed = 0x4C, /* 24 bits valid, write clears */
167 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
168 Config1 = 0x52, /* Config1 */
169 Config3 = 0x59, /* Config3 */
170 Config4 = 0x5A, /* Config4 */
171 MultiIntr = 0x5C, /* Multiple interrupt select */
172 BasicModeCtrl = 0x62, /* MII BMCR */
173 BasicModeStatus = 0x64, /* MII BMSR */
174 NWayAdvert = 0x66, /* MII ADVERTISE */
175 NWayLPAR = 0x68, /* MII LPA */
176 NWayExpansion = 0x6A, /* MII Expansion */
177 Config5 = 0xD8, /* Config5 */
178 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
179 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
180 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
181 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
182 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
183 TxThresh = 0xEC, /* Early Tx threshold */
184 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
185 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
186
187 /* Tx and Rx status descriptors */
188 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
189 RingEnd = (1 << 30), /* End of descriptor ring */
190 FirstFrag = (1 << 29), /* First segment of a packet */
191 LastFrag = (1 << 28), /* Final segment of a packet */
fcec3456
JG		 192 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
193 MSSShift = 16, /* MSS value position */
194 MSSMask = 0xfff, /* MSS value: 11 bits */
1da177e4
LT		 195 TxError = (1 << 23), /* Tx error summary */
196 RxError = (1 << 20), /* Rx error summary */
197 IPCS = (1 << 18), /* Calculate IP checksum */
198 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
199 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
200 TxVlanTag = (1 << 17), /* Add VLAN tag */
201 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
202 IPFail = (1 << 15), /* IP checksum failed */
203 UDPFail = (1 << 14), /* UDP/IP checksum failed */
204 TCPFail = (1 << 13), /* TCP/IP checksum failed */
205 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
206 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
207 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
208 RxProtoTCP = 1,
209 RxProtoUDP = 2,
210 RxProtoIP = 3,
211 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
212 TxOWC = (1 << 22), /* Tx Out-of-window collision */
213 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
214 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
215 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
216 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
217 RxErrFrame = (1 << 27), /* Rx frame alignment error */
218 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
219 RxErrCRC = (1 << 18), /* Rx CRC error */
220 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
221 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
222 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
223
224 /* StatsAddr register */
225 DumpStats = (1 << 3), /* Begin stats dump */
226
227 /* RxConfig register */
228 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
229 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
230 AcceptErr = 0x20, /* Accept packets with CRC errors */
231 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
232 AcceptBroadcast = 0x08, /* Accept broadcast packets */
233 AcceptMulticast = 0x04, /* Accept multicast packets */
234 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
235 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
236
237 /* IntrMask / IntrStatus registers */
238 PciErr = (1 << 15), /* System error on the PCI bus */
239 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
240 LenChg = (1 << 13), /* Cable length change */
241 SWInt = (1 << 8), /* Software-requested interrupt */
242 TxEmpty = (1 << 7), /* No Tx descriptors available */
243 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
244 LinkChg = (1 << 5), /* Packet underrun, or link change */
245 RxEmpty = (1 << 4), /* No Rx descriptors available */
246 TxErr = (1 << 3), /* Tx error */
247 TxOK = (1 << 2), /* Tx packet sent */
248 RxErr = (1 << 1), /* Rx error */
249 RxOK = (1 << 0), /* Rx packet received */
250 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
251 but hardware likes to raise it */
252
253 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
254 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
255 RxErr | RxOK | IntrResvd,
256
257 /* C mode command register */
258 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
259 RxOn = (1 << 3), /* Rx mode enable */
260 TxOn = (1 << 2), /* Tx mode enable */
261
262 /* C+ mode command register */
263 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
264 RxChkSum = (1 << 5), /* Rx checksum offload enable */
265 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
266 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
267 CpRxOn = (1 << 1), /* Rx mode enable */
268 CpTxOn = (1 << 0), /* Tx mode enable */
269
270 /* Cfg9436 EEPROM control register */
271 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
272 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
273
274 /* TxConfig register */
275 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
276 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
277
278 /* Early Tx Threshold register */
279 TxThreshMask = 0x3f, /* Mask bits 5-0 */
280 TxThreshMax = 2048, /* Max early Tx threshold */
281
282 /* Config1 register */
283 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
284 LWACT = (1 << 4), /* LWAKE active mode */
285 PMEnable = (1 << 0), /* Enable various PM features of chip */
286
287 /* Config3 register */
288 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
289 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
290 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
291
292 /* Config4 register */
293 LWPTN = (1 << 1), /* LWAKE Pattern */
294 LWPME = (1 << 4), /* LANWAKE vs PMEB */
295
296 /* Config5 register */
297 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
298 MWF = (1 << 5), /* Accept Multicast wakeup frame */
299 UWF = (1 << 4), /* Accept Unicast wakeup frame */
300 LANWake = (1 << 1), /* Enable LANWake signal */
301 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
302
303 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
304 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
305 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
306};
307
308static const unsigned int cp_rx_config =
309 (RX_FIFO_THRESH << RxCfgFIFOShift) |
310 (RX_DMA_BURST << RxCfgDMAShift);
311
312struct cp_desc {
313 u32 opts1;
314 u32 opts2;
315 u64 addr;
316};
317
318struct ring_info {
319 struct sk_buff *skb;
320 dma_addr_t mapping;
5734418d 321 u32 len;
1da177e4
LT		 322};
323
324struct cp_dma_stats {
325 u64 tx_ok;
326 u64 rx_ok;
327 u64 tx_err;
328 u32 rx_err;
329 u16 rx_fifo;
330 u16 frame_align;
331 u32 tx_ok_1col;
332 u32 tx_ok_mcol;
333 u64 rx_ok_phys;
334 u64 rx_ok_bcast;
335 u32 rx_ok_mcast;
336 u16 tx_abort;
337 u16 tx_underrun;
338} __attribute__((packed));
339
340struct cp_extra_stats {
341 unsigned long rx_frags;
342};
343
344struct cp_private {
345 void __iomem *regs;
346 struct net_device *dev;
347 spinlock_t lock;
348 u32 msg_enable;
349
350 struct pci_dev *pdev;
351 u32 rx_config;
352 u16 cpcmd;
353
354 struct net_device_stats net_stats;
355 struct cp_extra_stats cp_stats;
1da177e4
LT		 356
357 unsigned rx_tail ____cacheline_aligned;
358 struct cp_desc *rx_ring;
359 struct ring_info rx_skb[CP_RX_RING_SIZE];
360 unsigned rx_buf_sz;
361
362 unsigned tx_head ____cacheline_aligned;
363 unsigned tx_tail;
364
365 struct cp_desc *tx_ring;
366 struct ring_info tx_skb[CP_TX_RING_SIZE];
367 dma_addr_t ring_dma;
368
369#if CP_VLAN_TAG_USED
370 struct vlan_group *vlgrp;
371#endif
372
373 unsigned int wol_enabled : 1; /* Is Wake-on-LAN enabled? */
374
375 struct mii_if_info mii_if;
376};
377
378#define cpr8(reg) readb(cp->regs + (reg))
379#define cpr16(reg) readw(cp->regs + (reg))
380#define cpr32(reg) readl(cp->regs + (reg))
381#define cpw8(reg,val) writeb((val), cp->regs + (reg))
382#define cpw16(reg,val) writew((val), cp->regs + (reg))
383#define cpw32(reg,val) writel((val), cp->regs + (reg))
384#define cpw8_f(reg,val) do { \
385 writeb((val), cp->regs + (reg)); \
386 readb(cp->regs + (reg)); \
387 } while (0)
388#define cpw16_f(reg,val) do { \
389 writew((val), cp->regs + (reg)); \
390 readw(cp->regs + (reg)); \
391 } while (0)
392#define cpw32_f(reg,val) do { \
393 writel((val), cp->regs + (reg)); \
394 readl(cp->regs + (reg)); \
395 } while (0)
396
397
398static void __cp_set_rx_mode (struct net_device *dev);
399static void cp_tx (struct cp_private *cp);
400static void cp_clean_rings (struct cp_private *cp);
7502cd10
SK		 401#ifdef CONFIG_NET_POLL_CONTROLLER
402static void cp_poll_controller(struct net_device *dev);
403#endif
1da177e4
LT		 404
405static struct pci_device_id cp_pci_tbl[] = {
406 { PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139,
407 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
408 { PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322,
409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
410 { },
411};
412MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
413
414static struct {
415 const char str[ETH_GSTRING_LEN];
416} ethtool_stats_keys[] = {
417 { "tx_ok" },
418 { "rx_ok" },
419 { "tx_err" },
420 { "rx_err" },
421 { "rx_fifo" },
422 { "frame_align" },
423 { "tx_ok_1col" },
424 { "tx_ok_mcol" },
425 { "rx_ok_phys" },
426 { "rx_ok_bcast" },
427 { "rx_ok_mcast" },
428 { "tx_abort" },
429 { "tx_underrun" },
430 { "rx_frags" },
431};
432
433
434#if CP_VLAN_TAG_USED
435static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
436{
437 struct cp_private *cp = netdev_priv(dev);
438 unsigned long flags;
439
440 spin_lock_irqsave(&cp->lock, flags);
441 cp->vlgrp = grp;
442 cp->cpcmd |= RxVlanOn;
443 cpw16(CpCmd, cp->cpcmd);
444 spin_unlock_irqrestore(&cp->lock, flags);
445}
446
447static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
448{
449 struct cp_private *cp = netdev_priv(dev);
450 unsigned long flags;
451
452 spin_lock_irqsave(&cp->lock, flags);
453 cp->cpcmd &= ~RxVlanOn;
454 cpw16(CpCmd, cp->cpcmd);
455 if (cp->vlgrp)
456 cp->vlgrp->vlan_devices[vid] = NULL;
457 spin_unlock_irqrestore(&cp->lock, flags);
458}
459#endif /* CP_VLAN_TAG_USED */
460
461static inline void cp_set_rxbufsize (struct cp_private *cp)
462{
463 unsigned int mtu = cp->dev->mtu;
464
465 if (mtu > ETH_DATA_LEN)
466 /* MTU + ethernet header + FCS + optional VLAN tag */
467 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
468 else
469 cp->rx_buf_sz = PKT_BUF_SZ;
470}
471
472static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
473 struct cp_desc *desc)
474{
475 skb->protocol = eth_type_trans (skb, cp->dev);
476
477 cp->net_stats.rx_packets++;
478 cp->net_stats.rx_bytes += skb->len;
479 cp->dev->last_rx = jiffies;
480
481#if CP_VLAN_TAG_USED
482 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
483 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
484 be16_to_cpu(desc->opts2 & 0xffff));
485 } else
486#endif
487 netif_receive_skb(skb);
488}
489
490static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
491 u32 status, u32 len)
492{
493 if (netif_msg_rx_err (cp))
494 printk (KERN_DEBUG
495 "%s: rx err, slot %d status 0x%x len %d\n",
496 cp->dev->name, rx_tail, status, len);
497 cp->net_stats.rx_errors++;
498 if (status & RxErrFrame)
499 cp->net_stats.rx_frame_errors++;
500 if (status & RxErrCRC)
501 cp->net_stats.rx_crc_errors++;
502 if ((status & RxErrRunt) || (status & RxErrLong))
503 cp->net_stats.rx_length_errors++;
504 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
505 cp->net_stats.rx_length_errors++;
506 if (status & RxErrFIFO)
507 cp->net_stats.rx_fifo_errors++;
508}
509
510static inline unsigned int cp_rx_csum_ok (u32 status)
511{
512 unsigned int protocol = (status >> 16) & 0x3;
513
514 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
515 return 1;
516 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
517 return 1;
518 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
519 return 1;
520 return 0;
521}
522
523static int cp_rx_poll (struct net_device *dev, int *budget)
524{
525 struct cp_private *cp = netdev_priv(dev);
526 unsigned rx_tail = cp->rx_tail;
527 unsigned rx_work = dev->quota;
528 unsigned rx;
529
530rx_status_loop:
531 rx = 0;
532 cpw16(IntrStatus, cp_rx_intr_mask);
533
534 while (1) {
535 u32 status, len;
536 dma_addr_t mapping;
537 struct sk_buff *skb, *new_skb;
538 struct cp_desc *desc;
539 unsigned buflen;
540
541 skb = cp->rx_skb[rx_tail].skb;
542 if (!skb)
543 BUG();
544
545 desc = &cp->rx_ring[rx_tail];
546 status = le32_to_cpu(desc->opts1);
547 if (status & DescOwn)
548 break;
549
550 len = (status & 0x1fff) - 4;
551 mapping = cp->rx_skb[rx_tail].mapping;
552
553 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
554 /* we don't support incoming fragmented frames.
555 * instead, we attempt to ensure that the
556 * pre-allocated RX skbs are properly sized such
557 * that RX fragments are never encountered
558 */
559 cp_rx_err_acct(cp, rx_tail, status, len);
560 cp->net_stats.rx_dropped++;
561 cp->cp_stats.rx_frags++;
562 goto rx_next;
563 }
564
565 if (status & (RxError | RxErrFIFO)) {
566 cp_rx_err_acct(cp, rx_tail, status, len);
567 goto rx_next;
568 }
569
570 if (netif_msg_rx_status(cp))
571 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
572 cp->dev->name, rx_tail, status, len);
573
574 buflen = cp->rx_buf_sz + RX_OFFSET;
575 new_skb = dev_alloc_skb (buflen);
576 if (!new_skb) {
577 cp->net_stats.rx_dropped++;
578 goto rx_next;
579 }
580
581 skb_reserve(new_skb, RX_OFFSET);
582 new_skb->dev = cp->dev;
583
584 pci_unmap_single(cp->pdev, mapping,
585 buflen, PCI_DMA_FROMDEVICE);
586
587 /* Handle checksum offloading for incoming packets. */
588 if (cp_rx_csum_ok(status))
589 skb->ip_summed = CHECKSUM_UNNECESSARY;
590 else
591 skb->ip_summed = CHECKSUM_NONE;
592
593 skb_put(skb, len);
594
595 mapping =
596 cp->rx_skb[rx_tail].mapping =
689be439 597 pci_map_single(cp->pdev, new_skb->data,
1da177e4
LT		 598 buflen, PCI_DMA_FROMDEVICE);
599 cp->rx_skb[rx_tail].skb = new_skb;
600
601 cp_rx_skb(cp, skb, desc);
602 rx++;
603
604rx_next:
605 cp->rx_ring[rx_tail].opts2 = 0;
606 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
607 if (rx_tail == (CP_RX_RING_SIZE - 1))
608 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
609 cp->rx_buf_sz);
610 else
611 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
612 rx_tail = NEXT_RX(rx_tail);
613
614 if (!rx_work--)
615 break;
616 }
617
618 cp->rx_tail = rx_tail;
619
620 dev->quota -= rx;
621 *budget -= rx;
622
623 /* if we did not reach work limit, then we're done with
624 * this round of polling
625 */
626 if (rx_work) {
627 if (cpr16(IntrStatus) & cp_rx_intr_mask)
628 goto rx_status_loop;
629
630 local_irq_disable();
631 cpw16_f(IntrMask, cp_intr_mask);
632 __netif_rx_complete(dev);
633 local_irq_enable();
634
635 return 0; /* done */
636 }
637
638 return 1; /* not done */
639}
640
641static irqreturn_t
642cp_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
643{
644 struct net_device *dev = dev_instance;
645 struct cp_private *cp;
646 u16 status;
647
648 if (unlikely(dev == NULL))
649 return IRQ_NONE;
650 cp = netdev_priv(dev);
651
652 status = cpr16(IntrStatus);
653 if (!status || (status == 0xFFFF))
654 return IRQ_NONE;
655
656 if (netif_msg_intr(cp))
657 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
658 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
659
660 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
661
662 spin_lock(&cp->lock);
663
664 /* close possible race's with dev_close */
665 if (unlikely(!netif_running(dev))) {
666 cpw16(IntrMask, 0);
667 spin_unlock(&cp->lock);
668 return IRQ_HANDLED;
669 }
670
671 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
672 if (netif_rx_schedule_prep(dev)) {
673 cpw16_f(IntrMask, cp_norx_intr_mask);
674 __netif_rx_schedule(dev);
675 }
676
677 if (status & (TxOK | TxErr | TxEmpty | SWInt))
678 cp_tx(cp);
679 if (status & LinkChg)
680 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
681
682 spin_unlock(&cp->lock);
683
684 if (status & PciErr) {
685 u16 pci_status;
686
687 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
688 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
689 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
690 dev->name, status, pci_status);
691
692 /* TODO: reset hardware */
693 }
694
695 return IRQ_HANDLED;
696}
697
7502cd10
SK		 698#ifdef CONFIG_NET_POLL_CONTROLLER
699/*
700 * Polling receive - used by netconsole and other diagnostic tools
701 * to allow network i/o with interrupts disabled.
702 */
703static void cp_poll_controller(struct net_device *dev)
704{
705 disable_irq(dev->irq);
706 cp_interrupt(dev->irq, dev, NULL);
707 enable_irq(dev->irq);
708}
709#endif
710
1da177e4
LT		 711static void cp_tx (struct cp_private *cp)
712{
713 unsigned tx_head = cp->tx_head;
714 unsigned tx_tail = cp->tx_tail;
715
716 while (tx_tail != tx_head) {
717 struct sk_buff *skb;
718 u32 status;
719
720 rmb();
721 status = le32_to_cpu(cp->tx_ring[tx_tail].opts1);
722 if (status & DescOwn)
723 break;
724
725 skb = cp->tx_skb[tx_tail].skb;
726 if (!skb)
727 BUG();
728
729 pci_unmap_single(cp->pdev, cp->tx_skb[tx_tail].mapping,
5734418d 730 cp->tx_skb[tx_tail].len, PCI_DMA_TODEVICE);
1da177e4
LT		 731
732 if (status & LastFrag) {
733 if (status & (TxError | TxFIFOUnder)) {
734 if (netif_msg_tx_err(cp))
735 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
736 cp->dev->name, status);
737 cp->net_stats.tx_errors++;
738 if (status & TxOWC)
739 cp->net_stats.tx_window_errors++;
740 if (status & TxMaxCol)
741 cp->net_stats.tx_aborted_errors++;
742 if (status & TxLinkFail)
743 cp->net_stats.tx_carrier_errors++;
744 if (status & TxFIFOUnder)
745 cp->net_stats.tx_fifo_errors++;
746 } else {
747 cp->net_stats.collisions +=
748 ((status >> TxColCntShift) & TxColCntMask);
749 cp->net_stats.tx_packets++;
750 cp->net_stats.tx_bytes += skb->len;
751 if (netif_msg_tx_done(cp))
752 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
753 }
754 dev_kfree_skb_irq(skb);
755 }
756
757 cp->tx_skb[tx_tail].skb = NULL;
758
759 tx_tail = NEXT_TX(tx_tail);
760 }
761
762 cp->tx_tail = tx_tail;
763
764 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
765 netif_wake_queue(cp->dev);
766}
767
768static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
769{
770 struct cp_private *cp = netdev_priv(dev);
771 unsigned entry;
fcec3456 772 u32 eor, flags;
1da177e4
LT		 773#if CP_VLAN_TAG_USED
774 u32 vlan_tag = 0;
775#endif
fcec3456 776 int mss = 0;
1da177e4
LT		 777
778 spin_lock_irq(&cp->lock);
779
780 /* This is a hard error, log it. */
781 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
782 netif_stop_queue(dev);
783 spin_unlock_irq(&cp->lock);
784 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
785 dev->name);
786 return 1;
787 }
788
789#if CP_VLAN_TAG_USED
790 if (cp->vlgrp && vlan_tx_tag_present(skb))
791 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
792#endif
793
794 entry = cp->tx_head;
795 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
fcec3456
JG		 796 if (dev->features & NETIF_F_TSO)
797 mss = skb_shinfo(skb)->tso_size;
798
1da177e4
LT		 799 if (skb_shinfo(skb)->nr_frags == 0) {
800 struct cp_desc *txd = &cp->tx_ring[entry];
801 u32 len;
802 dma_addr_t mapping;
803
804 len = skb->len;
805 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
806 CP_VLAN_TX_TAG(txd, vlan_tag);
807 txd->addr = cpu_to_le64(mapping);
808 wmb();
809
fcec3456
JG		 810 flags = eor | len | DescOwn | FirstFrag | LastFrag;
811
812 if (mss)
813 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
814 else if (skb->ip_summed == CHECKSUM_HW) {
1da177e4
LT		 815 const struct iphdr *ip = skb->nh.iph;
816 if (ip->protocol == IPPROTO_TCP)
fcec3456 817 flags |= IPCS | TCPCS;
1da177e4 818 else if (ip->protocol == IPPROTO_UDP)
fcec3456 819 flags |= IPCS | UDPCS;
1da177e4 820 else
5734418d 821 WARN_ON(1); /* we need a WARN() */
fcec3456
JG		 822 }
823
824 txd->opts1 = cpu_to_le32(flags);
1da177e4
LT		 825 wmb();
826
827 cp->tx_skb[entry].skb = skb;
828 cp->tx_skb[entry].mapping = mapping;
5734418d 829 cp->tx_skb[entry].len = len;
1da177e4
LT		 830 entry = NEXT_TX(entry);
831 } else {
832 struct cp_desc *txd;
833 u32 first_len, first_eor;
834 dma_addr_t first_mapping;
835 int frag, first_entry = entry;
836 const struct iphdr *ip = skb->nh.iph;
837
838 /* We must give this initial chunk to the device last.
839 * Otherwise we could race with the device.
840 */
841 first_eor = eor;
842 first_len = skb_headlen(skb);
843 first_mapping = pci_map_single(cp->pdev, skb->data,
844 first_len, PCI_DMA_TODEVICE);
845 cp->tx_skb[entry].skb = skb;
846 cp->tx_skb[entry].mapping = first_mapping;
5734418d 847 cp->tx_skb[entry].len = first_len;
1da177e4
LT		 848 entry = NEXT_TX(entry);
849
850 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
851 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
852 u32 len;
853 u32 ctrl;
854 dma_addr_t mapping;
855
856 len = this_frag->size;
857 mapping = pci_map_single(cp->pdev,
858 ((void *) page_address(this_frag->page) +
859 this_frag->page_offset),
860 len, PCI_DMA_TODEVICE);
861 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
862
fcec3456
JG		 863 ctrl = eor | len | DescOwn;
864
865 if (mss)
866 ctrl |= LargeSend |
867 ((mss & MSSMask) << MSSShift);
868 else if (skb->ip_summed == CHECKSUM_HW) {
1da177e4 869 if (ip->protocol == IPPROTO_TCP)
fcec3456 870 ctrl |= IPCS | TCPCS;
1da177e4 871 else if (ip->protocol == IPPROTO_UDP)
fcec3456 872 ctrl |= IPCS | UDPCS;
1da177e4
LT		 873 else
874 BUG();
fcec3456 875 }
1da177e4
LT		 876
877 if (frag == skb_shinfo(skb)->nr_frags - 1)
878 ctrl |= LastFrag;
879
880 txd = &cp->tx_ring[entry];
881 CP_VLAN_TX_TAG(txd, vlan_tag);
882 txd->addr = cpu_to_le64(mapping);
883 wmb();
884
885 txd->opts1 = cpu_to_le32(ctrl);
886 wmb();
887
888 cp->tx_skb[entry].skb = skb;
889 cp->tx_skb[entry].mapping = mapping;
5734418d 890 cp->tx_skb[entry].len = len;
1da177e4
LT		 891 entry = NEXT_TX(entry);
892 }
893
894 txd = &cp->tx_ring[first_entry];
895 CP_VLAN_TX_TAG(txd, vlan_tag);
896 txd->addr = cpu_to_le64(first_mapping);
897 wmb();
898
899 if (skb->ip_summed == CHECKSUM_HW) {
900 if (ip->protocol == IPPROTO_TCP)
901 txd->opts1 = cpu_to_le32(first_eor | first_len |
902 FirstFrag | DescOwn |
903 IPCS | TCPCS);
904 else if (ip->protocol == IPPROTO_UDP)
905 txd->opts1 = cpu_to_le32(first_eor | first_len |
906 FirstFrag | DescOwn |
907 IPCS | UDPCS);
908 else
909 BUG();
910 } else
911 txd->opts1 = cpu_to_le32(first_eor | first_len |
912 FirstFrag | DescOwn);
913 wmb();
914 }
915 cp->tx_head = entry;
916 if (netif_msg_tx_queued(cp))
917 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
918 dev->name, entry, skb->len);
919 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
920 netif_stop_queue(dev);
921
922 spin_unlock_irq(&cp->lock);
923
924 cpw8(TxPoll, NormalTxPoll);
925 dev->trans_start = jiffies;
926
927 return 0;
928}
929
930/* Set or clear the multicast filter for this adaptor.
931 This routine is not state sensitive and need not be SMP locked. */
932
933static void __cp_set_rx_mode (struct net_device *dev)
934{
935 struct cp_private *cp = netdev_priv(dev);
936 u32 mc_filter[2]; /* Multicast hash filter */
937 int i, rx_mode;
938 u32 tmp;
939
940 /* Note: do not reorder, GCC is clever about common statements. */
941 if (dev->flags & IFF_PROMISC) {
942 /* Unconditionally log net taps. */
943 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
944 dev->name);
945 rx_mode =
946 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
947 AcceptAllPhys;
948 mc_filter[1] = mc_filter[0] = 0xffffffff;
949 } else if ((dev->mc_count > multicast_filter_limit)
950 || (dev->flags & IFF_ALLMULTI)) {
951 /* Too many to filter perfectly -- accept all multicasts. */
952 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
953 mc_filter[1] = mc_filter[0] = 0xffffffff;
954 } else {
955 struct dev_mc_list *mclist;
956 rx_mode = AcceptBroadcast | AcceptMyPhys;
957 mc_filter[1] = mc_filter[0] = 0;
958 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
959 i++, mclist = mclist->next) {
960 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
961
962 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
963 rx_mode |= AcceptMulticast;
964 }
965 }
966
967 /* We can safely update without stopping the chip. */
968 tmp = cp_rx_config | rx_mode;
969 if (cp->rx_config != tmp) {
970 cpw32_f (RxConfig, tmp);
971 cp->rx_config = tmp;
972 }
973 cpw32_f (MAR0 + 0, mc_filter[0]);
974 cpw32_f (MAR0 + 4, mc_filter[1]);
975}
976
977static void cp_set_rx_mode (struct net_device *dev)
978{
979 unsigned long flags;
980 struct cp_private *cp = netdev_priv(dev);
981
982 spin_lock_irqsave (&cp->lock, flags);
983 __cp_set_rx_mode(dev);
984 spin_unlock_irqrestore (&cp->lock, flags);
985}
986
987static void __cp_get_stats(struct cp_private *cp)
988{
989 /* only lower 24 bits valid; write any value to clear */
990 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
991 cpw32 (RxMissed, 0);
992}
993
994static struct net_device_stats *cp_get_stats(struct net_device *dev)
995{
996 struct cp_private *cp = netdev_priv(dev);
997 unsigned long flags;
998
999 /* The chip only need report frame silently dropped. */
1000 spin_lock_irqsave(&cp->lock, flags);
1001 if (netif_running(dev) && netif_device_present(dev))
1002 __cp_get_stats(cp);
1003 spin_unlock_irqrestore(&cp->lock, flags);
1004
1005 return &cp->net_stats;
1006}
1007
1008static void cp_stop_hw (struct cp_private *cp)
1009{
1010 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
1011 cpw16_f(IntrMask, 0);
1012 cpw8(Cmd, 0);
1013 cpw16_f(CpCmd, 0);
1014 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
1015
1016 cp->rx_tail = 0;
1017 cp->tx_head = cp->tx_tail = 0;
1018}
1019
1020static void cp_reset_hw (struct cp_private *cp)
1021{
1022 unsigned work = 1000;
1023
1024 cpw8(Cmd, CmdReset);
1025
1026 while (work--) {
1027 if (!(cpr8(Cmd) & CmdReset))
1028 return;
1029
3173c890 1030 schedule_timeout_uninterruptible(10);
1da177e4
LT		 1031 }
1032
1033 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1034}
1035
1036static inline void cp_start_hw (struct cp_private *cp)
1037{
1038 cpw16(CpCmd, cp->cpcmd);
1039 cpw8(Cmd, RxOn | TxOn);
1040}
1041
1042static void cp_init_hw (struct cp_private *cp)
1043{
1044 struct net_device *dev = cp->dev;
1045 dma_addr_t ring_dma;
1046
1047 cp_reset_hw(cp);
1048
1049 cpw8_f (Cfg9346, Cfg9346_Unlock);
1050
1051 /* Restore our idea of the MAC address. */
1052 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1053 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1054
1055 cp_start_hw(cp);
1056 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1057
1058 __cp_set_rx_mode(dev);
1059 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1060
1061 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1062 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1063 cpw8(Config3, PARMEnable);
1064 cp->wol_enabled = 0;
1065
1066 cpw8(Config5, cpr8(Config5) & PMEStatus);
1067
1068 cpw32_f(HiTxRingAddr, 0);
1069 cpw32_f(HiTxRingAddr + 4, 0);
1070
1071 ring_dma = cp->ring_dma;
1072 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1073 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1074
1075 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1076 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1077 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1078
1079 cpw16(MultiIntr, 0);
1080
1081 cpw16_f(IntrMask, cp_intr_mask);
1082
1083 cpw8_f(Cfg9346, Cfg9346_Lock);
1084}
1085
1086static int cp_refill_rx (struct cp_private *cp)
1087{
1088 unsigned i;
1089
1090 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1091 struct sk_buff *skb;
1092
1093 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1094 if (!skb)
1095 goto err_out;
1096
1097 skb->dev = cp->dev;
1098 skb_reserve(skb, RX_OFFSET);
1099
1100 cp->rx_skb[i].mapping = pci_map_single(cp->pdev,
689be439 1101 skb->data, cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1da177e4 1102 cp->rx_skb[i].skb = skb;
1da177e4
LT		 1103
1104 cp->rx_ring[i].opts2 = 0;
1105 cp->rx_ring[i].addr = cpu_to_le64(cp->rx_skb[i].mapping);
1106 if (i == (CP_RX_RING_SIZE - 1))
1107 cp->rx_ring[i].opts1 =
1108 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1109 else
1110 cp->rx_ring[i].opts1 =
1111 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1112 }
1113
1114 return 0;
1115
1116err_out:
1117 cp_clean_rings(cp);
1118 return -ENOMEM;
1119}
1120
576cfa93
FR		 1121static void cp_init_rings_index (struct cp_private *cp)
1122{
1123 cp->rx_tail = 0;
1124 cp->tx_head = cp->tx_tail = 0;
1125}
1126
1da177e4
LT		 1127static int cp_init_rings (struct cp_private *cp)
1128{
1129 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1130 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1131
576cfa93 1132 cp_init_rings_index(cp);
1da177e4
LT		 1133
1134 return cp_refill_rx (cp);
1135}
1136
1137static int cp_alloc_rings (struct cp_private *cp)
1138{
1139 void *mem;
1140
1141 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1142 if (!mem)
1143 return -ENOMEM;
1144
1145 cp->rx_ring = mem;
1146 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1147
1da177e4
LT		 1148 return cp_init_rings(cp);
1149}
1150
1151static void cp_clean_rings (struct cp_private *cp)
1152{
1153 unsigned i;
1154
1da177e4
LT		 1155 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1156 if (cp->rx_skb[i].skb) {
1157 pci_unmap_single(cp->pdev, cp->rx_skb[i].mapping,
1158 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1159 dev_kfree_skb(cp->rx_skb[i].skb);
1160 }
1161 }
1162
1163 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1164 if (cp->tx_skb[i].skb) {
1165 struct sk_buff *skb = cp->tx_skb[i].skb;
5734418d 1166
1da177e4 1167 pci_unmap_single(cp->pdev, cp->tx_skb[i].mapping,
5734418d
FR		 1168 cp->tx_skb[i].len, PCI_DMA_TODEVICE);
1169 if (le32_to_cpu(cp->tx_ring[i].opts1) & LastFrag)
1170 dev_kfree_skb(skb);
1da177e4
LT		 1171 cp->net_stats.tx_dropped++;
1172 }
1173 }
1174
5734418d
FR		 1175 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1176 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1177
1da177e4
LT		 1178 memset(&cp->rx_skb, 0, sizeof(struct ring_info) * CP_RX_RING_SIZE);
1179 memset(&cp->tx_skb, 0, sizeof(struct ring_info) * CP_TX_RING_SIZE);
1180}
1181
1182static void cp_free_rings (struct cp_private *cp)
1183{
1184 cp_clean_rings(cp);
1185 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1186 cp->rx_ring = NULL;
1187 cp->tx_ring = NULL;
1da177e4
LT		 1188}
1189
1190static int cp_open (struct net_device *dev)
1191{
1192 struct cp_private *cp = netdev_priv(dev);
1193 int rc;
1194
1195 if (netif_msg_ifup(cp))
1196 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1197
1198 rc = cp_alloc_rings(cp);
1199 if (rc)
1200 return rc;
1201
1202 cp_init_hw(cp);
1203
1204 rc = request_irq(dev->irq, cp_interrupt, SA_SHIRQ, dev->name, dev);
1205 if (rc)
1206 goto err_out_hw;
1207
1208 netif_carrier_off(dev);
1209 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1210 netif_start_queue(dev);
1211
1212 return 0;
1213
1214err_out_hw:
1215 cp_stop_hw(cp);
1216 cp_free_rings(cp);
1217 return rc;
1218}
1219
1220static int cp_close (struct net_device *dev)
1221{
1222 struct cp_private *cp = netdev_priv(dev);
1223 unsigned long flags;
1224
1225 if (netif_msg_ifdown(cp))
1226 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1227
1228 spin_lock_irqsave(&cp->lock, flags);
1229
1230 netif_stop_queue(dev);
1231 netif_carrier_off(dev);
1232
1233 cp_stop_hw(cp);
1234
1235 spin_unlock_irqrestore(&cp->lock, flags);
1236
1237 synchronize_irq(dev->irq);
1238 free_irq(dev->irq, dev);
1239
1240 cp_free_rings(cp);
1241 return 0;
1242}
1243
1244#ifdef BROKEN
1245static int cp_change_mtu(struct net_device *dev, int new_mtu)
1246{
1247 struct cp_private *cp = netdev_priv(dev);
1248 int rc;
1249 unsigned long flags;
1250
1251 /* check for invalid MTU, according to hardware limits */
1252 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1253 return -EINVAL;
1254
1255 /* if network interface not up, no need for complexity */
1256 if (!netif_running(dev)) {
1257 dev->mtu = new_mtu;
1258 cp_set_rxbufsize(cp); /* set new rx buf size */
1259 return 0;
1260 }
1261
1262 spin_lock_irqsave(&cp->lock, flags);
1263
1264 cp_stop_hw(cp); /* stop h/w and free rings */
1265 cp_clean_rings(cp);
1266
1267 dev->mtu = new_mtu;
1268 cp_set_rxbufsize(cp); /* set new rx buf size */
1269
1270 rc = cp_init_rings(cp); /* realloc and restart h/w */
1271 cp_start_hw(cp);
1272
1273 spin_unlock_irqrestore(&cp->lock, flags);
1274
1275 return rc;
1276}
1277#endif /* BROKEN */
1278
f71e1309 1279static const char mii_2_8139_map[8] = {
1da177e4
LT		 1280 BasicModeCtrl,
1281 BasicModeStatus,
1282 0,
1283 0,
1284 NWayAdvert,
1285 NWayLPAR,
1286 NWayExpansion,
1287 0
1288};
1289
1290static int mdio_read(struct net_device *dev, int phy_id, int location)
1291{
1292 struct cp_private *cp = netdev_priv(dev);
1293
1294 return location < 8 && mii_2_8139_map[location] ?
1295 readw(cp->regs + mii_2_8139_map[location]) : 0;
1296}
1297
1298
1299static void mdio_write(struct net_device *dev, int phy_id, int location,
1300 int value)
1301{
1302 struct cp_private *cp = netdev_priv(dev);
1303
1304 if (location == 0) {
1305 cpw8(Cfg9346, Cfg9346_Unlock);
1306 cpw16(BasicModeCtrl, value);
1307 cpw8(Cfg9346, Cfg9346_Lock);
1308 } else if (location < 8 && mii_2_8139_map[location])
1309 cpw16(mii_2_8139_map[location], value);
1310}
1311
1312/* Set the ethtool Wake-on-LAN settings */
1313static int netdev_set_wol (struct cp_private *cp,
1314 const struct ethtool_wolinfo *wol)
1315{
1316 u8 options;
1317
1318 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1319 /* If WOL is being disabled, no need for complexity */
1320 if (wol->wolopts) {
1321 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1322 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1323 }
1324
1325 cpw8 (Cfg9346, Cfg9346_Unlock);
1326 cpw8 (Config3, options);
1327 cpw8 (Cfg9346, Cfg9346_Lock);
1328
1329 options = 0; /* Paranoia setting */
1330 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1331 /* If WOL is being disabled, no need for complexity */
1332 if (wol->wolopts) {
1333 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1334 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1335 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1336 }
1337
1338 cpw8 (Config5, options);
1339
1340 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1341
1342 return 0;
1343}
1344
1345/* Get the ethtool Wake-on-LAN settings */
1346static void netdev_get_wol (struct cp_private *cp,
1347 struct ethtool_wolinfo *wol)
1348{
1349 u8 options;
1350
1351 wol->wolopts = 0; /* Start from scratch */
1352 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1353 WAKE_MCAST | WAKE_UCAST;
1354 /* We don't need to go on if WOL is disabled */
1355 if (!cp->wol_enabled) return;
1356
1357 options = cpr8 (Config3);
1358 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1359 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1360
1361 options = 0; /* Paranoia setting */
1362 options = cpr8 (Config5);
1363 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1364 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1365 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1366}
1367
1368static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1369{
1370 struct cp_private *cp = netdev_priv(dev);
1371
1372 strcpy (info->driver, DRV_NAME);
1373 strcpy (info->version, DRV_VERSION);
1374 strcpy (info->bus_info, pci_name(cp->pdev));
1375}
1376
1377static int cp_get_regs_len(struct net_device *dev)
1378{
1379 return CP_REGS_SIZE;
1380}
1381
1382static int cp_get_stats_count (struct net_device *dev)
1383{
1384 return CP_NUM_STATS;
1385}
1386
1387static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1388{
1389 struct cp_private *cp = netdev_priv(dev);
1390 int rc;
1391 unsigned long flags;
1392
1393 spin_lock_irqsave(&cp->lock, flags);
1394 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1395 spin_unlock_irqrestore(&cp->lock, flags);
1396
1397 return rc;
1398}
1399
1400static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1401{
1402 struct cp_private *cp = netdev_priv(dev);
1403 int rc;
1404 unsigned long flags;
1405
1406 spin_lock_irqsave(&cp->lock, flags);
1407 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1408 spin_unlock_irqrestore(&cp->lock, flags);
1409
1410 return rc;
1411}
1412
1413static int cp_nway_reset(struct net_device *dev)
1414{
1415 struct cp_private *cp = netdev_priv(dev);
1416 return mii_nway_restart(&cp->mii_if);
1417}
1418
1419static u32 cp_get_msglevel(struct net_device *dev)
1420{
1421 struct cp_private *cp = netdev_priv(dev);
1422 return cp->msg_enable;
1423}
1424
1425static void cp_set_msglevel(struct net_device *dev, u32 value)
1426{
1427 struct cp_private *cp = netdev_priv(dev);
1428 cp->msg_enable = value;
1429}
1430
1431static u32 cp_get_rx_csum(struct net_device *dev)
1432{
1433 struct cp_private *cp = netdev_priv(dev);
1434 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1435}
1436
1437static int cp_set_rx_csum(struct net_device *dev, u32 data)
1438{
1439 struct cp_private *cp = netdev_priv(dev);
1440 u16 cmd = cp->cpcmd, newcmd;
1441
1442 newcmd = cmd;
1443
1444 if (data)
1445 newcmd |= RxChkSum;
1446 else
1447 newcmd &= ~RxChkSum;
1448
1449 if (newcmd != cmd) {
1450 unsigned long flags;
1451
1452 spin_lock_irqsave(&cp->lock, flags);
1453 cp->cpcmd = newcmd;
1454 cpw16_f(CpCmd, newcmd);
1455 spin_unlock_irqrestore(&cp->lock, flags);
1456 }
1457
1458 return 0;
1459}
1460
1461static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1462 void *p)
1463{
1464 struct cp_private *cp = netdev_priv(dev);
1465 unsigned long flags;
1466
1467 if (regs->len < CP_REGS_SIZE)
1468 return /* -EINVAL */;
1469
1470 regs->version = CP_REGS_VER;
1471
1472 spin_lock_irqsave(&cp->lock, flags);
1473 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1474 spin_unlock_irqrestore(&cp->lock, flags);
1475}
1476
1477static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1478{
1479 struct cp_private *cp = netdev_priv(dev);
1480 unsigned long flags;
1481
1482 spin_lock_irqsave (&cp->lock, flags);
1483 netdev_get_wol (cp, wol);
1484 spin_unlock_irqrestore (&cp->lock, flags);
1485}
1486
1487static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1488{
1489 struct cp_private *cp = netdev_priv(dev);
1490 unsigned long flags;
1491 int rc;
1492
1493 spin_lock_irqsave (&cp->lock, flags);
1494 rc = netdev_set_wol (cp, wol);
1495 spin_unlock_irqrestore (&cp->lock, flags);
1496
1497 return rc;
1498}
1499
1500static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1501{
1502 switch (stringset) {
1503 case ETH_SS_STATS:
1504 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1505 break;
1506 default:
1507 BUG();
1508 break;
1509 }
1510}
1511
1512static void cp_get_ethtool_stats (struct net_device *dev,
1513 struct ethtool_stats *estats, u64 *tmp_stats)
1514{
1515 struct cp_private *cp = netdev_priv(dev);
8b512927
SH		 1516 struct cp_dma_stats *nic_stats;
1517 dma_addr_t dma;
1da177e4
LT		 1518 int i;
1519
8b512927
SH		 1520 nic_stats = pci_alloc_consistent(cp->pdev, sizeof(*nic_stats), &dma);
1521 if (!nic_stats)
1522 return;
97f568d8 1523
1da177e4 1524 /* begin NIC statistics dump */
8b512927
SH		 1525 cpw32(StatsAddr + 4, (u64)dma >> 32);
1526 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1da177e4
LT		 1527 cpr32(StatsAddr);
1528
97f568d8 1529 for (i = 0; i < 1000; i++) {
1da177e4
LT		 1530 if ((cpr32(StatsAddr) & DumpStats) == 0)
1531 break;
97f568d8 1532 udelay(10);
1da177e4 1533 }
97f568d8
SH		 1534 cpw32(StatsAddr, 0);
1535 cpw32(StatsAddr + 4, 0);
8b512927 1536 cpr32(StatsAddr);
1da177e4
LT		 1537
1538 i = 0;
8b512927
SH		 1539 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1540 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1541 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1542 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1543 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1544 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1545 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1546 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1547 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1548 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1549 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1550 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1551 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1da177e4
LT		 1552 tmp_stats[i++] = cp->cp_stats.rx_frags;
1553 if (i != CP_NUM_STATS)
1554 BUG();
8b512927
SH		 1555
1556 pci_free_consistent(cp->pdev, sizeof(*nic_stats), nic_stats, dma);
1da177e4
LT		 1557}
1558
1559static struct ethtool_ops cp_ethtool_ops = {
1560 .get_drvinfo = cp_get_drvinfo,
1561 .get_regs_len = cp_get_regs_len,
1562 .get_stats_count = cp_get_stats_count,
1563 .get_settings = cp_get_settings,
1564 .set_settings = cp_set_settings,
1565 .nway_reset = cp_nway_reset,
1566 .get_link = ethtool_op_get_link,
1567 .get_msglevel = cp_get_msglevel,
1568 .set_msglevel = cp_set_msglevel,
1569 .get_rx_csum = cp_get_rx_csum,
1570 .set_rx_csum = cp_set_rx_csum,
1571 .get_tx_csum = ethtool_op_get_tx_csum,
1572 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1573 .get_sg = ethtool_op_get_sg,
1574 .set_sg = ethtool_op_set_sg,
fcec3456
JG		 1575 .get_tso = ethtool_op_get_tso,
1576 .set_tso = ethtool_op_set_tso,
1da177e4
LT		 1577 .get_regs = cp_get_regs,
1578 .get_wol = cp_get_wol,
1579 .set_wol = cp_set_wol,
1580 .get_strings = cp_get_strings,
1581 .get_ethtool_stats = cp_get_ethtool_stats,
bb0ce608 1582 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 1583};
1584
1585static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1586{
1587 struct cp_private *cp = netdev_priv(dev);
1588 int rc;
1589 unsigned long flags;
1590
1591 if (!netif_running(dev))
1592 return -EINVAL;
1593
1594 spin_lock_irqsave(&cp->lock, flags);
1595 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1596 spin_unlock_irqrestore(&cp->lock, flags);
1597 return rc;
1598}
1599
1600/* Serial EEPROM section. */
1601
1602/* EEPROM_Ctrl bits. */
1603#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1604#define EE_CS 0x08 /* EEPROM chip select. */
1605#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1606#define EE_WRITE_0 0x00
1607#define EE_WRITE_1 0x02
1608#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1609#define EE_ENB (0x80 | EE_CS)
1610
1611/* Delay between EEPROM clock transitions.
1612 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1613 */
1614
1615#define eeprom_delay() readl(ee_addr)
1616
1617/* The EEPROM commands include the alway-set leading bit. */
1618#define EE_WRITE_CMD (5)
1619#define EE_READ_CMD (6)
1620#define EE_ERASE_CMD (7)
1621
1622static int read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1623{
1624 int i;
1625 unsigned retval = 0;
1626 void __iomem *ee_addr = ioaddr + Cfg9346;
1627 int read_cmd = location | (EE_READ_CMD << addr_len);
1628
1629 writeb (EE_ENB & ~EE_CS, ee_addr);
1630 writeb (EE_ENB, ee_addr);
1631 eeprom_delay ();
1632
1633 /* Shift the read command bits out. */
1634 for (i = 4 + addr_len; i >= 0; i--) {
1635 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1636 writeb (EE_ENB | dataval, ee_addr);
1637 eeprom_delay ();
1638 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1639 eeprom_delay ();
1640 }
1641 writeb (EE_ENB, ee_addr);
1642 eeprom_delay ();
1643
1644 for (i = 16; i > 0; i--) {
1645 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1646 eeprom_delay ();
1647 retval =
1648 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1649 0);
1650 writeb (EE_ENB, ee_addr);
1651 eeprom_delay ();
1652 }
1653
1654 /* Terminate the EEPROM access. */
1655 writeb (~EE_CS, ee_addr);
1656 eeprom_delay ();
1657
1658 return retval;
1659}
1660
1661/* Put the board into D3cold state and wait for WakeUp signal */
1662static void cp_set_d3_state (struct cp_private *cp)
1663{
1664 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1665 pci_set_power_state (cp->pdev, PCI_D3hot);
1666}
1667
1668static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1669{
1670 struct net_device *dev;
1671 struct cp_private *cp;
1672 int rc;
1673 void __iomem *regs;
1674 long pciaddr;
1675 unsigned int addr_len, i, pci_using_dac;
1676 u8 pci_rev;
1677
1678#ifndef MODULE
1679 static int version_printed;
1680 if (version_printed++ == 0)
1681 printk("%s", version);
1682#endif
1683
1684 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1685
1686 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1687 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
1688 printk(KERN_ERR PFX "pci dev %s (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1689 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
1690 printk(KERN_ERR PFX "Try the \"8139too\" driver instead.\n");
1691 return -ENODEV;
1692 }
1693
1694 dev = alloc_etherdev(sizeof(struct cp_private));
1695 if (!dev)
1696 return -ENOMEM;
1697 SET_MODULE_OWNER(dev);
1698 SET_NETDEV_DEV(dev, &pdev->dev);
1699
1700 cp = netdev_priv(dev);
1701 cp->pdev = pdev;
1702 cp->dev = dev;
1703 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1704 spin_lock_init (&cp->lock);
1705 cp->mii_if.dev = dev;
1706 cp->mii_if.mdio_read = mdio_read;
1707 cp->mii_if.mdio_write = mdio_write;
1708 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1709 cp->mii_if.phy_id_mask = 0x1f;
1710 cp->mii_if.reg_num_mask = 0x1f;
1711 cp_set_rxbufsize(cp);
1712
1713 rc = pci_enable_device(pdev);
1714 if (rc)
1715 goto err_out_free;
1716
1717 rc = pci_set_mwi(pdev);
1718 if (rc)
1719 goto err_out_disable;
1720
1721 rc = pci_request_regions(pdev, DRV_NAME);
1722 if (rc)
1723 goto err_out_mwi;
1724
1725 pciaddr = pci_resource_start(pdev, 1);
1726 if (!pciaddr) {
1727 rc = -EIO;
1728 printk(KERN_ERR PFX "no MMIO resource for pci dev %s\n",
1729 pci_name(pdev));
1730 goto err_out_res;
1731 }
1732 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1733 rc = -EIO;
1734 printk(KERN_ERR PFX "MMIO resource (%lx) too small on pci dev %s\n",
1735 pci_resource_len(pdev, 1), pci_name(pdev));
1736 goto err_out_res;
1737 }
1738
1739 /* Configure DMA attributes. */
1740 if ((sizeof(dma_addr_t) > 4) &&
8662d061
TK		 1741 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1742 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 1743 pci_using_dac = 1;
1744 } else {
1745 pci_using_dac = 0;
1746
8662d061 1747 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4
LT		 1748 if (rc) {
1749 printk(KERN_ERR PFX "No usable DMA configuration, "
1750 "aborting.\n");
1751 goto err_out_res;
1752 }
8662d061 1753 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4
LT		 1754 if (rc) {
1755 printk(KERN_ERR PFX "No usable consistent DMA configuration, "
1756 "aborting.\n");
1757 goto err_out_res;
1758 }
1759 }
1760
1761 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1762 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1763
1764 regs = ioremap(pciaddr, CP_REGS_SIZE);
1765 if (!regs) {
1766 rc = -EIO;
1767 printk(KERN_ERR PFX "Cannot map PCI MMIO (%lx@%lx) on pci dev %s\n",
1768 pci_resource_len(pdev, 1), pciaddr, pci_name(pdev));
1769 goto err_out_res;
1770 }
1771 dev->base_addr = (unsigned long) regs;
1772 cp->regs = regs;
1773
1774 cp_stop_hw(cp);
1775
1776 /* read MAC address from EEPROM */
1777 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1778 for (i = 0; i < 3; i++)
1779 ((u16 *) (dev->dev_addr))[i] =
1780 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
bb0ce608 1781 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1782
1783 dev->open = cp_open;
1784 dev->stop = cp_close;
1785 dev->set_multicast_list = cp_set_rx_mode;
1786 dev->hard_start_xmit = cp_start_xmit;
1787 dev->get_stats = cp_get_stats;
1788 dev->do_ioctl = cp_ioctl;
1789 dev->poll = cp_rx_poll;
7502cd10
SK		 1790#ifdef CONFIG_NET_POLL_CONTROLLER
1791 dev->poll_controller = cp_poll_controller;
1792#endif
1da177e4
LT		 1793 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1794#ifdef BROKEN
1795 dev->change_mtu = cp_change_mtu;
1796#endif
1797 dev->ethtool_ops = &cp_ethtool_ops;
1798#if 0
1799 dev->tx_timeout = cp_tx_timeout;
1800 dev->watchdog_timeo = TX_TIMEOUT;
1801#endif
1802
1803#if CP_VLAN_TAG_USED
1804 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1805 dev->vlan_rx_register = cp_vlan_rx_register;
1806 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1807#endif
1808
1809 if (pci_using_dac)
1810 dev->features |= NETIF_F_HIGHDMA;
1811
fcec3456
JG		 1812#if 0 /* disabled by default until verified */
1813 dev->features |= NETIF_F_TSO;
1814#endif
1815
1da177e4
LT		 1816 dev->irq = pdev->irq;
1817
1818 rc = register_netdev(dev);
1819 if (rc)
1820 goto err_out_iomap;
1821
1822 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1823 "%02x:%02x:%02x:%02x:%02x:%02x, "
1824 "IRQ %d\n",
1825 dev->name,
1826 dev->base_addr,
1827 dev->dev_addr[0], dev->dev_addr[1],
1828 dev->dev_addr[2], dev->dev_addr[3],
1829 dev->dev_addr[4], dev->dev_addr[5],
1830 dev->irq);
1831
1832 pci_set_drvdata(pdev, dev);
1833
1834 /* enable busmastering and memory-write-invalidate */
1835 pci_set_master(pdev);
1836
1837 if (cp->wol_enabled) cp_set_d3_state (cp);
1838
1839 return 0;
1840
1841err_out_iomap:
1842 iounmap(regs);
1843err_out_res:
1844 pci_release_regions(pdev);
1845err_out_mwi:
1846 pci_clear_mwi(pdev);
1847err_out_disable:
1848 pci_disable_device(pdev);
1849err_out_free:
1850 free_netdev(dev);
1851 return rc;
1852}
1853
1854static void cp_remove_one (struct pci_dev *pdev)
1855{
1856 struct net_device *dev = pci_get_drvdata(pdev);
1857 struct cp_private *cp = netdev_priv(dev);
1858
1859 if (!dev)
1860 BUG();
1861 unregister_netdev(dev);
1862 iounmap(cp->regs);
1863 if (cp->wol_enabled) pci_set_power_state (pdev, PCI_D0);
1864 pci_release_regions(pdev);
1865 pci_clear_mwi(pdev);
1866 pci_disable_device(pdev);
1867 pci_set_drvdata(pdev, NULL);
1868 free_netdev(dev);
1869}
1870
1871#ifdef CONFIG_PM
05adc3b7 1872static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 1873{
1874 struct net_device *dev;
1875 struct cp_private *cp;
1876 unsigned long flags;
1877
1878 dev = pci_get_drvdata (pdev);
1879 cp = netdev_priv(dev);
1880
1881 if (!dev || !netif_running (dev)) return 0;
1882
1883 netif_device_detach (dev);
1884 netif_stop_queue (dev);
1885
1886 spin_lock_irqsave (&cp->lock, flags);
1887
1888 /* Disable Rx and Tx */
1889 cpw16 (IntrMask, 0);
1890 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
1891
1892 spin_unlock_irqrestore (&cp->lock, flags);
1893
576cfa93
FR		 1894 pci_save_state(pdev);
1895 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
1896 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 1897
1898 return 0;
1899}
1900
1901static int cp_resume (struct pci_dev *pdev)
1902{
576cfa93
FR		 1903 struct net_device *dev = pci_get_drvdata (pdev);
1904 struct cp_private *cp = netdev_priv(dev);
a4cf0761 1905 unsigned long flags;
1da177e4 1906
576cfa93
FR		 1907 if (!netif_running(dev))
1908 return 0;
1da177e4
LT		 1909
1910 netif_device_attach (dev);
576cfa93
FR		 1911
1912 pci_set_power_state(pdev, PCI_D0);
1913 pci_restore_state(pdev);
1914 pci_enable_wake(pdev, PCI_D0, 0);
1915
1916 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
1917 cp_init_rings_index (cp);
1da177e4
LT		 1918 cp_init_hw (cp);
1919 netif_start_queue (dev);
a4cf0761
PO		 1920
1921 spin_lock_irqsave (&cp->lock, flags);
1922
1923 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
1924
1925 spin_unlock_irqrestore (&cp->lock, flags);
1da177e4
LT		 1926
1927 return 0;
1928}
1929#endif /* CONFIG_PM */
1930
1931static struct pci_driver cp_driver = {
1932 .name = DRV_NAME,
1933 .id_table = cp_pci_tbl,
1934 .probe = cp_init_one,
1935 .remove = cp_remove_one,
1936#ifdef CONFIG_PM
1937 .resume = cp_resume,
1938 .suspend = cp_suspend,
1939#endif
1940};
1941
1942static int __init cp_init (void)
1943{
1944#ifdef MODULE
1945 printk("%s", version);
1946#endif
1947 return pci_module_init (&cp_driver);
1948}
1949
1950static void __exit cp_exit (void)
1951{
1952 pci_unregister_driver (&cp_driver);
1953}
1954
1955module_init(cp_init);
1956module_exit(cp_exit);
Clone of davem's net-next-2.6 tree