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Merge branch 'sched-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[net-next-2.6.git] / drivers / net / 8139cp.c
CommitLineData
1da177e4
LT		 1/* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2/*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
f3b197ac 22
1da177e4
LT		 23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
f3b197ac 26
1da177e4
LT		 27 TODO:
28 * Test Tx checksumming thoroughly
1da177e4
LT		 29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
b4f18b3f
JP		 49#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
1da177e4 51#define DRV_NAME "8139cp"
d5b20697 52#define DRV_VERSION "1.3"
1da177e4
LT		 53#define DRV_RELDATE "Mar 22, 2004"
54
55
1da177e4 56#include <linux/module.h>
e21ba282 57#include <linux/moduleparam.h>
1da177e4
LT		 58#include <linux/kernel.h>
59#include <linux/compiler.h>
60#include <linux/netdevice.h>
61#include <linux/etherdevice.h>
62#include <linux/init.h>
63#include <linux/pci.h>
8662d061 64#include <linux/dma-mapping.h>
1da177e4
LT		 65#include <linux/delay.h>
66#include <linux/ethtool.h>
5a0e3ad6 67#include <linux/gfp.h>
1da177e4
LT		 68#include <linux/mii.h>
69#include <linux/if_vlan.h>
70#include <linux/crc32.h>
71#include <linux/in.h>
72#include <linux/ip.h>
73#include <linux/tcp.h>
74#include <linux/udp.h>
75#include <linux/cache.h>
76#include <asm/io.h>
77#include <asm/irq.h>
78#include <asm/uaccess.h>
79
80/* VLAN tagging feature enable/disable */
81#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
82#define CP_VLAN_TAG_USED 1
83#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
cf983019 84 do { (tx_desc)->opts2 = cpu_to_le32(vlan_tag_value); } while (0)
1da177e4
LT		 85#else
86#define CP_VLAN_TAG_USED 0
87#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
88 do { (tx_desc)->opts2 = 0; } while (0)
89#endif
90
91/* These identify the driver base version and may not be removed. */
92static char version[] =
9cc40855 93DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
1da177e4
LT		 94
95MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
96MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
a78d8927 97MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 98MODULE_LICENSE("GPL");
99
100static int debug = -1;
e21ba282 101module_param(debug, int, 0);
1da177e4
LT		 102MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
103
104/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
105 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
106static int multicast_filter_limit = 32;
e21ba282 107module_param(multicast_filter_limit, int, 0);
1da177e4
LT		 108MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
109
1da177e4
LT		 110#define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
111 NETIF_MSG_PROBE | \
112 NETIF_MSG_LINK)
113#define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
114#define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
115#define CP_REGS_SIZE (0xff + 1)
116#define CP_REGS_VER 1 /* version 1 */
117#define CP_RX_RING_SIZE 64
118#define CP_TX_RING_SIZE 64
119#define CP_RING_BYTES \
120 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
121 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
122 CP_STATS_SIZE)
123#define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
124#define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
125#define TX_BUFFS_AVAIL(CP) \
126 (((CP)->tx_tail <= (CP)->tx_head) ? \
127 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
128 (CP)->tx_tail - (CP)->tx_head - 1)
129
130#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
1da177e4
LT		 131#define CP_INTERNAL_PHY 32
132
133/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
134#define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
135#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
136#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
137#define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
138
139/* Time in jiffies before concluding the transmitter is hung. */
140#define TX_TIMEOUT (6*HZ)
141
142/* hardware minimum and maximum for a single frame's data payload */
143#define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
144#define CP_MAX_MTU 4096
145
146enum {
147 /* NIC register offsets */
148 MAC0 = 0x00, /* Ethernet hardware address. */
149 MAR0 = 0x08, /* Multicast filter. */
150 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
151 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
152 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
153 Cmd = 0x37, /* Command register */
154 IntrMask = 0x3C, /* Interrupt mask */
155 IntrStatus = 0x3E, /* Interrupt status */
156 TxConfig = 0x40, /* Tx configuration */
157 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
158 RxConfig = 0x44, /* Rx configuration */
159 RxMissed = 0x4C, /* 24 bits valid, write clears */
160 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
161 Config1 = 0x52, /* Config1 */
162 Config3 = 0x59, /* Config3 */
163 Config4 = 0x5A, /* Config4 */
164 MultiIntr = 0x5C, /* Multiple interrupt select */
165 BasicModeCtrl = 0x62, /* MII BMCR */
166 BasicModeStatus = 0x64, /* MII BMSR */
167 NWayAdvert = 0x66, /* MII ADVERTISE */
168 NWayLPAR = 0x68, /* MII LPA */
169 NWayExpansion = 0x6A, /* MII Expansion */
170 Config5 = 0xD8, /* Config5 */
171 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
172 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
173 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
174 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
175 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
176 TxThresh = 0xEC, /* Early Tx threshold */
177 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
178 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
179
180 /* Tx and Rx status descriptors */
181 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
182 RingEnd = (1 << 30), /* End of descriptor ring */
183 FirstFrag = (1 << 29), /* First segment of a packet */
184 LastFrag = (1 << 28), /* Final segment of a packet */
fcec3456
JG		 185 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
186 MSSShift = 16, /* MSS value position */
187 MSSMask = 0xfff, /* MSS value: 11 bits */
1da177e4
LT		 188 TxError = (1 << 23), /* Tx error summary */
189 RxError = (1 << 20), /* Rx error summary */
190 IPCS = (1 << 18), /* Calculate IP checksum */
191 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
192 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
193 TxVlanTag = (1 << 17), /* Add VLAN tag */
194 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
195 IPFail = (1 << 15), /* IP checksum failed */
196 UDPFail = (1 << 14), /* UDP/IP checksum failed */
197 TCPFail = (1 << 13), /* TCP/IP checksum failed */
198 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
199 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
200 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
201 RxProtoTCP = 1,
202 RxProtoUDP = 2,
203 RxProtoIP = 3,
204 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
205 TxOWC = (1 << 22), /* Tx Out-of-window collision */
206 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
207 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
208 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
209 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
210 RxErrFrame = (1 << 27), /* Rx frame alignment error */
211 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
212 RxErrCRC = (1 << 18), /* Rx CRC error */
213 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
214 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
215 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
216
217 /* StatsAddr register */
218 DumpStats = (1 << 3), /* Begin stats dump */
219
220 /* RxConfig register */
221 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
222 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
223 AcceptErr = 0x20, /* Accept packets with CRC errors */
224 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
225 AcceptBroadcast = 0x08, /* Accept broadcast packets */
226 AcceptMulticast = 0x04, /* Accept multicast packets */
227 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
228 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
229
230 /* IntrMask / IntrStatus registers */
231 PciErr = (1 << 15), /* System error on the PCI bus */
232 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
233 LenChg = (1 << 13), /* Cable length change */
234 SWInt = (1 << 8), /* Software-requested interrupt */
235 TxEmpty = (1 << 7), /* No Tx descriptors available */
236 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
237 LinkChg = (1 << 5), /* Packet underrun, or link change */
238 RxEmpty = (1 << 4), /* No Rx descriptors available */
239 TxErr = (1 << 3), /* Tx error */
240 TxOK = (1 << 2), /* Tx packet sent */
241 RxErr = (1 << 1), /* Rx error */
242 RxOK = (1 << 0), /* Rx packet received */
243 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
244 but hardware likes to raise it */
245
246 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
247 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
248 RxErr | RxOK | IntrResvd,
249
250 /* C mode command register */
251 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
252 RxOn = (1 << 3), /* Rx mode enable */
253 TxOn = (1 << 2), /* Tx mode enable */
254
255 /* C+ mode command register */
256 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
257 RxChkSum = (1 << 5), /* Rx checksum offload enable */
258 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
259 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
260 CpRxOn = (1 << 1), /* Rx mode enable */
261 CpTxOn = (1 << 0), /* Tx mode enable */
262
263 /* Cfg9436 EEPROM control register */
264 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
265 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
266
267 /* TxConfig register */
268 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
269 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
270
271 /* Early Tx Threshold register */
272 TxThreshMask = 0x3f, /* Mask bits 5-0 */
273 TxThreshMax = 2048, /* Max early Tx threshold */
274
275 /* Config1 register */
276 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
277 LWACT = (1 << 4), /* LWAKE active mode */
278 PMEnable = (1 << 0), /* Enable various PM features of chip */
279
280 /* Config3 register */
281 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
282 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
283 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
284
285 /* Config4 register */
286 LWPTN = (1 << 1), /* LWAKE Pattern */
287 LWPME = (1 << 4), /* LANWAKE vs PMEB */
288
289 /* Config5 register */
290 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
291 MWF = (1 << 5), /* Accept Multicast wakeup frame */
292 UWF = (1 << 4), /* Accept Unicast wakeup frame */
293 LANWake = (1 << 1), /* Enable LANWake signal */
294 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
295
296 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
297 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
298 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
299};
300
301static const unsigned int cp_rx_config =
302 (RX_FIFO_THRESH << RxCfgFIFOShift) |
303 (RX_DMA_BURST << RxCfgDMAShift);
304
305struct cp_desc {
03233b90 306 __le32 opts1;
cf983019 307 __le32 opts2;
03233b90 308 __le64 addr;
1da177e4
LT		 309};
310
1da177e4 311struct cp_dma_stats {
03233b90
AV		 312 __le64 tx_ok;
313 __le64 rx_ok;
314 __le64 tx_err;
315 __le32 rx_err;
316 __le16 rx_fifo;
317 __le16 frame_align;
318 __le32 tx_ok_1col;
319 __le32 tx_ok_mcol;
320 __le64 rx_ok_phys;
321 __le64 rx_ok_bcast;
322 __le32 rx_ok_mcast;
323 __le16 tx_abort;
324 __le16 tx_underrun;
1da177e4
LT		 325} __attribute__((packed));
326
327struct cp_extra_stats {
328 unsigned long rx_frags;
329};
330
331struct cp_private {
332 void __iomem *regs;
333 struct net_device *dev;
334 spinlock_t lock;
335 u32 msg_enable;
336
bea3348e
SH		 337 struct napi_struct napi;
338
1da177e4
LT		 339 struct pci_dev *pdev;
340 u32 rx_config;
341 u16 cpcmd;
342
1da177e4 343 struct cp_extra_stats cp_stats;
1da177e4 344
d03d376d
FR		 345 unsigned rx_head ____cacheline_aligned;
346 unsigned rx_tail;
1da177e4 347 struct cp_desc *rx_ring;
0ba894d4 348 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
1da177e4
LT		 349
350 unsigned tx_head ____cacheline_aligned;
351 unsigned tx_tail;
1da177e4 352 struct cp_desc *tx_ring;
48907e39 353 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
d03d376d
FR		 354
355 unsigned rx_buf_sz;
356 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
1da177e4
LT		 357
358#if CP_VLAN_TAG_USED
359 struct vlan_group *vlgrp;
360#endif
d03d376d 361 dma_addr_t ring_dma;
1da177e4
LT		 362
363 struct mii_if_info mii_if;
364};
365
366#define cpr8(reg) readb(cp->regs + (reg))
367#define cpr16(reg) readw(cp->regs + (reg))
368#define cpr32(reg) readl(cp->regs + (reg))
369#define cpw8(reg,val) writeb((val), cp->regs + (reg))
370#define cpw16(reg,val) writew((val), cp->regs + (reg))
371#define cpw32(reg,val) writel((val), cp->regs + (reg))
372#define cpw8_f(reg,val) do { \
373 writeb((val), cp->regs + (reg)); \
374 readb(cp->regs + (reg)); \
375 } while (0)
376#define cpw16_f(reg,val) do { \
377 writew((val), cp->regs + (reg)); \
378 readw(cp->regs + (reg)); \
379 } while (0)
380#define cpw32_f(reg,val) do { \
381 writel((val), cp->regs + (reg)); \
382 readl(cp->regs + (reg)); \
383 } while (0)
384
385
386static void __cp_set_rx_mode (struct net_device *dev);
387static void cp_tx (struct cp_private *cp);
388static void cp_clean_rings (struct cp_private *cp);
7502cd10
SK		 389#ifdef CONFIG_NET_POLL_CONTROLLER
390static void cp_poll_controller(struct net_device *dev);
391#endif
722fdb33
PC		 392static int cp_get_eeprom_len(struct net_device *dev);
393static int cp_get_eeprom(struct net_device *dev,
394 struct ethtool_eeprom *eeprom, u8 *data);
395static int cp_set_eeprom(struct net_device *dev,
396 struct ethtool_eeprom *eeprom, u8 *data);
1da177e4 397
a3aa1884 398static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
cccb20d3
FR		 399 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
400 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
1da177e4
LT		 401 { },
402};
403MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
404
405static struct {
406 const char str[ETH_GSTRING_LEN];
407} ethtool_stats_keys[] = {
408 { "tx_ok" },
409 { "rx_ok" },
410 { "tx_err" },
411 { "rx_err" },
412 { "rx_fifo" },
413 { "frame_align" },
414 { "tx_ok_1col" },
415 { "tx_ok_mcol" },
416 { "rx_ok_phys" },
417 { "rx_ok_bcast" },
418 { "rx_ok_mcast" },
419 { "tx_abort" },
420 { "tx_underrun" },
421 { "rx_frags" },
422};
423
424
425#if CP_VLAN_TAG_USED
426static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
427{
428 struct cp_private *cp = netdev_priv(dev);
429 unsigned long flags;
430
431 spin_lock_irqsave(&cp->lock, flags);
432 cp->vlgrp = grp;
7b332244
SH		 433 if (grp)
434 cp->cpcmd |= RxVlanOn;
435 else
436 cp->cpcmd &= ~RxVlanOn;
1da177e4 437
1da177e4 438 cpw16(CpCmd, cp->cpcmd);
1da177e4
LT		 439 spin_unlock_irqrestore(&cp->lock, flags);
440}
441#endif /* CP_VLAN_TAG_USED */
442
443static inline void cp_set_rxbufsize (struct cp_private *cp)
444{
445 unsigned int mtu = cp->dev->mtu;
f3b197ac 446
1da177e4
LT		 447 if (mtu > ETH_DATA_LEN)
448 /* MTU + ethernet header + FCS + optional VLAN tag */
449 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
450 else
451 cp->rx_buf_sz = PKT_BUF_SZ;
452}
453
454static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
455 struct cp_desc *desc)
456{
457 skb->protocol = eth_type_trans (skb, cp->dev);
458
237225f7
PZ		 459 cp->dev->stats.rx_packets++;
460 cp->dev->stats.rx_bytes += skb->len;
1da177e4
LT		 461
462#if CP_VLAN_TAG_USED
cf983019 463 if (cp->vlgrp && (desc->opts2 & cpu_to_le32(RxVlanTagged))) {
1da177e4 464 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
cf983019 465 swab16(le32_to_cpu(desc->opts2) & 0xffff));
1da177e4
LT		 466 } else
467#endif
468 netif_receive_skb(skb);
469}
470
471static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
472 u32 status, u32 len)
473{
b4f18b3f
JP		 474 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
475 rx_tail, status, len);
237225f7 476 cp->dev->stats.rx_errors++;
1da177e4 477 if (status & RxErrFrame)
237225f7 478 cp->dev->stats.rx_frame_errors++;
1da177e4 479 if (status & RxErrCRC)
237225f7 480 cp->dev->stats.rx_crc_errors++;
1da177e4 481 if ((status & RxErrRunt) || (status & RxErrLong))
237225f7 482 cp->dev->stats.rx_length_errors++;
1da177e4 483 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
237225f7 484 cp->dev->stats.rx_length_errors++;
1da177e4 485 if (status & RxErrFIFO)
237225f7 486 cp->dev->stats.rx_fifo_errors++;
1da177e4
LT		 487}
488
489static inline unsigned int cp_rx_csum_ok (u32 status)
490{
491 unsigned int protocol = (status >> 16) & 0x3;
f3b197ac 492
1da177e4
LT		 493 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
494 return 1;
495 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
496 return 1;
497 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
498 return 1;
499 return 0;
500}
501
bea3348e 502static int cp_rx_poll(struct napi_struct *napi, int budget)
1da177e4 503{
bea3348e
SH		 504 struct cp_private *cp = container_of(napi, struct cp_private, napi);
505 struct net_device *dev = cp->dev;
506 unsigned int rx_tail = cp->rx_tail;
507 int rx;
1da177e4
LT		 508
509rx_status_loop:
510 rx = 0;
511 cpw16(IntrStatus, cp_rx_intr_mask);
512
513 while (1) {
514 u32 status, len;
515 dma_addr_t mapping;
516 struct sk_buff *skb, *new_skb;
517 struct cp_desc *desc;
839d1624 518 const unsigned buflen = cp->rx_buf_sz;
1da177e4 519
0ba894d4 520 skb = cp->rx_skb[rx_tail];
5d9428de 521 BUG_ON(!skb);
1da177e4
LT		 522
523 desc = &cp->rx_ring[rx_tail];
524 status = le32_to_cpu(desc->opts1);
525 if (status & DescOwn)
526 break;
527
528 len = (status & 0x1fff) - 4;
3598b57b 529 mapping = le64_to_cpu(desc->addr);
1da177e4
LT		 530
531 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
532 /* we don't support incoming fragmented frames.
533 * instead, we attempt to ensure that the
534 * pre-allocated RX skbs are properly sized such
535 * that RX fragments are never encountered
536 */
537 cp_rx_err_acct(cp, rx_tail, status, len);
237225f7 538 dev->stats.rx_dropped++;
1da177e4
LT		 539 cp->cp_stats.rx_frags++;
540 goto rx_next;
541 }
542
543 if (status & (RxError | RxErrFIFO)) {
544 cp_rx_err_acct(cp, rx_tail, status, len);
545 goto rx_next;
546 }
547
b4f18b3f
JP		 548 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
549 rx_tail, status, len);
1da177e4 550
89d71a66 551 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
1da177e4 552 if (!new_skb) {
237225f7 553 dev->stats.rx_dropped++;
1da177e4
LT		 554 goto rx_next;
555 }
556
6cc92cdd 557 dma_unmap_single(&cp->pdev->dev, mapping,
1da177e4
LT		 558 buflen, PCI_DMA_FROMDEVICE);
559
560 /* Handle checksum offloading for incoming packets. */
561 if (cp_rx_csum_ok(status))
562 skb->ip_summed = CHECKSUM_UNNECESSARY;
563 else
564 skb->ip_summed = CHECKSUM_NONE;
565
566 skb_put(skb, len);
567
6cc92cdd 568 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
3598b57b 569 PCI_DMA_FROMDEVICE);
0ba894d4 570 cp->rx_skb[rx_tail] = new_skb;
1da177e4
LT		 571
572 cp_rx_skb(cp, skb, desc);
573 rx++;
574
575rx_next:
576 cp->rx_ring[rx_tail].opts2 = 0;
577 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
578 if (rx_tail == (CP_RX_RING_SIZE - 1))
579 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
580 cp->rx_buf_sz);
581 else
582 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
583 rx_tail = NEXT_RX(rx_tail);
584
bea3348e 585 if (rx >= budget)
1da177e4
LT		 586 break;
587 }
588
589 cp->rx_tail = rx_tail;
590
1da177e4
LT		 591 /* if we did not reach work limit, then we're done with
592 * this round of polling
593 */
bea3348e 594 if (rx < budget) {
d15e9c4d
FR		 595 unsigned long flags;
596
1da177e4
LT		 597 if (cpr16(IntrStatus) & cp_rx_intr_mask)
598 goto rx_status_loop;
599
bea3348e 600 spin_lock_irqsave(&cp->lock, flags);
288379f0 601 __napi_complete(napi);
349124a0 602 cpw16_f(IntrMask, cp_intr_mask);
bea3348e 603 spin_unlock_irqrestore(&cp->lock, flags);
1da177e4
LT		 604 }
605
bea3348e 606 return rx;
1da177e4
LT		 607}
608
7d12e780 609static irqreturn_t cp_interrupt (int irq, void *dev_instance)
1da177e4
LT		 610{
611 struct net_device *dev = dev_instance;
612 struct cp_private *cp;
613 u16 status;
614
615 if (unlikely(dev == NULL))
616 return IRQ_NONE;
617 cp = netdev_priv(dev);
618
619 status = cpr16(IntrStatus);
620 if (!status || (status == 0xFFFF))
621 return IRQ_NONE;
622
b4f18b3f
JP		 623 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
624 status, cpr8(Cmd), cpr16(CpCmd));
1da177e4
LT		 625
626 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
627
628 spin_lock(&cp->lock);
629
630 /* close possible race's with dev_close */
631 if (unlikely(!netif_running(dev))) {
632 cpw16(IntrMask, 0);
633 spin_unlock(&cp->lock);
634 return IRQ_HANDLED;
635 }
636
637 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
288379f0 638 if (napi_schedule_prep(&cp->napi)) {
1da177e4 639 cpw16_f(IntrMask, cp_norx_intr_mask);
288379f0 640 __napi_schedule(&cp->napi);
1da177e4
LT		 641 }
642
643 if (status & (TxOK | TxErr | TxEmpty | SWInt))
644 cp_tx(cp);
645 if (status & LinkChg)
2501f843 646 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
1da177e4
LT		 647
648 spin_unlock(&cp->lock);
649
650 if (status & PciErr) {
651 u16 pci_status;
652
653 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
654 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
b4f18b3f
JP		 655 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
656 status, pci_status);
1da177e4
LT		 657
658 /* TODO: reset hardware */
659 }
660
661 return IRQ_HANDLED;
662}
663
7502cd10
SK		 664#ifdef CONFIG_NET_POLL_CONTROLLER
665/*
666 * Polling receive - used by netconsole and other diagnostic tools
667 * to allow network i/o with interrupts disabled.
668 */
669static void cp_poll_controller(struct net_device *dev)
670{
671 disable_irq(dev->irq);
7d12e780 672 cp_interrupt(dev->irq, dev);
7502cd10
SK		 673 enable_irq(dev->irq);
674}
675#endif
676
1da177e4
LT		 677static void cp_tx (struct cp_private *cp)
678{
679 unsigned tx_head = cp->tx_head;
680 unsigned tx_tail = cp->tx_tail;
681
682 while (tx_tail != tx_head) {
3598b57b 683 struct cp_desc *txd = cp->tx_ring + tx_tail;
1da177e4
LT		 684 struct sk_buff *skb;
685 u32 status;
686
687 rmb();
3598b57b 688 status = le32_to_cpu(txd->opts1);
1da177e4
LT		 689 if (status & DescOwn)
690 break;
691
48907e39 692 skb = cp->tx_skb[tx_tail];
5d9428de 693 BUG_ON(!skb);
1da177e4 694
6cc92cdd 695 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
48907e39
FR		 696 le32_to_cpu(txd->opts1) & 0xffff,
697 PCI_DMA_TODEVICE);
1da177e4
LT		 698
699 if (status & LastFrag) {
700 if (status & (TxError | TxFIFOUnder)) {
b4f18b3f
JP		 701 netif_dbg(cp, tx_err, cp->dev,
702 "tx err, status 0x%x\n", status);
237225f7 703 cp->dev->stats.tx_errors++;
1da177e4 704 if (status & TxOWC)
237225f7 705 cp->dev->stats.tx_window_errors++;
1da177e4 706 if (status & TxMaxCol)
237225f7 707 cp->dev->stats.tx_aborted_errors++;
1da177e4 708 if (status & TxLinkFail)
237225f7 709 cp->dev->stats.tx_carrier_errors++;
1da177e4 710 if (status & TxFIFOUnder)
237225f7 711 cp->dev->stats.tx_fifo_errors++;
1da177e4 712 } else {
237225f7 713 cp->dev->stats.collisions +=
1da177e4 714 ((status >> TxColCntShift) & TxColCntMask);
237225f7
PZ		 715 cp->dev->stats.tx_packets++;
716 cp->dev->stats.tx_bytes += skb->len;
b4f18b3f
JP		 717 netif_dbg(cp, tx_done, cp->dev,
718 "tx done, slot %d\n", tx_tail);
1da177e4
LT		 719 }
720 dev_kfree_skb_irq(skb);
721 }
722
48907e39 723 cp->tx_skb[tx_tail] = NULL;
1da177e4
LT		 724
725 tx_tail = NEXT_TX(tx_tail);
726 }
727
728 cp->tx_tail = tx_tail;
729
730 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
731 netif_wake_queue(cp->dev);
732}
733
61357325
SH		 734static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
735 struct net_device *dev)
1da177e4
LT		 736{
737 struct cp_private *cp = netdev_priv(dev);
738 unsigned entry;
fcec3456 739 u32 eor, flags;
553af567 740 unsigned long intr_flags;
1da177e4
LT		 741#if CP_VLAN_TAG_USED
742 u32 vlan_tag = 0;
743#endif
fcec3456 744 int mss = 0;
1da177e4 745
553af567 746 spin_lock_irqsave(&cp->lock, intr_flags);
1da177e4
LT		 747
748 /* This is a hard error, log it. */
749 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
750 netif_stop_queue(dev);
553af567 751 spin_unlock_irqrestore(&cp->lock, intr_flags);
b4f18b3f 752 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
5b548140 753 return NETDEV_TX_BUSY;
1da177e4
LT		 754 }
755
756#if CP_VLAN_TAG_USED
757 if (cp->vlgrp && vlan_tx_tag_present(skb))
cf983019 758 vlan_tag = TxVlanTag | swab16(vlan_tx_tag_get(skb));
1da177e4
LT		 759#endif
760
761 entry = cp->tx_head;
762 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
fcec3456 763 if (dev->features & NETIF_F_TSO)
7967168c 764 mss = skb_shinfo(skb)->gso_size;
fcec3456 765
1da177e4
LT		 766 if (skb_shinfo(skb)->nr_frags == 0) {
767 struct cp_desc *txd = &cp->tx_ring[entry];
768 u32 len;
769 dma_addr_t mapping;
770
771 len = skb->len;
6cc92cdd 772 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
1da177e4
LT		 773 CP_VLAN_TX_TAG(txd, vlan_tag);
774 txd->addr = cpu_to_le64(mapping);
775 wmb();
776
fcec3456
JG		 777 flags = eor | len | DescOwn | FirstFrag | LastFrag;
778
779 if (mss)
780 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
84fa7933 781 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 782 const struct iphdr *ip = ip_hdr(skb);
1da177e4 783 if (ip->protocol == IPPROTO_TCP)
fcec3456 784 flags |= IPCS | TCPCS;
1da177e4 785 else if (ip->protocol == IPPROTO_UDP)
fcec3456 786 flags |= IPCS | UDPCS;
1da177e4 787 else
5734418d 788 WARN_ON(1); /* we need a WARN() */
fcec3456
JG		 789 }
790
791 txd->opts1 = cpu_to_le32(flags);
1da177e4
LT		 792 wmb();
793
48907e39 794 cp->tx_skb[entry] = skb;
1da177e4
LT		 795 entry = NEXT_TX(entry);
796 } else {
797 struct cp_desc *txd;
798 u32 first_len, first_eor;
799 dma_addr_t first_mapping;
800 int frag, first_entry = entry;
eddc9ec5 801 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 802
803 /* We must give this initial chunk to the device last.
804 * Otherwise we could race with the device.
805 */
806 first_eor = eor;
807 first_len = skb_headlen(skb);
6cc92cdd 808 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
1da177e4 809 first_len, PCI_DMA_TODEVICE);
48907e39 810 cp->tx_skb[entry] = skb;
1da177e4
LT		 811 entry = NEXT_TX(entry);
812
813 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
814 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
815 u32 len;
816 u32 ctrl;
817 dma_addr_t mapping;
818
819 len = this_frag->size;
6cc92cdd 820 mapping = dma_map_single(&cp->pdev->dev,
1da177e4
LT		 821 ((void *) page_address(this_frag->page) +
822 this_frag->page_offset),
823 len, PCI_DMA_TODEVICE);
824 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
825
fcec3456
JG		 826 ctrl = eor | len | DescOwn;
827
828 if (mss)
829 ctrl |= LargeSend |
830 ((mss & MSSMask) << MSSShift);
84fa7933 831 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4 832 if (ip->protocol == IPPROTO_TCP)
fcec3456 833 ctrl |= IPCS | TCPCS;
1da177e4 834 else if (ip->protocol == IPPROTO_UDP)
fcec3456 835 ctrl |= IPCS | UDPCS;
1da177e4
LT		 836 else
837 BUG();
fcec3456 838 }
1da177e4
LT		 839
840 if (frag == skb_shinfo(skb)->nr_frags - 1)
841 ctrl |= LastFrag;
842
843 txd = &cp->tx_ring[entry];
844 CP_VLAN_TX_TAG(txd, vlan_tag);
845 txd->addr = cpu_to_le64(mapping);
846 wmb();
847
848 txd->opts1 = cpu_to_le32(ctrl);
849 wmb();
850
48907e39 851 cp->tx_skb[entry] = skb;
1da177e4
LT		 852 entry = NEXT_TX(entry);
853 }
854
855 txd = &cp->tx_ring[first_entry];
856 CP_VLAN_TX_TAG(txd, vlan_tag);
857 txd->addr = cpu_to_le64(first_mapping);
858 wmb();
859
84fa7933 860 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 861 if (ip->protocol == IPPROTO_TCP)
862 txd->opts1 = cpu_to_le32(first_eor | first_len |
863 FirstFrag | DescOwn |
864 IPCS | TCPCS);
865 else if (ip->protocol == IPPROTO_UDP)
866 txd->opts1 = cpu_to_le32(first_eor | first_len |
867 FirstFrag | DescOwn |
868 IPCS | UDPCS);
869 else
870 BUG();
871 } else
872 txd->opts1 = cpu_to_le32(first_eor | first_len |
873 FirstFrag | DescOwn);
874 wmb();
875 }
876 cp->tx_head = entry;
b4f18b3f
JP		 877 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
878 entry, skb->len);
1da177e4
LT		 879 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
880 netif_stop_queue(dev);
881
553af567 882 spin_unlock_irqrestore(&cp->lock, intr_flags);
1da177e4
LT		 883
884 cpw8(TxPoll, NormalTxPoll);
1da177e4 885
6ed10654 886 return NETDEV_TX_OK;
1da177e4
LT		 887}
888
889/* Set or clear the multicast filter for this adaptor.
890 This routine is not state sensitive and need not be SMP locked. */
891
892static void __cp_set_rx_mode (struct net_device *dev)
893{
894 struct cp_private *cp = netdev_priv(dev);
895 u32 mc_filter[2]; /* Multicast hash filter */
a56ed41d 896 int rx_mode;
1da177e4
LT		 897 u32 tmp;
898
899 /* Note: do not reorder, GCC is clever about common statements. */
900 if (dev->flags & IFF_PROMISC) {
901 /* Unconditionally log net taps. */
1da177e4
LT		 902 rx_mode =
903 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
904 AcceptAllPhys;
905 mc_filter[1] = mc_filter[0] = 0xffffffff;
a56ed41d 906 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 907 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 908 /* Too many to filter perfectly -- accept all multicasts. */
909 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
910 mc_filter[1] = mc_filter[0] = 0xffffffff;
911 } else {
22bedad3 912 struct netdev_hw_addr *ha;
1da177e4
LT		 913 rx_mode = AcceptBroadcast | AcceptMyPhys;
914 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 915 netdev_for_each_mc_addr(ha, dev) {
916 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 917
918 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
919 rx_mode |= AcceptMulticast;
920 }
921 }
922
923 /* We can safely update without stopping the chip. */
924 tmp = cp_rx_config | rx_mode;
925 if (cp->rx_config != tmp) {
926 cpw32_f (RxConfig, tmp);
927 cp->rx_config = tmp;
928 }
929 cpw32_f (MAR0 + 0, mc_filter[0]);
930 cpw32_f (MAR0 + 4, mc_filter[1]);
931}
932
933static void cp_set_rx_mode (struct net_device *dev)
934{
935 unsigned long flags;
936 struct cp_private *cp = netdev_priv(dev);
937
938 spin_lock_irqsave (&cp->lock, flags);
939 __cp_set_rx_mode(dev);
940 spin_unlock_irqrestore (&cp->lock, flags);
941}
942
943static void __cp_get_stats(struct cp_private *cp)
944{
945 /* only lower 24 bits valid; write any value to clear */
237225f7 946 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
1da177e4
LT		 947 cpw32 (RxMissed, 0);
948}
949
950static struct net_device_stats *cp_get_stats(struct net_device *dev)
951{
952 struct cp_private *cp = netdev_priv(dev);
953 unsigned long flags;
954
955 /* The chip only need report frame silently dropped. */
956 spin_lock_irqsave(&cp->lock, flags);
957 if (netif_running(dev) && netif_device_present(dev))
958 __cp_get_stats(cp);
959 spin_unlock_irqrestore(&cp->lock, flags);
960
237225f7 961 return &dev->stats;
1da177e4
LT		 962}
963
964static void cp_stop_hw (struct cp_private *cp)
965{
966 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
967 cpw16_f(IntrMask, 0);
968 cpw8(Cmd, 0);
969 cpw16_f(CpCmd, 0);
970 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
971
972 cp->rx_tail = 0;
973 cp->tx_head = cp->tx_tail = 0;
974}
975
976static void cp_reset_hw (struct cp_private *cp)
977{
978 unsigned work = 1000;
979
980 cpw8(Cmd, CmdReset);
981
982 while (work--) {
983 if (!(cpr8(Cmd) & CmdReset))
984 return;
985
3173c890 986 schedule_timeout_uninterruptible(10);
1da177e4
LT		 987 }
988
b4f18b3f 989 netdev_err(cp->dev, "hardware reset timeout\n");
1da177e4
LT		 990}
991
992static inline void cp_start_hw (struct cp_private *cp)
993{
994 cpw16(CpCmd, cp->cpcmd);
995 cpw8(Cmd, RxOn | TxOn);
996}
997
998static void cp_init_hw (struct cp_private *cp)
999{
1000 struct net_device *dev = cp->dev;
1001 dma_addr_t ring_dma;
1002
1003 cp_reset_hw(cp);
1004
1005 cpw8_f (Cfg9346, Cfg9346_Unlock);
1006
1007 /* Restore our idea of the MAC address. */
03233b90
AV		 1008 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1009 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1da177e4
LT		 1010
1011 cp_start_hw(cp);
1012 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1013
1014 __cp_set_rx_mode(dev);
1015 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1016
1017 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1018 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1019 cpw8(Config3, PARMEnable);
1020 cp->wol_enabled = 0;
1021
f3b197ac 1022 cpw8(Config5, cpr8(Config5) & PMEStatus);
1da177e4
LT		 1023
1024 cpw32_f(HiTxRingAddr, 0);
1025 cpw32_f(HiTxRingAddr + 4, 0);
1026
1027 ring_dma = cp->ring_dma;
1028 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1029 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1030
1031 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1032 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1033 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1034
1035 cpw16(MultiIntr, 0);
1036
1037 cpw16_f(IntrMask, cp_intr_mask);
1038
1039 cpw8_f(Cfg9346, Cfg9346_Lock);
1040}
1041
a52be1cb 1042static int cp_refill_rx(struct cp_private *cp)
1da177e4 1043{
a52be1cb 1044 struct net_device *dev = cp->dev;
1da177e4
LT		 1045 unsigned i;
1046
1047 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1048 struct sk_buff *skb;
3598b57b 1049 dma_addr_t mapping;
1da177e4 1050
89d71a66 1051 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1da177e4
LT		 1052 if (!skb)
1053 goto err_out;
1054
6cc92cdd
JG		 1055 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1056 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1057 cp->rx_skb[i] = skb;
1da177e4
LT		 1058
1059 cp->rx_ring[i].opts2 = 0;
3598b57b 1060 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1da177e4
LT		 1061 if (i == (CP_RX_RING_SIZE - 1))
1062 cp->rx_ring[i].opts1 =
1063 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1064 else
1065 cp->rx_ring[i].opts1 =
1066 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1067 }
1068
1069 return 0;
1070
1071err_out:
1072 cp_clean_rings(cp);
1073 return -ENOMEM;
1074}
1075
576cfa93
FR		 1076static void cp_init_rings_index (struct cp_private *cp)
1077{
1078 cp->rx_tail = 0;
1079 cp->tx_head = cp->tx_tail = 0;
1080}
1081
1da177e4
LT		 1082static int cp_init_rings (struct cp_private *cp)
1083{
1084 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1085 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1086
576cfa93 1087 cp_init_rings_index(cp);
1da177e4
LT		 1088
1089 return cp_refill_rx (cp);
1090}
1091
1092static int cp_alloc_rings (struct cp_private *cp)
1093{
1094 void *mem;
1095
6cc92cdd
JG		 1096 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1097 &cp->ring_dma, GFP_KERNEL);
1da177e4
LT		 1098 if (!mem)
1099 return -ENOMEM;
1100
1101 cp->rx_ring = mem;
1102 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1103
1da177e4
LT		 1104 return cp_init_rings(cp);
1105}
1106
1107static void cp_clean_rings (struct cp_private *cp)
1108{
3598b57b 1109 struct cp_desc *desc;
1da177e4
LT		 1110 unsigned i;
1111
1da177e4 1112 for (i = 0; i < CP_RX_RING_SIZE; i++) {
0ba894d4 1113 if (cp->rx_skb[i]) {
3598b57b 1114 desc = cp->rx_ring + i;
6cc92cdd 1115 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1da177e4 1116 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1117 dev_kfree_skb(cp->rx_skb[i]);
1da177e4
LT		 1118 }
1119 }
1120
1121 for (i = 0; i < CP_TX_RING_SIZE; i++) {
48907e39
FR		 1122 if (cp->tx_skb[i]) {
1123 struct sk_buff *skb = cp->tx_skb[i];
5734418d 1124
3598b57b 1125 desc = cp->tx_ring + i;
6cc92cdd 1126 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
48907e39
FR		 1127 le32_to_cpu(desc->opts1) & 0xffff,
1128 PCI_DMA_TODEVICE);
3598b57b 1129 if (le32_to_cpu(desc->opts1) & LastFrag)
5734418d 1130 dev_kfree_skb(skb);
237225f7 1131 cp->dev->stats.tx_dropped++;
1da177e4
LT		 1132 }
1133 }
1134
5734418d
FR		 1135 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1136 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1137
0ba894d4 1138 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
48907e39 1139 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1da177e4
LT		 1140}
1141
1142static void cp_free_rings (struct cp_private *cp)
1143{
1144 cp_clean_rings(cp);
6cc92cdd
JG		 1145 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1146 cp->ring_dma);
1da177e4
LT		 1147 cp->rx_ring = NULL;
1148 cp->tx_ring = NULL;
1da177e4
LT		 1149}
1150
1151static int cp_open (struct net_device *dev)
1152{
1153 struct cp_private *cp = netdev_priv(dev);
1154 int rc;
1155
b4f18b3f 1156 netif_dbg(cp, ifup, dev, "enabling interface\n");
1da177e4
LT		 1157
1158 rc = cp_alloc_rings(cp);
1159 if (rc)
1160 return rc;
1161
bea3348e
SH		 1162 napi_enable(&cp->napi);
1163
1da177e4
LT		 1164 cp_init_hw(cp);
1165
1fb9df5d 1166 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1167 if (rc)
1168 goto err_out_hw;
1169
1170 netif_carrier_off(dev);
2501f843 1171 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1da177e4
LT		 1172 netif_start_queue(dev);
1173
1174 return 0;
1175
1176err_out_hw:
bea3348e 1177 napi_disable(&cp->napi);
1da177e4
LT		 1178 cp_stop_hw(cp);
1179 cp_free_rings(cp);
1180 return rc;
1181}
1182
1183static int cp_close (struct net_device *dev)
1184{
1185 struct cp_private *cp = netdev_priv(dev);
1186 unsigned long flags;
1187
bea3348e
SH		 1188 napi_disable(&cp->napi);
1189
b4f18b3f 1190 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1da177e4
LT		 1191
1192 spin_lock_irqsave(&cp->lock, flags);
1193
1194 netif_stop_queue(dev);
1195 netif_carrier_off(dev);
1196
1197 cp_stop_hw(cp);
1198
1199 spin_unlock_irqrestore(&cp->lock, flags);
1200
1da177e4
LT		 1201 free_irq(dev->irq, dev);
1202
1203 cp_free_rings(cp);
1204 return 0;
1205}
1206
9030c0d2
FR		 1207static void cp_tx_timeout(struct net_device *dev)
1208{
1209 struct cp_private *cp = netdev_priv(dev);
1210 unsigned long flags;
1211 int rc;
1212
b4f18b3f
JP		 1213 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1214 cpr8(Cmd), cpr16(CpCmd),
1215 cpr16(IntrStatus), cpr16(IntrMask));
9030c0d2
FR		 1216
1217 spin_lock_irqsave(&cp->lock, flags);
1218
1219 cp_stop_hw(cp);
1220 cp_clean_rings(cp);
1221 rc = cp_init_rings(cp);
1222 cp_start_hw(cp);
1223
1224 netif_wake_queue(dev);
1225
1226 spin_unlock_irqrestore(&cp->lock, flags);
9030c0d2
FR		 1227}
1228
1da177e4
LT		 1229#ifdef BROKEN
1230static int cp_change_mtu(struct net_device *dev, int new_mtu)
1231{
1232 struct cp_private *cp = netdev_priv(dev);
1233 int rc;
1234 unsigned long flags;
1235
1236 /* check for invalid MTU, according to hardware limits */
1237 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1238 return -EINVAL;
1239
1240 /* if network interface not up, no need for complexity */
1241 if (!netif_running(dev)) {
1242 dev->mtu = new_mtu;
1243 cp_set_rxbufsize(cp); /* set new rx buf size */
1244 return 0;
1245 }
1246
1247 spin_lock_irqsave(&cp->lock, flags);
1248
1249 cp_stop_hw(cp); /* stop h/w and free rings */
1250 cp_clean_rings(cp);
1251
1252 dev->mtu = new_mtu;
1253 cp_set_rxbufsize(cp); /* set new rx buf size */
1254
1255 rc = cp_init_rings(cp); /* realloc and restart h/w */
1256 cp_start_hw(cp);
1257
1258 spin_unlock_irqrestore(&cp->lock, flags);
1259
1260 return rc;
1261}
1262#endif /* BROKEN */
1263
f71e1309 1264static const char mii_2_8139_map[8] = {
1da177e4
LT		 1265 BasicModeCtrl,
1266 BasicModeStatus,
1267 0,
1268 0,
1269 NWayAdvert,
1270 NWayLPAR,
1271 NWayExpansion,
1272 0
1273};
1274
1275static int mdio_read(struct net_device *dev, int phy_id, int location)
1276{
1277 struct cp_private *cp = netdev_priv(dev);
1278
1279 return location < 8 && mii_2_8139_map[location] ?
1280 readw(cp->regs + mii_2_8139_map[location]) : 0;
1281}
1282
1283
1284static void mdio_write(struct net_device *dev, int phy_id, int location,
1285 int value)
1286{
1287 struct cp_private *cp = netdev_priv(dev);
1288
1289 if (location == 0) {
1290 cpw8(Cfg9346, Cfg9346_Unlock);
1291 cpw16(BasicModeCtrl, value);
1292 cpw8(Cfg9346, Cfg9346_Lock);
1293 } else if (location < 8 && mii_2_8139_map[location])
1294 cpw16(mii_2_8139_map[location], value);
1295}
1296
1297/* Set the ethtool Wake-on-LAN settings */
1298static int netdev_set_wol (struct cp_private *cp,
1299 const struct ethtool_wolinfo *wol)
1300{
1301 u8 options;
1302
1303 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1304 /* If WOL is being disabled, no need for complexity */
1305 if (wol->wolopts) {
1306 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1307 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1308 }
1309
1310 cpw8 (Cfg9346, Cfg9346_Unlock);
1311 cpw8 (Config3, options);
1312 cpw8 (Cfg9346, Cfg9346_Lock);
1313
1314 options = 0; /* Paranoia setting */
1315 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1316 /* If WOL is being disabled, no need for complexity */
1317 if (wol->wolopts) {
1318 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1319 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1320 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1321 }
1322
1323 cpw8 (Config5, options);
1324
1325 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1326
1327 return 0;
1328}
1329
1330/* Get the ethtool Wake-on-LAN settings */
1331static void netdev_get_wol (struct cp_private *cp,
1332 struct ethtool_wolinfo *wol)
1333{
1334 u8 options;
1335
1336 wol->wolopts = 0; /* Start from scratch */
1337 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1338 WAKE_MCAST | WAKE_UCAST;
1339 /* We don't need to go on if WOL is disabled */
1340 if (!cp->wol_enabled) return;
f3b197ac 1341
1da177e4
LT		 1342 options = cpr8 (Config3);
1343 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1344 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1345
1346 options = 0; /* Paranoia setting */
1347 options = cpr8 (Config5);
1348 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1349 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1350 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1351}
1352
1353static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1354{
1355 struct cp_private *cp = netdev_priv(dev);
1356
1357 strcpy (info->driver, DRV_NAME);
1358 strcpy (info->version, DRV_VERSION);
1359 strcpy (info->bus_info, pci_name(cp->pdev));
1360}
1361
1362static int cp_get_regs_len(struct net_device *dev)
1363{
1364 return CP_REGS_SIZE;
1365}
1366
b9f2c044 1367static int cp_get_sset_count (struct net_device *dev, int sset)
1da177e4 1368{
b9f2c044
JG		 1369 switch (sset) {
1370 case ETH_SS_STATS:
1371 return CP_NUM_STATS;
1372 default:
1373 return -EOPNOTSUPP;
1374 }
1da177e4
LT		 1375}
1376
1377static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1378{
1379 struct cp_private *cp = netdev_priv(dev);
1380 int rc;
1381 unsigned long flags;
1382
1383 spin_lock_irqsave(&cp->lock, flags);
1384 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1385 spin_unlock_irqrestore(&cp->lock, flags);
1386
1387 return rc;
1388}
1389
1390static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1391{
1392 struct cp_private *cp = netdev_priv(dev);
1393 int rc;
1394 unsigned long flags;
1395
1396 spin_lock_irqsave(&cp->lock, flags);
1397 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1398 spin_unlock_irqrestore(&cp->lock, flags);
1399
1400 return rc;
1401}
1402
1403static int cp_nway_reset(struct net_device *dev)
1404{
1405 struct cp_private *cp = netdev_priv(dev);
1406 return mii_nway_restart(&cp->mii_if);
1407}
1408
1409static u32 cp_get_msglevel(struct net_device *dev)
1410{
1411 struct cp_private *cp = netdev_priv(dev);
1412 return cp->msg_enable;
1413}
1414
1415static void cp_set_msglevel(struct net_device *dev, u32 value)
1416{
1417 struct cp_private *cp = netdev_priv(dev);
1418 cp->msg_enable = value;
1419}
1420
1421static u32 cp_get_rx_csum(struct net_device *dev)
1422{
1423 struct cp_private *cp = netdev_priv(dev);
1424 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1425}
1426
1427static int cp_set_rx_csum(struct net_device *dev, u32 data)
1428{
1429 struct cp_private *cp = netdev_priv(dev);
1430 u16 cmd = cp->cpcmd, newcmd;
1431
1432 newcmd = cmd;
1433
1434 if (data)
1435 newcmd |= RxChkSum;
1436 else
1437 newcmd &= ~RxChkSum;
1438
1439 if (newcmd != cmd) {
1440 unsigned long flags;
1441
1442 spin_lock_irqsave(&cp->lock, flags);
1443 cp->cpcmd = newcmd;
1444 cpw16_f(CpCmd, newcmd);
1445 spin_unlock_irqrestore(&cp->lock, flags);
1446 }
1447
1448 return 0;
1449}
1450
1451static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1452 void *p)
1453{
1454 struct cp_private *cp = netdev_priv(dev);
1455 unsigned long flags;
1456
1457 if (regs->len < CP_REGS_SIZE)
1458 return /* -EINVAL */;
1459
1460 regs->version = CP_REGS_VER;
1461
1462 spin_lock_irqsave(&cp->lock, flags);
1463 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1464 spin_unlock_irqrestore(&cp->lock, flags);
1465}
1466
1467static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1468{
1469 struct cp_private *cp = netdev_priv(dev);
1470 unsigned long flags;
1471
1472 spin_lock_irqsave (&cp->lock, flags);
1473 netdev_get_wol (cp, wol);
1474 spin_unlock_irqrestore (&cp->lock, flags);
1475}
1476
1477static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1478{
1479 struct cp_private *cp = netdev_priv(dev);
1480 unsigned long flags;
1481 int rc;
1482
1483 spin_lock_irqsave (&cp->lock, flags);
1484 rc = netdev_set_wol (cp, wol);
1485 spin_unlock_irqrestore (&cp->lock, flags);
1486
1487 return rc;
1488}
1489
1490static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1491{
1492 switch (stringset) {
1493 case ETH_SS_STATS:
1494 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1495 break;
1496 default:
1497 BUG();
1498 break;
1499 }
1500}
1501
1502static void cp_get_ethtool_stats (struct net_device *dev,
1503 struct ethtool_stats *estats, u64 *tmp_stats)
1504{
1505 struct cp_private *cp = netdev_priv(dev);
8b512927
SH		 1506 struct cp_dma_stats *nic_stats;
1507 dma_addr_t dma;
1da177e4
LT		 1508 int i;
1509
6cc92cdd
JG		 1510 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1511 &dma, GFP_KERNEL);
8b512927
SH		 1512 if (!nic_stats)
1513 return;
97f568d8 1514
1da177e4 1515 /* begin NIC statistics dump */
8b512927 1516 cpw32(StatsAddr + 4, (u64)dma >> 32);
284901a9 1517 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1da177e4
LT		 1518 cpr32(StatsAddr);
1519
97f568d8 1520 for (i = 0; i < 1000; i++) {
1da177e4
LT		 1521 if ((cpr32(StatsAddr) & DumpStats) == 0)
1522 break;
97f568d8 1523 udelay(10);
1da177e4 1524 }
97f568d8
SH		 1525 cpw32(StatsAddr, 0);
1526 cpw32(StatsAddr + 4, 0);
8b512927 1527 cpr32(StatsAddr);
1da177e4
LT		 1528
1529 i = 0;
8b512927
SH		 1530 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1531 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1532 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1533 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1534 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1535 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1536 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1537 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1538 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1539 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1540 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1541 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1542 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1da177e4 1543 tmp_stats[i++] = cp->cp_stats.rx_frags;
5d9428de 1544 BUG_ON(i != CP_NUM_STATS);
8b512927 1545
6cc92cdd 1546 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1da177e4
LT		 1547}
1548
7282d491 1549static const struct ethtool_ops cp_ethtool_ops = {
1da177e4
LT		 1550 .get_drvinfo = cp_get_drvinfo,
1551 .get_regs_len = cp_get_regs_len,
b9f2c044 1552 .get_sset_count = cp_get_sset_count,
1da177e4
LT		 1553 .get_settings = cp_get_settings,
1554 .set_settings = cp_set_settings,
1555 .nway_reset = cp_nway_reset,
1556 .get_link = ethtool_op_get_link,
1557 .get_msglevel = cp_get_msglevel,
1558 .set_msglevel = cp_set_msglevel,
1559 .get_rx_csum = cp_get_rx_csum,
1560 .set_rx_csum = cp_set_rx_csum,
1da177e4 1561 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1da177e4 1562 .set_sg = ethtool_op_set_sg,
fcec3456 1563 .set_tso = ethtool_op_set_tso,
1da177e4
LT		 1564 .get_regs = cp_get_regs,
1565 .get_wol = cp_get_wol,
1566 .set_wol = cp_set_wol,
1567 .get_strings = cp_get_strings,
1568 .get_ethtool_stats = cp_get_ethtool_stats,
722fdb33
PC		 1569 .get_eeprom_len = cp_get_eeprom_len,
1570 .get_eeprom = cp_get_eeprom,
1571 .set_eeprom = cp_set_eeprom,
1da177e4
LT		 1572};
1573
1574static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1575{
1576 struct cp_private *cp = netdev_priv(dev);
1577 int rc;
1578 unsigned long flags;
1579
1580 if (!netif_running(dev))
1581 return -EINVAL;
1582
1583 spin_lock_irqsave(&cp->lock, flags);
1584 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1585 spin_unlock_irqrestore(&cp->lock, flags);
1586 return rc;
1587}
1588
c048aaf4
JP		 1589static int cp_set_mac_address(struct net_device *dev, void *p)
1590{
1591 struct cp_private *cp = netdev_priv(dev);
1592 struct sockaddr *addr = p;
1593
1594 if (!is_valid_ether_addr(addr->sa_data))
1595 return -EADDRNOTAVAIL;
1596
1597 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1598
1599 spin_lock_irq(&cp->lock);
1600
1601 cpw8_f(Cfg9346, Cfg9346_Unlock);
1602 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1603 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1604 cpw8_f(Cfg9346, Cfg9346_Lock);
1605
1606 spin_unlock_irq(&cp->lock);
1607
1608 return 0;
1609}
1610
1da177e4
LT		 1611/* Serial EEPROM section. */
1612
1613/* EEPROM_Ctrl bits. */
1614#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1615#define EE_CS 0x08 /* EEPROM chip select. */
1616#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1617#define EE_WRITE_0 0x00
1618#define EE_WRITE_1 0x02
1619#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1620#define EE_ENB (0x80 | EE_CS)
1621
1622/* Delay between EEPROM clock transitions.
1623 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1624 */
1625
1626#define eeprom_delay() readl(ee_addr)
1627
1628/* The EEPROM commands include the alway-set leading bit. */
722fdb33 1629#define EE_EXTEND_CMD (4)
1da177e4
LT		 1630#define EE_WRITE_CMD (5)
1631#define EE_READ_CMD (6)
1632#define EE_ERASE_CMD (7)
1633
722fdb33
PC		 1634#define EE_EWDS_ADDR (0)
1635#define EE_WRAL_ADDR (1)
1636#define EE_ERAL_ADDR (2)
1637#define EE_EWEN_ADDR (3)
1638
1639#define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1da177e4 1640
722fdb33
PC		 1641static void eeprom_cmd_start(void __iomem *ee_addr)
1642{
1da177e4
LT		 1643 writeb (EE_ENB & ~EE_CS, ee_addr);
1644 writeb (EE_ENB, ee_addr);
1645 eeprom_delay ();
722fdb33 1646}
1da177e4 1647
722fdb33
PC		 1648static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1649{
1650 int i;
1651
1652 /* Shift the command bits out. */
1653 for (i = cmd_len - 1; i >= 0; i--) {
1654 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1da177e4
LT		 1655 writeb (EE_ENB | dataval, ee_addr);
1656 eeprom_delay ();
1657 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1658 eeprom_delay ();
1659 }
1660 writeb (EE_ENB, ee_addr);
1661 eeprom_delay ();
722fdb33
PC		 1662}
1663
1664static void eeprom_cmd_end(void __iomem *ee_addr)
1665{
1666 writeb (~EE_CS, ee_addr);
1667 eeprom_delay ();
1668}
1669
1670static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1671 int addr_len)
1672{
1673 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1674
1675 eeprom_cmd_start(ee_addr);
1676 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1677 eeprom_cmd_end(ee_addr);
1678}
1679
1680static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1681{
1682 int i;
1683 u16 retval = 0;
1684 void __iomem *ee_addr = ioaddr + Cfg9346;
1685 int read_cmd = location | (EE_READ_CMD << addr_len);
1686
1687 eeprom_cmd_start(ee_addr);
1688 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1da177e4
LT		 1689
1690 for (i = 16; i > 0; i--) {
1691 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1692 eeprom_delay ();
1693 retval =
1694 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1695 0);
1696 writeb (EE_ENB, ee_addr);
1697 eeprom_delay ();
1698 }
1699
722fdb33 1700 eeprom_cmd_end(ee_addr);
1da177e4
LT		 1701
1702 return retval;
1703}
1704
722fdb33
PC		 1705static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1706 int addr_len)
1707{
1708 int i;
1709 void __iomem *ee_addr = ioaddr + Cfg9346;
1710 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1711
1712 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1713
1714 eeprom_cmd_start(ee_addr);
1715 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1716 eeprom_cmd(ee_addr, val, 16);
1717 eeprom_cmd_end(ee_addr);
1718
1719 eeprom_cmd_start(ee_addr);
1720 for (i = 0; i < 20000; i++)
1721 if (readb(ee_addr) & EE_DATA_READ)
1722 break;
1723 eeprom_cmd_end(ee_addr);
1724
1725 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1726}
1727
1728static int cp_get_eeprom_len(struct net_device *dev)
1729{
1730 struct cp_private *cp = netdev_priv(dev);
1731 int size;
1732
1733 spin_lock_irq(&cp->lock);
1734 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1735 spin_unlock_irq(&cp->lock);
1736
1737 return size;
1738}
1739
1740static int cp_get_eeprom(struct net_device *dev,
1741 struct ethtool_eeprom *eeprom, u8 *data)
1742{
1743 struct cp_private *cp = netdev_priv(dev);
1744 unsigned int addr_len;
1745 u16 val;
1746 u32 offset = eeprom->offset >> 1;
1747 u32 len = eeprom->len;
1748 u32 i = 0;
1749
1750 eeprom->magic = CP_EEPROM_MAGIC;
1751
1752 spin_lock_irq(&cp->lock);
1753
1754 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1755
1756 if (eeprom->offset & 1) {
1757 val = read_eeprom(cp->regs, offset, addr_len);
1758 data[i++] = (u8)(val >> 8);
1759 offset++;
1760 }
1761
1762 while (i < len - 1) {
1763 val = read_eeprom(cp->regs, offset, addr_len);
1764 data[i++] = (u8)val;
1765 data[i++] = (u8)(val >> 8);
1766 offset++;
1767 }
1768
1769 if (i < len) {
1770 val = read_eeprom(cp->regs, offset, addr_len);
1771 data[i] = (u8)val;
1772 }
1773
1774 spin_unlock_irq(&cp->lock);
1775 return 0;
1776}
1777
1778static int cp_set_eeprom(struct net_device *dev,
1779 struct ethtool_eeprom *eeprom, u8 *data)
1780{
1781 struct cp_private *cp = netdev_priv(dev);
1782 unsigned int addr_len;
1783 u16 val;
1784 u32 offset = eeprom->offset >> 1;
1785 u32 len = eeprom->len;
1786 u32 i = 0;
1787
1788 if (eeprom->magic != CP_EEPROM_MAGIC)
1789 return -EINVAL;
1790
1791 spin_lock_irq(&cp->lock);
1792
1793 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1794
1795 if (eeprom->offset & 1) {
1796 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1797 val |= (u16)data[i++] << 8;
1798 write_eeprom(cp->regs, offset, val, addr_len);
1799 offset++;
1800 }
1801
1802 while (i < len - 1) {
1803 val = (u16)data[i++];
1804 val |= (u16)data[i++] << 8;
1805 write_eeprom(cp->regs, offset, val, addr_len);
1806 offset++;
1807 }
1808
1809 if (i < len) {
1810 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1811 val |= (u16)data[i];
1812 write_eeprom(cp->regs, offset, val, addr_len);
1813 }
1814
1815 spin_unlock_irq(&cp->lock);
1816 return 0;
1817}
1818
1da177e4
LT		 1819/* Put the board into D3cold state and wait for WakeUp signal */
1820static void cp_set_d3_state (struct cp_private *cp)
1821{
1822 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1823 pci_set_power_state (cp->pdev, PCI_D3hot);
1824}
1825
48dfcde4
SH		 1826static const struct net_device_ops cp_netdev_ops = {
1827 .ndo_open = cp_open,
1828 .ndo_stop = cp_close,
1829 .ndo_validate_addr = eth_validate_addr,
c048aaf4 1830 .ndo_set_mac_address = cp_set_mac_address,
48dfcde4
SH		 1831 .ndo_set_multicast_list = cp_set_rx_mode,
1832 .ndo_get_stats = cp_get_stats,
1833 .ndo_do_ioctl = cp_ioctl,
00829823 1834 .ndo_start_xmit = cp_start_xmit,
48dfcde4
SH		 1835 .ndo_tx_timeout = cp_tx_timeout,
1836#if CP_VLAN_TAG_USED
1837 .ndo_vlan_rx_register = cp_vlan_rx_register,
1838#endif
1839#ifdef BROKEN
1840 .ndo_change_mtu = cp_change_mtu,
1841#endif
fe96aaa1 1842
48dfcde4
SH		 1843#ifdef CONFIG_NET_POLL_CONTROLLER
1844 .ndo_poll_controller = cp_poll_controller,
1845#endif
1846};
1847
1da177e4
LT		 1848static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1849{
1850 struct net_device *dev;
1851 struct cp_private *cp;
1852 int rc;
1853 void __iomem *regs;
2427ddd8 1854 resource_size_t pciaddr;
1da177e4 1855 unsigned int addr_len, i, pci_using_dac;
1da177e4
LT		 1856
1857#ifndef MODULE
1858 static int version_printed;
1859 if (version_printed++ == 0)
b93d5847 1860 pr_info("%s", version);
1da177e4
LT		 1861#endif
1862
1da177e4 1863 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
44c10138 1864 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
de4549ca 1865 dev_info(&pdev->dev,
b4f18b3f
JP		 1866 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1867 pdev->vendor, pdev->device, pdev->revision);
1da177e4
LT		 1868 return -ENODEV;
1869 }
1870
1871 dev = alloc_etherdev(sizeof(struct cp_private));
1872 if (!dev)
1873 return -ENOMEM;
1da177e4
LT		 1874 SET_NETDEV_DEV(dev, &pdev->dev);
1875
1876 cp = netdev_priv(dev);
1877 cp->pdev = pdev;
1878 cp->dev = dev;
1879 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1880 spin_lock_init (&cp->lock);
1881 cp->mii_if.dev = dev;
1882 cp->mii_if.mdio_read = mdio_read;
1883 cp->mii_if.mdio_write = mdio_write;
1884 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1885 cp->mii_if.phy_id_mask = 0x1f;
1886 cp->mii_if.reg_num_mask = 0x1f;
1887 cp_set_rxbufsize(cp);
1888
1889 rc = pci_enable_device(pdev);
1890 if (rc)
1891 goto err_out_free;
1892
1893 rc = pci_set_mwi(pdev);
1894 if (rc)
1895 goto err_out_disable;
1896
1897 rc = pci_request_regions(pdev, DRV_NAME);
1898 if (rc)
1899 goto err_out_mwi;
1900
1901 pciaddr = pci_resource_start(pdev, 1);
1902 if (!pciaddr) {
1903 rc = -EIO;
9b91cf9d 1904 dev_err(&pdev->dev, "no MMIO resource\n");
1da177e4
LT		 1905 goto err_out_res;
1906 }
1907 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1908 rc = -EIO;
9b91cf9d 1909 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
2e8a538d 1910 (unsigned long long)pci_resource_len(pdev, 1));
1da177e4
LT		 1911 goto err_out_res;
1912 }
1913
1914 /* Configure DMA attributes. */
1915 if ((sizeof(dma_addr_t) > 4) &&
6a35528a
YH		 1916 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1917 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4
LT		 1918 pci_using_dac = 1;
1919 } else {
1920 pci_using_dac = 0;
1921
284901a9 1922 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 1923 if (rc) {
9b91cf9d 1924 dev_err(&pdev->dev,
b4f18b3f 1925 "No usable DMA configuration, aborting\n");
1da177e4
LT		 1926 goto err_out_res;
1927 }
284901a9 1928 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 1929 if (rc) {
9b91cf9d 1930 dev_err(&pdev->dev,
b4f18b3f 1931 "No usable consistent DMA configuration, aborting\n");
1da177e4
LT		 1932 goto err_out_res;
1933 }
1934 }
1935
1936 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1937 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1938
1939 regs = ioremap(pciaddr, CP_REGS_SIZE);
1940 if (!regs) {
1941 rc = -EIO;
4626dd46 1942 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
b4f18b3f 1943 (unsigned long long)pci_resource_len(pdev, 1),
2e8a538d 1944 (unsigned long long)pciaddr);
1da177e4
LT		 1945 goto err_out_res;
1946 }
1947 dev->base_addr = (unsigned long) regs;
1948 cp->regs = regs;
1949
1950 cp_stop_hw(cp);
1951
1952 /* read MAC address from EEPROM */
1953 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1954 for (i = 0; i < 3; i++)
03233b90
AV		 1955 ((__le16 *) (dev->dev_addr))[i] =
1956 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
bb0ce608 1957 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 1958
48dfcde4 1959 dev->netdev_ops = &cp_netdev_ops;
bea3348e 1960 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1da177e4 1961 dev->ethtool_ops = &cp_ethtool_ops;
1da177e4 1962 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4
LT		 1963
1964#if CP_VLAN_TAG_USED
1965 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 1966#endif
1967
1968 if (pci_using_dac)
1969 dev->features |= NETIF_F_HIGHDMA;
1970
fcec3456
JG		 1971#if 0 /* disabled by default until verified */
1972 dev->features |= NETIF_F_TSO;
1973#endif
1974
1da177e4
LT		 1975 dev->irq = pdev->irq;
1976
1977 rc = register_netdev(dev);
1978 if (rc)
1979 goto err_out_iomap;
1980
b4f18b3f
JP		 1981 netdev_info(dev, "RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1982 dev->base_addr, dev->dev_addr, dev->irq);
1da177e4
LT		 1983
1984 pci_set_drvdata(pdev, dev);
1985
1986 /* enable busmastering and memory-write-invalidate */
1987 pci_set_master(pdev);
1988
2e8a538d
JG		 1989 if (cp->wol_enabled)
1990 cp_set_d3_state (cp);
1da177e4
LT		 1991
1992 return 0;
1993
1994err_out_iomap:
1995 iounmap(regs);
1996err_out_res:
1997 pci_release_regions(pdev);
1998err_out_mwi:
1999 pci_clear_mwi(pdev);
2000err_out_disable:
2001 pci_disable_device(pdev);
2002err_out_free:
2003 free_netdev(dev);
2004 return rc;
2005}
2006
2007static void cp_remove_one (struct pci_dev *pdev)
2008{
2009 struct net_device *dev = pci_get_drvdata(pdev);
2010 struct cp_private *cp = netdev_priv(dev);
2011
1da177e4
LT		 2012 unregister_netdev(dev);
2013 iounmap(cp->regs);
2e8a538d
JG		 2014 if (cp->wol_enabled)
2015 pci_set_power_state (pdev, PCI_D0);
1da177e4
LT		 2016 pci_release_regions(pdev);
2017 pci_clear_mwi(pdev);
2018 pci_disable_device(pdev);
2019 pci_set_drvdata(pdev, NULL);
2020 free_netdev(dev);
2021}
2022
2023#ifdef CONFIG_PM
05adc3b7 2024static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4 2025{
7668a494
FR		 2026 struct net_device *dev = pci_get_drvdata(pdev);
2027 struct cp_private *cp = netdev_priv(dev);
1da177e4
LT		 2028 unsigned long flags;
2029
7668a494
FR		 2030 if (!netif_running(dev))
2031 return 0;
1da177e4
LT		 2032
2033 netif_device_detach (dev);
2034 netif_stop_queue (dev);
2035
2036 spin_lock_irqsave (&cp->lock, flags);
2037
2038 /* Disable Rx and Tx */
2039 cpw16 (IntrMask, 0);
2040 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2041
2042 spin_unlock_irqrestore (&cp->lock, flags);
2043
576cfa93
FR		 2044 pci_save_state(pdev);
2045 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2046 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 2047
2048 return 0;
2049}
2050
2051static int cp_resume (struct pci_dev *pdev)
2052{
576cfa93
FR		 2053 struct net_device *dev = pci_get_drvdata (pdev);
2054 struct cp_private *cp = netdev_priv(dev);
a4cf0761 2055 unsigned long flags;
1da177e4 2056
576cfa93
FR		 2057 if (!netif_running(dev))
2058 return 0;
1da177e4
LT		 2059
2060 netif_device_attach (dev);
576cfa93
FR		 2061
2062 pci_set_power_state(pdev, PCI_D0);
2063 pci_restore_state(pdev);
2064 pci_enable_wake(pdev, PCI_D0, 0);
2065
2066 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2067 cp_init_rings_index (cp);
1da177e4
LT		 2068 cp_init_hw (cp);
2069 netif_start_queue (dev);
a4cf0761
PO		 2070
2071 spin_lock_irqsave (&cp->lock, flags);
2072
2501f843 2073 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
a4cf0761
PO		 2074
2075 spin_unlock_irqrestore (&cp->lock, flags);
f3b197ac 2076
1da177e4
LT		 2077 return 0;
2078}
2079#endif /* CONFIG_PM */
2080
2081static struct pci_driver cp_driver = {
2082 .name = DRV_NAME,
2083 .id_table = cp_pci_tbl,
2084 .probe = cp_init_one,
2085 .remove = cp_remove_one,
2086#ifdef CONFIG_PM
2087 .resume = cp_resume,
2088 .suspend = cp_suspend,
2089#endif
2090};
2091
2092static int __init cp_init (void)
2093{
2094#ifdef MODULE
b93d5847 2095 pr_info("%s", version);
1da177e4 2096#endif
29917620 2097 return pci_register_driver(&cp_driver);
1da177e4
LT		 2098}
2099
2100static void __exit cp_exit (void)
2101{
2102 pci_unregister_driver (&cp_driver);
2103}
2104
2105module_init(cp_init);
2106module_exit(cp_exit);
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