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[TG3]: Fix race condition when calling register_netdev().
[net-next-2.6.git] / drivers / net / 8139cp.c
CommitLineData
1da177e4
LT		 1/* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2/*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
f3b197ac 22
1da177e4
LT		 23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
f3b197ac 26
1da177e4
LT		 27 TODO:
28 * Test Tx checksumming thoroughly
29 * Implement dev->tx_timeout
30
31 Low priority TODO:
32 * Complete reset on PciErr
33 * Consider Rx interrupt mitigation using TimerIntr
34 * Investigate using skb->priority with h/w VLAN priority
35 * Investigate using High Priority Tx Queue with skb->priority
36 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
37 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
38 * Implement Tx software interrupt mitigation via
39 Tx descriptor bit
40 * The real minimum of CP_MIN_MTU is 4 bytes. However,
41 for this to be supported, one must(?) turn on packet padding.
42 * Support external MII transceivers (patch available)
43
44 NOTES:
45 * TX checksumming is considered experimental. It is off by
46 default, use ethtool to turn it on.
47
48 */
49
50#define DRV_NAME "8139cp"
d5b20697 51#define DRV_VERSION "1.3"
1da177e4
LT		 52#define DRV_RELDATE "Mar 22, 2004"
53
54
1da177e4 55#include <linux/module.h>
e21ba282 56#include <linux/moduleparam.h>
1da177e4
LT		 57#include <linux/kernel.h>
58#include <linux/compiler.h>
59#include <linux/netdevice.h>
60#include <linux/etherdevice.h>
61#include <linux/init.h>
62#include <linux/pci.h>
8662d061 63#include <linux/dma-mapping.h>
1da177e4
LT		 64#include <linux/delay.h>
65#include <linux/ethtool.h>
66#include <linux/mii.h>
67#include <linux/if_vlan.h>
68#include <linux/crc32.h>
69#include <linux/in.h>
70#include <linux/ip.h>
71#include <linux/tcp.h>
72#include <linux/udp.h>
73#include <linux/cache.h>
74#include <asm/io.h>
75#include <asm/irq.h>
76#include <asm/uaccess.h>
77
78/* VLAN tagging feature enable/disable */
79#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
80#define CP_VLAN_TAG_USED 1
81#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
82 do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
83#else
84#define CP_VLAN_TAG_USED 0
85#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
86 do { (tx_desc)->opts2 = 0; } while (0)
87#endif
88
89/* These identify the driver base version and may not be removed. */
90static char version[] =
91KERN_INFO DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
92
93MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
94MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
a78d8927 95MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 96MODULE_LICENSE("GPL");
97
98static int debug = -1;
e21ba282 99module_param(debug, int, 0);
1da177e4
LT		 100MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
101
102/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
103 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
104static int multicast_filter_limit = 32;
e21ba282 105module_param(multicast_filter_limit, int, 0);
1da177e4
LT		 106MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
107
108#define PFX DRV_NAME ": "
109
110#ifndef TRUE
111#define FALSE 0
112#define TRUE (!FALSE)
113#endif
114
115#define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
116 NETIF_MSG_PROBE | \
117 NETIF_MSG_LINK)
118#define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
119#define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
120#define CP_REGS_SIZE (0xff + 1)
121#define CP_REGS_VER 1 /* version 1 */
122#define CP_RX_RING_SIZE 64
123#define CP_TX_RING_SIZE 64
124#define CP_RING_BYTES \
125 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
126 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
127 CP_STATS_SIZE)
128#define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
129#define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
130#define TX_BUFFS_AVAIL(CP) \
131 (((CP)->tx_tail <= (CP)->tx_head) ? \
132 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
133 (CP)->tx_tail - (CP)->tx_head - 1)
134
135#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
136#define RX_OFFSET 2
137#define CP_INTERNAL_PHY 32
138
139/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
140#define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
141#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
142#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
143#define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
144
145/* Time in jiffies before concluding the transmitter is hung. */
146#define TX_TIMEOUT (6*HZ)
147
148/* hardware minimum and maximum for a single frame's data payload */
149#define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
150#define CP_MAX_MTU 4096
151
152enum {
153 /* NIC register offsets */
154 MAC0 = 0x00, /* Ethernet hardware address. */
155 MAR0 = 0x08, /* Multicast filter. */
156 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
157 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
158 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
159 Cmd = 0x37, /* Command register */
160 IntrMask = 0x3C, /* Interrupt mask */
161 IntrStatus = 0x3E, /* Interrupt status */
162 TxConfig = 0x40, /* Tx configuration */
163 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
164 RxConfig = 0x44, /* Rx configuration */
165 RxMissed = 0x4C, /* 24 bits valid, write clears */
166 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
167 Config1 = 0x52, /* Config1 */
168 Config3 = 0x59, /* Config3 */
169 Config4 = 0x5A, /* Config4 */
170 MultiIntr = 0x5C, /* Multiple interrupt select */
171 BasicModeCtrl = 0x62, /* MII BMCR */
172 BasicModeStatus = 0x64, /* MII BMSR */
173 NWayAdvert = 0x66, /* MII ADVERTISE */
174 NWayLPAR = 0x68, /* MII LPA */
175 NWayExpansion = 0x6A, /* MII Expansion */
176 Config5 = 0xD8, /* Config5 */
177 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
178 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
179 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
180 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
181 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
182 TxThresh = 0xEC, /* Early Tx threshold */
183 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
184 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
185
186 /* Tx and Rx status descriptors */
187 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
188 RingEnd = (1 << 30), /* End of descriptor ring */
189 FirstFrag = (1 << 29), /* First segment of a packet */
190 LastFrag = (1 << 28), /* Final segment of a packet */
fcec3456
JG		 191 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
192 MSSShift = 16, /* MSS value position */
193 MSSMask = 0xfff, /* MSS value: 11 bits */
1da177e4
LT		 194 TxError = (1 << 23), /* Tx error summary */
195 RxError = (1 << 20), /* Rx error summary */
196 IPCS = (1 << 18), /* Calculate IP checksum */
197 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
198 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
199 TxVlanTag = (1 << 17), /* Add VLAN tag */
200 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
201 IPFail = (1 << 15), /* IP checksum failed */
202 UDPFail = (1 << 14), /* UDP/IP checksum failed */
203 TCPFail = (1 << 13), /* TCP/IP checksum failed */
204 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
205 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
206 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
207 RxProtoTCP = 1,
208 RxProtoUDP = 2,
209 RxProtoIP = 3,
210 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
211 TxOWC = (1 << 22), /* Tx Out-of-window collision */
212 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
213 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
214 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
215 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
216 RxErrFrame = (1 << 27), /* Rx frame alignment error */
217 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
218 RxErrCRC = (1 << 18), /* Rx CRC error */
219 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
220 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
221 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
222
223 /* StatsAddr register */
224 DumpStats = (1 << 3), /* Begin stats dump */
225
226 /* RxConfig register */
227 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
228 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
229 AcceptErr = 0x20, /* Accept packets with CRC errors */
230 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
231 AcceptBroadcast = 0x08, /* Accept broadcast packets */
232 AcceptMulticast = 0x04, /* Accept multicast packets */
233 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
234 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
235
236 /* IntrMask / IntrStatus registers */
237 PciErr = (1 << 15), /* System error on the PCI bus */
238 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
239 LenChg = (1 << 13), /* Cable length change */
240 SWInt = (1 << 8), /* Software-requested interrupt */
241 TxEmpty = (1 << 7), /* No Tx descriptors available */
242 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
243 LinkChg = (1 << 5), /* Packet underrun, or link change */
244 RxEmpty = (1 << 4), /* No Rx descriptors available */
245 TxErr = (1 << 3), /* Tx error */
246 TxOK = (1 << 2), /* Tx packet sent */
247 RxErr = (1 << 1), /* Rx error */
248 RxOK = (1 << 0), /* Rx packet received */
249 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
250 but hardware likes to raise it */
251
252 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
253 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
254 RxErr | RxOK | IntrResvd,
255
256 /* C mode command register */
257 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
258 RxOn = (1 << 3), /* Rx mode enable */
259 TxOn = (1 << 2), /* Tx mode enable */
260
261 /* C+ mode command register */
262 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
263 RxChkSum = (1 << 5), /* Rx checksum offload enable */
264 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
265 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
266 CpRxOn = (1 << 1), /* Rx mode enable */
267 CpTxOn = (1 << 0), /* Tx mode enable */
268
269 /* Cfg9436 EEPROM control register */
270 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
271 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
272
273 /* TxConfig register */
274 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
275 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
276
277 /* Early Tx Threshold register */
278 TxThreshMask = 0x3f, /* Mask bits 5-0 */
279 TxThreshMax = 2048, /* Max early Tx threshold */
280
281 /* Config1 register */
282 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
283 LWACT = (1 << 4), /* LWAKE active mode */
284 PMEnable = (1 << 0), /* Enable various PM features of chip */
285
286 /* Config3 register */
287 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
288 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
289 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
290
291 /* Config4 register */
292 LWPTN = (1 << 1), /* LWAKE Pattern */
293 LWPME = (1 << 4), /* LANWAKE vs PMEB */
294
295 /* Config5 register */
296 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
297 MWF = (1 << 5), /* Accept Multicast wakeup frame */
298 UWF = (1 << 4), /* Accept Unicast wakeup frame */
299 LANWake = (1 << 1), /* Enable LANWake signal */
300 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
301
302 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
303 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
304 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
305};
306
307static const unsigned int cp_rx_config =
308 (RX_FIFO_THRESH << RxCfgFIFOShift) |
309 (RX_DMA_BURST << RxCfgDMAShift);
310
311struct cp_desc {
312 u32 opts1;
313 u32 opts2;
314 u64 addr;
315};
316
1da177e4
LT		 317struct cp_dma_stats {
318 u64 tx_ok;
319 u64 rx_ok;
320 u64 tx_err;
321 u32 rx_err;
322 u16 rx_fifo;
323 u16 frame_align;
324 u32 tx_ok_1col;
325 u32 tx_ok_mcol;
326 u64 rx_ok_phys;
327 u64 rx_ok_bcast;
328 u32 rx_ok_mcast;
329 u16 tx_abort;
330 u16 tx_underrun;
331} __attribute__((packed));
332
333struct cp_extra_stats {
334 unsigned long rx_frags;
335};
336
337struct cp_private {
338 void __iomem *regs;
339 struct net_device *dev;
340 spinlock_t lock;
341 u32 msg_enable;
342
343 struct pci_dev *pdev;
344 u32 rx_config;
345 u16 cpcmd;
346
347 struct net_device_stats net_stats;
348 struct cp_extra_stats cp_stats;
1da177e4 349
d03d376d
FR		 350 unsigned rx_head ____cacheline_aligned;
351 unsigned rx_tail;
1da177e4 352 struct cp_desc *rx_ring;
0ba894d4 353 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
1da177e4
LT		 354
355 unsigned tx_head ____cacheline_aligned;
356 unsigned tx_tail;
1da177e4 357 struct cp_desc *tx_ring;
48907e39 358 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
d03d376d
FR		 359
360 unsigned rx_buf_sz;
361 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
1da177e4
LT		 362
363#if CP_VLAN_TAG_USED
364 struct vlan_group *vlgrp;
365#endif
d03d376d 366 dma_addr_t ring_dma;
1da177e4
LT		 367
368 struct mii_if_info mii_if;
369};
370
371#define cpr8(reg) readb(cp->regs + (reg))
372#define cpr16(reg) readw(cp->regs + (reg))
373#define cpr32(reg) readl(cp->regs + (reg))
374#define cpw8(reg,val) writeb((val), cp->regs + (reg))
375#define cpw16(reg,val) writew((val), cp->regs + (reg))
376#define cpw32(reg,val) writel((val), cp->regs + (reg))
377#define cpw8_f(reg,val) do { \
378 writeb((val), cp->regs + (reg)); \
379 readb(cp->regs + (reg)); \
380 } while (0)
381#define cpw16_f(reg,val) do { \
382 writew((val), cp->regs + (reg)); \
383 readw(cp->regs + (reg)); \
384 } while (0)
385#define cpw32_f(reg,val) do { \
386 writel((val), cp->regs + (reg)); \
387 readl(cp->regs + (reg)); \
388 } while (0)
389
390
391static void __cp_set_rx_mode (struct net_device *dev);
392static void cp_tx (struct cp_private *cp);
393static void cp_clean_rings (struct cp_private *cp);
7502cd10
SK		 394#ifdef CONFIG_NET_POLL_CONTROLLER
395static void cp_poll_controller(struct net_device *dev);
396#endif
722fdb33
PC		 397static int cp_get_eeprom_len(struct net_device *dev);
398static int cp_get_eeprom(struct net_device *dev,
399 struct ethtool_eeprom *eeprom, u8 *data);
400static int cp_set_eeprom(struct net_device *dev,
401 struct ethtool_eeprom *eeprom, u8 *data);
1da177e4
LT		 402
403static struct pci_device_id cp_pci_tbl[] = {
cccb20d3
FR		 404 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
405 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
1da177e4
LT		 406 { },
407};
408MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
409
410static struct {
411 const char str[ETH_GSTRING_LEN];
412} ethtool_stats_keys[] = {
413 { "tx_ok" },
414 { "rx_ok" },
415 { "tx_err" },
416 { "rx_err" },
417 { "rx_fifo" },
418 { "frame_align" },
419 { "tx_ok_1col" },
420 { "tx_ok_mcol" },
421 { "rx_ok_phys" },
422 { "rx_ok_bcast" },
423 { "rx_ok_mcast" },
424 { "tx_abort" },
425 { "tx_underrun" },
426 { "rx_frags" },
427};
428
429
430#if CP_VLAN_TAG_USED
431static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
432{
433 struct cp_private *cp = netdev_priv(dev);
434 unsigned long flags;
435
436 spin_lock_irqsave(&cp->lock, flags);
437 cp->vlgrp = grp;
438 cp->cpcmd |= RxVlanOn;
439 cpw16(CpCmd, cp->cpcmd);
440 spin_unlock_irqrestore(&cp->lock, flags);
441}
442
443static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
444{
445 struct cp_private *cp = netdev_priv(dev);
446 unsigned long flags;
447
448 spin_lock_irqsave(&cp->lock, flags);
449 cp->cpcmd &= ~RxVlanOn;
450 cpw16(CpCmd, cp->cpcmd);
451 if (cp->vlgrp)
452 cp->vlgrp->vlan_devices[vid] = NULL;
453 spin_unlock_irqrestore(&cp->lock, flags);
454}
455#endif /* CP_VLAN_TAG_USED */
456
457static inline void cp_set_rxbufsize (struct cp_private *cp)
458{
459 unsigned int mtu = cp->dev->mtu;
f3b197ac 460
1da177e4
LT		 461 if (mtu > ETH_DATA_LEN)
462 /* MTU + ethernet header + FCS + optional VLAN tag */
463 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
464 else
465 cp->rx_buf_sz = PKT_BUF_SZ;
466}
467
468static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
469 struct cp_desc *desc)
470{
471 skb->protocol = eth_type_trans (skb, cp->dev);
472
473 cp->net_stats.rx_packets++;
474 cp->net_stats.rx_bytes += skb->len;
475 cp->dev->last_rx = jiffies;
476
477#if CP_VLAN_TAG_USED
478 if (cp->vlgrp && (desc->opts2 & RxVlanTagged)) {
479 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
480 be16_to_cpu(desc->opts2 & 0xffff));
481 } else
482#endif
483 netif_receive_skb(skb);
484}
485
486static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
487 u32 status, u32 len)
488{
489 if (netif_msg_rx_err (cp))
490 printk (KERN_DEBUG
491 "%s: rx err, slot %d status 0x%x len %d\n",
492 cp->dev->name, rx_tail, status, len);
493 cp->net_stats.rx_errors++;
494 if (status & RxErrFrame)
495 cp->net_stats.rx_frame_errors++;
496 if (status & RxErrCRC)
497 cp->net_stats.rx_crc_errors++;
498 if ((status & RxErrRunt) || (status & RxErrLong))
499 cp->net_stats.rx_length_errors++;
500 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
501 cp->net_stats.rx_length_errors++;
502 if (status & RxErrFIFO)
503 cp->net_stats.rx_fifo_errors++;
504}
505
506static inline unsigned int cp_rx_csum_ok (u32 status)
507{
508 unsigned int protocol = (status >> 16) & 0x3;
f3b197ac 509
1da177e4
LT		 510 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
511 return 1;
512 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
513 return 1;
514 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
515 return 1;
516 return 0;
517}
518
519static int cp_rx_poll (struct net_device *dev, int *budget)
520{
521 struct cp_private *cp = netdev_priv(dev);
522 unsigned rx_tail = cp->rx_tail;
523 unsigned rx_work = dev->quota;
524 unsigned rx;
525
526rx_status_loop:
527 rx = 0;
528 cpw16(IntrStatus, cp_rx_intr_mask);
529
530 while (1) {
531 u32 status, len;
532 dma_addr_t mapping;
533 struct sk_buff *skb, *new_skb;
534 struct cp_desc *desc;
535 unsigned buflen;
536
0ba894d4 537 skb = cp->rx_skb[rx_tail];
5d9428de 538 BUG_ON(!skb);
1da177e4
LT		 539
540 desc = &cp->rx_ring[rx_tail];
541 status = le32_to_cpu(desc->opts1);
542 if (status & DescOwn)
543 break;
544
545 len = (status & 0x1fff) - 4;
3598b57b 546 mapping = le64_to_cpu(desc->addr);
1da177e4
LT		 547
548 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
549 /* we don't support incoming fragmented frames.
550 * instead, we attempt to ensure that the
551 * pre-allocated RX skbs are properly sized such
552 * that RX fragments are never encountered
553 */
554 cp_rx_err_acct(cp, rx_tail, status, len);
555 cp->net_stats.rx_dropped++;
556 cp->cp_stats.rx_frags++;
557 goto rx_next;
558 }
559
560 if (status & (RxError | RxErrFIFO)) {
561 cp_rx_err_acct(cp, rx_tail, status, len);
562 goto rx_next;
563 }
564
565 if (netif_msg_rx_status(cp))
566 printk(KERN_DEBUG "%s: rx slot %d status 0x%x len %d\n",
c48e9399 567 dev->name, rx_tail, status, len);
1da177e4
LT		 568
569 buflen = cp->rx_buf_sz + RX_OFFSET;
570 new_skb = dev_alloc_skb (buflen);
571 if (!new_skb) {
572 cp->net_stats.rx_dropped++;
573 goto rx_next;
574 }
575
576 skb_reserve(new_skb, RX_OFFSET);
c48e9399 577 new_skb->dev = dev;
1da177e4
LT		 578
579 pci_unmap_single(cp->pdev, mapping,
580 buflen, PCI_DMA_FROMDEVICE);
581
582 /* Handle checksum offloading for incoming packets. */
583 if (cp_rx_csum_ok(status))
584 skb->ip_summed = CHECKSUM_UNNECESSARY;
585 else
586 skb->ip_summed = CHECKSUM_NONE;
587
588 skb_put(skb, len);
589
3598b57b
FR		 590 mapping = pci_map_single(cp->pdev, new_skb->data, buflen,
591 PCI_DMA_FROMDEVICE);
0ba894d4 592 cp->rx_skb[rx_tail] = new_skb;
1da177e4
LT		 593
594 cp_rx_skb(cp, skb, desc);
595 rx++;
596
597rx_next:
598 cp->rx_ring[rx_tail].opts2 = 0;
599 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
600 if (rx_tail == (CP_RX_RING_SIZE - 1))
601 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
602 cp->rx_buf_sz);
603 else
604 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
605 rx_tail = NEXT_RX(rx_tail);
606
607 if (!rx_work--)
608 break;
609 }
610
611 cp->rx_tail = rx_tail;
612
613 dev->quota -= rx;
614 *budget -= rx;
615
616 /* if we did not reach work limit, then we're done with
617 * this round of polling
618 */
619 if (rx_work) {
620 if (cpr16(IntrStatus) & cp_rx_intr_mask)
621 goto rx_status_loop;
622
623 local_irq_disable();
624 cpw16_f(IntrMask, cp_intr_mask);
625 __netif_rx_complete(dev);
626 local_irq_enable();
627
628 return 0; /* done */
629 }
630
631 return 1; /* not done */
632}
633
7d12e780 634static irqreturn_t cp_interrupt (int irq, void *dev_instance)
1da177e4
LT		 635{
636 struct net_device *dev = dev_instance;
637 struct cp_private *cp;
638 u16 status;
639
640 if (unlikely(dev == NULL))
641 return IRQ_NONE;
642 cp = netdev_priv(dev);
643
644 status = cpr16(IntrStatus);
645 if (!status || (status == 0xFFFF))
646 return IRQ_NONE;
647
648 if (netif_msg_intr(cp))
649 printk(KERN_DEBUG "%s: intr, status %04x cmd %02x cpcmd %04x\n",
650 dev->name, status, cpr8(Cmd), cpr16(CpCmd));
651
652 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
653
654 spin_lock(&cp->lock);
655
656 /* close possible race's with dev_close */
657 if (unlikely(!netif_running(dev))) {
658 cpw16(IntrMask, 0);
659 spin_unlock(&cp->lock);
660 return IRQ_HANDLED;
661 }
662
663 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
664 if (netif_rx_schedule_prep(dev)) {
665 cpw16_f(IntrMask, cp_norx_intr_mask);
666 __netif_rx_schedule(dev);
667 }
668
669 if (status & (TxOK | TxErr | TxEmpty | SWInt))
670 cp_tx(cp);
671 if (status & LinkChg)
672 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
673
674 spin_unlock(&cp->lock);
675
676 if (status & PciErr) {
677 u16 pci_status;
678
679 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
680 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
681 printk(KERN_ERR "%s: PCI bus error, status=%04x, PCI status=%04x\n",
682 dev->name, status, pci_status);
683
684 /* TODO: reset hardware */
685 }
686
687 return IRQ_HANDLED;
688}
689
7502cd10
SK		 690#ifdef CONFIG_NET_POLL_CONTROLLER
691/*
692 * Polling receive - used by netconsole and other diagnostic tools
693 * to allow network i/o with interrupts disabled.
694 */
695static void cp_poll_controller(struct net_device *dev)
696{
697 disable_irq(dev->irq);
7d12e780 698 cp_interrupt(dev->irq, dev);
7502cd10
SK		 699 enable_irq(dev->irq);
700}
701#endif
702
1da177e4
LT		 703static void cp_tx (struct cp_private *cp)
704{
705 unsigned tx_head = cp->tx_head;
706 unsigned tx_tail = cp->tx_tail;
707
708 while (tx_tail != tx_head) {
3598b57b 709 struct cp_desc *txd = cp->tx_ring + tx_tail;
1da177e4
LT		 710 struct sk_buff *skb;
711 u32 status;
712
713 rmb();
3598b57b 714 status = le32_to_cpu(txd->opts1);
1da177e4
LT		 715 if (status & DescOwn)
716 break;
717
48907e39 718 skb = cp->tx_skb[tx_tail];
5d9428de 719 BUG_ON(!skb);
1da177e4 720
3598b57b 721 pci_unmap_single(cp->pdev, le64_to_cpu(txd->addr),
48907e39
FR		 722 le32_to_cpu(txd->opts1) & 0xffff,
723 PCI_DMA_TODEVICE);
1da177e4
LT		 724
725 if (status & LastFrag) {
726 if (status & (TxError | TxFIFOUnder)) {
727 if (netif_msg_tx_err(cp))
728 printk(KERN_DEBUG "%s: tx err, status 0x%x\n",
729 cp->dev->name, status);
730 cp->net_stats.tx_errors++;
731 if (status & TxOWC)
732 cp->net_stats.tx_window_errors++;
733 if (status & TxMaxCol)
734 cp->net_stats.tx_aborted_errors++;
735 if (status & TxLinkFail)
736 cp->net_stats.tx_carrier_errors++;
737 if (status & TxFIFOUnder)
738 cp->net_stats.tx_fifo_errors++;
739 } else {
740 cp->net_stats.collisions +=
741 ((status >> TxColCntShift) & TxColCntMask);
742 cp->net_stats.tx_packets++;
743 cp->net_stats.tx_bytes += skb->len;
744 if (netif_msg_tx_done(cp))
745 printk(KERN_DEBUG "%s: tx done, slot %d\n", cp->dev->name, tx_tail);
746 }
747 dev_kfree_skb_irq(skb);
748 }
749
48907e39 750 cp->tx_skb[tx_tail] = NULL;
1da177e4
LT		 751
752 tx_tail = NEXT_TX(tx_tail);
753 }
754
755 cp->tx_tail = tx_tail;
756
757 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
758 netif_wake_queue(cp->dev);
759}
760
761static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
762{
763 struct cp_private *cp = netdev_priv(dev);
764 unsigned entry;
fcec3456 765 u32 eor, flags;
1da177e4
LT		 766#if CP_VLAN_TAG_USED
767 u32 vlan_tag = 0;
768#endif
fcec3456 769 int mss = 0;
1da177e4
LT		 770
771 spin_lock_irq(&cp->lock);
772
773 /* This is a hard error, log it. */
774 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
775 netif_stop_queue(dev);
776 spin_unlock_irq(&cp->lock);
777 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
778 dev->name);
779 return 1;
780 }
781
782#if CP_VLAN_TAG_USED
783 if (cp->vlgrp && vlan_tx_tag_present(skb))
784 vlan_tag = TxVlanTag | cpu_to_be16(vlan_tx_tag_get(skb));
785#endif
786
787 entry = cp->tx_head;
788 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
fcec3456 789 if (dev->features & NETIF_F_TSO)
7967168c 790 mss = skb_shinfo(skb)->gso_size;
fcec3456 791
1da177e4
LT		 792 if (skb_shinfo(skb)->nr_frags == 0) {
793 struct cp_desc *txd = &cp->tx_ring[entry];
794 u32 len;
795 dma_addr_t mapping;
796
797 len = skb->len;
798 mapping = pci_map_single(cp->pdev, skb->data, len, PCI_DMA_TODEVICE);
799 CP_VLAN_TX_TAG(txd, vlan_tag);
800 txd->addr = cpu_to_le64(mapping);
801 wmb();
802
fcec3456
JG		 803 flags = eor | len | DescOwn | FirstFrag | LastFrag;
804
805 if (mss)
806 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
84fa7933 807 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 808 const struct iphdr *ip = skb->nh.iph;
809 if (ip->protocol == IPPROTO_TCP)
fcec3456 810 flags |= IPCS | TCPCS;
1da177e4 811 else if (ip->protocol == IPPROTO_UDP)
fcec3456 812 flags |= IPCS | UDPCS;
1da177e4 813 else
5734418d 814 WARN_ON(1); /* we need a WARN() */
fcec3456
JG		 815 }
816
817 txd->opts1 = cpu_to_le32(flags);
1da177e4
LT		 818 wmb();
819
48907e39 820 cp->tx_skb[entry] = skb;
1da177e4
LT		 821 entry = NEXT_TX(entry);
822 } else {
823 struct cp_desc *txd;
824 u32 first_len, first_eor;
825 dma_addr_t first_mapping;
826 int frag, first_entry = entry;
827 const struct iphdr *ip = skb->nh.iph;
828
829 /* We must give this initial chunk to the device last.
830 * Otherwise we could race with the device.
831 */
832 first_eor = eor;
833 first_len = skb_headlen(skb);
834 first_mapping = pci_map_single(cp->pdev, skb->data,
835 first_len, PCI_DMA_TODEVICE);
48907e39 836 cp->tx_skb[entry] = skb;
1da177e4
LT		 837 entry = NEXT_TX(entry);
838
839 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
840 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
841 u32 len;
842 u32 ctrl;
843 dma_addr_t mapping;
844
845 len = this_frag->size;
846 mapping = pci_map_single(cp->pdev,
847 ((void *) page_address(this_frag->page) +
848 this_frag->page_offset),
849 len, PCI_DMA_TODEVICE);
850 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
851
fcec3456
JG		 852 ctrl = eor | len | DescOwn;
853
854 if (mss)
855 ctrl |= LargeSend |
856 ((mss & MSSMask) << MSSShift);
84fa7933 857 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4 858 if (ip->protocol == IPPROTO_TCP)
fcec3456 859 ctrl |= IPCS | TCPCS;
1da177e4 860 else if (ip->protocol == IPPROTO_UDP)
fcec3456 861 ctrl |= IPCS | UDPCS;
1da177e4
LT		 862 else
863 BUG();
fcec3456 864 }
1da177e4
LT		 865
866 if (frag == skb_shinfo(skb)->nr_frags - 1)
867 ctrl |= LastFrag;
868
869 txd = &cp->tx_ring[entry];
870 CP_VLAN_TX_TAG(txd, vlan_tag);
871 txd->addr = cpu_to_le64(mapping);
872 wmb();
873
874 txd->opts1 = cpu_to_le32(ctrl);
875 wmb();
876
48907e39 877 cp->tx_skb[entry] = skb;
1da177e4
LT		 878 entry = NEXT_TX(entry);
879 }
880
881 txd = &cp->tx_ring[first_entry];
882 CP_VLAN_TX_TAG(txd, vlan_tag);
883 txd->addr = cpu_to_le64(first_mapping);
884 wmb();
885
84fa7933 886 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 887 if (ip->protocol == IPPROTO_TCP)
888 txd->opts1 = cpu_to_le32(first_eor | first_len |
889 FirstFrag | DescOwn |
890 IPCS | TCPCS);
891 else if (ip->protocol == IPPROTO_UDP)
892 txd->opts1 = cpu_to_le32(first_eor | first_len |
893 FirstFrag | DescOwn |
894 IPCS | UDPCS);
895 else
896 BUG();
897 } else
898 txd->opts1 = cpu_to_le32(first_eor | first_len |
899 FirstFrag | DescOwn);
900 wmb();
901 }
902 cp->tx_head = entry;
903 if (netif_msg_tx_queued(cp))
904 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
905 dev->name, entry, skb->len);
906 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
907 netif_stop_queue(dev);
908
909 spin_unlock_irq(&cp->lock);
910
911 cpw8(TxPoll, NormalTxPoll);
912 dev->trans_start = jiffies;
913
914 return 0;
915}
916
917/* Set or clear the multicast filter for this adaptor.
918 This routine is not state sensitive and need not be SMP locked. */
919
920static void __cp_set_rx_mode (struct net_device *dev)
921{
922 struct cp_private *cp = netdev_priv(dev);
923 u32 mc_filter[2]; /* Multicast hash filter */
924 int i, rx_mode;
925 u32 tmp;
926
927 /* Note: do not reorder, GCC is clever about common statements. */
928 if (dev->flags & IFF_PROMISC) {
929 /* Unconditionally log net taps. */
1da177e4
LT		 930 rx_mode =
931 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
932 AcceptAllPhys;
933 mc_filter[1] = mc_filter[0] = 0xffffffff;
934 } else if ((dev->mc_count > multicast_filter_limit)
935 || (dev->flags & IFF_ALLMULTI)) {
936 /* Too many to filter perfectly -- accept all multicasts. */
937 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
938 mc_filter[1] = mc_filter[0] = 0xffffffff;
939 } else {
940 struct dev_mc_list *mclist;
941 rx_mode = AcceptBroadcast | AcceptMyPhys;
942 mc_filter[1] = mc_filter[0] = 0;
943 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
944 i++, mclist = mclist->next) {
945 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
946
947 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
948 rx_mode |= AcceptMulticast;
949 }
950 }
951
952 /* We can safely update without stopping the chip. */
953 tmp = cp_rx_config | rx_mode;
954 if (cp->rx_config != tmp) {
955 cpw32_f (RxConfig, tmp);
956 cp->rx_config = tmp;
957 }
958 cpw32_f (MAR0 + 0, mc_filter[0]);
959 cpw32_f (MAR0 + 4, mc_filter[1]);
960}
961
962static void cp_set_rx_mode (struct net_device *dev)
963{
964 unsigned long flags;
965 struct cp_private *cp = netdev_priv(dev);
966
967 spin_lock_irqsave (&cp->lock, flags);
968 __cp_set_rx_mode(dev);
969 spin_unlock_irqrestore (&cp->lock, flags);
970}
971
972static void __cp_get_stats(struct cp_private *cp)
973{
974 /* only lower 24 bits valid; write any value to clear */
975 cp->net_stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
976 cpw32 (RxMissed, 0);
977}
978
979static struct net_device_stats *cp_get_stats(struct net_device *dev)
980{
981 struct cp_private *cp = netdev_priv(dev);
982 unsigned long flags;
983
984 /* The chip only need report frame silently dropped. */
985 spin_lock_irqsave(&cp->lock, flags);
986 if (netif_running(dev) && netif_device_present(dev))
987 __cp_get_stats(cp);
988 spin_unlock_irqrestore(&cp->lock, flags);
989
990 return &cp->net_stats;
991}
992
993static void cp_stop_hw (struct cp_private *cp)
994{
995 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
996 cpw16_f(IntrMask, 0);
997 cpw8(Cmd, 0);
998 cpw16_f(CpCmd, 0);
999 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
1000
1001 cp->rx_tail = 0;
1002 cp->tx_head = cp->tx_tail = 0;
1003}
1004
1005static void cp_reset_hw (struct cp_private *cp)
1006{
1007 unsigned work = 1000;
1008
1009 cpw8(Cmd, CmdReset);
1010
1011 while (work--) {
1012 if (!(cpr8(Cmd) & CmdReset))
1013 return;
1014
3173c890 1015 schedule_timeout_uninterruptible(10);
1da177e4
LT		 1016 }
1017
1018 printk(KERN_ERR "%s: hardware reset timeout\n", cp->dev->name);
1019}
1020
1021static inline void cp_start_hw (struct cp_private *cp)
1022{
1023 cpw16(CpCmd, cp->cpcmd);
1024 cpw8(Cmd, RxOn | TxOn);
1025}
1026
1027static void cp_init_hw (struct cp_private *cp)
1028{
1029 struct net_device *dev = cp->dev;
1030 dma_addr_t ring_dma;
1031
1032 cp_reset_hw(cp);
1033
1034 cpw8_f (Cfg9346, Cfg9346_Unlock);
1035
1036 /* Restore our idea of the MAC address. */
1037 cpw32_f (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1038 cpw32_f (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1039
1040 cp_start_hw(cp);
1041 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1042
1043 __cp_set_rx_mode(dev);
1044 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1045
1046 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1047 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1048 cpw8(Config3, PARMEnable);
1049 cp->wol_enabled = 0;
1050
f3b197ac 1051 cpw8(Config5, cpr8(Config5) & PMEStatus);
1da177e4
LT		 1052
1053 cpw32_f(HiTxRingAddr, 0);
1054 cpw32_f(HiTxRingAddr + 4, 0);
1055
1056 ring_dma = cp->ring_dma;
1057 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1058 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1059
1060 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1061 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1062 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1063
1064 cpw16(MultiIntr, 0);
1065
1066 cpw16_f(IntrMask, cp_intr_mask);
1067
1068 cpw8_f(Cfg9346, Cfg9346_Lock);
1069}
1070
1071static int cp_refill_rx (struct cp_private *cp)
1072{
1073 unsigned i;
1074
1075 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1076 struct sk_buff *skb;
3598b57b 1077 dma_addr_t mapping;
1da177e4
LT		 1078
1079 skb = dev_alloc_skb(cp->rx_buf_sz + RX_OFFSET);
1080 if (!skb)
1081 goto err_out;
1082
1083 skb->dev = cp->dev;
1084 skb_reserve(skb, RX_OFFSET);
1085
3598b57b
FR		 1086 mapping = pci_map_single(cp->pdev, skb->data, cp->rx_buf_sz,
1087 PCI_DMA_FROMDEVICE);
0ba894d4 1088 cp->rx_skb[i] = skb;
1da177e4
LT		 1089
1090 cp->rx_ring[i].opts2 = 0;
3598b57b 1091 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1da177e4
LT		 1092 if (i == (CP_RX_RING_SIZE - 1))
1093 cp->rx_ring[i].opts1 =
1094 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1095 else
1096 cp->rx_ring[i].opts1 =
1097 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1098 }
1099
1100 return 0;
1101
1102err_out:
1103 cp_clean_rings(cp);
1104 return -ENOMEM;
1105}
1106
576cfa93
FR		 1107static void cp_init_rings_index (struct cp_private *cp)
1108{
1109 cp->rx_tail = 0;
1110 cp->tx_head = cp->tx_tail = 0;
1111}
1112
1da177e4
LT		 1113static int cp_init_rings (struct cp_private *cp)
1114{
1115 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1116 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1117
576cfa93 1118 cp_init_rings_index(cp);
1da177e4
LT		 1119
1120 return cp_refill_rx (cp);
1121}
1122
1123static int cp_alloc_rings (struct cp_private *cp)
1124{
1125 void *mem;
1126
1127 mem = pci_alloc_consistent(cp->pdev, CP_RING_BYTES, &cp->ring_dma);
1128 if (!mem)
1129 return -ENOMEM;
1130
1131 cp->rx_ring = mem;
1132 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1133
1da177e4
LT		 1134 return cp_init_rings(cp);
1135}
1136
1137static void cp_clean_rings (struct cp_private *cp)
1138{
3598b57b 1139 struct cp_desc *desc;
1da177e4
LT		 1140 unsigned i;
1141
1da177e4 1142 for (i = 0; i < CP_RX_RING_SIZE; i++) {
0ba894d4 1143 if (cp->rx_skb[i]) {
3598b57b
FR		 1144 desc = cp->rx_ring + i;
1145 pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr),
1da177e4 1146 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
0ba894d4 1147 dev_kfree_skb(cp->rx_skb[i]);
1da177e4
LT		 1148 }
1149 }
1150
1151 for (i = 0; i < CP_TX_RING_SIZE; i++) {
48907e39
FR		 1152 if (cp->tx_skb[i]) {
1153 struct sk_buff *skb = cp->tx_skb[i];
5734418d 1154
3598b57b
FR		 1155 desc = cp->tx_ring + i;
1156 pci_unmap_single(cp->pdev, le64_to_cpu(desc->addr),
48907e39
FR		 1157 le32_to_cpu(desc->opts1) & 0xffff,
1158 PCI_DMA_TODEVICE);
3598b57b 1159 if (le32_to_cpu(desc->opts1) & LastFrag)
5734418d 1160 dev_kfree_skb(skb);
1da177e4
LT		 1161 cp->net_stats.tx_dropped++;
1162 }
1163 }
1164
5734418d
FR		 1165 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1166 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1167
0ba894d4 1168 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
48907e39 1169 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1da177e4
LT		 1170}
1171
1172static void cp_free_rings (struct cp_private *cp)
1173{
1174 cp_clean_rings(cp);
1175 pci_free_consistent(cp->pdev, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1176 cp->rx_ring = NULL;
1177 cp->tx_ring = NULL;
1da177e4
LT		 1178}
1179
1180static int cp_open (struct net_device *dev)
1181{
1182 struct cp_private *cp = netdev_priv(dev);
1183 int rc;
1184
1185 if (netif_msg_ifup(cp))
1186 printk(KERN_DEBUG "%s: enabling interface\n", dev->name);
1187
1188 rc = cp_alloc_rings(cp);
1189 if (rc)
1190 return rc;
1191
1192 cp_init_hw(cp);
1193
1fb9df5d 1194 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 1195 if (rc)
1196 goto err_out_hw;
1197
1198 netif_carrier_off(dev);
1199 mii_check_media(&cp->mii_if, netif_msg_link(cp), TRUE);
1200 netif_start_queue(dev);
1201
1202 return 0;
1203
1204err_out_hw:
1205 cp_stop_hw(cp);
1206 cp_free_rings(cp);
1207 return rc;
1208}
1209
1210static int cp_close (struct net_device *dev)
1211{
1212 struct cp_private *cp = netdev_priv(dev);
1213 unsigned long flags;
1214
1215 if (netif_msg_ifdown(cp))
1216 printk(KERN_DEBUG "%s: disabling interface\n", dev->name);
1217
1218 spin_lock_irqsave(&cp->lock, flags);
1219
1220 netif_stop_queue(dev);
1221 netif_carrier_off(dev);
1222
1223 cp_stop_hw(cp);
1224
1225 spin_unlock_irqrestore(&cp->lock, flags);
1226
1227 synchronize_irq(dev->irq);
1228 free_irq(dev->irq, dev);
1229
1230 cp_free_rings(cp);
1231 return 0;
1232}
1233
1234#ifdef BROKEN
1235static int cp_change_mtu(struct net_device *dev, int new_mtu)
1236{
1237 struct cp_private *cp = netdev_priv(dev);
1238 int rc;
1239 unsigned long flags;
1240
1241 /* check for invalid MTU, according to hardware limits */
1242 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1243 return -EINVAL;
1244
1245 /* if network interface not up, no need for complexity */
1246 if (!netif_running(dev)) {
1247 dev->mtu = new_mtu;
1248 cp_set_rxbufsize(cp); /* set new rx buf size */
1249 return 0;
1250 }
1251
1252 spin_lock_irqsave(&cp->lock, flags);
1253
1254 cp_stop_hw(cp); /* stop h/w and free rings */
1255 cp_clean_rings(cp);
1256
1257 dev->mtu = new_mtu;
1258 cp_set_rxbufsize(cp); /* set new rx buf size */
1259
1260 rc = cp_init_rings(cp); /* realloc and restart h/w */
1261 cp_start_hw(cp);
1262
1263 spin_unlock_irqrestore(&cp->lock, flags);
1264
1265 return rc;
1266}
1267#endif /* BROKEN */
1268
f71e1309 1269static const char mii_2_8139_map[8] = {
1da177e4
LT		 1270 BasicModeCtrl,
1271 BasicModeStatus,
1272 0,
1273 0,
1274 NWayAdvert,
1275 NWayLPAR,
1276 NWayExpansion,
1277 0
1278};
1279
1280static int mdio_read(struct net_device *dev, int phy_id, int location)
1281{
1282 struct cp_private *cp = netdev_priv(dev);
1283
1284 return location < 8 && mii_2_8139_map[location] ?
1285 readw(cp->regs + mii_2_8139_map[location]) : 0;
1286}
1287
1288
1289static void mdio_write(struct net_device *dev, int phy_id, int location,
1290 int value)
1291{
1292 struct cp_private *cp = netdev_priv(dev);
1293
1294 if (location == 0) {
1295 cpw8(Cfg9346, Cfg9346_Unlock);
1296 cpw16(BasicModeCtrl, value);
1297 cpw8(Cfg9346, Cfg9346_Lock);
1298 } else if (location < 8 && mii_2_8139_map[location])
1299 cpw16(mii_2_8139_map[location], value);
1300}
1301
1302/* Set the ethtool Wake-on-LAN settings */
1303static int netdev_set_wol (struct cp_private *cp,
1304 const struct ethtool_wolinfo *wol)
1305{
1306 u8 options;
1307
1308 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1309 /* If WOL is being disabled, no need for complexity */
1310 if (wol->wolopts) {
1311 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1312 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1313 }
1314
1315 cpw8 (Cfg9346, Cfg9346_Unlock);
1316 cpw8 (Config3, options);
1317 cpw8 (Cfg9346, Cfg9346_Lock);
1318
1319 options = 0; /* Paranoia setting */
1320 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1321 /* If WOL is being disabled, no need for complexity */
1322 if (wol->wolopts) {
1323 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1324 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1325 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1326 }
1327
1328 cpw8 (Config5, options);
1329
1330 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1331
1332 return 0;
1333}
1334
1335/* Get the ethtool Wake-on-LAN settings */
1336static void netdev_get_wol (struct cp_private *cp,
1337 struct ethtool_wolinfo *wol)
1338{
1339 u8 options;
1340
1341 wol->wolopts = 0; /* Start from scratch */
1342 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1343 WAKE_MCAST | WAKE_UCAST;
1344 /* We don't need to go on if WOL is disabled */
1345 if (!cp->wol_enabled) return;
f3b197ac 1346
1da177e4
LT		 1347 options = cpr8 (Config3);
1348 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1349 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1350
1351 options = 0; /* Paranoia setting */
1352 options = cpr8 (Config5);
1353 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1354 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1355 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1356}
1357
1358static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1359{
1360 struct cp_private *cp = netdev_priv(dev);
1361
1362 strcpy (info->driver, DRV_NAME);
1363 strcpy (info->version, DRV_VERSION);
1364 strcpy (info->bus_info, pci_name(cp->pdev));
1365}
1366
1367static int cp_get_regs_len(struct net_device *dev)
1368{
1369 return CP_REGS_SIZE;
1370}
1371
1372static int cp_get_stats_count (struct net_device *dev)
1373{
1374 return CP_NUM_STATS;
1375}
1376
1377static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1378{
1379 struct cp_private *cp = netdev_priv(dev);
1380 int rc;
1381 unsigned long flags;
1382
1383 spin_lock_irqsave(&cp->lock, flags);
1384 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1385 spin_unlock_irqrestore(&cp->lock, flags);
1386
1387 return rc;
1388}
1389
1390static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1391{
1392 struct cp_private *cp = netdev_priv(dev);
1393 int rc;
1394 unsigned long flags;
1395
1396 spin_lock_irqsave(&cp->lock, flags);
1397 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1398 spin_unlock_irqrestore(&cp->lock, flags);
1399
1400 return rc;
1401}
1402
1403static int cp_nway_reset(struct net_device *dev)
1404{
1405 struct cp_private *cp = netdev_priv(dev);
1406 return mii_nway_restart(&cp->mii_if);
1407}
1408
1409static u32 cp_get_msglevel(struct net_device *dev)
1410{
1411 struct cp_private *cp = netdev_priv(dev);
1412 return cp->msg_enable;
1413}
1414
1415static void cp_set_msglevel(struct net_device *dev, u32 value)
1416{
1417 struct cp_private *cp = netdev_priv(dev);
1418 cp->msg_enable = value;
1419}
1420
1421static u32 cp_get_rx_csum(struct net_device *dev)
1422{
1423 struct cp_private *cp = netdev_priv(dev);
1424 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1425}
1426
1427static int cp_set_rx_csum(struct net_device *dev, u32 data)
1428{
1429 struct cp_private *cp = netdev_priv(dev);
1430 u16 cmd = cp->cpcmd, newcmd;
1431
1432 newcmd = cmd;
1433
1434 if (data)
1435 newcmd |= RxChkSum;
1436 else
1437 newcmd &= ~RxChkSum;
1438
1439 if (newcmd != cmd) {
1440 unsigned long flags;
1441
1442 spin_lock_irqsave(&cp->lock, flags);
1443 cp->cpcmd = newcmd;
1444 cpw16_f(CpCmd, newcmd);
1445 spin_unlock_irqrestore(&cp->lock, flags);
1446 }
1447
1448 return 0;
1449}
1450
1451static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1452 void *p)
1453{
1454 struct cp_private *cp = netdev_priv(dev);
1455 unsigned long flags;
1456
1457 if (regs->len < CP_REGS_SIZE)
1458 return /* -EINVAL */;
1459
1460 regs->version = CP_REGS_VER;
1461
1462 spin_lock_irqsave(&cp->lock, flags);
1463 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1464 spin_unlock_irqrestore(&cp->lock, flags);
1465}
1466
1467static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1468{
1469 struct cp_private *cp = netdev_priv(dev);
1470 unsigned long flags;
1471
1472 spin_lock_irqsave (&cp->lock, flags);
1473 netdev_get_wol (cp, wol);
1474 spin_unlock_irqrestore (&cp->lock, flags);
1475}
1476
1477static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1478{
1479 struct cp_private *cp = netdev_priv(dev);
1480 unsigned long flags;
1481 int rc;
1482
1483 spin_lock_irqsave (&cp->lock, flags);
1484 rc = netdev_set_wol (cp, wol);
1485 spin_unlock_irqrestore (&cp->lock, flags);
1486
1487 return rc;
1488}
1489
1490static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1491{
1492 switch (stringset) {
1493 case ETH_SS_STATS:
1494 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1495 break;
1496 default:
1497 BUG();
1498 break;
1499 }
1500}
1501
1502static void cp_get_ethtool_stats (struct net_device *dev,
1503 struct ethtool_stats *estats, u64 *tmp_stats)
1504{
1505 struct cp_private *cp = netdev_priv(dev);
8b512927
SH		 1506 struct cp_dma_stats *nic_stats;
1507 dma_addr_t dma;
1da177e4
LT		 1508 int i;
1509
8b512927
SH		 1510 nic_stats = pci_alloc_consistent(cp->pdev, sizeof(*nic_stats), &dma);
1511 if (!nic_stats)
1512 return;
97f568d8 1513
1da177e4 1514 /* begin NIC statistics dump */
8b512927
SH		 1515 cpw32(StatsAddr + 4, (u64)dma >> 32);
1516 cpw32(StatsAddr, ((u64)dma & DMA_32BIT_MASK) | DumpStats);
1da177e4
LT		 1517 cpr32(StatsAddr);
1518
97f568d8 1519 for (i = 0; i < 1000; i++) {
1da177e4
LT		 1520 if ((cpr32(StatsAddr) & DumpStats) == 0)
1521 break;
97f568d8 1522 udelay(10);
1da177e4 1523 }
97f568d8
SH		 1524 cpw32(StatsAddr, 0);
1525 cpw32(StatsAddr + 4, 0);
8b512927 1526 cpr32(StatsAddr);
1da177e4
LT		 1527
1528 i = 0;
8b512927
SH		 1529 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1530 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1531 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1532 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1533 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1534 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1535 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1536 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1537 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1538 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1539 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1540 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1541 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1da177e4 1542 tmp_stats[i++] = cp->cp_stats.rx_frags;
5d9428de 1543 BUG_ON(i != CP_NUM_STATS);
8b512927
SH		 1544
1545 pci_free_consistent(cp->pdev, sizeof(*nic_stats), nic_stats, dma);
1da177e4
LT		 1546}
1547
7282d491 1548static const struct ethtool_ops cp_ethtool_ops = {
1da177e4
LT		 1549 .get_drvinfo = cp_get_drvinfo,
1550 .get_regs_len = cp_get_regs_len,
1551 .get_stats_count = cp_get_stats_count,
1552 .get_settings = cp_get_settings,
1553 .set_settings = cp_set_settings,
1554 .nway_reset = cp_nway_reset,
1555 .get_link = ethtool_op_get_link,
1556 .get_msglevel = cp_get_msglevel,
1557 .set_msglevel = cp_set_msglevel,
1558 .get_rx_csum = cp_get_rx_csum,
1559 .set_rx_csum = cp_set_rx_csum,
1560 .get_tx_csum = ethtool_op_get_tx_csum,
1561 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1562 .get_sg = ethtool_op_get_sg,
1563 .set_sg = ethtool_op_set_sg,
fcec3456
JG		 1564 .get_tso = ethtool_op_get_tso,
1565 .set_tso = ethtool_op_set_tso,
1da177e4
LT		 1566 .get_regs = cp_get_regs,
1567 .get_wol = cp_get_wol,
1568 .set_wol = cp_set_wol,
1569 .get_strings = cp_get_strings,
1570 .get_ethtool_stats = cp_get_ethtool_stats,
bb0ce608 1571 .get_perm_addr = ethtool_op_get_perm_addr,
722fdb33
PC		 1572 .get_eeprom_len = cp_get_eeprom_len,
1573 .get_eeprom = cp_get_eeprom,
1574 .set_eeprom = cp_set_eeprom,
1da177e4
LT		 1575};
1576
1577static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1578{
1579 struct cp_private *cp = netdev_priv(dev);
1580 int rc;
1581 unsigned long flags;
1582
1583 if (!netif_running(dev))
1584 return -EINVAL;
1585
1586 spin_lock_irqsave(&cp->lock, flags);
1587 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1588 spin_unlock_irqrestore(&cp->lock, flags);
1589 return rc;
1590}
1591
1592/* Serial EEPROM section. */
1593
1594/* EEPROM_Ctrl bits. */
1595#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1596#define EE_CS 0x08 /* EEPROM chip select. */
1597#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1598#define EE_WRITE_0 0x00
1599#define EE_WRITE_1 0x02
1600#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1601#define EE_ENB (0x80 | EE_CS)
1602
1603/* Delay between EEPROM clock transitions.
1604 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1605 */
1606
1607#define eeprom_delay() readl(ee_addr)
1608
1609/* The EEPROM commands include the alway-set leading bit. */
722fdb33 1610#define EE_EXTEND_CMD (4)
1da177e4
LT		 1611#define EE_WRITE_CMD (5)
1612#define EE_READ_CMD (6)
1613#define EE_ERASE_CMD (7)
1614
722fdb33
PC		 1615#define EE_EWDS_ADDR (0)
1616#define EE_WRAL_ADDR (1)
1617#define EE_ERAL_ADDR (2)
1618#define EE_EWEN_ADDR (3)
1619
1620#define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1da177e4 1621
722fdb33
PC		 1622static void eeprom_cmd_start(void __iomem *ee_addr)
1623{
1da177e4
LT		 1624 writeb (EE_ENB & ~EE_CS, ee_addr);
1625 writeb (EE_ENB, ee_addr);
1626 eeprom_delay ();
722fdb33 1627}
1da177e4 1628
722fdb33
PC		 1629static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1630{
1631 int i;
1632
1633 /* Shift the command bits out. */
1634 for (i = cmd_len - 1; i >= 0; i--) {
1635 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1da177e4
LT		 1636 writeb (EE_ENB | dataval, ee_addr);
1637 eeprom_delay ();
1638 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1639 eeprom_delay ();
1640 }
1641 writeb (EE_ENB, ee_addr);
1642 eeprom_delay ();
722fdb33
PC		 1643}
1644
1645static void eeprom_cmd_end(void __iomem *ee_addr)
1646{
1647 writeb (~EE_CS, ee_addr);
1648 eeprom_delay ();
1649}
1650
1651static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1652 int addr_len)
1653{
1654 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1655
1656 eeprom_cmd_start(ee_addr);
1657 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1658 eeprom_cmd_end(ee_addr);
1659}
1660
1661static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1662{
1663 int i;
1664 u16 retval = 0;
1665 void __iomem *ee_addr = ioaddr + Cfg9346;
1666 int read_cmd = location | (EE_READ_CMD << addr_len);
1667
1668 eeprom_cmd_start(ee_addr);
1669 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1da177e4
LT		 1670
1671 for (i = 16; i > 0; i--) {
1672 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1673 eeprom_delay ();
1674 retval =
1675 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1676 0);
1677 writeb (EE_ENB, ee_addr);
1678 eeprom_delay ();
1679 }
1680
722fdb33 1681 eeprom_cmd_end(ee_addr);
1da177e4
LT		 1682
1683 return retval;
1684}
1685
722fdb33
PC		 1686static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1687 int addr_len)
1688{
1689 int i;
1690 void __iomem *ee_addr = ioaddr + Cfg9346;
1691 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1692
1693 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1694
1695 eeprom_cmd_start(ee_addr);
1696 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1697 eeprom_cmd(ee_addr, val, 16);
1698 eeprom_cmd_end(ee_addr);
1699
1700 eeprom_cmd_start(ee_addr);
1701 for (i = 0; i < 20000; i++)
1702 if (readb(ee_addr) & EE_DATA_READ)
1703 break;
1704 eeprom_cmd_end(ee_addr);
1705
1706 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1707}
1708
1709static int cp_get_eeprom_len(struct net_device *dev)
1710{
1711 struct cp_private *cp = netdev_priv(dev);
1712 int size;
1713
1714 spin_lock_irq(&cp->lock);
1715 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1716 spin_unlock_irq(&cp->lock);
1717
1718 return size;
1719}
1720
1721static int cp_get_eeprom(struct net_device *dev,
1722 struct ethtool_eeprom *eeprom, u8 *data)
1723{
1724 struct cp_private *cp = netdev_priv(dev);
1725 unsigned int addr_len;
1726 u16 val;
1727 u32 offset = eeprom->offset >> 1;
1728 u32 len = eeprom->len;
1729 u32 i = 0;
1730
1731 eeprom->magic = CP_EEPROM_MAGIC;
1732
1733 spin_lock_irq(&cp->lock);
1734
1735 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1736
1737 if (eeprom->offset & 1) {
1738 val = read_eeprom(cp->regs, offset, addr_len);
1739 data[i++] = (u8)(val >> 8);
1740 offset++;
1741 }
1742
1743 while (i < len - 1) {
1744 val = read_eeprom(cp->regs, offset, addr_len);
1745 data[i++] = (u8)val;
1746 data[i++] = (u8)(val >> 8);
1747 offset++;
1748 }
1749
1750 if (i < len) {
1751 val = read_eeprom(cp->regs, offset, addr_len);
1752 data[i] = (u8)val;
1753 }
1754
1755 spin_unlock_irq(&cp->lock);
1756 return 0;
1757}
1758
1759static int cp_set_eeprom(struct net_device *dev,
1760 struct ethtool_eeprom *eeprom, u8 *data)
1761{
1762 struct cp_private *cp = netdev_priv(dev);
1763 unsigned int addr_len;
1764 u16 val;
1765 u32 offset = eeprom->offset >> 1;
1766 u32 len = eeprom->len;
1767 u32 i = 0;
1768
1769 if (eeprom->magic != CP_EEPROM_MAGIC)
1770 return -EINVAL;
1771
1772 spin_lock_irq(&cp->lock);
1773
1774 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1775
1776 if (eeprom->offset & 1) {
1777 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1778 val |= (u16)data[i++] << 8;
1779 write_eeprom(cp->regs, offset, val, addr_len);
1780 offset++;
1781 }
1782
1783 while (i < len - 1) {
1784 val = (u16)data[i++];
1785 val |= (u16)data[i++] << 8;
1786 write_eeprom(cp->regs, offset, val, addr_len);
1787 offset++;
1788 }
1789
1790 if (i < len) {
1791 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1792 val |= (u16)data[i];
1793 write_eeprom(cp->regs, offset, val, addr_len);
1794 }
1795
1796 spin_unlock_irq(&cp->lock);
1797 return 0;
1798}
1799
1da177e4
LT		 1800/* Put the board into D3cold state and wait for WakeUp signal */
1801static void cp_set_d3_state (struct cp_private *cp)
1802{
1803 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1804 pci_set_power_state (cp->pdev, PCI_D3hot);
1805}
1806
1807static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1808{
1809 struct net_device *dev;
1810 struct cp_private *cp;
1811 int rc;
1812 void __iomem *regs;
2427ddd8 1813 resource_size_t pciaddr;
1da177e4
LT		 1814 unsigned int addr_len, i, pci_using_dac;
1815 u8 pci_rev;
1816
1817#ifndef MODULE
1818 static int version_printed;
1819 if (version_printed++ == 0)
1820 printk("%s", version);
1821#endif
1822
1823 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
1824
1825 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1826 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev < 0x20) {
9b91cf9d 1827 dev_err(&pdev->dev,
2e8a538d
JG		 1828 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip\n",
1829 pdev->vendor, pdev->device, pci_rev);
9b91cf9d 1830 dev_err(&pdev->dev, "Try the \"8139too\" driver instead.\n");
1da177e4
LT		 1831 return -ENODEV;
1832 }
1833
1834 dev = alloc_etherdev(sizeof(struct cp_private));
1835 if (!dev)
1836 return -ENOMEM;
1837 SET_MODULE_OWNER(dev);
1838 SET_NETDEV_DEV(dev, &pdev->dev);
1839
1840 cp = netdev_priv(dev);
1841 cp->pdev = pdev;
1842 cp->dev = dev;
1843 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1844 spin_lock_init (&cp->lock);
1845 cp->mii_if.dev = dev;
1846 cp->mii_if.mdio_read = mdio_read;
1847 cp->mii_if.mdio_write = mdio_write;
1848 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1849 cp->mii_if.phy_id_mask = 0x1f;
1850 cp->mii_if.reg_num_mask = 0x1f;
1851 cp_set_rxbufsize(cp);
1852
1853 rc = pci_enable_device(pdev);
1854 if (rc)
1855 goto err_out_free;
1856
1857 rc = pci_set_mwi(pdev);
1858 if (rc)
1859 goto err_out_disable;
1860
1861 rc = pci_request_regions(pdev, DRV_NAME);
1862 if (rc)
1863 goto err_out_mwi;
1864
1865 pciaddr = pci_resource_start(pdev, 1);
1866 if (!pciaddr) {
1867 rc = -EIO;
9b91cf9d 1868 dev_err(&pdev->dev, "no MMIO resource\n");
1da177e4
LT		 1869 goto err_out_res;
1870 }
1871 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1872 rc = -EIO;
9b91cf9d 1873 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
2e8a538d 1874 (unsigned long long)pci_resource_len(pdev, 1));
1da177e4
LT		 1875 goto err_out_res;
1876 }
1877
1878 /* Configure DMA attributes. */
1879 if ((sizeof(dma_addr_t) > 4) &&
8662d061
TK		 1880 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) &&
1881 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 1882 pci_using_dac = 1;
1883 } else {
1884 pci_using_dac = 0;
1885
8662d061 1886 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4 1887 if (rc) {
9b91cf9d 1888 dev_err(&pdev->dev,
2e8a538d 1889 "No usable DMA configuration, aborting.\n");
1da177e4
LT		 1890 goto err_out_res;
1891 }
8662d061 1892 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1da177e4 1893 if (rc) {
9b91cf9d 1894 dev_err(&pdev->dev,
2e8a538d
JG		 1895 "No usable consistent DMA configuration, "
1896 "aborting.\n");
1da177e4
LT		 1897 goto err_out_res;
1898 }
1899 }
1900
1901 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1902 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1903
1904 regs = ioremap(pciaddr, CP_REGS_SIZE);
1905 if (!regs) {
1906 rc = -EIO;
4626dd46 1907 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
2e8a538d
JG		 1908 (unsigned long long)pci_resource_len(pdev, 1),
1909 (unsigned long long)pciaddr);
1da177e4
LT		 1910 goto err_out_res;
1911 }
1912 dev->base_addr = (unsigned long) regs;
1913 cp->regs = regs;
1914
1915 cp_stop_hw(cp);
1916
1917 /* read MAC address from EEPROM */
1918 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1919 for (i = 0; i < 3; i++)
1920 ((u16 *) (dev->dev_addr))[i] =
1921 le16_to_cpu (read_eeprom (regs, i + 7, addr_len));
bb0ce608 1922 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1923
1924 dev->open = cp_open;
1925 dev->stop = cp_close;
1926 dev->set_multicast_list = cp_set_rx_mode;
1927 dev->hard_start_xmit = cp_start_xmit;
1928 dev->get_stats = cp_get_stats;
1929 dev->do_ioctl = cp_ioctl;
1930 dev->poll = cp_rx_poll;
7502cd10
SK		 1931#ifdef CONFIG_NET_POLL_CONTROLLER
1932 dev->poll_controller = cp_poll_controller;
1933#endif
1da177e4
LT		 1934 dev->weight = 16; /* arbitrary? from NAPI_HOWTO.txt. */
1935#ifdef BROKEN
1936 dev->change_mtu = cp_change_mtu;
1937#endif
1938 dev->ethtool_ops = &cp_ethtool_ops;
1939#if 0
1940 dev->tx_timeout = cp_tx_timeout;
1941 dev->watchdog_timeo = TX_TIMEOUT;
1942#endif
1943
1944#if CP_VLAN_TAG_USED
1945 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1946 dev->vlan_rx_register = cp_vlan_rx_register;
1947 dev->vlan_rx_kill_vid = cp_vlan_rx_kill_vid;
1948#endif
1949
1950 if (pci_using_dac)
1951 dev->features |= NETIF_F_HIGHDMA;
1952
fcec3456
JG		 1953#if 0 /* disabled by default until verified */
1954 dev->features |= NETIF_F_TSO;
1955#endif
1956
1da177e4
LT		 1957 dev->irq = pdev->irq;
1958
1959 rc = register_netdev(dev);
1960 if (rc)
1961 goto err_out_iomap;
1962
1963 printk (KERN_INFO "%s: RTL-8139C+ at 0x%lx, "
1964 "%02x:%02x:%02x:%02x:%02x:%02x, "
1965 "IRQ %d\n",
1966 dev->name,
1967 dev->base_addr,
1968 dev->dev_addr[0], dev->dev_addr[1],
1969 dev->dev_addr[2], dev->dev_addr[3],
1970 dev->dev_addr[4], dev->dev_addr[5],
1971 dev->irq);
1972
1973 pci_set_drvdata(pdev, dev);
1974
1975 /* enable busmastering and memory-write-invalidate */
1976 pci_set_master(pdev);
1977
2e8a538d
JG		 1978 if (cp->wol_enabled)
1979 cp_set_d3_state (cp);
1da177e4
LT		 1980
1981 return 0;
1982
1983err_out_iomap:
1984 iounmap(regs);
1985err_out_res:
1986 pci_release_regions(pdev);
1987err_out_mwi:
1988 pci_clear_mwi(pdev);
1989err_out_disable:
1990 pci_disable_device(pdev);
1991err_out_free:
1992 free_netdev(dev);
1993 return rc;
1994}
1995
1996static void cp_remove_one (struct pci_dev *pdev)
1997{
1998 struct net_device *dev = pci_get_drvdata(pdev);
1999 struct cp_private *cp = netdev_priv(dev);
2000
1da177e4
LT		 2001 unregister_netdev(dev);
2002 iounmap(cp->regs);
2e8a538d
JG		 2003 if (cp->wol_enabled)
2004 pci_set_power_state (pdev, PCI_D0);
1da177e4
LT		 2005 pci_release_regions(pdev);
2006 pci_clear_mwi(pdev);
2007 pci_disable_device(pdev);
2008 pci_set_drvdata(pdev, NULL);
2009 free_netdev(dev);
2010}
2011
2012#ifdef CONFIG_PM
05adc3b7 2013static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4 2014{
7668a494
FR		 2015 struct net_device *dev = pci_get_drvdata(pdev);
2016 struct cp_private *cp = netdev_priv(dev);
1da177e4
LT		 2017 unsigned long flags;
2018
7668a494
FR		 2019 if (!netif_running(dev))
2020 return 0;
1da177e4
LT		 2021
2022 netif_device_detach (dev);
2023 netif_stop_queue (dev);
2024
2025 spin_lock_irqsave (&cp->lock, flags);
2026
2027 /* Disable Rx and Tx */
2028 cpw16 (IntrMask, 0);
2029 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2030
2031 spin_unlock_irqrestore (&cp->lock, flags);
2032
576cfa93
FR		 2033 pci_save_state(pdev);
2034 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2035 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 2036
2037 return 0;
2038}
2039
2040static int cp_resume (struct pci_dev *pdev)
2041{
576cfa93
FR		 2042 struct net_device *dev = pci_get_drvdata (pdev);
2043 struct cp_private *cp = netdev_priv(dev);
a4cf0761 2044 unsigned long flags;
1da177e4 2045
576cfa93
FR		 2046 if (!netif_running(dev))
2047 return 0;
1da177e4
LT		 2048
2049 netif_device_attach (dev);
576cfa93
FR		 2050
2051 pci_set_power_state(pdev, PCI_D0);
2052 pci_restore_state(pdev);
2053 pci_enable_wake(pdev, PCI_D0, 0);
2054
2055 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2056 cp_init_rings_index (cp);
1da177e4
LT		 2057 cp_init_hw (cp);
2058 netif_start_queue (dev);
a4cf0761
PO		 2059
2060 spin_lock_irqsave (&cp->lock, flags);
2061
2062 mii_check_media(&cp->mii_if, netif_msg_link(cp), FALSE);
2063
2064 spin_unlock_irqrestore (&cp->lock, flags);
f3b197ac 2065
1da177e4
LT		 2066 return 0;
2067}
2068#endif /* CONFIG_PM */
2069
2070static struct pci_driver cp_driver = {
2071 .name = DRV_NAME,
2072 .id_table = cp_pci_tbl,
2073 .probe = cp_init_one,
2074 .remove = cp_remove_one,
2075#ifdef CONFIG_PM
2076 .resume = cp_resume,
2077 .suspend = cp_suspend,
2078#endif
2079};
2080
2081static int __init cp_init (void)
2082{
2083#ifdef MODULE
2084 printk("%s", version);
2085#endif
29917620 2086 return pci_register_driver(&cp_driver);
1da177e4
LT		 2087}
2088
2089static void __exit cp_exit (void)
2090{
2091 pci_unregister_driver (&cp_driver);
2092}
2093
2094module_init(cp_init);
2095module_exit(cp_exit);
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