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Commit | Line | Data |
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cd5f6346 KP |
1 | /* |
2 | * linux/drivers/mtd/onenand/onenand_base.c | |
3 | * | |
75384b0d | 4 | * Copyright (C) 2005-2007 Samsung Electronics |
cd5f6346 KP |
5 | * Kyungmin Park <kyungmin.park@samsung.com> |
6 | * | |
81280d58 AH |
7 | * Credits: |
8 | * Adrian Hunter <ext-adrian.hunter@nokia.com>: | |
9 | * auto-placement support, read-while load support, various fixes | |
10 | * Copyright (C) Nokia Corporation, 2007 | |
11 | * | |
cd5f6346 KP |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
015953d7 | 20 | #include <linux/sched.h> |
2c22120f | 21 | #include <linux/interrupt.h> |
015953d7 | 22 | #include <linux/jiffies.h> |
cd5f6346 KP |
23 | #include <linux/mtd/mtd.h> |
24 | #include <linux/mtd/onenand.h> | |
25 | #include <linux/mtd/partitions.h> | |
26 | ||
27 | #include <asm/io.h> | |
28 | ||
29 | /** | |
30 | * onenand_oob_64 - oob info for large (2KB) page | |
31 | */ | |
5bd34c09 | 32 | static struct nand_ecclayout onenand_oob_64 = { |
cd5f6346 KP |
33 | .eccbytes = 20, |
34 | .eccpos = { | |
35 | 8, 9, 10, 11, 12, | |
36 | 24, 25, 26, 27, 28, | |
37 | 40, 41, 42, 43, 44, | |
38 | 56, 57, 58, 59, 60, | |
39 | }, | |
40 | .oobfree = { | |
41 | {2, 3}, {14, 2}, {18, 3}, {30, 2}, | |
d9777f1c JL |
42 | {34, 3}, {46, 2}, {50, 3}, {62, 2} |
43 | } | |
cd5f6346 KP |
44 | }; |
45 | ||
46 | /** | |
47 | * onenand_oob_32 - oob info for middle (1KB) page | |
48 | */ | |
5bd34c09 | 49 | static struct nand_ecclayout onenand_oob_32 = { |
cd5f6346 KP |
50 | .eccbytes = 10, |
51 | .eccpos = { | |
52 | 8, 9, 10, 11, 12, | |
53 | 24, 25, 26, 27, 28, | |
54 | }, | |
55 | .oobfree = { {2, 3}, {14, 2}, {18, 3}, {30, 2} } | |
56 | }; | |
57 | ||
58 | static const unsigned char ffchars[] = { | |
59 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
60 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */ | |
61 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
62 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 32 */ | |
63 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
64 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 48 */ | |
65 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
66 | 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 64 */ | |
67 | }; | |
68 | ||
69 | /** | |
70 | * onenand_readw - [OneNAND Interface] Read OneNAND register | |
71 | * @param addr address to read | |
72 | * | |
73 | * Read OneNAND register | |
74 | */ | |
75 | static unsigned short onenand_readw(void __iomem *addr) | |
76 | { | |
77 | return readw(addr); | |
78 | } | |
79 | ||
80 | /** | |
81 | * onenand_writew - [OneNAND Interface] Write OneNAND register with value | |
82 | * @param value value to write | |
83 | * @param addr address to write | |
84 | * | |
85 | * Write OneNAND register with value | |
86 | */ | |
87 | static void onenand_writew(unsigned short value, void __iomem *addr) | |
88 | { | |
89 | writew(value, addr); | |
90 | } | |
91 | ||
92 | /** | |
93 | * onenand_block_address - [DEFAULT] Get block address | |
83a36838 | 94 | * @param this onenand chip data structure |
cd5f6346 KP |
95 | * @param block the block |
96 | * @return translated block address if DDP, otherwise same | |
97 | * | |
98 | * Setup Start Address 1 Register (F100h) | |
99 | */ | |
83a36838 | 100 | static int onenand_block_address(struct onenand_chip *this, int block) |
cd5f6346 | 101 | { |
738d61f5 KP |
102 | /* Device Flash Core select, NAND Flash Block Address */ |
103 | if (block & this->density_mask) | |
104 | return ONENAND_DDP_CHIP1 | (block ^ this->density_mask); | |
cd5f6346 KP |
105 | |
106 | return block; | |
107 | } | |
108 | ||
109 | /** | |
110 | * onenand_bufferram_address - [DEFAULT] Get bufferram address | |
83a36838 | 111 | * @param this onenand chip data structure |
cd5f6346 KP |
112 | * @param block the block |
113 | * @return set DBS value if DDP, otherwise 0 | |
114 | * | |
115 | * Setup Start Address 2 Register (F101h) for DDP | |
116 | */ | |
83a36838 | 117 | static int onenand_bufferram_address(struct onenand_chip *this, int block) |
cd5f6346 | 118 | { |
738d61f5 KP |
119 | /* Device BufferRAM Select */ |
120 | if (block & this->density_mask) | |
121 | return ONENAND_DDP_CHIP1; | |
cd5f6346 | 122 | |
738d61f5 | 123 | return ONENAND_DDP_CHIP0; |
cd5f6346 KP |
124 | } |
125 | ||
126 | /** | |
127 | * onenand_page_address - [DEFAULT] Get page address | |
128 | * @param page the page address | |
129 | * @param sector the sector address | |
130 | * @return combined page and sector address | |
131 | * | |
132 | * Setup Start Address 8 Register (F107h) | |
133 | */ | |
134 | static int onenand_page_address(int page, int sector) | |
135 | { | |
136 | /* Flash Page Address, Flash Sector Address */ | |
137 | int fpa, fsa; | |
138 | ||
139 | fpa = page & ONENAND_FPA_MASK; | |
140 | fsa = sector & ONENAND_FSA_MASK; | |
141 | ||
142 | return ((fpa << ONENAND_FPA_SHIFT) | fsa); | |
143 | } | |
144 | ||
145 | /** | |
146 | * onenand_buffer_address - [DEFAULT] Get buffer address | |
147 | * @param dataram1 DataRAM index | |
148 | * @param sectors the sector address | |
149 | * @param count the number of sectors | |
150 | * @return the start buffer value | |
151 | * | |
152 | * Setup Start Buffer Register (F200h) | |
153 | */ | |
154 | static int onenand_buffer_address(int dataram1, int sectors, int count) | |
155 | { | |
156 | int bsa, bsc; | |
157 | ||
158 | /* BufferRAM Sector Address */ | |
159 | bsa = sectors & ONENAND_BSA_MASK; | |
160 | ||
161 | if (dataram1) | |
162 | bsa |= ONENAND_BSA_DATARAM1; /* DataRAM1 */ | |
163 | else | |
164 | bsa |= ONENAND_BSA_DATARAM0; /* DataRAM0 */ | |
165 | ||
166 | /* BufferRAM Sector Count */ | |
167 | bsc = count & ONENAND_BSC_MASK; | |
168 | ||
169 | return ((bsa << ONENAND_BSA_SHIFT) | bsc); | |
170 | } | |
171 | ||
172 | /** | |
173 | * onenand_command - [DEFAULT] Send command to OneNAND device | |
174 | * @param mtd MTD device structure | |
175 | * @param cmd the command to be sent | |
176 | * @param addr offset to read from or write to | |
177 | * @param len number of bytes to read or write | |
178 | * | |
179 | * Send command to OneNAND device. This function is used for middle/large page | |
180 | * devices (1KB/2KB Bytes per page) | |
181 | */ | |
182 | static int onenand_command(struct mtd_info *mtd, int cmd, loff_t addr, size_t len) | |
183 | { | |
184 | struct onenand_chip *this = mtd->priv; | |
493c6460 | 185 | int value, readcmd = 0, block_cmd = 0; |
cd5f6346 | 186 | int block, page; |
cd5f6346 KP |
187 | |
188 | /* Address translation */ | |
189 | switch (cmd) { | |
190 | case ONENAND_CMD_UNLOCK: | |
191 | case ONENAND_CMD_LOCK: | |
192 | case ONENAND_CMD_LOCK_TIGHT: | |
28b79ff9 | 193 | case ONENAND_CMD_UNLOCK_ALL: |
cd5f6346 KP |
194 | block = -1; |
195 | page = -1; | |
196 | break; | |
197 | ||
198 | case ONENAND_CMD_ERASE: | |
199 | case ONENAND_CMD_BUFFERRAM: | |
493c6460 KP |
200 | case ONENAND_CMD_OTP_ACCESS: |
201 | block_cmd = 1; | |
cd5f6346 KP |
202 | block = (int) (addr >> this->erase_shift); |
203 | page = -1; | |
204 | break; | |
205 | ||
206 | default: | |
207 | block = (int) (addr >> this->erase_shift); | |
208 | page = (int) (addr >> this->page_shift); | |
209 | page &= this->page_mask; | |
210 | break; | |
211 | } | |
212 | ||
213 | /* NOTE: The setting order of the registers is very important! */ | |
214 | if (cmd == ONENAND_CMD_BUFFERRAM) { | |
215 | /* Select DataRAM for DDP */ | |
83a36838 | 216 | value = onenand_bufferram_address(this, block); |
cd5f6346 KP |
217 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); |
218 | ||
219 | /* Switch to the next data buffer */ | |
220 | ONENAND_SET_NEXT_BUFFERRAM(this); | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | if (block != -1) { | |
226 | /* Write 'DFS, FBA' of Flash */ | |
83a36838 | 227 | value = onenand_block_address(this, block); |
cd5f6346 | 228 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); |
3cecf69e | 229 | |
75287070 | 230 | if (block_cmd) { |
3cecf69e KP |
231 | /* Select DataRAM for DDP */ |
232 | value = onenand_bufferram_address(this, block); | |
233 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
234 | } | |
cd5f6346 KP |
235 | } |
236 | ||
237 | if (page != -1) { | |
60d84f97 KP |
238 | /* Now we use page size operation */ |
239 | int sectors = 4, count = 4; | |
cd5f6346 KP |
240 | int dataram; |
241 | ||
242 | switch (cmd) { | |
243 | case ONENAND_CMD_READ: | |
244 | case ONENAND_CMD_READOOB: | |
245 | dataram = ONENAND_SET_NEXT_BUFFERRAM(this); | |
246 | readcmd = 1; | |
247 | break; | |
248 | ||
249 | default: | |
250 | dataram = ONENAND_CURRENT_BUFFERRAM(this); | |
251 | break; | |
252 | } | |
253 | ||
254 | /* Write 'FPA, FSA' of Flash */ | |
255 | value = onenand_page_address(page, sectors); | |
256 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS8); | |
257 | ||
258 | /* Write 'BSA, BSC' of DataRAM */ | |
259 | value = onenand_buffer_address(dataram, sectors, count); | |
260 | this->write_word(value, this->base + ONENAND_REG_START_BUFFER); | |
d5c5e78a | 261 | |
cd5f6346 KP |
262 | if (readcmd) { |
263 | /* Select DataRAM for DDP */ | |
83a36838 | 264 | value = onenand_bufferram_address(this, block); |
cd5f6346 KP |
265 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); |
266 | } | |
267 | } | |
268 | ||
269 | /* Interrupt clear */ | |
270 | this->write_word(ONENAND_INT_CLEAR, this->base + ONENAND_REG_INTERRUPT); | |
271 | ||
272 | /* Write command */ | |
273 | this->write_word(cmd, this->base + ONENAND_REG_COMMAND); | |
274 | ||
275 | return 0; | |
276 | } | |
277 | ||
278 | /** | |
279 | * onenand_wait - [DEFAULT] wait until the command is done | |
280 | * @param mtd MTD device structure | |
281 | * @param state state to select the max. timeout value | |
282 | * | |
283 | * Wait for command done. This applies to all OneNAND command | |
284 | * Read can take up to 30us, erase up to 2ms and program up to 350us | |
285 | * according to general OneNAND specs | |
286 | */ | |
287 | static int onenand_wait(struct mtd_info *mtd, int state) | |
288 | { | |
289 | struct onenand_chip * this = mtd->priv; | |
290 | unsigned long timeout; | |
291 | unsigned int flags = ONENAND_INT_MASTER; | |
292 | unsigned int interrupt = 0; | |
2fd32d4a | 293 | unsigned int ctrl; |
cd5f6346 KP |
294 | |
295 | /* The 20 msec is enough */ | |
296 | timeout = jiffies + msecs_to_jiffies(20); | |
297 | while (time_before(jiffies, timeout)) { | |
298 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
299 | ||
300 | if (interrupt & flags) | |
301 | break; | |
302 | ||
303 | if (state != FL_READING) | |
304 | cond_resched(); | |
305 | } | |
306 | /* To get correct interrupt status in timeout case */ | |
307 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
308 | ||
309 | ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); | |
310 | ||
311 | if (ctrl & ONENAND_CTRL_ERROR) { | |
211ac75f | 312 | printk(KERN_ERR "onenand_wait: controller error = 0x%04x\n", ctrl); |
f6272487 | 313 | if (ctrl & ONENAND_CTRL_LOCK) |
211ac75f | 314 | printk(KERN_ERR "onenand_wait: it's locked error.\n"); |
f6272487 | 315 | return ctrl; |
cd5f6346 KP |
316 | } |
317 | ||
318 | if (interrupt & ONENAND_INT_READ) { | |
2fd32d4a | 319 | int ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); |
f4f91ac3 | 320 | if (ecc) { |
211ac75f | 321 | printk(KERN_ERR "onenand_wait: ECC error = 0x%04x\n", ecc); |
b3c9f8bf | 322 | if (ecc & ONENAND_ECC_2BIT_ALL) { |
f4f91ac3 | 323 | mtd->ecc_stats.failed++; |
b3c9f8bf KP |
324 | return ecc; |
325 | } else if (ecc & ONENAND_ECC_1BIT_ALL) | |
f4f91ac3 | 326 | mtd->ecc_stats.corrected++; |
cd5f6346 | 327 | } |
9d032801 AH |
328 | } else if (state == FL_READING) { |
329 | printk(KERN_ERR "onenand_wait: read timeout! ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt); | |
330 | return -EIO; | |
cd5f6346 KP |
331 | } |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
2c22120f KP |
336 | /* |
337 | * onenand_interrupt - [DEFAULT] onenand interrupt handler | |
338 | * @param irq onenand interrupt number | |
339 | * @param dev_id interrupt data | |
340 | * | |
341 | * complete the work | |
342 | */ | |
343 | static irqreturn_t onenand_interrupt(int irq, void *data) | |
344 | { | |
345 | struct onenand_chip *this = (struct onenand_chip *) data; | |
346 | ||
347 | /* To handle shared interrupt */ | |
348 | if (!this->complete.done) | |
349 | complete(&this->complete); | |
350 | ||
351 | return IRQ_HANDLED; | |
352 | } | |
353 | ||
354 | /* | |
355 | * onenand_interrupt_wait - [DEFAULT] wait until the command is done | |
356 | * @param mtd MTD device structure | |
357 | * @param state state to select the max. timeout value | |
358 | * | |
359 | * Wait for command done. | |
360 | */ | |
361 | static int onenand_interrupt_wait(struct mtd_info *mtd, int state) | |
362 | { | |
363 | struct onenand_chip *this = mtd->priv; | |
364 | ||
2c22120f KP |
365 | wait_for_completion(&this->complete); |
366 | ||
367 | return onenand_wait(mtd, state); | |
368 | } | |
369 | ||
370 | /* | |
371 | * onenand_try_interrupt_wait - [DEFAULT] try interrupt wait | |
372 | * @param mtd MTD device structure | |
373 | * @param state state to select the max. timeout value | |
374 | * | |
375 | * Try interrupt based wait (It is used one-time) | |
376 | */ | |
377 | static int onenand_try_interrupt_wait(struct mtd_info *mtd, int state) | |
378 | { | |
379 | struct onenand_chip *this = mtd->priv; | |
380 | unsigned long remain, timeout; | |
381 | ||
382 | /* We use interrupt wait first */ | |
383 | this->wait = onenand_interrupt_wait; | |
384 | ||
2c22120f KP |
385 | timeout = msecs_to_jiffies(100); |
386 | remain = wait_for_completion_timeout(&this->complete, timeout); | |
387 | if (!remain) { | |
388 | printk(KERN_INFO "OneNAND: There's no interrupt. " | |
389 | "We use the normal wait\n"); | |
390 | ||
391 | /* Release the irq */ | |
392 | free_irq(this->irq, this); | |
c9ac5977 | 393 | |
2c22120f KP |
394 | this->wait = onenand_wait; |
395 | } | |
396 | ||
397 | return onenand_wait(mtd, state); | |
398 | } | |
399 | ||
400 | /* | |
401 | * onenand_setup_wait - [OneNAND Interface] setup onenand wait method | |
402 | * @param mtd MTD device structure | |
403 | * | |
404 | * There's two method to wait onenand work | |
405 | * 1. polling - read interrupt status register | |
406 | * 2. interrupt - use the kernel interrupt method | |
407 | */ | |
408 | static void onenand_setup_wait(struct mtd_info *mtd) | |
409 | { | |
410 | struct onenand_chip *this = mtd->priv; | |
411 | int syscfg; | |
412 | ||
413 | init_completion(&this->complete); | |
414 | ||
415 | if (this->irq <= 0) { | |
416 | this->wait = onenand_wait; | |
417 | return; | |
418 | } | |
419 | ||
420 | if (request_irq(this->irq, &onenand_interrupt, | |
421 | IRQF_SHARED, "onenand", this)) { | |
422 | /* If we can't get irq, use the normal wait */ | |
423 | this->wait = onenand_wait; | |
424 | return; | |
425 | } | |
426 | ||
427 | /* Enable interrupt */ | |
428 | syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); | |
429 | syscfg |= ONENAND_SYS_CFG1_IOBE; | |
430 | this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); | |
431 | ||
432 | this->wait = onenand_try_interrupt_wait; | |
433 | } | |
434 | ||
cd5f6346 KP |
435 | /** |
436 | * onenand_bufferram_offset - [DEFAULT] BufferRAM offset | |
437 | * @param mtd MTD data structure | |
438 | * @param area BufferRAM area | |
439 | * @return offset given area | |
440 | * | |
441 | * Return BufferRAM offset given area | |
442 | */ | |
443 | static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area) | |
444 | { | |
445 | struct onenand_chip *this = mtd->priv; | |
446 | ||
447 | if (ONENAND_CURRENT_BUFFERRAM(this)) { | |
448 | if (area == ONENAND_DATARAM) | |
28318776 | 449 | return mtd->writesize; |
cd5f6346 KP |
450 | if (area == ONENAND_SPARERAM) |
451 | return mtd->oobsize; | |
452 | } | |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | /** | |
458 | * onenand_read_bufferram - [OneNAND Interface] Read the bufferram area | |
459 | * @param mtd MTD data structure | |
460 | * @param area BufferRAM area | |
461 | * @param buffer the databuffer to put/get data | |
462 | * @param offset offset to read from or write to | |
463 | * @param count number of bytes to read/write | |
464 | * | |
465 | * Read the BufferRAM area | |
466 | */ | |
467 | static int onenand_read_bufferram(struct mtd_info *mtd, int area, | |
468 | unsigned char *buffer, int offset, size_t count) | |
469 | { | |
470 | struct onenand_chip *this = mtd->priv; | |
471 | void __iomem *bufferram; | |
472 | ||
473 | bufferram = this->base + area; | |
474 | ||
475 | bufferram += onenand_bufferram_offset(mtd, area); | |
476 | ||
9c01f87d KP |
477 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
478 | unsigned short word; | |
479 | ||
480 | /* Align with word(16-bit) size */ | |
481 | count--; | |
482 | ||
483 | /* Read word and save byte */ | |
484 | word = this->read_word(bufferram + offset + count); | |
485 | buffer[count] = (word & 0xff); | |
486 | } | |
487 | ||
cd5f6346 KP |
488 | memcpy(buffer, bufferram + offset, count); |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
52b0eea7 KP |
493 | /** |
494 | * onenand_sync_read_bufferram - [OneNAND Interface] Read the bufferram area with Sync. Burst mode | |
495 | * @param mtd MTD data structure | |
496 | * @param area BufferRAM area | |
497 | * @param buffer the databuffer to put/get data | |
498 | * @param offset offset to read from or write to | |
499 | * @param count number of bytes to read/write | |
500 | * | |
501 | * Read the BufferRAM area with Sync. Burst Mode | |
502 | */ | |
503 | static int onenand_sync_read_bufferram(struct mtd_info *mtd, int area, | |
504 | unsigned char *buffer, int offset, size_t count) | |
505 | { | |
506 | struct onenand_chip *this = mtd->priv; | |
507 | void __iomem *bufferram; | |
508 | ||
509 | bufferram = this->base + area; | |
510 | ||
511 | bufferram += onenand_bufferram_offset(mtd, area); | |
512 | ||
513 | this->mmcontrol(mtd, ONENAND_SYS_CFG1_SYNC_READ); | |
514 | ||
9c01f87d KP |
515 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
516 | unsigned short word; | |
517 | ||
518 | /* Align with word(16-bit) size */ | |
519 | count--; | |
520 | ||
521 | /* Read word and save byte */ | |
522 | word = this->read_word(bufferram + offset + count); | |
523 | buffer[count] = (word & 0xff); | |
524 | } | |
525 | ||
52b0eea7 KP |
526 | memcpy(buffer, bufferram + offset, count); |
527 | ||
528 | this->mmcontrol(mtd, 0); | |
529 | ||
530 | return 0; | |
531 | } | |
532 | ||
cd5f6346 KP |
533 | /** |
534 | * onenand_write_bufferram - [OneNAND Interface] Write the bufferram area | |
535 | * @param mtd MTD data structure | |
536 | * @param area BufferRAM area | |
537 | * @param buffer the databuffer to put/get data | |
538 | * @param offset offset to read from or write to | |
539 | * @param count number of bytes to read/write | |
540 | * | |
541 | * Write the BufferRAM area | |
542 | */ | |
543 | static int onenand_write_bufferram(struct mtd_info *mtd, int area, | |
544 | const unsigned char *buffer, int offset, size_t count) | |
545 | { | |
546 | struct onenand_chip *this = mtd->priv; | |
547 | void __iomem *bufferram; | |
548 | ||
549 | bufferram = this->base + area; | |
550 | ||
551 | bufferram += onenand_bufferram_offset(mtd, area); | |
552 | ||
9c01f87d KP |
553 | if (ONENAND_CHECK_BYTE_ACCESS(count)) { |
554 | unsigned short word; | |
555 | int byte_offset; | |
556 | ||
557 | /* Align with word(16-bit) size */ | |
558 | count--; | |
559 | ||
560 | /* Calculate byte access offset */ | |
561 | byte_offset = offset + count; | |
562 | ||
563 | /* Read word and save byte */ | |
564 | word = this->read_word(bufferram + byte_offset); | |
565 | word = (word & ~0xff) | buffer[count]; | |
566 | this->write_word(word, bufferram + byte_offset); | |
567 | } | |
568 | ||
cd5f6346 KP |
569 | memcpy(bufferram + offset, buffer, count); |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
574 | /** | |
575 | * onenand_check_bufferram - [GENERIC] Check BufferRAM information | |
576 | * @param mtd MTD data structure | |
577 | * @param addr address to check | |
d5c5e78a | 578 | * @return 1 if there are valid data, otherwise 0 |
cd5f6346 KP |
579 | * |
580 | * Check bufferram if there is data we required | |
581 | */ | |
582 | static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr) | |
583 | { | |
584 | struct onenand_chip *this = mtd->priv; | |
cde36b37 | 585 | int blockpage, found = 0; |
abf3c0f2 | 586 | unsigned int i; |
d5c5e78a | 587 | |
abf3c0f2 | 588 | blockpage = (int) (addr >> this->page_shift); |
cd5f6346 | 589 | |
abf3c0f2 | 590 | /* Is there valid data? */ |
cd5f6346 | 591 | i = ONENAND_CURRENT_BUFFERRAM(this); |
abf3c0f2 | 592 | if (this->bufferram[i].blockpage == blockpage) |
cde36b37 AH |
593 | found = 1; |
594 | else { | |
595 | /* Check another BufferRAM */ | |
596 | i = ONENAND_NEXT_BUFFERRAM(this); | |
597 | if (this->bufferram[i].blockpage == blockpage) { | |
598 | ONENAND_SET_NEXT_BUFFERRAM(this); | |
599 | found = 1; | |
600 | } | |
601 | } | |
cd5f6346 | 602 | |
cde36b37 AH |
603 | if (found && ONENAND_IS_DDP(this)) { |
604 | /* Select DataRAM for DDP */ | |
605 | int block = (int) (addr >> this->erase_shift); | |
606 | int value = onenand_bufferram_address(this, block); | |
607 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
abf3c0f2 | 608 | } |
cd5f6346 | 609 | |
cde36b37 | 610 | return found; |
cd5f6346 KP |
611 | } |
612 | ||
613 | /** | |
614 | * onenand_update_bufferram - [GENERIC] Update BufferRAM information | |
615 | * @param mtd MTD data structure | |
616 | * @param addr address to update | |
617 | * @param valid valid flag | |
618 | * | |
619 | * Update BufferRAM information | |
620 | */ | |
abf3c0f2 | 621 | static void onenand_update_bufferram(struct mtd_info *mtd, loff_t addr, |
cd5f6346 KP |
622 | int valid) |
623 | { | |
624 | struct onenand_chip *this = mtd->priv; | |
abf3c0f2 KP |
625 | int blockpage; |
626 | unsigned int i; | |
d5c5e78a | 627 | |
abf3c0f2 | 628 | blockpage = (int) (addr >> this->page_shift); |
cd5f6346 | 629 | |
abf3c0f2 KP |
630 | /* Invalidate another BufferRAM */ |
631 | i = ONENAND_NEXT_BUFFERRAM(this); | |
5b4246f1 | 632 | if (this->bufferram[i].blockpage == blockpage) |
abf3c0f2 | 633 | this->bufferram[i].blockpage = -1; |
cd5f6346 KP |
634 | |
635 | /* Update BufferRAM */ | |
636 | i = ONENAND_CURRENT_BUFFERRAM(this); | |
abf3c0f2 KP |
637 | if (valid) |
638 | this->bufferram[i].blockpage = blockpage; | |
639 | else | |
640 | this->bufferram[i].blockpage = -1; | |
cd5f6346 KP |
641 | } |
642 | ||
480b9dfb AH |
643 | /** |
644 | * onenand_invalidate_bufferram - [GENERIC] Invalidate BufferRAM information | |
645 | * @param mtd MTD data structure | |
646 | * @param addr start address to invalidate | |
647 | * @param len length to invalidate | |
648 | * | |
649 | * Invalidate BufferRAM information | |
650 | */ | |
651 | static void onenand_invalidate_bufferram(struct mtd_info *mtd, loff_t addr, | |
652 | unsigned int len) | |
653 | { | |
654 | struct onenand_chip *this = mtd->priv; | |
655 | int i; | |
656 | loff_t end_addr = addr + len; | |
657 | ||
658 | /* Invalidate BufferRAM */ | |
659 | for (i = 0; i < MAX_BUFFERRAM; i++) { | |
660 | loff_t buf_addr = this->bufferram[i].blockpage << this->page_shift; | |
661 | if (buf_addr >= addr && buf_addr < end_addr) | |
662 | this->bufferram[i].blockpage = -1; | |
663 | } | |
664 | } | |
665 | ||
cd5f6346 KP |
666 | /** |
667 | * onenand_get_device - [GENERIC] Get chip for selected access | |
668 | * @param mtd MTD device structure | |
669 | * @param new_state the state which is requested | |
670 | * | |
671 | * Get the device and lock it for exclusive access | |
672 | */ | |
a41371eb | 673 | static int onenand_get_device(struct mtd_info *mtd, int new_state) |
cd5f6346 KP |
674 | { |
675 | struct onenand_chip *this = mtd->priv; | |
676 | DECLARE_WAITQUEUE(wait, current); | |
677 | ||
678 | /* | |
679 | * Grab the lock and see if the device is available | |
680 | */ | |
681 | while (1) { | |
682 | spin_lock(&this->chip_lock); | |
683 | if (this->state == FL_READY) { | |
684 | this->state = new_state; | |
685 | spin_unlock(&this->chip_lock); | |
686 | break; | |
687 | } | |
a41371eb KP |
688 | if (new_state == FL_PM_SUSPENDED) { |
689 | spin_unlock(&this->chip_lock); | |
690 | return (this->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN; | |
691 | } | |
cd5f6346 KP |
692 | set_current_state(TASK_UNINTERRUPTIBLE); |
693 | add_wait_queue(&this->wq, &wait); | |
694 | spin_unlock(&this->chip_lock); | |
695 | schedule(); | |
696 | remove_wait_queue(&this->wq, &wait); | |
697 | } | |
a41371eb KP |
698 | |
699 | return 0; | |
cd5f6346 KP |
700 | } |
701 | ||
702 | /** | |
703 | * onenand_release_device - [GENERIC] release chip | |
704 | * @param mtd MTD device structure | |
705 | * | |
706 | * Deselect, release chip lock and wake up anyone waiting on the device | |
707 | */ | |
708 | static void onenand_release_device(struct mtd_info *mtd) | |
709 | { | |
710 | struct onenand_chip *this = mtd->priv; | |
711 | ||
712 | /* Release the chip */ | |
713 | spin_lock(&this->chip_lock); | |
714 | this->state = FL_READY; | |
715 | wake_up(&this->wq); | |
716 | spin_unlock(&this->chip_lock); | |
717 | } | |
718 | ||
719 | /** | |
9223a456 | 720 | * onenand_read - [MTD Interface] Read data from flash |
cd5f6346 KP |
721 | * @param mtd MTD device structure |
722 | * @param from offset to read from | |
723 | * @param len number of bytes to read | |
724 | * @param retlen pointer to variable to store the number of read bytes | |
725 | * @param buf the databuffer to put data | |
cd5f6346 | 726 | * |
9223a456 TG |
727 | * Read with ecc |
728 | */ | |
729 | static int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, | |
730 | size_t *retlen, u_char *buf) | |
cd5f6346 KP |
731 | { |
732 | struct onenand_chip *this = mtd->priv; | |
f4f91ac3 | 733 | struct mtd_ecc_stats stats; |
cd5f6346 KP |
734 | int read = 0, column; |
735 | int thislen; | |
0fc2ccea | 736 | int ret = 0, boundary = 0; |
cd5f6346 | 737 | |
9223a456 | 738 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_read: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); |
cd5f6346 KP |
739 | |
740 | /* Do not allow reads past end of device */ | |
741 | if ((from + len) > mtd->size) { | |
211ac75f | 742 | printk(KERN_ERR "onenand_read: Attempt read beyond end of device\n"); |
cd5f6346 KP |
743 | *retlen = 0; |
744 | return -EINVAL; | |
745 | } | |
746 | ||
747 | /* Grab the lock and see if the device is available */ | |
748 | onenand_get_device(mtd, FL_READING); | |
749 | ||
f4f91ac3 | 750 | stats = mtd->ecc_stats; |
61a7e198 | 751 | |
a8de85d5 AH |
752 | /* Read-while-load method */ |
753 | ||
754 | /* Do first load to bufferRAM */ | |
755 | if (read < len) { | |
756 | if (!onenand_check_bufferram(mtd, from)) { | |
757 | this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize); | |
758 | ret = this->wait(mtd, FL_READING); | |
759 | onenand_update_bufferram(mtd, from, !ret); | |
760 | } | |
761 | } | |
762 | ||
763 | thislen = min_t(int, mtd->writesize, len - read); | |
764 | column = from & (mtd->writesize - 1); | |
765 | if (column + thislen > mtd->writesize) | |
766 | thislen = mtd->writesize - column; | |
767 | ||
768 | while (!ret) { | |
769 | /* If there is more to load then start next load */ | |
770 | from += thislen; | |
771 | if (read + thislen < len) { | |
772 | this->command(mtd, ONENAND_CMD_READ, from, mtd->writesize); | |
0fc2ccea AH |
773 | /* |
774 | * Chip boundary handling in DDP | |
775 | * Now we issued chip 1 read and pointed chip 1 | |
776 | * bufferam so we have to point chip 0 bufferam. | |
777 | */ | |
738d61f5 KP |
778 | if (ONENAND_IS_DDP(this) && |
779 | unlikely(from == (this->chipsize >> 1))) { | |
780 | this->write_word(ONENAND_DDP_CHIP0, this->base + ONENAND_REG_START_ADDRESS2); | |
0fc2ccea AH |
781 | boundary = 1; |
782 | } else | |
783 | boundary = 0; | |
a8de85d5 AH |
784 | ONENAND_SET_PREV_BUFFERRAM(this); |
785 | } | |
786 | /* While load is going, read from last bufferRAM */ | |
787 | this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen); | |
788 | /* See if we are done */ | |
789 | read += thislen; | |
790 | if (read == len) | |
791 | break; | |
792 | /* Set up for next read from bufferRAM */ | |
0fc2ccea | 793 | if (unlikely(boundary)) |
738d61f5 | 794 | this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2); |
a8de85d5 AH |
795 | ONENAND_SET_NEXT_BUFFERRAM(this); |
796 | buf += thislen; | |
797 | thislen = min_t(int, mtd->writesize, len - read); | |
798 | column = 0; | |
799 | cond_resched(); | |
800 | /* Now wait for load */ | |
801 | ret = this->wait(mtd, FL_READING); | |
802 | onenand_update_bufferram(mtd, from, !ret); | |
803 | } | |
cd5f6346 | 804 | |
cd5f6346 KP |
805 | /* Deselect and wake up anyone waiting on the device */ |
806 | onenand_release_device(mtd); | |
807 | ||
808 | /* | |
809 | * Return success, if no ECC failures, else -EBADMSG | |
810 | * fs driver will take care of that, because | |
811 | * retlen == desired len and result == -EBADMSG | |
812 | */ | |
813 | *retlen = read; | |
f4f91ac3 KP |
814 | |
815 | if (mtd->ecc_stats.failed - stats.failed) | |
816 | return -EBADMSG; | |
817 | ||
a8de85d5 AH |
818 | if (ret) |
819 | return ret; | |
820 | ||
f4f91ac3 | 821 | return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; |
cd5f6346 KP |
822 | } |
823 | ||
a5e7c7b4 AH |
824 | /** |
825 | * onenand_transfer_auto_oob - [Internal] oob auto-placement transfer | |
826 | * @param mtd MTD device structure | |
827 | * @param buf destination address | |
828 | * @param column oob offset to read from | |
829 | * @param thislen oob length to read | |
830 | */ | |
831 | static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, int column, | |
832 | int thislen) | |
833 | { | |
834 | struct onenand_chip *this = mtd->priv; | |
835 | struct nand_oobfree *free; | |
836 | int readcol = column; | |
837 | int readend = column + thislen; | |
838 | int lastgap = 0; | |
ad286343 | 839 | unsigned int i; |
470bc844 | 840 | uint8_t *oob_buf = this->oob_buf; |
a5e7c7b4 | 841 | |
ad286343 KP |
842 | free = this->ecclayout->oobfree; |
843 | for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { | |
a5e7c7b4 AH |
844 | if (readcol >= lastgap) |
845 | readcol += free->offset - lastgap; | |
846 | if (readend >= lastgap) | |
847 | readend += free->offset - lastgap; | |
848 | lastgap = free->offset + free->length; | |
849 | } | |
4f4fad27 | 850 | this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize); |
ad286343 KP |
851 | free = this->ecclayout->oobfree; |
852 | for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { | |
a5e7c7b4 AH |
853 | int free_end = free->offset + free->length; |
854 | if (free->offset < readend && free_end > readcol) { | |
855 | int st = max_t(int,free->offset,readcol); | |
856 | int ed = min_t(int,free_end,readend); | |
857 | int n = ed - st; | |
858 | memcpy(buf, oob_buf + st, n); | |
859 | buf += n; | |
c36c46d5 | 860 | } else if (column == 0) |
5bc399e9 | 861 | break; |
a5e7c7b4 AH |
862 | } |
863 | return 0; | |
864 | } | |
865 | ||
cd5f6346 | 866 | /** |
8593fbc6 | 867 | * onenand_do_read_oob - [MTD Interface] OneNAND read out-of-band |
cd5f6346 KP |
868 | * @param mtd MTD device structure |
869 | * @param from offset to read from | |
870 | * @param len number of bytes to read | |
871 | * @param retlen pointer to variable to store the number of read bytes | |
872 | * @param buf the databuffer to put data | |
a5e7c7b4 | 873 | * @param mode operation mode |
cd5f6346 KP |
874 | * |
875 | * OneNAND read out-of-band data from the spare area | |
876 | */ | |
211ac75f | 877 | static int onenand_do_read_oob(struct mtd_info *mtd, loff_t from, size_t len, |
a5e7c7b4 | 878 | size_t *retlen, u_char *buf, mtd_oob_mode_t mode) |
cd5f6346 KP |
879 | { |
880 | struct onenand_chip *this = mtd->priv; | |
a5e7c7b4 | 881 | int read = 0, thislen, column, oobsize; |
cd5f6346 KP |
882 | int ret = 0; |
883 | ||
884 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); | |
885 | ||
886 | /* Initialize return length value */ | |
887 | *retlen = 0; | |
888 | ||
a5e7c7b4 AH |
889 | if (mode == MTD_OOB_AUTO) |
890 | oobsize = this->ecclayout->oobavail; | |
891 | else | |
892 | oobsize = mtd->oobsize; | |
893 | ||
894 | column = from & (mtd->oobsize - 1); | |
895 | ||
896 | if (unlikely(column >= oobsize)) { | |
211ac75f | 897 | printk(KERN_ERR "onenand_read_oob: Attempted to start read outside oob\n"); |
a5e7c7b4 AH |
898 | return -EINVAL; |
899 | } | |
900 | ||
cd5f6346 | 901 | /* Do not allow reads past end of device */ |
a5e7c7b4 AH |
902 | if (unlikely(from >= mtd->size || |
903 | column + len > ((mtd->size >> this->page_shift) - | |
904 | (from >> this->page_shift)) * oobsize)) { | |
211ac75f | 905 | printk(KERN_ERR "onenand_read_oob: Attempted to read beyond end of device\n"); |
cd5f6346 KP |
906 | return -EINVAL; |
907 | } | |
908 | ||
909 | /* Grab the lock and see if the device is available */ | |
910 | onenand_get_device(mtd, FL_READING); | |
911 | ||
cd5f6346 | 912 | while (read < len) { |
61a7e198 AB |
913 | cond_resched(); |
914 | ||
a5e7c7b4 | 915 | thislen = oobsize - column; |
cd5f6346 KP |
916 | thislen = min_t(int, thislen, len); |
917 | ||
918 | this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); | |
919 | ||
920 | onenand_update_bufferram(mtd, from, 0); | |
921 | ||
922 | ret = this->wait(mtd, FL_READING); | |
923 | /* First copy data and check return value for ECC handling */ | |
924 | ||
a5e7c7b4 AH |
925 | if (mode == MTD_OOB_AUTO) |
926 | onenand_transfer_auto_oob(mtd, buf, column, thislen); | |
927 | else | |
928 | this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen); | |
cd5f6346 | 929 | |
f6272487 | 930 | if (ret) { |
211ac75f | 931 | printk(KERN_ERR "onenand_read_oob: read failed = 0x%x\n", ret); |
5b4246f1 | 932 | break; |
f6272487 KP |
933 | } |
934 | ||
cd5f6346 KP |
935 | read += thislen; |
936 | ||
937 | if (read == len) | |
938 | break; | |
939 | ||
cd5f6346 KP |
940 | buf += thislen; |
941 | ||
942 | /* Read more? */ | |
943 | if (read < len) { | |
944 | /* Page size */ | |
28318776 | 945 | from += mtd->writesize; |
cd5f6346 KP |
946 | column = 0; |
947 | } | |
948 | } | |
949 | ||
cd5f6346 KP |
950 | /* Deselect and wake up anyone waiting on the device */ |
951 | onenand_release_device(mtd); | |
952 | ||
953 | *retlen = read; | |
954 | return ret; | |
955 | } | |
956 | ||
8593fbc6 TG |
957 | /** |
958 | * onenand_read_oob - [MTD Interface] NAND write data and/or out-of-band | |
e3da8067 KP |
959 | * @param mtd: MTD device structure |
960 | * @param from: offset to read from | |
961 | * @param ops: oob operation description structure | |
8593fbc6 TG |
962 | */ |
963 | static int onenand_read_oob(struct mtd_info *mtd, loff_t from, | |
964 | struct mtd_oob_ops *ops) | |
965 | { | |
4f4fad27 | 966 | switch (ops->mode) { |
a5e7c7b4 AH |
967 | case MTD_OOB_PLACE: |
968 | case MTD_OOB_AUTO: | |
969 | break; | |
970 | case MTD_OOB_RAW: | |
4f4fad27 | 971 | /* Not implemented yet */ |
a5e7c7b4 AH |
972 | default: |
973 | return -EINVAL; | |
974 | } | |
66a1e421 | 975 | return onenand_do_read_oob(mtd, from + ops->ooboffs, ops->ooblen, |
a5e7c7b4 | 976 | &ops->oobretlen, ops->oobbuf, ops->mode); |
8593fbc6 TG |
977 | } |
978 | ||
211ac75f KP |
979 | /** |
980 | * onenand_bbt_wait - [DEFAULT] wait until the command is done | |
981 | * @param mtd MTD device structure | |
982 | * @param state state to select the max. timeout value | |
983 | * | |
984 | * Wait for command done. | |
985 | */ | |
986 | static int onenand_bbt_wait(struct mtd_info *mtd, int state) | |
987 | { | |
988 | struct onenand_chip *this = mtd->priv; | |
989 | unsigned long timeout; | |
990 | unsigned int interrupt; | |
991 | unsigned int ctrl; | |
992 | ||
993 | /* The 20 msec is enough */ | |
994 | timeout = jiffies + msecs_to_jiffies(20); | |
995 | while (time_before(jiffies, timeout)) { | |
996 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
997 | if (interrupt & ONENAND_INT_MASTER) | |
998 | break; | |
999 | } | |
1000 | /* To get correct interrupt status in timeout case */ | |
1001 | interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); | |
1002 | ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); | |
1003 | ||
1004 | if (ctrl & ONENAND_CTRL_ERROR) { | |
1005 | printk(KERN_DEBUG "onenand_bbt_wait: controller error = 0x%04x\n", ctrl); | |
1006 | /* Initial bad block case */ | |
1007 | if (ctrl & ONENAND_CTRL_LOAD) | |
1008 | return ONENAND_BBT_READ_ERROR; | |
1009 | return ONENAND_BBT_READ_FATAL_ERROR; | |
1010 | } | |
1011 | ||
1012 | if (interrupt & ONENAND_INT_READ) { | |
1013 | int ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); | |
1014 | if (ecc & ONENAND_ECC_2BIT_ALL) | |
1015 | return ONENAND_BBT_READ_ERROR; | |
1016 | } else { | |
1017 | printk(KERN_ERR "onenand_bbt_wait: read timeout!" | |
1018 | "ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt); | |
1019 | return ONENAND_BBT_READ_FATAL_ERROR; | |
1020 | } | |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
1025 | /** | |
1026 | * onenand_bbt_read_oob - [MTD Interface] OneNAND read out-of-band for bbt scan | |
1027 | * @param mtd MTD device structure | |
1028 | * @param from offset to read from | |
e3da8067 | 1029 | * @param ops oob operation description structure |
211ac75f KP |
1030 | * |
1031 | * OneNAND read out-of-band data from the spare area for bbt scan | |
1032 | */ | |
1033 | int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, | |
1034 | struct mtd_oob_ops *ops) | |
1035 | { | |
1036 | struct onenand_chip *this = mtd->priv; | |
1037 | int read = 0, thislen, column; | |
1038 | int ret = 0; | |
1039 | size_t len = ops->ooblen; | |
1040 | u_char *buf = ops->oobbuf; | |
1041 | ||
5785bdd6 | 1042 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_bbt_read_oob: from = 0x%08x, len = %zi\n", (unsigned int) from, len); |
211ac75f KP |
1043 | |
1044 | /* Initialize return value */ | |
1045 | ops->oobretlen = 0; | |
1046 | ||
1047 | /* Do not allow reads past end of device */ | |
1048 | if (unlikely((from + len) > mtd->size)) { | |
1049 | printk(KERN_ERR "onenand_bbt_read_oob: Attempt read beyond end of device\n"); | |
1050 | return ONENAND_BBT_READ_FATAL_ERROR; | |
1051 | } | |
1052 | ||
1053 | /* Grab the lock and see if the device is available */ | |
1054 | onenand_get_device(mtd, FL_READING); | |
1055 | ||
1056 | column = from & (mtd->oobsize - 1); | |
1057 | ||
1058 | while (read < len) { | |
1059 | cond_resched(); | |
1060 | ||
1061 | thislen = mtd->oobsize - column; | |
1062 | thislen = min_t(int, thislen, len); | |
1063 | ||
1064 | this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); | |
1065 | ||
1066 | onenand_update_bufferram(mtd, from, 0); | |
1067 | ||
1068 | ret = onenand_bbt_wait(mtd, FL_READING); | |
1069 | if (ret) | |
1070 | break; | |
1071 | ||
1072 | this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen); | |
1073 | read += thislen; | |
1074 | if (read == len) | |
1075 | break; | |
1076 | ||
1077 | buf += thislen; | |
1078 | ||
1079 | /* Read more? */ | |
1080 | if (read < len) { | |
1081 | /* Update Page size */ | |
1082 | from += mtd->writesize; | |
1083 | column = 0; | |
1084 | } | |
1085 | } | |
1086 | ||
1087 | /* Deselect and wake up anyone waiting on the device */ | |
1088 | onenand_release_device(mtd); | |
1089 | ||
1090 | ops->oobretlen = read; | |
1091 | return ret; | |
1092 | } | |
1093 | ||
cd5f6346 | 1094 | #ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE |
8e6ec690 KP |
1095 | /** |
1096 | * onenand_verify_oob - [GENERIC] verify the oob contents after a write | |
1097 | * @param mtd MTD device structure | |
1098 | * @param buf the databuffer to verify | |
1099 | * @param to offset to read from | |
8e6ec690 KP |
1100 | * |
1101 | */ | |
a5e7c7b4 | 1102 | static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to) |
8e6ec690 KP |
1103 | { |
1104 | struct onenand_chip *this = mtd->priv; | |
91014e9b | 1105 | char oobbuf[64]; |
8e6ec690 KP |
1106 | int status, i; |
1107 | ||
1108 | this->command(mtd, ONENAND_CMD_READOOB, to, mtd->oobsize); | |
1109 | onenand_update_bufferram(mtd, to, 0); | |
1110 | status = this->wait(mtd, FL_READING); | |
1111 | if (status) | |
1112 | return status; | |
1113 | ||
91014e9b KP |
1114 | this->read_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize); |
1115 | for (i = 0; i < mtd->oobsize; i++) | |
1116 | if (buf[i] != 0xFF && buf[i] != oobbuf[i]) | |
8e6ec690 KP |
1117 | return -EBADMSG; |
1118 | ||
1119 | return 0; | |
1120 | } | |
1121 | ||
cd5f6346 | 1122 | /** |
8b29c0b6 AH |
1123 | * onenand_verify - [GENERIC] verify the chip contents after a write |
1124 | * @param mtd MTD device structure | |
1125 | * @param buf the databuffer to verify | |
1126 | * @param addr offset to read from | |
1127 | * @param len number of bytes to read and compare | |
cd5f6346 | 1128 | * |
cd5f6346 | 1129 | */ |
8b29c0b6 | 1130 | static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr, size_t len) |
cd5f6346 KP |
1131 | { |
1132 | struct onenand_chip *this = mtd->priv; | |
8b29c0b6 | 1133 | void __iomem *dataram; |
cd5f6346 | 1134 | int ret = 0; |
8b29c0b6 | 1135 | int thislen, column; |
cd5f6346 | 1136 | |
8b29c0b6 AH |
1137 | while (len != 0) { |
1138 | thislen = min_t(int, mtd->writesize, len); | |
1139 | column = addr & (mtd->writesize - 1); | |
1140 | if (column + thislen > mtd->writesize) | |
1141 | thislen = mtd->writesize - column; | |
60d84f97 | 1142 | |
8b29c0b6 | 1143 | this->command(mtd, ONENAND_CMD_READ, addr, mtd->writesize); |
cd5f6346 | 1144 | |
8b29c0b6 AH |
1145 | onenand_update_bufferram(mtd, addr, 0); |
1146 | ||
1147 | ret = this->wait(mtd, FL_READING); | |
1148 | if (ret) | |
1149 | return ret; | |
cd5f6346 | 1150 | |
8b29c0b6 | 1151 | onenand_update_bufferram(mtd, addr, 1); |
cd5f6346 | 1152 | |
8b29c0b6 AH |
1153 | dataram = this->base + ONENAND_DATARAM; |
1154 | dataram += onenand_bufferram_offset(mtd, ONENAND_DATARAM); | |
cd5f6346 | 1155 | |
8b29c0b6 AH |
1156 | if (memcmp(buf, dataram + column, thislen)) |
1157 | return -EBADMSG; | |
1158 | ||
1159 | len -= thislen; | |
1160 | buf += thislen; | |
1161 | addr += thislen; | |
1162 | } | |
d5c5e78a | 1163 | |
cd5f6346 KP |
1164 | return 0; |
1165 | } | |
1166 | #else | |
8b29c0b6 | 1167 | #define onenand_verify(...) (0) |
8e6ec690 | 1168 | #define onenand_verify_oob(...) (0) |
cd5f6346 KP |
1169 | #endif |
1170 | ||
60d84f97 | 1171 | #define NOTALIGNED(x) ((x & (this->subpagesize - 1)) != 0) |
cd5f6346 KP |
1172 | |
1173 | /** | |
9223a456 | 1174 | * onenand_write - [MTD Interface] write buffer to FLASH |
cd5f6346 KP |
1175 | * @param mtd MTD device structure |
1176 | * @param to offset to write to | |
1177 | * @param len number of bytes to write | |
1178 | * @param retlen pointer to variable to store the number of written bytes | |
1179 | * @param buf the data to write | |
cd5f6346 | 1180 | * |
9223a456 | 1181 | * Write with ECC |
cd5f6346 | 1182 | */ |
9223a456 TG |
1183 | static int onenand_write(struct mtd_info *mtd, loff_t to, size_t len, |
1184 | size_t *retlen, const u_char *buf) | |
cd5f6346 KP |
1185 | { |
1186 | struct onenand_chip *this = mtd->priv; | |
1187 | int written = 0; | |
1188 | int ret = 0; | |
60d84f97 | 1189 | int column, subpage; |
cd5f6346 | 1190 | |
9223a456 | 1191 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_write: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); |
cd5f6346 KP |
1192 | |
1193 | /* Initialize retlen, in case of early exit */ | |
1194 | *retlen = 0; | |
1195 | ||
1196 | /* Do not allow writes past end of device */ | |
1197 | if (unlikely((to + len) > mtd->size)) { | |
211ac75f | 1198 | printk(KERN_ERR "onenand_write: Attempt write to past end of device\n"); |
cd5f6346 KP |
1199 | return -EINVAL; |
1200 | } | |
1201 | ||
1202 | /* Reject writes, which are not page aligned */ | |
1203 | if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) { | |
211ac75f | 1204 | printk(KERN_ERR "onenand_write: Attempt to write not page aligned data\n"); |
cd5f6346 KP |
1205 | return -EINVAL; |
1206 | } | |
1207 | ||
60d84f97 | 1208 | column = to & (mtd->writesize - 1); |
60d84f97 | 1209 | |
cd5f6346 KP |
1210 | /* Grab the lock and see if the device is available */ |
1211 | onenand_get_device(mtd, FL_WRITING); | |
1212 | ||
1213 | /* Loop until all data write */ | |
1214 | while (written < len) { | |
81f38e11 | 1215 | int thislen = min_t(int, mtd->writesize - column, len - written); |
60d84f97 KP |
1216 | u_char *wbuf = (u_char *) buf; |
1217 | ||
61a7e198 AB |
1218 | cond_resched(); |
1219 | ||
81f38e11 | 1220 | this->command(mtd, ONENAND_CMD_BUFFERRAM, to, thislen); |
60d84f97 KP |
1221 | |
1222 | /* Partial page write */ | |
81f38e11 | 1223 | subpage = thislen < mtd->writesize; |
60d84f97 | 1224 | if (subpage) { |
60d84f97 | 1225 | memset(this->page_buf, 0xff, mtd->writesize); |
81f38e11 | 1226 | memcpy(this->page_buf + column, buf, thislen); |
60d84f97 | 1227 | wbuf = this->page_buf; |
60d84f97 | 1228 | } |
cd5f6346 | 1229 | |
81f38e11 | 1230 | this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, mtd->writesize); |
cd5f6346 KP |
1231 | this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, mtd->oobsize); |
1232 | ||
28318776 | 1233 | this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize); |
cd5f6346 | 1234 | |
81f38e11 AH |
1235 | ret = this->wait(mtd, FL_WRITING); |
1236 | ||
60d84f97 | 1237 | /* In partial page write we don't update bufferram */ |
81f38e11 | 1238 | onenand_update_bufferram(mtd, to, !ret && !subpage); |
cd5f6346 | 1239 | |
cd5f6346 | 1240 | if (ret) { |
211ac75f | 1241 | printk(KERN_ERR "onenand_write: write filaed %d\n", ret); |
60d84f97 | 1242 | break; |
cd5f6346 KP |
1243 | } |
1244 | ||
cd5f6346 | 1245 | /* Only check verify write turn on */ |
8b29c0b6 | 1246 | ret = onenand_verify(mtd, (u_char *) wbuf, to, thislen); |
cd5f6346 | 1247 | if (ret) { |
211ac75f | 1248 | printk(KERN_ERR "onenand_write: verify failed %d\n", ret); |
60d84f97 | 1249 | break; |
cd5f6346 KP |
1250 | } |
1251 | ||
60d84f97 | 1252 | written += thislen; |
81f38e11 | 1253 | |
cd5f6346 KP |
1254 | if (written == len) |
1255 | break; | |
1256 | ||
60d84f97 | 1257 | column = 0; |
cd5f6346 KP |
1258 | to += thislen; |
1259 | buf += thislen; | |
1260 | } | |
1261 | ||
cd5f6346 KP |
1262 | /* Deselect and wake up anyone waiting on the device */ |
1263 | onenand_release_device(mtd); | |
1264 | ||
1265 | *retlen = written; | |
d5c5e78a | 1266 | |
cd5f6346 KP |
1267 | return ret; |
1268 | } | |
1269 | ||
a5e7c7b4 AH |
1270 | /** |
1271 | * onenand_fill_auto_oob - [Internal] oob auto-placement transfer | |
1272 | * @param mtd MTD device structure | |
1273 | * @param oob_buf oob buffer | |
1274 | * @param buf source address | |
1275 | * @param column oob offset to write to | |
1276 | * @param thislen oob length to write | |
1277 | */ | |
1278 | static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf, | |
1279 | const u_char *buf, int column, int thislen) | |
1280 | { | |
1281 | struct onenand_chip *this = mtd->priv; | |
1282 | struct nand_oobfree *free; | |
1283 | int writecol = column; | |
1284 | int writeend = column + thislen; | |
1285 | int lastgap = 0; | |
ad286343 | 1286 | unsigned int i; |
a5e7c7b4 | 1287 | |
ad286343 KP |
1288 | free = this->ecclayout->oobfree; |
1289 | for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { | |
a5e7c7b4 AH |
1290 | if (writecol >= lastgap) |
1291 | writecol += free->offset - lastgap; | |
1292 | if (writeend >= lastgap) | |
1293 | writeend += free->offset - lastgap; | |
1294 | lastgap = free->offset + free->length; | |
1295 | } | |
ad286343 KP |
1296 | free = this->ecclayout->oobfree; |
1297 | for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { | |
a5e7c7b4 AH |
1298 | int free_end = free->offset + free->length; |
1299 | if (free->offset < writeend && free_end > writecol) { | |
1300 | int st = max_t(int,free->offset,writecol); | |
1301 | int ed = min_t(int,free_end,writeend); | |
1302 | int n = ed - st; | |
1303 | memcpy(oob_buf + st, buf, n); | |
1304 | buf += n; | |
c36c46d5 | 1305 | } else if (column == 0) |
5bc399e9 | 1306 | break; |
a5e7c7b4 AH |
1307 | } |
1308 | return 0; | |
1309 | } | |
1310 | ||
cd5f6346 | 1311 | /** |
8593fbc6 | 1312 | * onenand_do_write_oob - [Internal] OneNAND write out-of-band |
cd5f6346 KP |
1313 | * @param mtd MTD device structure |
1314 | * @param to offset to write to | |
1315 | * @param len number of bytes to write | |
1316 | * @param retlen pointer to variable to store the number of written bytes | |
1317 | * @param buf the data to write | |
a5e7c7b4 | 1318 | * @param mode operation mode |
cd5f6346 KP |
1319 | * |
1320 | * OneNAND write out-of-band | |
1321 | */ | |
8593fbc6 | 1322 | static int onenand_do_write_oob(struct mtd_info *mtd, loff_t to, size_t len, |
a5e7c7b4 | 1323 | size_t *retlen, const u_char *buf, mtd_oob_mode_t mode) |
cd5f6346 KP |
1324 | { |
1325 | struct onenand_chip *this = mtd->priv; | |
a5e7c7b4 | 1326 | int column, ret = 0, oobsize; |
cd5f6346 | 1327 | int written = 0; |
91014e9b | 1328 | u_char *oobbuf; |
cd5f6346 KP |
1329 | |
1330 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); | |
1331 | ||
1332 | /* Initialize retlen, in case of early exit */ | |
1333 | *retlen = 0; | |
1334 | ||
a5e7c7b4 AH |
1335 | if (mode == MTD_OOB_AUTO) |
1336 | oobsize = this->ecclayout->oobavail; | |
1337 | else | |
1338 | oobsize = mtd->oobsize; | |
1339 | ||
1340 | column = to & (mtd->oobsize - 1); | |
1341 | ||
1342 | if (unlikely(column >= oobsize)) { | |
211ac75f | 1343 | printk(KERN_ERR "onenand_write_oob: Attempted to start write outside oob\n"); |
a5e7c7b4 AH |
1344 | return -EINVAL; |
1345 | } | |
1346 | ||
52e4200a | 1347 | /* For compatibility with NAND: Do not allow write past end of page */ |
91014e9b | 1348 | if (unlikely(column + len > oobsize)) { |
211ac75f | 1349 | printk(KERN_ERR "onenand_write_oob: " |
52e4200a AH |
1350 | "Attempt to write past end of page\n"); |
1351 | return -EINVAL; | |
1352 | } | |
1353 | ||
a5e7c7b4 AH |
1354 | /* Do not allow reads past end of device */ |
1355 | if (unlikely(to >= mtd->size || | |
1356 | column + len > ((mtd->size >> this->page_shift) - | |
1357 | (to >> this->page_shift)) * oobsize)) { | |
211ac75f | 1358 | printk(KERN_ERR "onenand_write_oob: Attempted to write past end of device\n"); |
cd5f6346 KP |
1359 | return -EINVAL; |
1360 | } | |
1361 | ||
1362 | /* Grab the lock and see if the device is available */ | |
1363 | onenand_get_device(mtd, FL_WRITING); | |
1364 | ||
470bc844 | 1365 | oobbuf = this->oob_buf; |
91014e9b | 1366 | |
cd5f6346 KP |
1367 | /* Loop until all data write */ |
1368 | while (written < len) { | |
a5e7c7b4 | 1369 | int thislen = min_t(int, oobsize, len - written); |
cd5f6346 | 1370 | |
61a7e198 AB |
1371 | cond_resched(); |
1372 | ||
cd5f6346 KP |
1373 | this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize); |
1374 | ||
34c10609 KP |
1375 | /* We send data to spare ram with oobsize |
1376 | * to prevent byte access */ | |
91014e9b | 1377 | memset(oobbuf, 0xff, mtd->oobsize); |
a5e7c7b4 | 1378 | if (mode == MTD_OOB_AUTO) |
91014e9b | 1379 | onenand_fill_auto_oob(mtd, oobbuf, buf, column, thislen); |
a5e7c7b4 | 1380 | else |
91014e9b KP |
1381 | memcpy(oobbuf + column, buf, thislen); |
1382 | this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize); | |
cd5f6346 KP |
1383 | |
1384 | this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize); | |
1385 | ||
1386 | onenand_update_bufferram(mtd, to, 0); | |
1387 | ||
8e6ec690 KP |
1388 | ret = this->wait(mtd, FL_WRITING); |
1389 | if (ret) { | |
211ac75f | 1390 | printk(KERN_ERR "onenand_write_oob: write failed %d\n", ret); |
5b4246f1 | 1391 | break; |
8e6ec690 KP |
1392 | } |
1393 | ||
91014e9b | 1394 | ret = onenand_verify_oob(mtd, oobbuf, to); |
8e6ec690 | 1395 | if (ret) { |
211ac75f | 1396 | printk(KERN_ERR "onenand_write_oob: verify failed %d\n", ret); |
5b4246f1 | 1397 | break; |
8e6ec690 | 1398 | } |
cd5f6346 KP |
1399 | |
1400 | written += thislen; | |
cd5f6346 KP |
1401 | if (written == len) |
1402 | break; | |
1403 | ||
a5e7c7b4 | 1404 | to += mtd->writesize; |
cd5f6346 | 1405 | buf += thislen; |
a5e7c7b4 | 1406 | column = 0; |
cd5f6346 KP |
1407 | } |
1408 | ||
cd5f6346 KP |
1409 | /* Deselect and wake up anyone waiting on the device */ |
1410 | onenand_release_device(mtd); | |
1411 | ||
1412 | *retlen = written; | |
d5c5e78a | 1413 | |
8e6ec690 | 1414 | return ret; |
cd5f6346 KP |
1415 | } |
1416 | ||
8593fbc6 TG |
1417 | /** |
1418 | * onenand_write_oob - [MTD Interface] NAND write data and/or out-of-band | |
e3da8067 KP |
1419 | * @param mtd: MTD device structure |
1420 | * @param to: offset to write | |
1421 | * @param ops: oob operation description structure | |
8593fbc6 TG |
1422 | */ |
1423 | static int onenand_write_oob(struct mtd_info *mtd, loff_t to, | |
1424 | struct mtd_oob_ops *ops) | |
1425 | { | |
4f4fad27 | 1426 | switch (ops->mode) { |
a5e7c7b4 AH |
1427 | case MTD_OOB_PLACE: |
1428 | case MTD_OOB_AUTO: | |
1429 | break; | |
1430 | case MTD_OOB_RAW: | |
4f4fad27 | 1431 | /* Not implemented yet */ |
a5e7c7b4 AH |
1432 | default: |
1433 | return -EINVAL; | |
1434 | } | |
66a1e421 | 1435 | return onenand_do_write_oob(mtd, to + ops->ooboffs, ops->ooblen, |
a5e7c7b4 | 1436 | &ops->oobretlen, ops->oobbuf, ops->mode); |
8593fbc6 TG |
1437 | } |
1438 | ||
cdc00130 KP |
1439 | /** |
1440 | * onenand_block_checkbad - [GENERIC] Check if a block is marked bad | |
1441 | * @param mtd MTD device structure | |
1442 | * @param ofs offset from device start | |
1443 | * @param getchip 0, if the chip is already selected | |
1444 | * @param allowbbt 1, if its allowed to access the bbt area | |
1445 | * | |
1446 | * Check, if the block is bad. Either by reading the bad block table or | |
1447 | * calling of the scan function. | |
1448 | */ | |
1449 | static int onenand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip, int allowbbt) | |
1450 | { | |
1451 | struct onenand_chip *this = mtd->priv; | |
1452 | struct bbm_info *bbm = this->bbm; | |
1453 | ||
1454 | /* Return info from the table */ | |
1455 | return bbm->isbad_bbt(mtd, ofs, allowbbt); | |
1456 | } | |
1457 | ||
cd5f6346 KP |
1458 | /** |
1459 | * onenand_erase - [MTD Interface] erase block(s) | |
1460 | * @param mtd MTD device structure | |
1461 | * @param instr erase instruction | |
1462 | * | |
1463 | * Erase one ore more blocks | |
1464 | */ | |
1465 | static int onenand_erase(struct mtd_info *mtd, struct erase_info *instr) | |
1466 | { | |
1467 | struct onenand_chip *this = mtd->priv; | |
1468 | unsigned int block_size; | |
1469 | loff_t addr; | |
1470 | int len; | |
1471 | int ret = 0; | |
1472 | ||
1473 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_erase: start = 0x%08x, len = %i\n", (unsigned int) instr->addr, (unsigned int) instr->len); | |
1474 | ||
1475 | block_size = (1 << this->erase_shift); | |
1476 | ||
1477 | /* Start address must align on block boundary */ | |
1478 | if (unlikely(instr->addr & (block_size - 1))) { | |
211ac75f | 1479 | printk(KERN_ERR "onenand_erase: Unaligned address\n"); |
cd5f6346 KP |
1480 | return -EINVAL; |
1481 | } | |
1482 | ||
1483 | /* Length must align on block boundary */ | |
1484 | if (unlikely(instr->len & (block_size - 1))) { | |
211ac75f | 1485 | printk(KERN_ERR "onenand_erase: Length not block aligned\n"); |
cd5f6346 KP |
1486 | return -EINVAL; |
1487 | } | |
1488 | ||
1489 | /* Do not allow erase past end of device */ | |
1490 | if (unlikely((instr->len + instr->addr) > mtd->size)) { | |
211ac75f | 1491 | printk(KERN_ERR "onenand_erase: Erase past end of device\n"); |
cd5f6346 KP |
1492 | return -EINVAL; |
1493 | } | |
1494 | ||
1495 | instr->fail_addr = 0xffffffff; | |
1496 | ||
1497 | /* Grab the lock and see if the device is available */ | |
1498 | onenand_get_device(mtd, FL_ERASING); | |
1499 | ||
1500 | /* Loop throught the pages */ | |
1501 | len = instr->len; | |
1502 | addr = instr->addr; | |
1503 | ||
1504 | instr->state = MTD_ERASING; | |
1505 | ||
1506 | while (len) { | |
61a7e198 | 1507 | cond_resched(); |
cd5f6346 | 1508 | |
cdc00130 KP |
1509 | /* Check if we have a bad block, we do not erase bad blocks */ |
1510 | if (onenand_block_checkbad(mtd, addr, 0, 0)) { | |
1511 | printk (KERN_WARNING "onenand_erase: attempt to erase a bad block at addr 0x%08x\n", (unsigned int) addr); | |
1512 | instr->state = MTD_ERASE_FAILED; | |
1513 | goto erase_exit; | |
1514 | } | |
cd5f6346 KP |
1515 | |
1516 | this->command(mtd, ONENAND_CMD_ERASE, addr, block_size); | |
1517 | ||
480b9dfb AH |
1518 | onenand_invalidate_bufferram(mtd, addr, block_size); |
1519 | ||
cd5f6346 KP |
1520 | ret = this->wait(mtd, FL_ERASING); |
1521 | /* Check, if it is write protected */ | |
1522 | if (ret) { | |
211ac75f | 1523 | printk(KERN_ERR "onenand_erase: Failed erase, block %d\n", (unsigned) (addr >> this->erase_shift)); |
cd5f6346 KP |
1524 | instr->state = MTD_ERASE_FAILED; |
1525 | instr->fail_addr = addr; | |
1526 | goto erase_exit; | |
1527 | } | |
1528 | ||
1529 | len -= block_size; | |
1530 | addr += block_size; | |
1531 | } | |
1532 | ||
1533 | instr->state = MTD_ERASE_DONE; | |
1534 | ||
1535 | erase_exit: | |
1536 | ||
1537 | ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO; | |
1538 | /* Do call back function */ | |
1539 | if (!ret) | |
1540 | mtd_erase_callback(instr); | |
1541 | ||
1542 | /* Deselect and wake up anyone waiting on the device */ | |
1543 | onenand_release_device(mtd); | |
1544 | ||
1545 | return ret; | |
1546 | } | |
1547 | ||
1548 | /** | |
1549 | * onenand_sync - [MTD Interface] sync | |
1550 | * @param mtd MTD device structure | |
1551 | * | |
1552 | * Sync is actually a wait for chip ready function | |
1553 | */ | |
1554 | static void onenand_sync(struct mtd_info *mtd) | |
1555 | { | |
1556 | DEBUG(MTD_DEBUG_LEVEL3, "onenand_sync: called\n"); | |
1557 | ||
1558 | /* Grab the lock and see if the device is available */ | |
1559 | onenand_get_device(mtd, FL_SYNCING); | |
1560 | ||
1561 | /* Release it and go back */ | |
1562 | onenand_release_device(mtd); | |
1563 | } | |
1564 | ||
1565 | /** | |
1566 | * onenand_block_isbad - [MTD Interface] Check whether the block at the given offset is bad | |
1567 | * @param mtd MTD device structure | |
1568 | * @param ofs offset relative to mtd start | |
cdc00130 KP |
1569 | * |
1570 | * Check whether the block is bad | |
cd5f6346 KP |
1571 | */ |
1572 | static int onenand_block_isbad(struct mtd_info *mtd, loff_t ofs) | |
1573 | { | |
cdc00130 KP |
1574 | /* Check for invalid offset */ |
1575 | if (ofs > mtd->size) | |
1576 | return -EINVAL; | |
1577 | ||
1578 | return onenand_block_checkbad(mtd, ofs, 1, 0); | |
1579 | } | |
1580 | ||
1581 | /** | |
1582 | * onenand_default_block_markbad - [DEFAULT] mark a block bad | |
1583 | * @param mtd MTD device structure | |
1584 | * @param ofs offset from device start | |
1585 | * | |
1586 | * This is the default implementation, which can be overridden by | |
1587 | * a hardware specific driver. | |
1588 | */ | |
1589 | static int onenand_default_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
1590 | { | |
1591 | struct onenand_chip *this = mtd->priv; | |
1592 | struct bbm_info *bbm = this->bbm; | |
1593 | u_char buf[2] = {0, 0}; | |
1594 | size_t retlen; | |
1595 | int block; | |
1596 | ||
1597 | /* Get block number */ | |
1598 | block = ((int) ofs) >> bbm->bbt_erase_shift; | |
1599 | if (bbm->bbt) | |
1600 | bbm->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1); | |
1601 | ||
1602 | /* We write two bytes, so we dont have to mess with 16 bit access */ | |
1603 | ofs += mtd->oobsize + (bbm->badblockpos & ~0x01); | |
a5e7c7b4 | 1604 | return onenand_do_write_oob(mtd, ofs , 2, &retlen, buf, MTD_OOB_PLACE); |
cd5f6346 KP |
1605 | } |
1606 | ||
1607 | /** | |
1608 | * onenand_block_markbad - [MTD Interface] Mark the block at the given offset as bad | |
1609 | * @param mtd MTD device structure | |
1610 | * @param ofs offset relative to mtd start | |
cdc00130 KP |
1611 | * |
1612 | * Mark the block as bad | |
cd5f6346 KP |
1613 | */ |
1614 | static int onenand_block_markbad(struct mtd_info *mtd, loff_t ofs) | |
1615 | { | |
cdc00130 KP |
1616 | struct onenand_chip *this = mtd->priv; |
1617 | int ret; | |
1618 | ||
1619 | ret = onenand_block_isbad(mtd, ofs); | |
1620 | if (ret) { | |
1621 | /* If it was bad already, return success and do nothing */ | |
1622 | if (ret > 0) | |
1623 | return 0; | |
1624 | return ret; | |
1625 | } | |
1626 | ||
1627 | return this->block_markbad(mtd, ofs); | |
cd5f6346 KP |
1628 | } |
1629 | ||
1630 | /** | |
08f782b6 | 1631 | * onenand_do_lock_cmd - [OneNAND Interface] Lock or unlock block(s) |
cd5f6346 KP |
1632 | * @param mtd MTD device structure |
1633 | * @param ofs offset relative to mtd start | |
08f782b6 | 1634 | * @param len number of bytes to lock or unlock |
e3da8067 | 1635 | * @param cmd lock or unlock command |
cd5f6346 | 1636 | * |
08f782b6 | 1637 | * Lock or unlock one or more blocks |
cd5f6346 | 1638 | */ |
08f782b6 | 1639 | static int onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs, size_t len, int cmd) |
cd5f6346 KP |
1640 | { |
1641 | struct onenand_chip *this = mtd->priv; | |
1642 | int start, end, block, value, status; | |
08f782b6 | 1643 | int wp_status_mask; |
cd5f6346 KP |
1644 | |
1645 | start = ofs >> this->erase_shift; | |
1646 | end = len >> this->erase_shift; | |
1647 | ||
08f782b6 KP |
1648 | if (cmd == ONENAND_CMD_LOCK) |
1649 | wp_status_mask = ONENAND_WP_LS; | |
1650 | else | |
1651 | wp_status_mask = ONENAND_WP_US; | |
1652 | ||
cd5f6346 | 1653 | /* Continuous lock scheme */ |
28b79ff9 | 1654 | if (this->options & ONENAND_HAS_CONT_LOCK) { |
cd5f6346 KP |
1655 | /* Set start block address */ |
1656 | this->write_word(start, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
1657 | /* Set end block address */ | |
28b79ff9 | 1658 | this->write_word(start + end - 1, this->base + ONENAND_REG_END_BLOCK_ADDRESS); |
08f782b6 KP |
1659 | /* Write lock command */ |
1660 | this->command(mtd, cmd, 0, 0); | |
cd5f6346 KP |
1661 | |
1662 | /* There's no return value */ | |
08f782b6 | 1663 | this->wait(mtd, FL_LOCKING); |
cd5f6346 KP |
1664 | |
1665 | /* Sanity check */ | |
1666 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1667 | & ONENAND_CTRL_ONGO) | |
1668 | continue; | |
1669 | ||
1670 | /* Check lock status */ | |
1671 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
08f782b6 | 1672 | if (!(status & wp_status_mask)) |
cd5f6346 KP |
1673 | printk(KERN_ERR "wp status = 0x%x\n", status); |
1674 | ||
1675 | return 0; | |
1676 | } | |
1677 | ||
1678 | /* Block lock scheme */ | |
28b79ff9 | 1679 | for (block = start; block < start + end; block++) { |
20ba89a3 KP |
1680 | /* Set block address */ |
1681 | value = onenand_block_address(this, block); | |
1682 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); | |
1683 | /* Select DataRAM for DDP */ | |
1684 | value = onenand_bufferram_address(this, block); | |
1685 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
cd5f6346 KP |
1686 | /* Set start block address */ |
1687 | this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
08f782b6 KP |
1688 | /* Write lock command */ |
1689 | this->command(mtd, cmd, 0, 0); | |
cd5f6346 KP |
1690 | |
1691 | /* There's no return value */ | |
08f782b6 | 1692 | this->wait(mtd, FL_LOCKING); |
cd5f6346 KP |
1693 | |
1694 | /* Sanity check */ | |
1695 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1696 | & ONENAND_CTRL_ONGO) | |
1697 | continue; | |
1698 | ||
cd5f6346 KP |
1699 | /* Check lock status */ |
1700 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
08f782b6 | 1701 | if (!(status & wp_status_mask)) |
cd5f6346 KP |
1702 | printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status); |
1703 | } | |
d5c5e78a | 1704 | |
cd5f6346 KP |
1705 | return 0; |
1706 | } | |
1707 | ||
08f782b6 KP |
1708 | /** |
1709 | * onenand_lock - [MTD Interface] Lock block(s) | |
1710 | * @param mtd MTD device structure | |
1711 | * @param ofs offset relative to mtd start | |
1712 | * @param len number of bytes to unlock | |
1713 | * | |
1714 | * Lock one or more blocks | |
1715 | */ | |
1716 | static int onenand_lock(struct mtd_info *mtd, loff_t ofs, size_t len) | |
1717 | { | |
1718 | return onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_LOCK); | |
1719 | } | |
1720 | ||
08f782b6 KP |
1721 | /** |
1722 | * onenand_unlock - [MTD Interface] Unlock block(s) | |
1723 | * @param mtd MTD device structure | |
1724 | * @param ofs offset relative to mtd start | |
1725 | * @param len number of bytes to unlock | |
1726 | * | |
1727 | * Unlock one or more blocks | |
1728 | */ | |
1729 | static int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len) | |
1730 | { | |
1731 | return onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK); | |
1732 | } | |
1733 | ||
28b79ff9 KP |
1734 | /** |
1735 | * onenand_check_lock_status - [OneNAND Interface] Check lock status | |
1736 | * @param this onenand chip data structure | |
1737 | * | |
1738 | * Check lock status | |
1739 | */ | |
1740 | static void onenand_check_lock_status(struct onenand_chip *this) | |
1741 | { | |
1742 | unsigned int value, block, status; | |
1743 | unsigned int end; | |
1744 | ||
1745 | end = this->chipsize >> this->erase_shift; | |
1746 | for (block = 0; block < end; block++) { | |
1747 | /* Set block address */ | |
1748 | value = onenand_block_address(this, block); | |
1749 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS1); | |
1750 | /* Select DataRAM for DDP */ | |
1751 | value = onenand_bufferram_address(this, block); | |
1752 | this->write_word(value, this->base + ONENAND_REG_START_ADDRESS2); | |
1753 | /* Set start block address */ | |
1754 | this->write_word(block, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
1755 | ||
1756 | /* Check lock status */ | |
1757 | status = this->read_word(this->base + ONENAND_REG_WP_STATUS); | |
1758 | if (!(status & ONENAND_WP_US)) | |
1759 | printk(KERN_ERR "block = %d, wp status = 0x%x\n", block, status); | |
1760 | } | |
1761 | } | |
1762 | ||
1763 | /** | |
1764 | * onenand_unlock_all - [OneNAND Interface] unlock all blocks | |
1765 | * @param mtd MTD device structure | |
1766 | * | |
1767 | * Unlock all blocks | |
1768 | */ | |
1769 | static int onenand_unlock_all(struct mtd_info *mtd) | |
1770 | { | |
1771 | struct onenand_chip *this = mtd->priv; | |
1772 | ||
1773 | if (this->options & ONENAND_HAS_UNLOCK_ALL) { | |
10b7a2bd KP |
1774 | /* Set start block address */ |
1775 | this->write_word(0, this->base + ONENAND_REG_START_BLOCK_ADDRESS); | |
28b79ff9 KP |
1776 | /* Write unlock command */ |
1777 | this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0); | |
1778 | ||
1779 | /* There's no return value */ | |
08f782b6 | 1780 | this->wait(mtd, FL_LOCKING); |
28b79ff9 KP |
1781 | |
1782 | /* Sanity check */ | |
1783 | while (this->read_word(this->base + ONENAND_REG_CTRL_STATUS) | |
1784 | & ONENAND_CTRL_ONGO) | |
1785 | continue; | |
1786 | ||
1787 | /* Workaround for all block unlock in DDP */ | |
738d61f5 | 1788 | if (ONENAND_IS_DDP(this)) { |
28b79ff9 | 1789 | /* 1st block on another chip */ |
10b7a2bd KP |
1790 | loff_t ofs = this->chipsize >> 1; |
1791 | size_t len = mtd->erasesize; | |
28b79ff9 KP |
1792 | |
1793 | onenand_unlock(mtd, ofs, len); | |
1794 | } | |
1795 | ||
1796 | onenand_check_lock_status(this); | |
1797 | ||
1798 | return 0; | |
1799 | } | |
1800 | ||
08f782b6 | 1801 | onenand_unlock(mtd, 0x0, this->chipsize); |
28b79ff9 KP |
1802 | |
1803 | return 0; | |
1804 | } | |
1805 | ||
493c6460 KP |
1806 | #ifdef CONFIG_MTD_ONENAND_OTP |
1807 | ||
1808 | /* Interal OTP operation */ | |
1809 | typedef int (*otp_op_t)(struct mtd_info *mtd, loff_t form, size_t len, | |
1810 | size_t *retlen, u_char *buf); | |
1811 | ||
1812 | /** | |
1813 | * do_otp_read - [DEFAULT] Read OTP block area | |
1814 | * @param mtd MTD device structure | |
1815 | * @param from The offset to read | |
1816 | * @param len number of bytes to read | |
1817 | * @param retlen pointer to variable to store the number of readbytes | |
1818 | * @param buf the databuffer to put/get data | |
1819 | * | |
1820 | * Read OTP block area. | |
1821 | */ | |
1822 | static int do_otp_read(struct mtd_info *mtd, loff_t from, size_t len, | |
1823 | size_t *retlen, u_char *buf) | |
1824 | { | |
1825 | struct onenand_chip *this = mtd->priv; | |
1826 | int ret; | |
1827 | ||
1828 | /* Enter OTP access mode */ | |
1829 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1830 | this->wait(mtd, FL_OTPING); | |
1831 | ||
1832 | ret = mtd->read(mtd, from, len, retlen, buf); | |
1833 | ||
1834 | /* Exit OTP access mode */ | |
1835 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1836 | this->wait(mtd, FL_RESETING); | |
1837 | ||
1838 | return ret; | |
1839 | } | |
1840 | ||
1841 | /** | |
1842 | * do_otp_write - [DEFAULT] Write OTP block area | |
1843 | * @param mtd MTD device structure | |
1844 | * @param from The offset to write | |
1845 | * @param len number of bytes to write | |
1846 | * @param retlen pointer to variable to store the number of write bytes | |
1847 | * @param buf the databuffer to put/get data | |
1848 | * | |
1849 | * Write OTP block area. | |
1850 | */ | |
1851 | static int do_otp_write(struct mtd_info *mtd, loff_t from, size_t len, | |
1852 | size_t *retlen, u_char *buf) | |
1853 | { | |
1854 | struct onenand_chip *this = mtd->priv; | |
1855 | unsigned char *pbuf = buf; | |
1856 | int ret; | |
1857 | ||
1858 | /* Force buffer page aligned */ | |
28318776 | 1859 | if (len < mtd->writesize) { |
493c6460 | 1860 | memcpy(this->page_buf, buf, len); |
28318776 | 1861 | memset(this->page_buf + len, 0xff, mtd->writesize - len); |
493c6460 | 1862 | pbuf = this->page_buf; |
28318776 | 1863 | len = mtd->writesize; |
493c6460 KP |
1864 | } |
1865 | ||
1866 | /* Enter OTP access mode */ | |
1867 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1868 | this->wait(mtd, FL_OTPING); | |
1869 | ||
1870 | ret = mtd->write(mtd, from, len, retlen, pbuf); | |
1871 | ||
1872 | /* Exit OTP access mode */ | |
1873 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1874 | this->wait(mtd, FL_RESETING); | |
1875 | ||
1876 | return ret; | |
1877 | } | |
1878 | ||
1879 | /** | |
1880 | * do_otp_lock - [DEFAULT] Lock OTP block area | |
1881 | * @param mtd MTD device structure | |
1882 | * @param from The offset to lock | |
1883 | * @param len number of bytes to lock | |
1884 | * @param retlen pointer to variable to store the number of lock bytes | |
1885 | * @param buf the databuffer to put/get data | |
1886 | * | |
1887 | * Lock OTP block area. | |
1888 | */ | |
1889 | static int do_otp_lock(struct mtd_info *mtd, loff_t from, size_t len, | |
1890 | size_t *retlen, u_char *buf) | |
1891 | { | |
1892 | struct onenand_chip *this = mtd->priv; | |
1893 | int ret; | |
1894 | ||
1895 | /* Enter OTP access mode */ | |
1896 | this->command(mtd, ONENAND_CMD_OTP_ACCESS, 0, 0); | |
1897 | this->wait(mtd, FL_OTPING); | |
1898 | ||
a5e7c7b4 | 1899 | ret = onenand_do_write_oob(mtd, from, len, retlen, buf, MTD_OOB_PLACE); |
493c6460 KP |
1900 | |
1901 | /* Exit OTP access mode */ | |
1902 | this->command(mtd, ONENAND_CMD_RESET, 0, 0); | |
1903 | this->wait(mtd, FL_RESETING); | |
1904 | ||
1905 | return ret; | |
1906 | } | |
1907 | ||
1908 | /** | |
1909 | * onenand_otp_walk - [DEFAULT] Handle OTP operation | |
1910 | * @param mtd MTD device structure | |
1911 | * @param from The offset to read/write | |
1912 | * @param len number of bytes to read/write | |
1913 | * @param retlen pointer to variable to store the number of read bytes | |
1914 | * @param buf the databuffer to put/get data | |
1915 | * @param action do given action | |
1916 | * @param mode specify user and factory | |
1917 | * | |
1918 | * Handle OTP operation. | |
1919 | */ | |
1920 | static int onenand_otp_walk(struct mtd_info *mtd, loff_t from, size_t len, | |
1921 | size_t *retlen, u_char *buf, | |
1922 | otp_op_t action, int mode) | |
1923 | { | |
1924 | struct onenand_chip *this = mtd->priv; | |
1925 | int otp_pages; | |
1926 | int density; | |
1927 | int ret = 0; | |
1928 | ||
1929 | *retlen = 0; | |
1930 | ||
1931 | density = this->device_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
1932 | if (density < ONENAND_DEVICE_DENSITY_512Mb) | |
1933 | otp_pages = 20; | |
1934 | else | |
1935 | otp_pages = 10; | |
1936 | ||
1937 | if (mode == MTD_OTP_FACTORY) { | |
28318776 | 1938 | from += mtd->writesize * otp_pages; |
493c6460 KP |
1939 | otp_pages = 64 - otp_pages; |
1940 | } | |
1941 | ||
1942 | /* Check User/Factory boundary */ | |
28318776 | 1943 | if (((mtd->writesize * otp_pages) - (from + len)) < 0) |
493c6460 KP |
1944 | return 0; |
1945 | ||
1946 | while (len > 0 && otp_pages > 0) { | |
1947 | if (!action) { /* OTP Info functions */ | |
1948 | struct otp_info *otpinfo; | |
1949 | ||
1950 | len -= sizeof(struct otp_info); | |
1951 | if (len <= 0) | |
1952 | return -ENOSPC; | |
1953 | ||
1954 | otpinfo = (struct otp_info *) buf; | |
1955 | otpinfo->start = from; | |
28318776 | 1956 | otpinfo->length = mtd->writesize; |
493c6460 KP |
1957 | otpinfo->locked = 0; |
1958 | ||
28318776 | 1959 | from += mtd->writesize; |
493c6460 KP |
1960 | buf += sizeof(struct otp_info); |
1961 | *retlen += sizeof(struct otp_info); | |
1962 | } else { | |
1963 | size_t tmp_retlen; | |
1964 | int size = len; | |
1965 | ||
1966 | ret = action(mtd, from, len, &tmp_retlen, buf); | |
1967 | ||
1968 | buf += size; | |
1969 | len -= size; | |
1970 | *retlen += size; | |
1971 | ||
1972 | if (ret < 0) | |
1973 | return ret; | |
1974 | } | |
1975 | otp_pages--; | |
1976 | } | |
1977 | ||
1978 | return 0; | |
1979 | } | |
1980 | ||
1981 | /** | |
1982 | * onenand_get_fact_prot_info - [MTD Interface] Read factory OTP info | |
1983 | * @param mtd MTD device structure | |
1984 | * @param buf the databuffer to put/get data | |
1985 | * @param len number of bytes to read | |
1986 | * | |
1987 | * Read factory OTP info. | |
1988 | */ | |
1989 | static int onenand_get_fact_prot_info(struct mtd_info *mtd, | |
1990 | struct otp_info *buf, size_t len) | |
1991 | { | |
1992 | size_t retlen; | |
1993 | int ret; | |
1994 | ||
1995 | ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_FACTORY); | |
1996 | ||
1997 | return ret ? : retlen; | |
1998 | } | |
1999 | ||
2000 | /** | |
2001 | * onenand_read_fact_prot_reg - [MTD Interface] Read factory OTP area | |
2002 | * @param mtd MTD device structure | |
2003 | * @param from The offset to read | |
2004 | * @param len number of bytes to read | |
2005 | * @param retlen pointer to variable to store the number of read bytes | |
2006 | * @param buf the databuffer to put/get data | |
2007 | * | |
2008 | * Read factory OTP area. | |
2009 | */ | |
2010 | static int onenand_read_fact_prot_reg(struct mtd_info *mtd, loff_t from, | |
2011 | size_t len, size_t *retlen, u_char *buf) | |
2012 | { | |
2013 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_FACTORY); | |
2014 | } | |
2015 | ||
2016 | /** | |
2017 | * onenand_get_user_prot_info - [MTD Interface] Read user OTP info | |
2018 | * @param mtd MTD device structure | |
2019 | * @param buf the databuffer to put/get data | |
2020 | * @param len number of bytes to read | |
2021 | * | |
2022 | * Read user OTP info. | |
2023 | */ | |
2024 | static int onenand_get_user_prot_info(struct mtd_info *mtd, | |
2025 | struct otp_info *buf, size_t len) | |
2026 | { | |
2027 | size_t retlen; | |
2028 | int ret; | |
2029 | ||
2030 | ret = onenand_otp_walk(mtd, 0, len, &retlen, (u_char *) buf, NULL, MTD_OTP_USER); | |
2031 | ||
2032 | return ret ? : retlen; | |
2033 | } | |
2034 | ||
2035 | /** | |
2036 | * onenand_read_user_prot_reg - [MTD Interface] Read user OTP area | |
2037 | * @param mtd MTD device structure | |
2038 | * @param from The offset to read | |
2039 | * @param len number of bytes to read | |
2040 | * @param retlen pointer to variable to store the number of read bytes | |
2041 | * @param buf the databuffer to put/get data | |
2042 | * | |
2043 | * Read user OTP area. | |
2044 | */ | |
2045 | static int onenand_read_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
2046 | size_t len, size_t *retlen, u_char *buf) | |
2047 | { | |
2048 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_read, MTD_OTP_USER); | |
2049 | } | |
2050 | ||
2051 | /** | |
2052 | * onenand_write_user_prot_reg - [MTD Interface] Write user OTP area | |
2053 | * @param mtd MTD device structure | |
2054 | * @param from The offset to write | |
2055 | * @param len number of bytes to write | |
2056 | * @param retlen pointer to variable to store the number of write bytes | |
2057 | * @param buf the databuffer to put/get data | |
2058 | * | |
2059 | * Write user OTP area. | |
2060 | */ | |
2061 | static int onenand_write_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
2062 | size_t len, size_t *retlen, u_char *buf) | |
2063 | { | |
2064 | return onenand_otp_walk(mtd, from, len, retlen, buf, do_otp_write, MTD_OTP_USER); | |
2065 | } | |
2066 | ||
2067 | /** | |
2068 | * onenand_lock_user_prot_reg - [MTD Interface] Lock user OTP area | |
2069 | * @param mtd MTD device structure | |
2070 | * @param from The offset to lock | |
2071 | * @param len number of bytes to unlock | |
2072 | * | |
2073 | * Write lock mark on spare area in page 0 in OTP block | |
2074 | */ | |
2075 | static int onenand_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, | |
2076 | size_t len) | |
2077 | { | |
2078 | unsigned char oob_buf[64]; | |
2079 | size_t retlen; | |
2080 | int ret; | |
2081 | ||
2082 | memset(oob_buf, 0xff, mtd->oobsize); | |
2083 | /* | |
2084 | * Note: OTP lock operation | |
2085 | * OTP block : 0xXXFC | |
2086 | * 1st block : 0xXXF3 (If chip support) | |
2087 | * Both : 0xXXF0 (If chip support) | |
2088 | */ | |
2089 | oob_buf[ONENAND_OTP_LOCK_OFFSET] = 0xFC; | |
2090 | ||
2091 | /* | |
2092 | * Write lock mark to 8th word of sector0 of page0 of the spare0. | |
2093 | * We write 16 bytes spare area instead of 2 bytes. | |
2094 | */ | |
2095 | from = 0; | |
2096 | len = 16; | |
2097 | ||
2098 | ret = onenand_otp_walk(mtd, from, len, &retlen, oob_buf, do_otp_lock, MTD_OTP_USER); | |
2099 | ||
2100 | return ret ? : retlen; | |
2101 | } | |
2102 | #endif /* CONFIG_MTD_ONENAND_OTP */ | |
2103 | ||
28b79ff9 | 2104 | /** |
75384b0d | 2105 | * onenand_check_features - Check and set OneNAND features |
28b79ff9 KP |
2106 | * @param mtd MTD data structure |
2107 | * | |
75384b0d KP |
2108 | * Check and set OneNAND features |
2109 | * - lock scheme | |
28b79ff9 | 2110 | */ |
75384b0d | 2111 | static void onenand_check_features(struct mtd_info *mtd) |
28b79ff9 KP |
2112 | { |
2113 | struct onenand_chip *this = mtd->priv; | |
2114 | unsigned int density, process; | |
2115 | ||
2116 | /* Lock scheme depends on density and process */ | |
2117 | density = this->device_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
2118 | process = this->version_id >> ONENAND_VERSION_PROCESS_SHIFT; | |
2119 | ||
2120 | /* Lock scheme */ | |
2121 | if (density >= ONENAND_DEVICE_DENSITY_1Gb) { | |
2122 | /* A-Die has all block unlock */ | |
2123 | if (process) { | |
2124 | printk(KERN_DEBUG "Chip support all block unlock\n"); | |
2125 | this->options |= ONENAND_HAS_UNLOCK_ALL; | |
2126 | } | |
2127 | } else { | |
2128 | /* Some OneNAND has continues lock scheme */ | |
2129 | if (!process) { | |
2130 | printk(KERN_DEBUG "Lock scheme is Continues Lock\n"); | |
2131 | this->options |= ONENAND_HAS_CONT_LOCK; | |
2132 | } | |
2133 | } | |
2134 | } | |
2135 | ||
cd5f6346 | 2136 | /** |
e3da8067 | 2137 | * onenand_print_device_info - Print device & version ID |
cd5f6346 | 2138 | * @param device device ID |
e3da8067 | 2139 | * @param version version ID |
cd5f6346 | 2140 | * |
e3da8067 | 2141 | * Print device & version ID |
cd5f6346 | 2142 | */ |
28b79ff9 | 2143 | static void onenand_print_device_info(int device, int version) |
cd5f6346 KP |
2144 | { |
2145 | int vcc, demuxed, ddp, density; | |
2146 | ||
2147 | vcc = device & ONENAND_DEVICE_VCC_MASK; | |
2148 | demuxed = device & ONENAND_DEVICE_IS_DEMUX; | |
2149 | ddp = device & ONENAND_DEVICE_IS_DDP; | |
2150 | density = device >> ONENAND_DEVICE_DENSITY_SHIFT; | |
2151 | printk(KERN_INFO "%sOneNAND%s %dMB %sV 16-bit (0x%02x)\n", | |
2152 | demuxed ? "" : "Muxed ", | |
2153 | ddp ? "(DDP)" : "", | |
2154 | (16 << density), | |
2155 | vcc ? "2.65/3.3" : "1.8", | |
2156 | device); | |
28b79ff9 | 2157 | printk(KERN_DEBUG "OneNAND version = 0x%04x\n", version); |
cd5f6346 KP |
2158 | } |
2159 | ||
2160 | static const struct onenand_manufacturers onenand_manuf_ids[] = { | |
2161 | {ONENAND_MFR_SAMSUNG, "Samsung"}, | |
cd5f6346 KP |
2162 | }; |
2163 | ||
2164 | /** | |
2165 | * onenand_check_maf - Check manufacturer ID | |
2166 | * @param manuf manufacturer ID | |
2167 | * | |
2168 | * Check manufacturer ID | |
2169 | */ | |
2170 | static int onenand_check_maf(int manuf) | |
2171 | { | |
37b1cc39 KP |
2172 | int size = ARRAY_SIZE(onenand_manuf_ids); |
2173 | char *name; | |
cd5f6346 KP |
2174 | int i; |
2175 | ||
37b1cc39 | 2176 | for (i = 0; i < size; i++) |
cd5f6346 KP |
2177 | if (manuf == onenand_manuf_ids[i].id) |
2178 | break; | |
cd5f6346 | 2179 | |
37b1cc39 KP |
2180 | if (i < size) |
2181 | name = onenand_manuf_ids[i].name; | |
2182 | else | |
2183 | name = "Unknown"; | |
2184 | ||
2185 | printk(KERN_DEBUG "OneNAND Manufacturer: %s (0x%0x)\n", name, manuf); | |
cd5f6346 | 2186 | |
37b1cc39 | 2187 | return (i == size); |
cd5f6346 KP |
2188 | } |
2189 | ||
2190 | /** | |
2191 | * onenand_probe - [OneNAND Interface] Probe the OneNAND device | |
2192 | * @param mtd MTD device structure | |
2193 | * | |
2194 | * OneNAND detection method: | |
2195 | * Compare the the values from command with ones from register | |
2196 | */ | |
2197 | static int onenand_probe(struct mtd_info *mtd) | |
2198 | { | |
2199 | struct onenand_chip *this = mtd->priv; | |
28b79ff9 | 2200 | int bram_maf_id, bram_dev_id, maf_id, dev_id, ver_id; |
cd5f6346 | 2201 | int density; |
47e777e0 KP |
2202 | int syscfg; |
2203 | ||
2204 | /* Save system configuration 1 */ | |
2205 | syscfg = this->read_word(this->base + ONENAND_REG_SYS_CFG1); | |
2206 | /* Clear Sync. Burst Read mode to read BootRAM */ | |
2207 | this->write_word((syscfg & ~ONENAND_SYS_CFG1_SYNC_READ), this->base + ONENAND_REG_SYS_CFG1); | |
cd5f6346 KP |
2208 | |
2209 | /* Send the command for reading device ID from BootRAM */ | |
2210 | this->write_word(ONENAND_CMD_READID, this->base + ONENAND_BOOTRAM); | |
2211 | ||
2212 | /* Read manufacturer and device IDs from BootRAM */ | |
2213 | bram_maf_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x0); | |
2214 | bram_dev_id = this->read_word(this->base + ONENAND_BOOTRAM + 0x2); | |
2215 | ||
47e777e0 KP |
2216 | /* Reset OneNAND to read default register values */ |
2217 | this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM); | |
2218 | /* Wait reset */ | |
2219 | this->wait(mtd, FL_RESETING); | |
2220 | ||
2221 | /* Restore system configuration 1 */ | |
2222 | this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); | |
2223 | ||
cd5f6346 KP |
2224 | /* Check manufacturer ID */ |
2225 | if (onenand_check_maf(bram_maf_id)) | |
2226 | return -ENXIO; | |
2227 | ||
cd5f6346 KP |
2228 | /* Read manufacturer and device IDs from Register */ |
2229 | maf_id = this->read_word(this->base + ONENAND_REG_MANUFACTURER_ID); | |
2230 | dev_id = this->read_word(this->base + ONENAND_REG_DEVICE_ID); | |
f4f91ac3 | 2231 | ver_id = this->read_word(this->base + ONENAND_REG_VERSION_ID); |
cd5f6346 KP |
2232 | |
2233 | /* Check OneNAND device */ | |
2234 | if (maf_id != bram_maf_id || dev_id != bram_dev_id) | |
2235 | return -ENXIO; | |
2236 | ||
2237 | /* Flash device information */ | |
28b79ff9 | 2238 | onenand_print_device_info(dev_id, ver_id); |
cd5f6346 | 2239 | this->device_id = dev_id; |
28b79ff9 | 2240 | this->version_id = ver_id; |
cd5f6346 KP |
2241 | |
2242 | density = dev_id >> ONENAND_DEVICE_DENSITY_SHIFT; | |
2243 | this->chipsize = (16 << density) << 20; | |
83a36838 | 2244 | /* Set density mask. it is used for DDP */ |
738d61f5 KP |
2245 | if (ONENAND_IS_DDP(this)) |
2246 | this->density_mask = (1 << (density + 6)); | |
2247 | else | |
2248 | this->density_mask = 0; | |
cd5f6346 KP |
2249 | |
2250 | /* OneNAND page size & block size */ | |
2251 | /* The data buffer size is equal to page size */ | |
28318776 JE |
2252 | mtd->writesize = this->read_word(this->base + ONENAND_REG_DATA_BUFFER_SIZE); |
2253 | mtd->oobsize = mtd->writesize >> 5; | |
9bfbc9b2 | 2254 | /* Pages per a block are always 64 in OneNAND */ |
28318776 | 2255 | mtd->erasesize = mtd->writesize << 6; |
cd5f6346 KP |
2256 | |
2257 | this->erase_shift = ffs(mtd->erasesize) - 1; | |
28318776 | 2258 | this->page_shift = ffs(mtd->writesize) - 1; |
9bfbc9b2 | 2259 | this->page_mask = (1 << (this->erase_shift - this->page_shift)) - 1; |
cd5f6346 KP |
2260 | |
2261 | /* REVIST: Multichip handling */ | |
2262 | ||
2263 | mtd->size = this->chipsize; | |
2264 | ||
75384b0d KP |
2265 | /* Check OneNAND features */ |
2266 | onenand_check_features(mtd); | |
d5c5e78a | 2267 | |
cd5f6346 KP |
2268 | return 0; |
2269 | } | |
2270 | ||
a41371eb KP |
2271 | /** |
2272 | * onenand_suspend - [MTD Interface] Suspend the OneNAND flash | |
2273 | * @param mtd MTD device structure | |
2274 | */ | |
2275 | static int onenand_suspend(struct mtd_info *mtd) | |
2276 | { | |
2277 | return onenand_get_device(mtd, FL_PM_SUSPENDED); | |
2278 | } | |
2279 | ||
2280 | /** | |
2281 | * onenand_resume - [MTD Interface] Resume the OneNAND flash | |
2282 | * @param mtd MTD device structure | |
2283 | */ | |
2284 | static void onenand_resume(struct mtd_info *mtd) | |
2285 | { | |
2286 | struct onenand_chip *this = mtd->priv; | |
2287 | ||
2288 | if (this->state == FL_PM_SUSPENDED) | |
2289 | onenand_release_device(mtd); | |
2290 | else | |
2291 | printk(KERN_ERR "resume() called for the chip which is not" | |
2292 | "in suspended state\n"); | |
2293 | } | |
2294 | ||
cd5f6346 KP |
2295 | /** |
2296 | * onenand_scan - [OneNAND Interface] Scan for the OneNAND device | |
2297 | * @param mtd MTD device structure | |
2298 | * @param maxchips Number of chips to scan for | |
2299 | * | |
2300 | * This fills out all the not initialized function pointers | |
2301 | * with the defaults. | |
2302 | * The flash ID is read and the mtd/chip structures are | |
2303 | * filled with the appropriate values. | |
2304 | */ | |
2305 | int onenand_scan(struct mtd_info *mtd, int maxchips) | |
2306 | { | |
a5e7c7b4 | 2307 | int i; |
cd5f6346 KP |
2308 | struct onenand_chip *this = mtd->priv; |
2309 | ||
2310 | if (!this->read_word) | |
2311 | this->read_word = onenand_readw; | |
2312 | if (!this->write_word) | |
2313 | this->write_word = onenand_writew; | |
2314 | ||
2315 | if (!this->command) | |
2316 | this->command = onenand_command; | |
2317 | if (!this->wait) | |
2c22120f | 2318 | onenand_setup_wait(mtd); |
cd5f6346 KP |
2319 | |
2320 | if (!this->read_bufferram) | |
2321 | this->read_bufferram = onenand_read_bufferram; | |
2322 | if (!this->write_bufferram) | |
2323 | this->write_bufferram = onenand_write_bufferram; | |
2324 | ||
cdc00130 KP |
2325 | if (!this->block_markbad) |
2326 | this->block_markbad = onenand_default_block_markbad; | |
2327 | if (!this->scan_bbt) | |
2328 | this->scan_bbt = onenand_default_bbt; | |
2329 | ||
cd5f6346 KP |
2330 | if (onenand_probe(mtd)) |
2331 | return -ENXIO; | |
2332 | ||
52b0eea7 KP |
2333 | /* Set Sync. Burst Read after probing */ |
2334 | if (this->mmcontrol) { | |
2335 | printk(KERN_INFO "OneNAND Sync. Burst Read support\n"); | |
2336 | this->read_bufferram = onenand_sync_read_bufferram; | |
2337 | } | |
2338 | ||
532a37cf KP |
2339 | /* Allocate buffers, if necessary */ |
2340 | if (!this->page_buf) { | |
470bc844 | 2341 | this->page_buf = kzalloc(mtd->writesize, GFP_KERNEL); |
532a37cf KP |
2342 | if (!this->page_buf) { |
2343 | printk(KERN_ERR "onenand_scan(): Can't allocate page_buf\n"); | |
2344 | return -ENOMEM; | |
2345 | } | |
2346 | this->options |= ONENAND_PAGEBUF_ALLOC; | |
2347 | } | |
470bc844 KP |
2348 | if (!this->oob_buf) { |
2349 | this->oob_buf = kzalloc(mtd->oobsize, GFP_KERNEL); | |
2350 | if (!this->oob_buf) { | |
2351 | printk(KERN_ERR "onenand_scan(): Can't allocate oob_buf\n"); | |
2352 | if (this->options & ONENAND_PAGEBUF_ALLOC) { | |
2353 | this->options &= ~ONENAND_PAGEBUF_ALLOC; | |
2354 | kfree(this->page_buf); | |
2355 | } | |
2356 | return -ENOMEM; | |
2357 | } | |
2358 | this->options |= ONENAND_OOBBUF_ALLOC; | |
2359 | } | |
532a37cf | 2360 | |
cd5f6346 KP |
2361 | this->state = FL_READY; |
2362 | init_waitqueue_head(&this->wq); | |
2363 | spin_lock_init(&this->chip_lock); | |
2364 | ||
60d84f97 KP |
2365 | /* |
2366 | * Allow subpage writes up to oobsize. | |
2367 | */ | |
cd5f6346 KP |
2368 | switch (mtd->oobsize) { |
2369 | case 64: | |
5bd34c09 | 2370 | this->ecclayout = &onenand_oob_64; |
60d84f97 | 2371 | mtd->subpage_sft = 2; |
cd5f6346 KP |
2372 | break; |
2373 | ||
2374 | case 32: | |
5bd34c09 | 2375 | this->ecclayout = &onenand_oob_32; |
60d84f97 | 2376 | mtd->subpage_sft = 1; |
cd5f6346 KP |
2377 | break; |
2378 | ||
2379 | default: | |
2380 | printk(KERN_WARNING "No OOB scheme defined for oobsize %d\n", | |
2381 | mtd->oobsize); | |
60d84f97 | 2382 | mtd->subpage_sft = 0; |
cd5f6346 | 2383 | /* To prevent kernel oops */ |
5bd34c09 | 2384 | this->ecclayout = &onenand_oob_32; |
cd5f6346 KP |
2385 | break; |
2386 | } | |
2387 | ||
60d84f97 | 2388 | this->subpagesize = mtd->writesize >> mtd->subpage_sft; |
a5e7c7b4 AH |
2389 | |
2390 | /* | |
2391 | * The number of bytes available for a client to place data into | |
2392 | * the out of band area | |
2393 | */ | |
2394 | this->ecclayout->oobavail = 0; | |
ad286343 KP |
2395 | for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && |
2396 | this->ecclayout->oobfree[i].length; i++) | |
a5e7c7b4 AH |
2397 | this->ecclayout->oobavail += |
2398 | this->ecclayout->oobfree[i].length; | |
1f92267c | 2399 | mtd->oobavail = this->ecclayout->oobavail; |
a5e7c7b4 | 2400 | |
5bd34c09 | 2401 | mtd->ecclayout = this->ecclayout; |
d5c5e78a | 2402 | |
cd5f6346 KP |
2403 | /* Fill in remaining MTD driver data */ |
2404 | mtd->type = MTD_NANDFLASH; | |
5fa43394 | 2405 | mtd->flags = MTD_CAP_NANDFLASH; |
cd5f6346 KP |
2406 | mtd->erase = onenand_erase; |
2407 | mtd->point = NULL; | |
2408 | mtd->unpoint = NULL; | |
2409 | mtd->read = onenand_read; | |
2410 | mtd->write = onenand_write; | |
cd5f6346 KP |
2411 | mtd->read_oob = onenand_read_oob; |
2412 | mtd->write_oob = onenand_write_oob; | |
493c6460 KP |
2413 | #ifdef CONFIG_MTD_ONENAND_OTP |
2414 | mtd->get_fact_prot_info = onenand_get_fact_prot_info; | |
2415 | mtd->read_fact_prot_reg = onenand_read_fact_prot_reg; | |
2416 | mtd->get_user_prot_info = onenand_get_user_prot_info; | |
2417 | mtd->read_user_prot_reg = onenand_read_user_prot_reg; | |
2418 | mtd->write_user_prot_reg = onenand_write_user_prot_reg; | |
2419 | mtd->lock_user_prot_reg = onenand_lock_user_prot_reg; | |
2420 | #endif | |
cd5f6346 | 2421 | mtd->sync = onenand_sync; |
08f782b6 | 2422 | mtd->lock = onenand_lock; |
cd5f6346 | 2423 | mtd->unlock = onenand_unlock; |
a41371eb KP |
2424 | mtd->suspend = onenand_suspend; |
2425 | mtd->resume = onenand_resume; | |
cd5f6346 KP |
2426 | mtd->block_isbad = onenand_block_isbad; |
2427 | mtd->block_markbad = onenand_block_markbad; | |
2428 | mtd->owner = THIS_MODULE; | |
2429 | ||
2430 | /* Unlock whole block */ | |
28b79ff9 | 2431 | onenand_unlock_all(mtd); |
cd5f6346 | 2432 | |
cdc00130 | 2433 | return this->scan_bbt(mtd); |
cd5f6346 KP |
2434 | } |
2435 | ||
2436 | /** | |
2437 | * onenand_release - [OneNAND Interface] Free resources held by the OneNAND device | |
2438 | * @param mtd MTD device structure | |
2439 | */ | |
2440 | void onenand_release(struct mtd_info *mtd) | |
2441 | { | |
532a37cf KP |
2442 | struct onenand_chip *this = mtd->priv; |
2443 | ||
cd5f6346 KP |
2444 | #ifdef CONFIG_MTD_PARTITIONS |
2445 | /* Deregister partitions */ | |
2446 | del_mtd_partitions (mtd); | |
2447 | #endif | |
2448 | /* Deregister the device */ | |
2449 | del_mtd_device (mtd); | |
532a37cf KP |
2450 | |
2451 | /* Free bad block table memory, if allocated */ | |
f00b0046 AH |
2452 | if (this->bbm) { |
2453 | struct bbm_info *bbm = this->bbm; | |
2454 | kfree(bbm->bbt); | |
532a37cf | 2455 | kfree(this->bbm); |
f00b0046 | 2456 | } |
470bc844 | 2457 | /* Buffers allocated by onenand_scan */ |
532a37cf KP |
2458 | if (this->options & ONENAND_PAGEBUF_ALLOC) |
2459 | kfree(this->page_buf); | |
470bc844 KP |
2460 | if (this->options & ONENAND_OOBBUF_ALLOC) |
2461 | kfree(this->oob_buf); | |
cd5f6346 KP |
2462 | } |
2463 | ||
2464 | EXPORT_SYMBOL_GPL(onenand_scan); | |
2465 | EXPORT_SYMBOL_GPL(onenand_release); | |
2466 | ||
2467 | MODULE_LICENSE("GPL"); | |
2468 | MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>"); | |
2469 | MODULE_DESCRIPTION("Generic OneNAND flash driver code"); |