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Merge branch 'for-linus' of git://git.infradead.org/users/eparis/notify
[net-next-2.6.git] / drivers / mtd / nand / r852.c
CommitLineData
67e054e9
ML		 1/*
2 * Copyright © 2009 - Maxim Levitsky
3 * driver for Ricoh xD readers
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/jiffies.h>
13#include <linux/workqueue.h>
14#include <linux/interrupt.h>
f696aa43 15#include <linux/pci.h>
67e054e9 16#include <linux/pci_ids.h>
ada49657 17#include <linux/delay.h>
05d71b46 18#include <linux/slab.h>
67e054e9
ML		 19#include <asm/byteorder.h>
20#include <linux/sched.h>
21#include "sm_common.h"
22#include "r852.h"
23
24
ada49657
SR		 25static int r852_enable_dma = 1;
26module_param(r852_enable_dma, bool, S_IRUGO);
27MODULE_PARM_DESC(r852_enable_dma, "Enable usage of the DMA (default)");
67e054e9
ML		 28
29static int debug;
30module_param(debug, int, S_IRUGO | S_IWUSR);
31MODULE_PARM_DESC(debug, "Debug level (0-2)");
32
33/* read register */
34static inline uint8_t r852_read_reg(struct r852_device *dev, int address)
35{
36 uint8_t reg = readb(dev->mmio + address);
37 return reg;
38}
39
40/* write register */
41static inline void r852_write_reg(struct r852_device *dev,
42 int address, uint8_t value)
43{
44 writeb(value, dev->mmio + address);
45 mmiowb();
46}
47
48
49/* read dword sized register */
50static inline uint32_t r852_read_reg_dword(struct r852_device *dev, int address)
51{
52 uint32_t reg = le32_to_cpu(readl(dev->mmio + address));
53 return reg;
54}
55
56/* write dword sized register */
57static inline void r852_write_reg_dword(struct r852_device *dev,
58 int address, uint32_t value)
59{
60 writel(cpu_to_le32(value), dev->mmio + address);
61 mmiowb();
62}
63
64/* returns pointer to our private structure */
65static inline struct r852_device *r852_get_dev(struct mtd_info *mtd)
66{
d5af6dcf
KV		 67 struct nand_chip *chip = mtd->priv;
68 return chip->priv;
67e054e9
ML		 69}
70
71
72/* check if controller supports dma */
73static void r852_dma_test(struct r852_device *dev)
74{
75 dev->dma_usable = (r852_read_reg(dev, R852_DMA_CAP) &
76 (R852_DMA1 | R852_DMA2)) == (R852_DMA1 | R852_DMA2);
77
78 if (!dev->dma_usable)
79 message("Non dma capable device detected, dma disabled");
80
ada49657 81 if (!r852_enable_dma) {
67e054e9
ML		 82 message("disabling dma on user request");
83 dev->dma_usable = 0;
84 }
85}
86
87/*
88 * Enable dma. Enables ether first or second stage of the DMA,
89 * Expects dev->dma_dir and dev->dma_state be set
90 */
91static void r852_dma_enable(struct r852_device *dev)
92{
93 uint8_t dma_reg, dma_irq_reg;
94
95 /* Set up dma settings */
96 dma_reg = r852_read_reg_dword(dev, R852_DMA_SETTINGS);
97 dma_reg &= ~(R852_DMA_READ | R852_DMA_INTERNAL | R852_DMA_MEMORY);
98
99 if (dev->dma_dir)
100 dma_reg |= R852_DMA_READ;
101
fb45d323 102 if (dev->dma_state == DMA_INTERNAL) {
67e054e9 103 dma_reg |= R852_DMA_INTERNAL;
fb45d323
ML		 104 /* Precaution to make sure HW doesn't write */
105 /* to random kernel memory */
106 r852_write_reg_dword(dev, R852_DMA_ADDR,
107 cpu_to_le32(dev->phys_bounce_buffer));
108 } else {
67e054e9
ML		 109 dma_reg |= R852_DMA_MEMORY;
110 r852_write_reg_dword(dev, R852_DMA_ADDR,
111 cpu_to_le32(dev->phys_dma_addr));
112 }
113
fb45d323
ML		 114 /* Precaution: make sure write reached the device */
115 r852_read_reg_dword(dev, R852_DMA_ADDR);
116
67e054e9
ML		 117 r852_write_reg_dword(dev, R852_DMA_SETTINGS, dma_reg);
118
119 /* Set dma irq */
120 dma_irq_reg = r852_read_reg_dword(dev, R852_DMA_IRQ_ENABLE);
121 r852_write_reg_dword(dev, R852_DMA_IRQ_ENABLE,
122 dma_irq_reg |
123 R852_DMA_IRQ_INTERNAL |
124 R852_DMA_IRQ_ERROR |
125 R852_DMA_IRQ_MEMORY);
126}
127
128/*
129 * Disable dma, called from the interrupt handler, which specifies
130 * success of the operation via 'error' argument
131 */
132static void r852_dma_done(struct r852_device *dev, int error)
133{
134 WARN_ON(dev->dma_stage == 0);
135
136 r852_write_reg_dword(dev, R852_DMA_IRQ_STA,
137 r852_read_reg_dword(dev, R852_DMA_IRQ_STA));
138
139 r852_write_reg_dword(dev, R852_DMA_SETTINGS, 0);
140 r852_write_reg_dword(dev, R852_DMA_IRQ_ENABLE, 0);
141
fb45d323
ML		 142 /* Precaution to make sure HW doesn't write to random kernel memory */
143 r852_write_reg_dword(dev, R852_DMA_ADDR,
144 cpu_to_le32(dev->phys_bounce_buffer));
145 r852_read_reg_dword(dev, R852_DMA_ADDR);
146
67e054e9
ML		 147 dev->dma_error = error;
148 dev->dma_stage = 0;
149
150 if (dev->phys_dma_addr && dev->phys_dma_addr != dev->phys_bounce_buffer)
151 pci_unmap_single(dev->pci_dev, dev->phys_dma_addr, R852_DMA_LEN,
152 dev->dma_dir ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
67e054e9
ML		 153}
154
155/*
156 * Wait, till dma is done, which includes both phases of it
157 */
158static int r852_dma_wait(struct r852_device *dev)
159{
160 long timeout = wait_for_completion_timeout(&dev->dma_done,
161 msecs_to_jiffies(1000));
162 if (!timeout) {
163 dbg("timeout waiting for DMA interrupt");
164 return -ETIMEDOUT;
165 }
166
167 return 0;
168}
169
170/*
171 * Read/Write one page using dma. Only pages can be read (512 bytes)
172*/
173static void r852_do_dma(struct r852_device *dev, uint8_t *buf, int do_read)
174{
175 int bounce = 0;
176 unsigned long flags;
177 int error;
178
179 dev->dma_error = 0;
180
181 /* Set dma direction */
182 dev->dma_dir = do_read;
183 dev->dma_stage = 1;
9489be8c 184 INIT_COMPLETION(dev->dma_done);
67e054e9
ML		 185
186 dbg_verbose("doing dma %s ", do_read ? "read" : "write");
187
188 /* Set intial dma state: for reading first fill on board buffer,
189 from device, for writes first fill the buffer from memory*/
190 dev->dma_state = do_read ? DMA_INTERNAL : DMA_MEMORY;
191
192 /* if incoming buffer is not page aligned, we should do bounce */
193 if ((unsigned long)buf & (R852_DMA_LEN-1))
194 bounce = 1;
195
196 if (!bounce) {
197 dev->phys_dma_addr = pci_map_single(dev->pci_dev, (void *)buf,
198 R852_DMA_LEN,
199 (do_read ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE));
200
0c82d3ce 201 if (pci_dma_mapping_error(dev->pci_dev, dev->phys_dma_addr))
67e054e9
ML		 202 bounce = 1;
203 }
204
205 if (bounce) {
206 dbg_verbose("dma: using bounce buffer");
207 dev->phys_dma_addr = dev->phys_bounce_buffer;
208 if (!do_read)
209 memcpy(dev->bounce_buffer, buf, R852_DMA_LEN);
210 }
211
212 /* Enable DMA */
213 spin_lock_irqsave(&dev->irqlock, flags);
214 r852_dma_enable(dev);
215 spin_unlock_irqrestore(&dev->irqlock, flags);
216
217 /* Wait till complete */
218 error = r852_dma_wait(dev);
219
220 if (error) {
221 r852_dma_done(dev, error);
222 return;
223 }
224
225 if (do_read && bounce)
226 memcpy((void *)buf, dev->bounce_buffer, R852_DMA_LEN);
227}
228
229/*
230 * Program data lines of the nand chip to send data to it
231 */
232void r852_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
233{
234 struct r852_device *dev = r852_get_dev(mtd);
235 uint32_t reg;
236
237 /* Don't allow any access to hardware if we suspect card removal */
238 if (dev->card_unstable)
239 return;
240
241 /* Special case for whole sector read */
242 if (len == R852_DMA_LEN && dev->dma_usable) {
243 r852_do_dma(dev, (uint8_t *)buf, 0);
244 return;
245 }
246
247 /* write DWORD chinks - faster */
248 while (len) {
249 reg = buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24;
250 r852_write_reg_dword(dev, R852_DATALINE, reg);
251 buf += 4;
252 len -= 4;
253
254 }
255
256 /* write rest */
257 while (len)
258 r852_write_reg(dev, R852_DATALINE, *buf++);
259}
260
261/*
262 * Read data lines of the nand chip to retrieve data
263 */
264void r852_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
265{
266 struct r852_device *dev = r852_get_dev(mtd);
267 uint32_t reg;
268
269 if (dev->card_unstable) {
270 /* since we can't signal error here, at least, return
271 predictable buffer */
272 memset(buf, 0, len);
273 return;
274 }
275
276 /* special case for whole sector read */
277 if (len == R852_DMA_LEN && dev->dma_usable) {
278 r852_do_dma(dev, buf, 1);
279 return;
280 }
281
282 /* read in dword sized chunks */
283 while (len >= 4) {
284
285 reg = r852_read_reg_dword(dev, R852_DATALINE);
286 *buf++ = reg & 0xFF;
287 *buf++ = (reg >> 8) & 0xFF;
288 *buf++ = (reg >> 16) & 0xFF;
289 *buf++ = (reg >> 24) & 0xFF;
290 len -= 4;
291 }
292
293 /* read the reset by bytes */
294 while (len--)
295 *buf++ = r852_read_reg(dev, R852_DATALINE);
296}
297
298/*
299 * Read one byte from nand chip
300 */
301static uint8_t r852_read_byte(struct mtd_info *mtd)
302{
303 struct r852_device *dev = r852_get_dev(mtd);
304
305 /* Same problem as in r852_read_buf.... */
306 if (dev->card_unstable)
307 return 0;
308
309 return r852_read_reg(dev, R852_DATALINE);
310}
311
312
313/*
314 * Readback the buffer to verify it
315 */
316int r852_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
317{
318 struct r852_device *dev = r852_get_dev(mtd);
319
320 /* We can't be sure about anything here... */
321 if (dev->card_unstable)
322 return -1;
323
324 /* This will never happen, unless you wired up a nand chip
325 with > 512 bytes page size to the reader */
326 if (len > SM_SECTOR_SIZE)
327 return 0;
328
329 r852_read_buf(mtd, dev->tmp_buffer, len);
330 return memcmp(buf, dev->tmp_buffer, len);
331}
332
333/*
334 * Control several chip lines & send commands
335 */
336void r852_cmdctl(struct mtd_info *mtd, int dat, unsigned int ctrl)
337{
338 struct r852_device *dev = r852_get_dev(mtd);
339
340 if (dev->card_unstable)
341 return;
342
343 if (ctrl & NAND_CTRL_CHANGE) {
344
345 dev->ctlreg &= ~(R852_CTL_DATA | R852_CTL_COMMAND |
346 R852_CTL_ON | R852_CTL_CARDENABLE);
347
348 if (ctrl & NAND_ALE)
349 dev->ctlreg |= R852_CTL_DATA;
350
351 if (ctrl & NAND_CLE)
352 dev->ctlreg |= R852_CTL_COMMAND;
353
354 if (ctrl & NAND_NCE)
355 dev->ctlreg |= (R852_CTL_CARDENABLE | R852_CTL_ON);
356 else
357 dev->ctlreg &= ~R852_CTL_WRITE;
358
359 /* when write is stareted, enable write access */
360 if (dat == NAND_CMD_ERASE1)
361 dev->ctlreg |= R852_CTL_WRITE;
362
363 r852_write_reg(dev, R852_CTL, dev->ctlreg);
364 }
365
366 /* HACK: NAND_CMD_SEQIN is called without NAND_CTRL_CHANGE, but we need
367 to set write mode */
368 if (dat == NAND_CMD_SEQIN && (dev->ctlreg & R852_CTL_COMMAND)) {
369 dev->ctlreg |= R852_CTL_WRITE;
370 r852_write_reg(dev, R852_CTL, dev->ctlreg);
371 }
372
373 if (dat != NAND_CMD_NONE)
374 r852_write_reg(dev, R852_DATALINE, dat);
375}
376
377/*
378 * Wait till card is ready.
379 * based on nand_wait, but returns errors on DMA error
380 */
381int r852_wait(struct mtd_info *mtd, struct nand_chip *chip)
382{
029919c1 383 struct r852_device *dev = chip->priv;
67e054e9
ML		 384
385 unsigned long timeout;
386 int status;
387
388 timeout = jiffies + (chip->state == FL_ERASING ?
389 msecs_to_jiffies(400) : msecs_to_jiffies(20));
390
391 while (time_before(jiffies, timeout))
392 if (chip->dev_ready(mtd))
393 break;
394
395 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
396 status = (int)chip->read_byte(mtd);
397
398 /* Unfortunelly, no way to send detailed error status... */
399 if (dev->dma_error) {
400 status |= NAND_STATUS_FAIL;
401 dev->dma_error = 0;
402 }
403 return status;
404}
405
406/*
407 * Check if card is ready
408 */
409
410int r852_ready(struct mtd_info *mtd)
411{
412 struct r852_device *dev = r852_get_dev(mtd);
413 return !(r852_read_reg(dev, R852_CARD_STA) & R852_CARD_STA_BUSY);
414}
415
416
417/*
418 * Set ECC engine mode
419*/
420
421void r852_ecc_hwctl(struct mtd_info *mtd, int mode)
422{
423 struct r852_device *dev = r852_get_dev(mtd);
424
425 if (dev->card_unstable)
426 return;
427
428 switch (mode) {
429 case NAND_ECC_READ:
430 case NAND_ECC_WRITE:
431 /* enable ecc generation/check*/
432 dev->ctlreg |= R852_CTL_ECC_ENABLE;
433
434 /* flush ecc buffer */
435 r852_write_reg(dev, R852_CTL,
436 dev->ctlreg | R852_CTL_ECC_ACCESS);
437
438 r852_read_reg_dword(dev, R852_DATALINE);
439 r852_write_reg(dev, R852_CTL, dev->ctlreg);
440 return;
441
442 case NAND_ECC_READSYN:
443 /* disable ecc generation */
444 dev->ctlreg &= ~R852_CTL_ECC_ENABLE;
445 r852_write_reg(dev, R852_CTL, dev->ctlreg);
446 }
447}
448
449/*
450 * Calculate ECC, only used for writes
451 */
452
453int r852_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
454 uint8_t *ecc_code)
455{
456 struct r852_device *dev = r852_get_dev(mtd);
457 struct sm_oob *oob = (struct sm_oob *)ecc_code;
458 uint32_t ecc1, ecc2;
459
460 if (dev->card_unstable)
461 return 0;
462
463 dev->ctlreg &= ~R852_CTL_ECC_ENABLE;
464 r852_write_reg(dev, R852_CTL, dev->ctlreg | R852_CTL_ECC_ACCESS);
465
466 ecc1 = r852_read_reg_dword(dev, R852_DATALINE);
467 ecc2 = r852_read_reg_dword(dev, R852_DATALINE);
468
469 oob->ecc1[0] = (ecc1) & 0xFF;
470 oob->ecc1[1] = (ecc1 >> 8) & 0xFF;
471 oob->ecc1[2] = (ecc1 >> 16) & 0xFF;
472
473 oob->ecc2[0] = (ecc2) & 0xFF;
474 oob->ecc2[1] = (ecc2 >> 8) & 0xFF;
475 oob->ecc2[2] = (ecc2 >> 16) & 0xFF;
476
477 r852_write_reg(dev, R852_CTL, dev->ctlreg);
478 return 0;
479}
480
481/*
482 * Correct the data using ECC, hw did almost everything for us
483 */
484
485int r852_ecc_correct(struct mtd_info *mtd, uint8_t *dat,
486 uint8_t *read_ecc, uint8_t *calc_ecc)
487{
488 uint16_t ecc_reg;
489 uint8_t ecc_status, err_byte;
490 int i, error = 0;
491
492 struct r852_device *dev = r852_get_dev(mtd);
493
494 if (dev->card_unstable)
495 return 0;
496
9489be8c
ML		 497 if (dev->dma_error) {
498 dev->dma_error = 0;
499 return -1;
500 }
501
67e054e9
ML		 502 r852_write_reg(dev, R852_CTL, dev->ctlreg | R852_CTL_ECC_ACCESS);
503 ecc_reg = r852_read_reg_dword(dev, R852_DATALINE);
504 r852_write_reg(dev, R852_CTL, dev->ctlreg);
505
506 for (i = 0 ; i <= 1 ; i++) {
507
508 ecc_status = (ecc_reg >> 8) & 0xFF;
509
510 /* ecc uncorrectable error */
511 if (ecc_status & R852_ECC_FAIL) {
512 dbg("ecc: unrecoverable error, in half %d", i);
513 error = -1;
514 goto exit;
515 }
516
517 /* correctable error */
518 if (ecc_status & R852_ECC_CORRECTABLE) {
519
520 err_byte = ecc_reg & 0xFF;
521 dbg("ecc: recoverable error, "
522 "in half %d, byte %d, bit %d", i,
523 err_byte, ecc_status & R852_ECC_ERR_BIT_MSK);
524
525 dat[err_byte] ^=
526 1 << (ecc_status & R852_ECC_ERR_BIT_MSK);
527 error++;
528 }
529
530 dat += 256;
531 ecc_reg >>= 16;
532 }
533exit:
534 return error;
535}
536
537/*
538 * This is copy of nand_read_oob_std
539 * nand_read_oob_syndrome assumes we can send column address - we can't
540 */
541static int r852_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
542 int page, int sndcmd)
543{
544 if (sndcmd) {
545 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
546 sndcmd = 0;
547 }
548 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
549 return sndcmd;
550}
551
552/*
553 * Start the nand engine
554 */
555
556void r852_engine_enable(struct r852_device *dev)
557{
558 if (r852_read_reg_dword(dev, R852_HW) & R852_HW_UNKNOWN) {
559 r852_write_reg(dev, R852_CTL, R852_CTL_RESET | R852_CTL_ON);
560 r852_write_reg_dword(dev, R852_HW, R852_HW_ENABLED);
561 } else {
562 r852_write_reg_dword(dev, R852_HW, R852_HW_ENABLED);
563 r852_write_reg(dev, R852_CTL, R852_CTL_RESET | R852_CTL_ON);
564 }
565 msleep(300);
566 r852_write_reg(dev, R852_CTL, 0);
567}
568
569
570/*
571 * Stop the nand engine
572 */
573
574void r852_engine_disable(struct r852_device *dev)
575{
576 r852_write_reg_dword(dev, R852_HW, 0);
577 r852_write_reg(dev, R852_CTL, R852_CTL_RESET);
578}
579
580/*
581 * Test if card is present
582 */
583
584void r852_card_update_present(struct r852_device *dev)
585{
586 unsigned long flags;
587 uint8_t reg;
588
589 spin_lock_irqsave(&dev->irqlock, flags);
590 reg = r852_read_reg(dev, R852_CARD_STA);
591 dev->card_detected = !!(reg & R852_CARD_STA_PRESENT);
592 spin_unlock_irqrestore(&dev->irqlock, flags);
593}
594
595/*
596 * Update card detection IRQ state according to current card state
597 * which is read in r852_card_update_present
598 */
599void r852_update_card_detect(struct r852_device *dev)
600{
601 int card_detect_reg = r852_read_reg(dev, R852_CARD_IRQ_ENABLE);
fb45d323 602 dev->card_unstable = 0;
67e054e9
ML		 603
604 card_detect_reg &= ~(R852_CARD_IRQ_REMOVE | R852_CARD_IRQ_INSERT);
605 card_detect_reg |= R852_CARD_IRQ_GENABLE;
606
607 card_detect_reg |= dev->card_detected ?
608 R852_CARD_IRQ_REMOVE : R852_CARD_IRQ_INSERT;
609
610 r852_write_reg(dev, R852_CARD_IRQ_ENABLE, card_detect_reg);
611}
612
613ssize_t r852_media_type_show(struct device *sys_dev,
614 struct device_attribute *attr, char *buf)
615{
616 struct mtd_info *mtd = container_of(sys_dev, struct mtd_info, dev);
617 struct r852_device *dev = r852_get_dev(mtd);
618 char *data = dev->sm ? "smartmedia" : "xd";
619
620 strcpy(buf, data);
621 return strlen(data);
622}
623
624DEVICE_ATTR(media_type, S_IRUGO, r852_media_type_show, NULL);
625
626
627/* Detect properties of card in slot */
628void r852_update_media_status(struct r852_device *dev)
629{
630 uint8_t reg;
631 unsigned long flags;
632 int readonly;
633
634 spin_lock_irqsave(&dev->irqlock, flags);
635 if (!dev->card_detected) {
636 message("card removed");
637 spin_unlock_irqrestore(&dev->irqlock, flags);
638 return ;
639 }
640
641 readonly = r852_read_reg(dev, R852_CARD_STA) & R852_CARD_STA_RO;
642 reg = r852_read_reg(dev, R852_DMA_CAP);
643 dev->sm = (reg & (R852_DMA1 | R852_DMA2)) && (reg & R852_SMBIT);
644
645 message("detected %s %s card in slot",
646 dev->sm ? "SmartMedia" : "xD",
647 readonly ? "readonly" : "writeable");
648
649 dev->readonly = readonly;
650 spin_unlock_irqrestore(&dev->irqlock, flags);
651}
652
653/*
654 * Register the nand device
655 * Called when the card is detected
656 */
657int r852_register_nand_device(struct r852_device *dev)
658{
659 dev->mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
660
661 if (!dev->mtd)
662 goto error1;
663
664 WARN_ON(dev->card_registred);
665
666 dev->mtd->owner = THIS_MODULE;
667 dev->mtd->priv = dev->chip;
668 dev->mtd->dev.parent = &dev->pci_dev->dev;
669
670 if (dev->readonly)
671 dev->chip->options |= NAND_ROM;
672
673 r852_engine_enable(dev);
674
c3611570 675 if (sm_register_device(dev->mtd, dev->sm))
67e054e9
ML		 676 goto error2;
677
133fa8c7
ML		 678 if (device_create_file(&dev->mtd->dev, &dev_attr_media_type))
679 message("can't create media type sysfs attribute");
680
67e054e9
ML		 681 dev->card_registred = 1;
682 return 0;
683error2:
684 kfree(dev->mtd);
685error1:
686 /* Force card redetect */
687 dev->card_detected = 0;
688 return -1;
689}
690
691/*
692 * Unregister the card
693 */
694
695void r852_unregister_nand_device(struct r852_device *dev)
696{
697 if (!dev->card_registred)
698 return;
699
700 device_remove_file(&dev->mtd->dev, &dev_attr_media_type);
701 nand_release(dev->mtd);
702 r852_engine_disable(dev);
703 dev->card_registred = 0;
704 kfree(dev->mtd);
705 dev->mtd = NULL;
706}
707
708/* Card state updater */
709void r852_card_detect_work(struct work_struct *work)
710{
711 struct r852_device *dev =
712 container_of(work, struct r852_device, card_detect_work.work);
713
fb45d323 714 r852_card_update_present(dev);
ac373f7e 715 r852_update_card_detect(dev);
67e054e9
ML		 716 dev->card_unstable = 0;
717
fb45d323 718 /* False alarm */
67e054e9
ML		 719 if (dev->card_detected == dev->card_registred)
720 goto exit;
721
722 /* Read media properties */
723 r852_update_media_status(dev);
724
725 /* Register the card */
726 if (dev->card_detected)
727 r852_register_nand_device(dev);
728 else
729 r852_unregister_nand_device(dev);
730exit:
67e054e9
ML		 731 r852_update_card_detect(dev);
732}
733
734/* Ack + disable IRQ generation */
735static void r852_disable_irqs(struct r852_device *dev)
736{
737 uint8_t reg;
738 reg = r852_read_reg(dev, R852_CARD_IRQ_ENABLE);
739 r852_write_reg(dev, R852_CARD_IRQ_ENABLE, reg & ~R852_CARD_IRQ_MASK);
740
741 reg = r852_read_reg_dword(dev, R852_DMA_IRQ_ENABLE);
742 r852_write_reg_dword(dev, R852_DMA_IRQ_ENABLE,
743 reg & ~R852_DMA_IRQ_MASK);
744
745 r852_write_reg(dev, R852_CARD_IRQ_STA, R852_CARD_IRQ_MASK);
746 r852_write_reg_dword(dev, R852_DMA_IRQ_STA, R852_DMA_IRQ_MASK);
747}
748
749/* Interrupt handler */
750static irqreturn_t r852_irq(int irq, void *data)
751{
752 struct r852_device *dev = (struct r852_device *)data;
753
754 uint8_t card_status, dma_status;
755 unsigned long flags;
756 irqreturn_t ret = IRQ_NONE;
757
758 spin_lock_irqsave(&dev->irqlock, flags);
759
67e054e9
ML		 760 /* handle card detection interrupts first */
761 card_status = r852_read_reg(dev, R852_CARD_IRQ_STA);
762 r852_write_reg(dev, R852_CARD_IRQ_STA, card_status);
763
764 if (card_status & (R852_CARD_IRQ_INSERT|R852_CARD_IRQ_REMOVE)) {
765
766 ret = IRQ_HANDLED;
767 dev->card_detected = !!(card_status & R852_CARD_IRQ_INSERT);
768
769 /* we shouldn't recieve any interrupts if we wait for card
770 to settle */
771 WARN_ON(dev->card_unstable);
772
773 /* disable irqs while card is unstable */
774 /* this will timeout DMA if active, but better that garbage */
775 r852_disable_irqs(dev);
776
777 if (dev->card_unstable)
778 goto out;
779
780 /* let, card state to settle a bit, and then do the work */
781 dev->card_unstable = 1;
782 queue_delayed_work(dev->card_workqueue,
783 &dev->card_detect_work, msecs_to_jiffies(100));
784 goto out;
785 }
786
787
788 /* Handle dma interrupts */
789 dma_status = r852_read_reg_dword(dev, R852_DMA_IRQ_STA);
790 r852_write_reg_dword(dev, R852_DMA_IRQ_STA, dma_status);
791
792 if (dma_status & R852_DMA_IRQ_MASK) {
793
794 ret = IRQ_HANDLED;
795
796 if (dma_status & R852_DMA_IRQ_ERROR) {
797 dbg("recieved dma error IRQ");
798 r852_dma_done(dev, -EIO);
9489be8c 799 complete(&dev->dma_done);
67e054e9
ML		 800 goto out;
801 }
802
803 /* recieved DMA interrupt out of nowhere? */
804 WARN_ON_ONCE(dev->dma_stage == 0);
805
806 if (dev->dma_stage == 0)
807 goto out;
808
809 /* done device access */
810 if (dev->dma_state == DMA_INTERNAL &&
811 (dma_status & R852_DMA_IRQ_INTERNAL)) {
812
813 dev->dma_state = DMA_MEMORY;
814 dev->dma_stage++;
815 }
816
817 /* done memory DMA */
818 if (dev->dma_state == DMA_MEMORY &&
819 (dma_status & R852_DMA_IRQ_MEMORY)) {
820 dev->dma_state = DMA_INTERNAL;
821 dev->dma_stage++;
822 }
823
824 /* Enable 2nd half of dma dance */
825 if (dev->dma_stage == 2)
826 r852_dma_enable(dev);
827
828 /* Operation done */
9489be8c 829 if (dev->dma_stage == 3) {
67e054e9 830 r852_dma_done(dev, 0);
9489be8c
ML		 831 complete(&dev->dma_done);
832 }
67e054e9
ML		 833 goto out;
834 }
835
836 /* Handle unknown interrupts */
837 if (dma_status)
838 dbg("bad dma IRQ status = %x", dma_status);
839
840 if (card_status & ~R852_CARD_STA_CD)
841 dbg("strange card status = %x", card_status);
842
843out:
844 spin_unlock_irqrestore(&dev->irqlock, flags);
845 return ret;
846}
847
848int r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
849{
850 int error;
851 struct nand_chip *chip;
852 struct r852_device *dev;
853
854 /* pci initialization */
855 error = pci_enable_device(pci_dev);
856
857 if (error)
858 goto error1;
859
860 pci_set_master(pci_dev);
861
133fa8c7 862 error = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
67e054e9
ML		 863 if (error)
864 goto error2;
865
866 error = pci_request_regions(pci_dev, DRV_NAME);
867
868 if (error)
869 goto error3;
870
871 error = -ENOMEM;
872
873 /* init nand chip, but register it only on card insert */
874 chip = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
875
876 if (!chip)
877 goto error4;
878
879 /* commands */
880 chip->cmd_ctrl = r852_cmdctl;
881 chip->waitfunc = r852_wait;
882 chip->dev_ready = r852_ready;
883
884 /* I/O */
885 chip->read_byte = r852_read_byte;
886 chip->read_buf = r852_read_buf;
887 chip->write_buf = r852_write_buf;
888 chip->verify_buf = r852_verify_buf;
889
890 /* ecc */
891 chip->ecc.mode = NAND_ECC_HW_SYNDROME;
892 chip->ecc.size = R852_DMA_LEN;
893 chip->ecc.bytes = SM_OOB_SIZE;
894 chip->ecc.hwctl = r852_ecc_hwctl;
895 chip->ecc.calculate = r852_ecc_calculate;
896 chip->ecc.correct = r852_ecc_correct;
897
898 /* TODO: hack */
899 chip->ecc.read_oob = r852_read_oob;
900
901 /* init our device structure */
902 dev = kzalloc(sizeof(struct r852_device), GFP_KERNEL);
903
904 if (!dev)
905 goto error5;
906
907 chip->priv = dev;
908 dev->chip = chip;
909 dev->pci_dev = pci_dev;
910 pci_set_drvdata(pci_dev, dev);
911
912 dev->bounce_buffer = pci_alloc_consistent(pci_dev, R852_DMA_LEN,
913 &dev->phys_bounce_buffer);
914
915 if (!dev->bounce_buffer)
916 goto error6;
917
918
919 error = -ENODEV;
920 dev->mmio = pci_ioremap_bar(pci_dev, 0);
921
922 if (!dev->mmio)
923 goto error7;
924
925 error = -ENOMEM;
926 dev->tmp_buffer = kzalloc(SM_SECTOR_SIZE, GFP_KERNEL);
927
928 if (!dev->tmp_buffer)
929 goto error8;
930
931 init_completion(&dev->dma_done);
932
933 dev->card_workqueue = create_freezeable_workqueue(DRV_NAME);
934
935 if (!dev->card_workqueue)
936 goto error9;
937
938 INIT_DELAYED_WORK(&dev->card_detect_work, r852_card_detect_work);
939
940 /* shutdown everything - precation */
941 r852_engine_disable(dev);
942 r852_disable_irqs(dev);
943
944 r852_dma_test(dev);
945
cc1fed00
ML		 946 dev->irq = pci_dev->irq;
947 spin_lock_init(&dev->irqlock);
948
949 dev->card_detected = 0;
950 r852_card_update_present(dev);
951
67e054e9
ML		 952 /*register irq handler*/
953 error = -ENODEV;
954 if (request_irq(pci_dev->irq, &r852_irq, IRQF_SHARED,
955 DRV_NAME, dev))
956 goto error10;
957
67e054e9 958 /* kick initial present test */
67e054e9
ML		 959 queue_delayed_work(dev->card_workqueue,
960 &dev->card_detect_work, 0);
961
962
963 printk(KERN_NOTICE DRV_NAME ": driver loaded succesfully\n");
964 return 0;
965
966error10:
967 destroy_workqueue(dev->card_workqueue);
968error9:
969 kfree(dev->tmp_buffer);
970error8:
971 pci_iounmap(pci_dev, dev->mmio);
972error7:
973 pci_free_consistent(pci_dev, R852_DMA_LEN,
974 dev->bounce_buffer, dev->phys_bounce_buffer);
975error6:
976 kfree(dev);
977error5:
978 kfree(chip);
979error4:
980 pci_release_regions(pci_dev);
981error3:
982error2:
983 pci_disable_device(pci_dev);
984error1:
985 return error;
986}
987
988void r852_remove(struct pci_dev *pci_dev)
989{
990 struct r852_device *dev = pci_get_drvdata(pci_dev);
991
992 /* Stop detect workqueue -
993 we are going to unregister the device anyway*/
994 cancel_delayed_work_sync(&dev->card_detect_work);
995 destroy_workqueue(dev->card_workqueue);
996
997 /* Unregister the device, this might make more IO */
998 r852_unregister_nand_device(dev);
999
1000 /* Stop interrupts */
1001 r852_disable_irqs(dev);
1002 synchronize_irq(dev->irq);
1003 free_irq(dev->irq, dev);
1004
1005 /* Cleanup */
1006 kfree(dev->tmp_buffer);
1007 pci_iounmap(pci_dev, dev->mmio);
1008 pci_free_consistent(pci_dev, R852_DMA_LEN,
1009 dev->bounce_buffer, dev->phys_bounce_buffer);
1010
1011 kfree(dev->chip);
1012 kfree(dev);
1013
1014 /* Shutdown the PCI device */
1015 pci_release_regions(pci_dev);
1016 pci_disable_device(pci_dev);
1017}
1018
1019void r852_shutdown(struct pci_dev *pci_dev)
1020{
1021 struct r852_device *dev = pci_get_drvdata(pci_dev);
1022
1023 cancel_delayed_work_sync(&dev->card_detect_work);
1024 r852_disable_irqs(dev);
1025 synchronize_irq(dev->irq);
1026 pci_disable_device(pci_dev);
1027}
1028
b2aaf7a2 1029#ifdef CONFIG_PM
67e054e9
ML		 1030int r852_suspend(struct device *device)
1031{
1032 struct r852_device *dev = pci_get_drvdata(to_pci_dev(device));
67e054e9
ML		 1033
1034 if (dev->ctlreg & R852_CTL_CARDENABLE)
1035 return -EBUSY;
1036
1037 /* First make sure the detect work is gone */
1038 cancel_delayed_work_sync(&dev->card_detect_work);
1039
1040 /* Turn off the interrupts and stop the device */
1041 r852_disable_irqs(dev);
1042 r852_engine_disable(dev);
1043
67e054e9
ML		 1044 /* If card was pulled off just during the suspend, which is very
1045 unlikely, we will remove it on resume, it too late now
1046 anyway... */
1047 dev->card_unstable = 0;
9bf70717 1048 return 0;
67e054e9
ML		 1049}
1050
1051int r852_resume(struct device *device)
1052{
1053 struct r852_device *dev = pci_get_drvdata(to_pci_dev(device));
67e054e9
ML		 1054
1055 r852_disable_irqs(dev);
1056 r852_card_update_present(dev);
1057 r852_engine_disable(dev);
1058
1059
67e054e9
ML		 1060 /* If card status changed, just do the work */
1061 if (dev->card_detected != dev->card_registred) {
1062 dbg("card was %s during low power state",
1063 dev->card_detected ? "added" : "removed");
1064
1065 queue_delayed_work(dev->card_workqueue,
9489be8c 1066 &dev->card_detect_work, msecs_to_jiffies(1000));
67e054e9
ML		 1067 return 0;
1068 }
1069
1070 /* Otherwise, initialize the card */
1071 if (dev->card_registred) {
1072 r852_engine_enable(dev);
1073 dev->chip->select_chip(dev->mtd, 0);
1074 dev->chip->cmdfunc(dev->mtd, NAND_CMD_RESET, -1, -1);
1075 dev->chip->select_chip(dev->mtd, -1);
1076 }
1077
1078 /* Program card detection IRQ */
1079 r852_update_card_detect(dev);
1080 return 0;
1081}
b2aaf7a2
RD		 1082#else
1083#define r852_suspend NULL
1084#define r852_resume NULL
1085#endif
67e054e9
ML		 1086
1087static const struct pci_device_id r852_pci_id_tbl[] = {
1088
d4080cb3 1089 { PCI_VDEVICE(RICOH, 0x0852), },
67e054e9
ML		 1090 { },
1091};
1092
1093MODULE_DEVICE_TABLE(pci, r852_pci_id_tbl);
1094
1095SIMPLE_DEV_PM_OPS(r852_pm_ops, r852_suspend, r852_resume);
1096
67e054e9
ML		 1097static struct pci_driver r852_pci_driver = {
1098 .name = DRV_NAME,
1099 .id_table = r852_pci_id_tbl,
1100 .probe = r852_probe,
1101 .remove = r852_remove,
1102 .shutdown = r852_shutdown,
1103 .driver.pm = &r852_pm_ops,
1104};
1105
1106static __init int r852_module_init(void)
1107{
1108 return pci_register_driver(&r852_pci_driver);
1109}
1110
1111static void __exit r852_module_exit(void)
1112{
1113 pci_unregister_driver(&r852_pci_driver);
1114}
1115
1116module_init(r852_module_init);
1117module_exit(r852_module_exit);
1118
1119MODULE_LICENSE("GPL");
1120MODULE_AUTHOR("Maxim Levitsky <maximlevitsky@gmail.com>");
1121MODULE_DESCRIPTION("Ricoh 85xx xD/smartmedia card reader driver");
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