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Merge branch 'mxc-nand' of git://git.pengutronix.de/git/imx/linux-2.6
[net-next-2.6.git] / drivers / mtd / nand / nandsim.c
CommitLineData
1da177e4
LT		 1/*
2 * NAND flash simulator.
3 *
4 * Author: Artem B. Bityuckiy <dedekind@oktetlabs.ru>, <dedekind@infradead.org>
5 *
61b03bd7 6 * Copyright (C) 2004 Nokia Corporation
1da177e4
LT		 7 *
8 * Note: NS means "NAND Simulator".
9 * Note: Input means input TO flash chip, output means output FROM chip.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2, or (at your option) any later
14 * version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
19 * Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
1da177e4
LT		 24 */
25
1da177e4
LT		 26#include <linux/init.h>
27#include <linux/types.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/vmalloc.h>
fc1f397b 31#include <asm/div64.h>
1da177e4
LT		 32#include <linux/slab.h>
33#include <linux/errno.h>
34#include <linux/string.h>
35#include <linux/mtd/mtd.h>
36#include <linux/mtd/nand.h>
37#include <linux/mtd/partitions.h>
38#include <linux/delay.h>
2b77a0ed 39#include <linux/list.h>
514087e7 40#include <linux/random.h>
a5cce42f 41#include <linux/sched.h>
a9fc8991
AH		 42#include <linux/fs.h>
43#include <linux/pagemap.h>
1da177e4
LT		 44
45/* Default simulator parameters values */
46#if !defined(CONFIG_NANDSIM_FIRST_ID_BYTE) || \
47 !defined(CONFIG_NANDSIM_SECOND_ID_BYTE) || \
48 !defined(CONFIG_NANDSIM_THIRD_ID_BYTE) || \
49 !defined(CONFIG_NANDSIM_FOURTH_ID_BYTE)
50#define CONFIG_NANDSIM_FIRST_ID_BYTE 0x98
51#define CONFIG_NANDSIM_SECOND_ID_BYTE 0x39
52#define CONFIG_NANDSIM_THIRD_ID_BYTE 0xFF /* No byte */
53#define CONFIG_NANDSIM_FOURTH_ID_BYTE 0xFF /* No byte */
54#endif
55
56#ifndef CONFIG_NANDSIM_ACCESS_DELAY
57#define CONFIG_NANDSIM_ACCESS_DELAY 25
58#endif
59#ifndef CONFIG_NANDSIM_PROGRAMM_DELAY
60#define CONFIG_NANDSIM_PROGRAMM_DELAY 200
61#endif
62#ifndef CONFIG_NANDSIM_ERASE_DELAY
63#define CONFIG_NANDSIM_ERASE_DELAY 2
64#endif
65#ifndef CONFIG_NANDSIM_OUTPUT_CYCLE
66#define CONFIG_NANDSIM_OUTPUT_CYCLE 40
67#endif
68#ifndef CONFIG_NANDSIM_INPUT_CYCLE
69#define CONFIG_NANDSIM_INPUT_CYCLE 50
70#endif
71#ifndef CONFIG_NANDSIM_BUS_WIDTH
72#define CONFIG_NANDSIM_BUS_WIDTH 8
73#endif
74#ifndef CONFIG_NANDSIM_DO_DELAYS
75#define CONFIG_NANDSIM_DO_DELAYS 0
76#endif
77#ifndef CONFIG_NANDSIM_LOG
78#define CONFIG_NANDSIM_LOG 0
79#endif
80#ifndef CONFIG_NANDSIM_DBG
81#define CONFIG_NANDSIM_DBG 0
82#endif
83
84static uint first_id_byte = CONFIG_NANDSIM_FIRST_ID_BYTE;
85static uint second_id_byte = CONFIG_NANDSIM_SECOND_ID_BYTE;
86static uint third_id_byte = CONFIG_NANDSIM_THIRD_ID_BYTE;
87static uint fourth_id_byte = CONFIG_NANDSIM_FOURTH_ID_BYTE;
88static uint access_delay = CONFIG_NANDSIM_ACCESS_DELAY;
89static uint programm_delay = CONFIG_NANDSIM_PROGRAMM_DELAY;
90static uint erase_delay = CONFIG_NANDSIM_ERASE_DELAY;
91static uint output_cycle = CONFIG_NANDSIM_OUTPUT_CYCLE;
92static uint input_cycle = CONFIG_NANDSIM_INPUT_CYCLE;
93static uint bus_width = CONFIG_NANDSIM_BUS_WIDTH;
94static uint do_delays = CONFIG_NANDSIM_DO_DELAYS;
95static uint log = CONFIG_NANDSIM_LOG;
96static uint dbg = CONFIG_NANDSIM_DBG;
2b77a0ed
AH		 97static unsigned long parts[MAX_MTD_DEVICES];
98static unsigned int parts_num;
514087e7
AH		 99static char *badblocks = NULL;
100static char *weakblocks = NULL;
101static char *weakpages = NULL;
102static unsigned int bitflips = 0;
103static char *gravepages = NULL;
57aa6b54 104static unsigned int rptwear = 0;
a5ac8aeb 105static unsigned int overridesize = 0;
a9fc8991 106static char *cache_file = NULL;
1da177e4
LT		 107
108module_param(first_id_byte, uint, 0400);
109module_param(second_id_byte, uint, 0400);
110module_param(third_id_byte, uint, 0400);
111module_param(fourth_id_byte, uint, 0400);
112module_param(access_delay, uint, 0400);
113module_param(programm_delay, uint, 0400);
114module_param(erase_delay, uint, 0400);
115module_param(output_cycle, uint, 0400);
116module_param(input_cycle, uint, 0400);
117module_param(bus_width, uint, 0400);
118module_param(do_delays, uint, 0400);
119module_param(log, uint, 0400);
120module_param(dbg, uint, 0400);
2b77a0ed 121module_param_array(parts, ulong, &parts_num, 0400);
514087e7
AH		 122module_param(badblocks, charp, 0400);
123module_param(weakblocks, charp, 0400);
124module_param(weakpages, charp, 0400);
125module_param(bitflips, uint, 0400);
126module_param(gravepages, charp, 0400);
57aa6b54 127module_param(rptwear, uint, 0400);
a5ac8aeb 128module_param(overridesize, uint, 0400);
a9fc8991 129module_param(cache_file, charp, 0400);
1da177e4 130
a5ac8aeb 131MODULE_PARM_DESC(first_id_byte, "The first byte returned by NAND Flash 'read ID' command (manufacturer ID)");
1da177e4
LT		 132MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID)");
133MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command");
134MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command");
a9fc8991 135MODULE_PARM_DESC(access_delay, "Initial page access delay (microseconds)");
1da177e4
LT		 136MODULE_PARM_DESC(programm_delay, "Page programm delay (microseconds");
137MODULE_PARM_DESC(erase_delay, "Sector erase delay (milliseconds)");
138MODULE_PARM_DESC(output_cycle, "Word output (from flash) time (nanodeconds)");
139MODULE_PARM_DESC(input_cycle, "Word input (to flash) time (nanodeconds)");
140MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)");
141MODULE_PARM_DESC(do_delays, "Simulate NAND delays using busy-waits if not zero");
142MODULE_PARM_DESC(log, "Perform logging if not zero");
143MODULE_PARM_DESC(dbg, "Output debug information if not zero");
2b77a0ed 144MODULE_PARM_DESC(parts, "Partition sizes (in erase blocks) separated by commas");
514087e7
AH		 145/* Page and erase block positions for the following parameters are independent of any partitions */
146MODULE_PARM_DESC(badblocks, "Erase blocks that are initially marked bad, separated by commas");
147MODULE_PARM_DESC(weakblocks, "Weak erase blocks [: remaining erase cycles (defaults to 3)]"
148 " separated by commas e.g. 113:2 means eb 113"
149 " can be erased only twice before failing");
150MODULE_PARM_DESC(weakpages, "Weak pages [: maximum writes (defaults to 3)]"
151 " separated by commas e.g. 1401:2 means page 1401"
152 " can be written only twice before failing");
153MODULE_PARM_DESC(bitflips, "Maximum number of random bit flips per page (zero by default)");
154MODULE_PARM_DESC(gravepages, "Pages that lose data [: maximum reads (defaults to 3)]"
155 " separated by commas e.g. 1401:2 means page 1401"
156 " can be read only twice before failing");
57aa6b54 157MODULE_PARM_DESC(rptwear, "Number of erases inbetween reporting wear, if not zero");
a5ac8aeb
AH		 158MODULE_PARM_DESC(overridesize, "Specifies the NAND Flash size overriding the ID bytes. "
159 "The size is specified in erase blocks and as the exponent of a power of two"
160 " e.g. 5 means a size of 32 erase blocks");
a9fc8991 161MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of memory");
1da177e4
LT		 162
163/* The largest possible page size */
164#define NS_LARGEST_PAGE_SIZE 2048
61b03bd7 165
1da177e4
LT		 166/* The prefix for simulator output */
167#define NS_OUTPUT_PREFIX "[nandsim]"
168
169/* Simulator's output macros (logging, debugging, warning, error) */
170#define NS_LOG(args...) \
171 do { if (log) printk(KERN_DEBUG NS_OUTPUT_PREFIX " log: " args); } while(0)
172#define NS_DBG(args...) \
173 do { if (dbg) printk(KERN_DEBUG NS_OUTPUT_PREFIX " debug: " args); } while(0)
174#define NS_WARN(args...) \
2b77a0ed 175 do { printk(KERN_WARNING NS_OUTPUT_PREFIX " warning: " args); } while(0)
1da177e4 176#define NS_ERR(args...) \
2b77a0ed 177 do { printk(KERN_ERR NS_OUTPUT_PREFIX " error: " args); } while(0)
57aa6b54
AH		 178#define NS_INFO(args...) \
179 do { printk(KERN_INFO NS_OUTPUT_PREFIX " " args); } while(0)
1da177e4
LT		 180
181/* Busy-wait delay macros (microseconds, milliseconds) */
182#define NS_UDELAY(us) \
183 do { if (do_delays) udelay(us); } while(0)
184#define NS_MDELAY(us) \
185 do { if (do_delays) mdelay(us); } while(0)
61b03bd7 186
1da177e4
LT		 187/* Is the nandsim structure initialized ? */
188#define NS_IS_INITIALIZED(ns) ((ns)->geom.totsz != 0)
189
190/* Good operation completion status */
191#define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0)))
192
193/* Operation failed completion status */
61b03bd7 194#define NS_STATUS_FAILED(ns) (NAND_STATUS_FAIL | NS_STATUS_OK(ns))
1da177e4
LT		 195
196/* Calculate the page offset in flash RAM image by (row, column) address */
197#define NS_RAW_OFFSET(ns) \
198 (((ns)->regs.row << (ns)->geom.pgshift) + ((ns)->regs.row * (ns)->geom.oobsz) + (ns)->regs.column)
61b03bd7 199
1da177e4
LT		 200/* Calculate the OOB offset in flash RAM image by (row, column) address */
201#define NS_RAW_OFFSET_OOB(ns) (NS_RAW_OFFSET(ns) + ns->geom.pgsz)
202
203/* After a command is input, the simulator goes to one of the following states */
204#define STATE_CMD_READ0 0x00000001 /* read data from the beginning of page */
205#define STATE_CMD_READ1 0x00000002 /* read data from the second half of page */
4a0c50c0 206#define STATE_CMD_READSTART 0x00000003 /* read data second command (large page devices) */
1da177e4
LT		 207#define STATE_CMD_PAGEPROG 0x00000004 /* start page programm */
208#define STATE_CMD_READOOB 0x00000005 /* read OOB area */
209#define STATE_CMD_ERASE1 0x00000006 /* sector erase first command */
210#define STATE_CMD_STATUS 0x00000007 /* read status */
211#define STATE_CMD_STATUS_M 0x00000008 /* read multi-plane status (isn't implemented) */
212#define STATE_CMD_SEQIN 0x00000009 /* sequential data imput */
213#define STATE_CMD_READID 0x0000000A /* read ID */
214#define STATE_CMD_ERASE2 0x0000000B /* sector erase second command */
215#define STATE_CMD_RESET 0x0000000C /* reset */
74216be4
AB		 216#define STATE_CMD_RNDOUT 0x0000000D /* random output command */
217#define STATE_CMD_RNDOUTSTART 0x0000000E /* random output start command */
1da177e4
LT		 218#define STATE_CMD_MASK 0x0000000F /* command states mask */
219
8e87d782 220/* After an address is input, the simulator goes to one of these states */
1da177e4
LT		 221#define STATE_ADDR_PAGE 0x00000010 /* full (row, column) address is accepted */
222#define STATE_ADDR_SEC 0x00000020 /* sector address was accepted */
74216be4
AB		 223#define STATE_ADDR_COLUMN 0x00000030 /* column address was accepted */
224#define STATE_ADDR_ZERO 0x00000040 /* one byte zero address was accepted */
225#define STATE_ADDR_MASK 0x00000070 /* address states mask */
1da177e4
LT		 226
227/* Durind data input/output the simulator is in these states */
228#define STATE_DATAIN 0x00000100 /* waiting for data input */
229#define STATE_DATAIN_MASK 0x00000100 /* data input states mask */
230
231#define STATE_DATAOUT 0x00001000 /* waiting for page data output */
232#define STATE_DATAOUT_ID 0x00002000 /* waiting for ID bytes output */
233#define STATE_DATAOUT_STATUS 0x00003000 /* waiting for status output */
234#define STATE_DATAOUT_STATUS_M 0x00004000 /* waiting for multi-plane status output */
235#define STATE_DATAOUT_MASK 0x00007000 /* data output states mask */
236
237/* Previous operation is done, ready to accept new requests */
238#define STATE_READY 0x00000000
239
240/* This state is used to mark that the next state isn't known yet */
241#define STATE_UNKNOWN 0x10000000
242
243/* Simulator's actions bit masks */
244#define ACTION_CPY 0x00100000 /* copy page/OOB to the internal buffer */
245#define ACTION_PRGPAGE 0x00200000 /* programm the internal buffer to flash */
246#define ACTION_SECERASE 0x00300000 /* erase sector */
247#define ACTION_ZEROOFF 0x00400000 /* don't add any offset to address */
248#define ACTION_HALFOFF 0x00500000 /* add to address half of page */
249#define ACTION_OOBOFF 0x00600000 /* add to address OOB offset */
250#define ACTION_MASK 0x00700000 /* action mask */
251
74216be4 252#define NS_OPER_NUM 13 /* Number of operations supported by the simulator */
1da177e4
LT		 253#define NS_OPER_STATES 6 /* Maximum number of states in operation */
254
255#define OPT_ANY 0xFFFFFFFF /* any chip supports this operation */
256#define OPT_PAGE256 0x00000001 /* 256-byte page chips */
257#define OPT_PAGE512 0x00000002 /* 512-byte page chips */
258#define OPT_PAGE2048 0x00000008 /* 2048-byte page chips */
259#define OPT_SMARTMEDIA 0x00000010 /* SmartMedia technology chips */
260#define OPT_AUTOINCR 0x00000020 /* page number auto inctimentation is possible */
261#define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */
262#define OPT_LARGEPAGE (OPT_PAGE2048) /* 2048-byte page chips */
263#define OPT_SMALLPAGE (OPT_PAGE256 | OPT_PAGE512) /* 256 and 512-byte page chips */
264
265/* Remove action bits ftom state */
266#define NS_STATE(x) ((x) & ~ACTION_MASK)
61b03bd7
TG		 267
268/*
1da177e4
LT		 269 * Maximum previous states which need to be saved. Currently saving is
270 * only needed for page programm operation with preceeded read command
271 * (which is only valid for 512-byte pages).
272 */
273#define NS_MAX_PREVSTATES 1
274
a9fc8991
AH		 275/* Maximum page cache pages needed to read or write a NAND page to the cache_file */
276#define NS_MAX_HELD_PAGES 16
277
d086d436
VK		 278/*
279 * A union to represent flash memory contents and flash buffer.
280 */
281union ns_mem {
282 u_char *byte; /* for byte access */
283 uint16_t *word; /* for 16-bit word access */
284};
285
61b03bd7 286/*
1da177e4
LT		 287 * The structure which describes all the internal simulator data.
288 */
289struct nandsim {
2b77a0ed
AH		 290 struct mtd_partition partitions[MAX_MTD_DEVICES];
291 unsigned int nbparts;
1da177e4
LT		 292
293 uint busw; /* flash chip bus width (8 or 16) */
294 u_char ids[4]; /* chip's ID bytes */
295 uint32_t options; /* chip's characteristic bits */
296 uint32_t state; /* current chip state */
297 uint32_t nxstate; /* next expected state */
61b03bd7 298
1da177e4
LT		 299 uint32_t *op; /* current operation, NULL operations isn't known yet */
300 uint32_t pstates[NS_MAX_PREVSTATES]; /* previous states */
301 uint16_t npstates; /* number of previous states saved */
302 uint16_t stateidx; /* current state index */
303
d086d436
VK		 304 /* The simulated NAND flash pages array */
305 union ns_mem *pages;
1da177e4 306
8a4c2495
AK		 307 /* Slab allocator for nand pages */
308 struct kmem_cache *nand_pages_slab;
309
1da177e4 310 /* Internal buffer of page + OOB size bytes */
d086d436 311 union ns_mem buf;
1da177e4
LT		 312
313 /* NAND flash "geometry" */
314 struct nandsin_geometry {
6eda7a55 315 uint64_t totsz; /* total flash size, bytes */
1da177e4
LT		 316 uint32_t secsz; /* flash sector (erase block) size, bytes */
317 uint pgsz; /* NAND flash page size, bytes */
318 uint oobsz; /* page OOB area size, bytes */
6eda7a55 319 uint64_t totszoob; /* total flash size including OOB, bytes */
1da177e4
LT		 320 uint pgszoob; /* page size including OOB , bytes*/
321 uint secszoob; /* sector size including OOB, bytes */
322 uint pgnum; /* total number of pages */
323 uint pgsec; /* number of pages per sector */
324 uint secshift; /* bits number in sector size */
325 uint pgshift; /* bits number in page size */
326 uint oobshift; /* bits number in OOB size */
327 uint pgaddrbytes; /* bytes per page address */
328 uint secaddrbytes; /* bytes per sector address */
329 uint idbytes; /* the number ID bytes that this chip outputs */
330 } geom;
331
332 /* NAND flash internal registers */
333 struct nandsim_regs {
334 unsigned command; /* the command register */
335 u_char status; /* the status register */
336 uint row; /* the page number */
337 uint column; /* the offset within page */
338 uint count; /* internal counter */
339 uint num; /* number of bytes which must be processed */
340 uint off; /* fixed page offset */
341 } regs;
342
343 /* NAND flash lines state */
344 struct ns_lines_status {
345 int ce; /* chip Enable */
346 int cle; /* command Latch Enable */
347 int ale; /* address Latch Enable */
348 int wp; /* write Protect */
349 } lines;
a9fc8991
AH		 350
351 /* Fields needed when using a cache file */
352 struct file *cfile; /* Open file */
353 unsigned char *pages_written; /* Which pages have been written */
354 void *file_buf;
355 struct page *held_pages[NS_MAX_HELD_PAGES];
356 int held_cnt;
1da177e4
LT		 357};
358
359/*
360 * Operations array. To perform any operation the simulator must pass
361 * through the correspondent states chain.
362 */
363static struct nandsim_operations {
364 uint32_t reqopts; /* options which are required to perform the operation */
365 uint32_t states[NS_OPER_STATES]; /* operation's states */
366} ops[NS_OPER_NUM] = {
367 /* Read page + OOB from the beginning */
368 {OPT_SMALLPAGE, {STATE_CMD_READ0 | ACTION_ZEROOFF, STATE_ADDR_PAGE | ACTION_CPY,
369 STATE_DATAOUT, STATE_READY}},
370 /* Read page + OOB from the second half */
371 {OPT_PAGE512_8BIT, {STATE_CMD_READ1 | ACTION_HALFOFF, STATE_ADDR_PAGE | ACTION_CPY,
372 STATE_DATAOUT, STATE_READY}},
373 /* Read OOB */
374 {OPT_SMALLPAGE, {STATE_CMD_READOOB | ACTION_OOBOFF, STATE_ADDR_PAGE | ACTION_CPY,
375 STATE_DATAOUT, STATE_READY}},
376 /* Programm page starting from the beginning */
377 {OPT_ANY, {STATE_CMD_SEQIN, STATE_ADDR_PAGE, STATE_DATAIN,
378 STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
379 /* Programm page starting from the beginning */
380 {OPT_SMALLPAGE, {STATE_CMD_READ0, STATE_CMD_SEQIN | ACTION_ZEROOFF, STATE_ADDR_PAGE,
381 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
382 /* Programm page starting from the second half */
383 {OPT_PAGE512, {STATE_CMD_READ1, STATE_CMD_SEQIN | ACTION_HALFOFF, STATE_ADDR_PAGE,
384 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
385 /* Programm OOB */
386 {OPT_SMALLPAGE, {STATE_CMD_READOOB, STATE_CMD_SEQIN | ACTION_OOBOFF, STATE_ADDR_PAGE,
387 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
388 /* Erase sector */
389 {OPT_ANY, {STATE_CMD_ERASE1, STATE_ADDR_SEC, STATE_CMD_ERASE2 | ACTION_SECERASE, STATE_READY}},
390 /* Read status */
391 {OPT_ANY, {STATE_CMD_STATUS, STATE_DATAOUT_STATUS, STATE_READY}},
392 /* Read multi-plane status */
393 {OPT_SMARTMEDIA, {STATE_CMD_STATUS_M, STATE_DATAOUT_STATUS_M, STATE_READY}},
394 /* Read ID */
395 {OPT_ANY, {STATE_CMD_READID, STATE_ADDR_ZERO, STATE_DATAOUT_ID, STATE_READY}},
396 /* Large page devices read page */
397 {OPT_LARGEPAGE, {STATE_CMD_READ0, STATE_ADDR_PAGE, STATE_CMD_READSTART | ACTION_CPY,
74216be4
AB		 398 STATE_DATAOUT, STATE_READY}},
399 /* Large page devices random page read */
400 {OPT_LARGEPAGE, {STATE_CMD_RNDOUT, STATE_ADDR_COLUMN, STATE_CMD_RNDOUTSTART | ACTION_CPY,
401 STATE_DATAOUT, STATE_READY}},
1da177e4
LT		 402};
403
514087e7
AH		 404struct weak_block {
405 struct list_head list;
406 unsigned int erase_block_no;
407 unsigned int max_erases;
408 unsigned int erases_done;
409};
410
411static LIST_HEAD(weak_blocks);
412
413struct weak_page {
414 struct list_head list;
415 unsigned int page_no;
416 unsigned int max_writes;
417 unsigned int writes_done;
418};
419
420static LIST_HEAD(weak_pages);
421
422struct grave_page {
423 struct list_head list;
424 unsigned int page_no;
425 unsigned int max_reads;
426 unsigned int reads_done;
427};
428
429static LIST_HEAD(grave_pages);
430
57aa6b54
AH		 431static unsigned long *erase_block_wear = NULL;
432static unsigned int wear_eb_count = 0;
433static unsigned long total_wear = 0;
434static unsigned int rptwear_cnt = 0;
435
1da177e4
LT		 436/* MTD structure for NAND controller */
437static struct mtd_info *nsmtd;
438
439static u_char ns_verify_buf[NS_LARGEST_PAGE_SIZE];
440
d086d436 441/*
8a4c2495
AK		 442 * Allocate array of page pointers, create slab allocation for an array
443 * and initialize the array by NULL pointers.
d086d436
VK		 444 *
445 * RETURNS: 0 if success, -ENOMEM if memory alloc fails.
446 */
a5602146 447static int alloc_device(struct nandsim *ns)
d086d436 448{
a9fc8991
AH		 449 struct file *cfile;
450 int i, err;
451
452 if (cache_file) {
453 cfile = filp_open(cache_file, O_CREAT | O_RDWR | O_LARGEFILE, 0600);
454 if (IS_ERR(cfile))
455 return PTR_ERR(cfile);
456 if (!cfile->f_op || (!cfile->f_op->read && !cfile->f_op->aio_read)) {
457 NS_ERR("alloc_device: cache file not readable\n");
458 err = -EINVAL;
459 goto err_close;
460 }
461 if (!cfile->f_op->write && !cfile->f_op->aio_write) {
462 NS_ERR("alloc_device: cache file not writeable\n");
463 err = -EINVAL;
464 goto err_close;
465 }
466 ns->pages_written = vmalloc(ns->geom.pgnum);
467 if (!ns->pages_written) {
468 NS_ERR("alloc_device: unable to allocate pages written array\n");
469 err = -ENOMEM;
470 goto err_close;
471 }
472 ns->file_buf = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
473 if (!ns->file_buf) {
474 NS_ERR("alloc_device: unable to allocate file buf\n");
475 err = -ENOMEM;
476 goto err_free;
477 }
478 ns->cfile = cfile;
479 memset(ns->pages_written, 0, ns->geom.pgnum);
480 return 0;
481 }
d086d436
VK		 482
483 ns->pages = vmalloc(ns->geom.pgnum * sizeof(union ns_mem));
484 if (!ns->pages) {
a9fc8991 485 NS_ERR("alloc_device: unable to allocate page array\n");
d086d436
VK		 486 return -ENOMEM;
487 }
488 for (i = 0; i < ns->geom.pgnum; i++) {
489 ns->pages[i].byte = NULL;
490 }
8a4c2495
AK		 491 ns->nand_pages_slab = kmem_cache_create("nandsim",
492 ns->geom.pgszoob, 0, 0, NULL);
493 if (!ns->nand_pages_slab) {
494 NS_ERR("cache_create: unable to create kmem_cache\n");
495 return -ENOMEM;
496 }
d086d436
VK		 497
498 return 0;
a9fc8991
AH		 499
500err_free:
501 vfree(ns->pages_written);
502err_close:
503 filp_close(cfile, NULL);
504 return err;
d086d436
VK		 505}
506
507/*
508 * Free any allocated pages, and free the array of page pointers.
509 */
a5602146 510static void free_device(struct nandsim *ns)
d086d436
VK		 511{
512 int i;
513
a9fc8991
AH		 514 if (ns->cfile) {
515 kfree(ns->file_buf);
516 vfree(ns->pages_written);
517 filp_close(ns->cfile, NULL);
518 return;
519 }
520
d086d436
VK		 521 if (ns->pages) {
522 for (i = 0; i < ns->geom.pgnum; i++) {
523 if (ns->pages[i].byte)
8a4c2495
AK		 524 kmem_cache_free(ns->nand_pages_slab,
525 ns->pages[i].byte);
d086d436 526 }
8a4c2495 527 kmem_cache_destroy(ns->nand_pages_slab);
d086d436
VK		 528 vfree(ns->pages);
529 }
530}
531
2b77a0ed
AH		 532static char *get_partition_name(int i)
533{
534 char buf[64];
535 sprintf(buf, "NAND simulator partition %d", i);
536 return kstrdup(buf, GFP_KERNEL);
537}
538
0f07a0be 539static uint64_t divide(uint64_t n, uint32_t d)
6eda7a55
AH		 540{
541 do_div(n, d);
542 return n;
543}
544
1da177e4
LT		 545/*
546 * Initialize the nandsim structure.
547 *
548 * RETURNS: 0 if success, -ERRNO if failure.
549 */
a5602146 550static int init_nandsim(struct mtd_info *mtd)
1da177e4
LT		 551{
552 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
553 struct nandsim *ns = (struct nandsim *)(chip->priv);
2b77a0ed 554 int i, ret = 0;
0f07a0be
DW		 555 uint64_t remains;
556 uint64_t next_offset;
1da177e4
LT		 557
558 if (NS_IS_INITIALIZED(ns)) {
559 NS_ERR("init_nandsim: nandsim is already initialized\n");
560 return -EIO;
561 }
562
563 /* Force mtd to not do delays */
564 chip->chip_delay = 0;
565
566 /* Initialize the NAND flash parameters */
567 ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8;
568 ns->geom.totsz = mtd->size;
28318776 569 ns->geom.pgsz = mtd->writesize;
1da177e4
LT		 570 ns->geom.oobsz = mtd->oobsize;
571 ns->geom.secsz = mtd->erasesize;
572 ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz;
6eda7a55
AH		 573 ns->geom.pgnum = divide(ns->geom.totsz, ns->geom.pgsz);
574 ns->geom.totszoob = ns->geom.totsz + (uint64_t)ns->geom.pgnum * ns->geom.oobsz;
1da177e4
LT		 575 ns->geom.secshift = ffs(ns->geom.secsz) - 1;
576 ns->geom.pgshift = chip->page_shift;
577 ns->geom.oobshift = ffs(ns->geom.oobsz) - 1;
578 ns->geom.pgsec = ns->geom.secsz / ns->geom.pgsz;
579 ns->geom.secszoob = ns->geom.secsz + ns->geom.oobsz * ns->geom.pgsec;
580 ns->options = 0;
581
582 if (ns->geom.pgsz == 256) {
583 ns->options |= OPT_PAGE256;
584 }
585 else if (ns->geom.pgsz == 512) {
586 ns->options |= (OPT_PAGE512 | OPT_AUTOINCR);
587 if (ns->busw == 8)
588 ns->options |= OPT_PAGE512_8BIT;
589 } else if (ns->geom.pgsz == 2048) {
590 ns->options |= OPT_PAGE2048;
591 } else {
592 NS_ERR("init_nandsim: unknown page size %u\n", ns->geom.pgsz);
593 return -EIO;
594 }
595
596 if (ns->options & OPT_SMALLPAGE) {
af3deccf 597 if (ns->geom.totsz <= (32 << 20)) {
1da177e4
LT		 598 ns->geom.pgaddrbytes = 3;
599 ns->geom.secaddrbytes = 2;
600 } else {
601 ns->geom.pgaddrbytes = 4;
602 ns->geom.secaddrbytes = 3;
603 }
604 } else {
605 if (ns->geom.totsz <= (128 << 20)) {
4a0c50c0 606 ns->geom.pgaddrbytes = 4;
1da177e4
LT		 607 ns->geom.secaddrbytes = 2;
608 } else {
609 ns->geom.pgaddrbytes = 5;
610 ns->geom.secaddrbytes = 3;
611 }
612 }
61b03bd7 613
2b77a0ed
AH		 614 /* Fill the partition_info structure */
615 if (parts_num > ARRAY_SIZE(ns->partitions)) {
616 NS_ERR("too many partitions.\n");
617 ret = -EINVAL;
618 goto error;
619 }
620 remains = ns->geom.totsz;
621 next_offset = 0;
622 for (i = 0; i < parts_num; ++i) {
0f07a0be 623 uint64_t part_sz = (uint64_t)parts[i] * ns->geom.secsz;
6eda7a55
AH		 624
625 if (!part_sz || part_sz > remains) {
2b77a0ed
AH		 626 NS_ERR("bad partition size.\n");
627 ret = -EINVAL;
628 goto error;
629 }
630 ns->partitions[i].name = get_partition_name(i);
631 ns->partitions[i].offset = next_offset;
6eda7a55 632 ns->partitions[i].size = part_sz;
2b77a0ed
AH		 633 next_offset += ns->partitions[i].size;
634 remains -= ns->partitions[i].size;
635 }
636 ns->nbparts = parts_num;
637 if (remains) {
638 if (parts_num + 1 > ARRAY_SIZE(ns->partitions)) {
639 NS_ERR("too many partitions.\n");
640 ret = -EINVAL;
641 goto error;
642 }
643 ns->partitions[i].name = get_partition_name(i);
644 ns->partitions[i].offset = next_offset;
645 ns->partitions[i].size = remains;
646 ns->nbparts += 1;
647 }
648
1da177e4
LT		 649 /* Detect how many ID bytes the NAND chip outputs */
650 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
651 if (second_id_byte != nand_flash_ids[i].id)
652 continue;
653 if (!(nand_flash_ids[i].options & NAND_NO_AUTOINCR))
654 ns->options |= OPT_AUTOINCR;
655 }
656
657 if (ns->busw == 16)
658 NS_WARN("16-bit flashes support wasn't tested\n");
659
e4c094a5
AM		 660 printk("flash size: %llu MiB\n",
661 (unsigned long long)ns->geom.totsz >> 20);
1da177e4
LT		 662 printk("page size: %u bytes\n", ns->geom.pgsz);
663 printk("OOB area size: %u bytes\n", ns->geom.oobsz);
664 printk("sector size: %u KiB\n", ns->geom.secsz >> 10);
665 printk("pages number: %u\n", ns->geom.pgnum);
666 printk("pages per sector: %u\n", ns->geom.pgsec);
667 printk("bus width: %u\n", ns->busw);
668 printk("bits in sector size: %u\n", ns->geom.secshift);
669 printk("bits in page size: %u\n", ns->geom.pgshift);
e4c094a5
AM		 670 printk("bits in OOB size: %u\n", ns->geom.oobshift);
671 printk("flash size with OOB: %llu KiB\n",
672 (unsigned long long)ns->geom.totszoob >> 10);
1da177e4
LT		 673 printk("page address bytes: %u\n", ns->geom.pgaddrbytes);
674 printk("sector address bytes: %u\n", ns->geom.secaddrbytes);
675 printk("options: %#x\n", ns->options);
676
2b77a0ed 677 if ((ret = alloc_device(ns)) != 0)
d086d436 678 goto error;
1da177e4
LT		 679
680 /* Allocate / initialize the internal buffer */
681 ns->buf.byte = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
682 if (!ns->buf.byte) {
683 NS_ERR("init_nandsim: unable to allocate %u bytes for the internal buffer\n",
684 ns->geom.pgszoob);
2b77a0ed 685 ret = -ENOMEM;
1da177e4
LT		 686 goto error;
687 }
688 memset(ns->buf.byte, 0xFF, ns->geom.pgszoob);
689
1da177e4
LT		 690 return 0;
691
692error:
d086d436 693 free_device(ns);
1da177e4 694
2b77a0ed 695 return ret;
1da177e4
LT		 696}
697
698/*
699 * Free the nandsim structure.
700 */
a5602146 701static void free_nandsim(struct nandsim *ns)
1da177e4
LT		 702{
703 kfree(ns->buf.byte);
d086d436 704 free_device(ns);
1da177e4
LT		 705
706 return;
707}
708
514087e7
AH		 709static int parse_badblocks(struct nandsim *ns, struct mtd_info *mtd)
710{
711 char *w;
712 int zero_ok;
713 unsigned int erase_block_no;
714 loff_t offset;
715
716 if (!badblocks)
717 return 0;
718 w = badblocks;
719 do {
720 zero_ok = (*w == '0' ? 1 : 0);
721 erase_block_no = simple_strtoul(w, &w, 0);
722 if (!zero_ok && !erase_block_no) {
723 NS_ERR("invalid badblocks.\n");
724 return -EINVAL;
725 }
726 offset = erase_block_no * ns->geom.secsz;
727 if (mtd->block_markbad(mtd, offset)) {
728 NS_ERR("invalid badblocks.\n");
729 return -EINVAL;
730 }
731 if (*w == ',')
732 w += 1;
733 } while (*w);
734 return 0;
735}
736
737static int parse_weakblocks(void)
738{
739 char *w;
740 int zero_ok;
741 unsigned int erase_block_no;
742 unsigned int max_erases;
743 struct weak_block *wb;
744
745 if (!weakblocks)
746 return 0;
747 w = weakblocks;
748 do {
749 zero_ok = (*w == '0' ? 1 : 0);
750 erase_block_no = simple_strtoul(w, &w, 0);
751 if (!zero_ok && !erase_block_no) {
752 NS_ERR("invalid weakblocks.\n");
753 return -EINVAL;
754 }
755 max_erases = 3;
756 if (*w == ':') {
757 w += 1;
758 max_erases = simple_strtoul(w, &w, 0);
759 }
760 if (*w == ',')
761 w += 1;
762 wb = kzalloc(sizeof(*wb), GFP_KERNEL);
763 if (!wb) {
764 NS_ERR("unable to allocate memory.\n");
765 return -ENOMEM;
766 }
767 wb->erase_block_no = erase_block_no;
768 wb->max_erases = max_erases;
769 list_add(&wb->list, &weak_blocks);
770 } while (*w);
771 return 0;
772}
773
774static int erase_error(unsigned int erase_block_no)
775{
776 struct weak_block *wb;
777
778 list_for_each_entry(wb, &weak_blocks, list)
779 if (wb->erase_block_no == erase_block_no) {
780 if (wb->erases_done >= wb->max_erases)
781 return 1;
782 wb->erases_done += 1;
783 return 0;
784 }
785 return 0;
786}
787
788static int parse_weakpages(void)
789{
790 char *w;
791 int zero_ok;
792 unsigned int page_no;
793 unsigned int max_writes;
794 struct weak_page *wp;
795
796 if (!weakpages)
797 return 0;
798 w = weakpages;
799 do {
800 zero_ok = (*w == '0' ? 1 : 0);
801 page_no = simple_strtoul(w, &w, 0);
802 if (!zero_ok && !page_no) {
803 NS_ERR("invalid weakpagess.\n");
804 return -EINVAL;
805 }
806 max_writes = 3;
807 if (*w == ':') {
808 w += 1;
809 max_writes = simple_strtoul(w, &w, 0);
810 }
811 if (*w == ',')
812 w += 1;
813 wp = kzalloc(sizeof(*wp), GFP_KERNEL);
814 if (!wp) {
815 NS_ERR("unable to allocate memory.\n");
816 return -ENOMEM;
817 }
818 wp->page_no = page_no;
819 wp->max_writes = max_writes;
820 list_add(&wp->list, &weak_pages);
821 } while (*w);
822 return 0;
823}
824
825static int write_error(unsigned int page_no)
826{
827 struct weak_page *wp;
828
829 list_for_each_entry(wp, &weak_pages, list)
830 if (wp->page_no == page_no) {
831 if (wp->writes_done >= wp->max_writes)
832 return 1;
833 wp->writes_done += 1;
834 return 0;
835 }
836 return 0;
837}
838
839static int parse_gravepages(void)
840{
841 char *g;
842 int zero_ok;
843 unsigned int page_no;
844 unsigned int max_reads;
845 struct grave_page *gp;
846
847 if (!gravepages)
848 return 0;
849 g = gravepages;
850 do {
851 zero_ok = (*g == '0' ? 1 : 0);
852 page_no = simple_strtoul(g, &g, 0);
853 if (!zero_ok && !page_no) {
854 NS_ERR("invalid gravepagess.\n");
855 return -EINVAL;
856 }
857 max_reads = 3;
858 if (*g == ':') {
859 g += 1;
860 max_reads = simple_strtoul(g, &g, 0);
861 }
862 if (*g == ',')
863 g += 1;
864 gp = kzalloc(sizeof(*gp), GFP_KERNEL);
865 if (!gp) {
866 NS_ERR("unable to allocate memory.\n");
867 return -ENOMEM;
868 }
869 gp->page_no = page_no;
870 gp->max_reads = max_reads;
871 list_add(&gp->list, &grave_pages);
872 } while (*g);
873 return 0;
874}
875
876static int read_error(unsigned int page_no)
877{
878 struct grave_page *gp;
879
880 list_for_each_entry(gp, &grave_pages, list)
881 if (gp->page_no == page_no) {
882 if (gp->reads_done >= gp->max_reads)
883 return 1;
884 gp->reads_done += 1;
885 return 0;
886 }
887 return 0;
888}
889
890static void free_lists(void)
891{
892 struct list_head *pos, *n;
893 list_for_each_safe(pos, n, &weak_blocks) {
894 list_del(pos);
895 kfree(list_entry(pos, struct weak_block, list));
896 }
897 list_for_each_safe(pos, n, &weak_pages) {
898 list_del(pos);
899 kfree(list_entry(pos, struct weak_page, list));
900 }
901 list_for_each_safe(pos, n, &grave_pages) {
902 list_del(pos);
903 kfree(list_entry(pos, struct grave_page, list));
904 }
57aa6b54
AH		 905 kfree(erase_block_wear);
906}
907
908static int setup_wear_reporting(struct mtd_info *mtd)
909{
910 size_t mem;
911
912 if (!rptwear)
913 return 0;
6eda7a55 914 wear_eb_count = divide(mtd->size, mtd->erasesize);
57aa6b54
AH		 915 mem = wear_eb_count * sizeof(unsigned long);
916 if (mem / sizeof(unsigned long) != wear_eb_count) {
917 NS_ERR("Too many erase blocks for wear reporting\n");
918 return -ENOMEM;
919 }
920 erase_block_wear = kzalloc(mem, GFP_KERNEL);
921 if (!erase_block_wear) {
922 NS_ERR("Too many erase blocks for wear reporting\n");
923 return -ENOMEM;
924 }
925 return 0;
926}
927
928static void update_wear(unsigned int erase_block_no)
929{
930 unsigned long wmin = -1, wmax = 0, avg;
931 unsigned long deciles[10], decile_max[10], tot = 0;
932 unsigned int i;
933
934 if (!erase_block_wear)
935 return;
936 total_wear += 1;
937 if (total_wear == 0)
938 NS_ERR("Erase counter total overflow\n");
939 erase_block_wear[erase_block_no] += 1;
940 if (erase_block_wear[erase_block_no] == 0)
941 NS_ERR("Erase counter overflow for erase block %u\n", erase_block_no);
942 rptwear_cnt += 1;
943 if (rptwear_cnt < rptwear)
944 return;
945 rptwear_cnt = 0;
946 /* Calc wear stats */
947 for (i = 0; i < wear_eb_count; ++i) {
948 unsigned long wear = erase_block_wear[i];
949 if (wear < wmin)
950 wmin = wear;
951 if (wear > wmax)
952 wmax = wear;
953 tot += wear;
954 }
955 for (i = 0; i < 9; ++i) {
956 deciles[i] = 0;
957 decile_max[i] = (wmax * (i + 1) + 5) / 10;
958 }
959 deciles[9] = 0;
960 decile_max[9] = wmax;
961 for (i = 0; i < wear_eb_count; ++i) {
962 int d;
963 unsigned long wear = erase_block_wear[i];
964 for (d = 0; d < 10; ++d)
965 if (wear <= decile_max[d]) {
966 deciles[d] += 1;
967 break;
968 }
969 }
970 avg = tot / wear_eb_count;
971 /* Output wear report */
972 NS_INFO("*** Wear Report ***\n");
973 NS_INFO("Total numbers of erases: %lu\n", tot);
974 NS_INFO("Number of erase blocks: %u\n", wear_eb_count);
975 NS_INFO("Average number of erases: %lu\n", avg);
976 NS_INFO("Maximum number of erases: %lu\n", wmax);
977 NS_INFO("Minimum number of erases: %lu\n", wmin);
978 for (i = 0; i < 10; ++i) {
979 unsigned long from = (i ? decile_max[i - 1] + 1 : 0);
980 if (from > decile_max[i])
981 continue;
982 NS_INFO("Number of ebs with erase counts from %lu to %lu : %lu\n",
983 from,
984 decile_max[i],
985 deciles[i]);
986 }
987 NS_INFO("*** End of Wear Report ***\n");
514087e7
AH		 988}
989
1da177e4
LT		 990/*
991 * Returns the string representation of 'state' state.
992 */
a5602146 993static char *get_state_name(uint32_t state)
1da177e4
LT		 994{
995 switch (NS_STATE(state)) {
996 case STATE_CMD_READ0:
997 return "STATE_CMD_READ0";
998 case STATE_CMD_READ1:
999 return "STATE_CMD_READ1";
1000 case STATE_CMD_PAGEPROG:
1001 return "STATE_CMD_PAGEPROG";
1002 case STATE_CMD_READOOB:
1003 return "STATE_CMD_READOOB";
1004 case STATE_CMD_READSTART:
1005 return "STATE_CMD_READSTART";
1006 case STATE_CMD_ERASE1:
1007 return "STATE_CMD_ERASE1";
1008 case STATE_CMD_STATUS:
1009 return "STATE_CMD_STATUS";
1010 case STATE_CMD_STATUS_M:
1011 return "STATE_CMD_STATUS_M";
1012 case STATE_CMD_SEQIN:
1013 return "STATE_CMD_SEQIN";
1014 case STATE_CMD_READID:
1015 return "STATE_CMD_READID";
1016 case STATE_CMD_ERASE2:
1017 return "STATE_CMD_ERASE2";
1018 case STATE_CMD_RESET:
1019 return "STATE_CMD_RESET";
74216be4
AB		 1020 case STATE_CMD_RNDOUT:
1021 return "STATE_CMD_RNDOUT";
1022 case STATE_CMD_RNDOUTSTART:
1023 return "STATE_CMD_RNDOUTSTART";
1da177e4
LT		 1024 case STATE_ADDR_PAGE:
1025 return "STATE_ADDR_PAGE";
1026 case STATE_ADDR_SEC:
1027 return "STATE_ADDR_SEC";
1028 case STATE_ADDR_ZERO:
1029 return "STATE_ADDR_ZERO";
74216be4
AB		 1030 case STATE_ADDR_COLUMN:
1031 return "STATE_ADDR_COLUMN";
1da177e4
LT		 1032 case STATE_DATAIN:
1033 return "STATE_DATAIN";
1034 case STATE_DATAOUT:
1035 return "STATE_DATAOUT";
1036 case STATE_DATAOUT_ID:
1037 return "STATE_DATAOUT_ID";
1038 case STATE_DATAOUT_STATUS:
1039 return "STATE_DATAOUT_STATUS";
1040 case STATE_DATAOUT_STATUS_M:
1041 return "STATE_DATAOUT_STATUS_M";
1042 case STATE_READY:
1043 return "STATE_READY";
1044 case STATE_UNKNOWN:
1045 return "STATE_UNKNOWN";
1046 }
1047
1048 NS_ERR("get_state_name: unknown state, BUG\n");
1049 return NULL;
1050}
1051
1052/*
1053 * Check if command is valid.
1054 *
1055 * RETURNS: 1 if wrong command, 0 if right.
1056 */
a5602146 1057static int check_command(int cmd)
1da177e4
LT		 1058{
1059 switch (cmd) {
61b03bd7 1060
1da177e4 1061 case NAND_CMD_READ0:
74216be4 1062 case NAND_CMD_READ1:
1da177e4
LT		 1063 case NAND_CMD_READSTART:
1064 case NAND_CMD_PAGEPROG:
1065 case NAND_CMD_READOOB:
1066 case NAND_CMD_ERASE1:
1067 case NAND_CMD_STATUS:
1068 case NAND_CMD_SEQIN:
1069 case NAND_CMD_READID:
1070 case NAND_CMD_ERASE2:
1071 case NAND_CMD_RESET:
74216be4
AB		 1072 case NAND_CMD_RNDOUT:
1073 case NAND_CMD_RNDOUTSTART:
1da177e4 1074 return 0;
61b03bd7 1075
1da177e4
LT		 1076 case NAND_CMD_STATUS_MULTI:
1077 default:
1078 return 1;
1079 }
1080}
1081
1082/*
1083 * Returns state after command is accepted by command number.
1084 */
a5602146 1085static uint32_t get_state_by_command(unsigned command)
1da177e4
LT		 1086{
1087 switch (command) {
1088 case NAND_CMD_READ0:
1089 return STATE_CMD_READ0;
1090 case NAND_CMD_READ1:
1091 return STATE_CMD_READ1;
1092 case NAND_CMD_PAGEPROG:
1093 return STATE_CMD_PAGEPROG;
1094 case NAND_CMD_READSTART:
1095 return STATE_CMD_READSTART;
1096 case NAND_CMD_READOOB:
1097 return STATE_CMD_READOOB;
1098 case NAND_CMD_ERASE1:
1099 return STATE_CMD_ERASE1;
1100 case NAND_CMD_STATUS:
1101 return STATE_CMD_STATUS;
1102 case NAND_CMD_STATUS_MULTI:
1103 return STATE_CMD_STATUS_M;
1104 case NAND_CMD_SEQIN:
1105 return STATE_CMD_SEQIN;
1106 case NAND_CMD_READID:
1107 return STATE_CMD_READID;
1108 case NAND_CMD_ERASE2:
1109 return STATE_CMD_ERASE2;
1110 case NAND_CMD_RESET:
1111 return STATE_CMD_RESET;
74216be4
AB		 1112 case NAND_CMD_RNDOUT:
1113 return STATE_CMD_RNDOUT;
1114 case NAND_CMD_RNDOUTSTART:
1115 return STATE_CMD_RNDOUTSTART;
1da177e4
LT		 1116 }
1117
1118 NS_ERR("get_state_by_command: unknown command, BUG\n");
1119 return 0;
1120}
1121
1122/*
1123 * Move an address byte to the correspondent internal register.
1124 */
a5602146 1125static inline void accept_addr_byte(struct nandsim *ns, u_char bt)
1da177e4
LT		 1126{
1127 uint byte = (uint)bt;
61b03bd7 1128
1da177e4
LT		 1129 if (ns->regs.count < (ns->geom.pgaddrbytes - ns->geom.secaddrbytes))
1130 ns->regs.column |= (byte << 8 * ns->regs.count);
1131 else {
1132 ns->regs.row |= (byte << 8 * (ns->regs.count -
1133 ns->geom.pgaddrbytes +
1134 ns->geom.secaddrbytes));
1135 }
1136
1137 return;
1138}
61b03bd7 1139
1da177e4
LT		 1140/*
1141 * Switch to STATE_READY state.
1142 */
a5602146 1143static inline void switch_to_ready_state(struct nandsim *ns, u_char status)
1da177e4
LT		 1144{
1145 NS_DBG("switch_to_ready_state: switch to %s state\n", get_state_name(STATE_READY));
1146
1147 ns->state = STATE_READY;
1148 ns->nxstate = STATE_UNKNOWN;
1149 ns->op = NULL;
1150 ns->npstates = 0;
1151 ns->stateidx = 0;
1152 ns->regs.num = 0;
1153 ns->regs.count = 0;
1154 ns->regs.off = 0;
1155 ns->regs.row = 0;
1156 ns->regs.column = 0;
1157 ns->regs.status = status;
1158}
1159
1160/*
1161 * If the operation isn't known yet, try to find it in the global array
1162 * of supported operations.
1163 *
1164 * Operation can be unknown because of the following.
1165 * 1. New command was accepted and this is the firs call to find the
1166 * correspondent states chain. In this case ns->npstates = 0;
1167 * 2. There is several operations which begin with the same command(s)
1168 * (for example program from the second half and read from the
1169 * second half operations both begin with the READ1 command). In this
1170 * case the ns->pstates[] array contains previous states.
61b03bd7 1171 *
1da177e4
LT		 1172 * Thus, the function tries to find operation containing the following
1173 * states (if the 'flag' parameter is 0):
1174 * ns->pstates[0], ... ns->pstates[ns->npstates], ns->state
1175 *
1176 * If (one and only one) matching operation is found, it is accepted (
1177 * ns->ops, ns->state, ns->nxstate are initialized, ns->npstate is
1178 * zeroed).
61b03bd7 1179 *
1da177e4
LT		 1180 * If there are several maches, the current state is pushed to the
1181 * ns->pstates.
1182 *
1183 * The operation can be unknown only while commands are input to the chip.
1184 * As soon as address command is accepted, the operation must be known.
1185 * In such situation the function is called with 'flag' != 0, and the
1186 * operation is searched using the following pattern:
1187 * ns->pstates[0], ... ns->pstates[ns->npstates], <address input>
61b03bd7 1188 *
1da177e4
LT		 1189 * It is supposed that this pattern must either match one operation on
1190 * none. There can't be ambiguity in that case.
1191 *
1192 * If no matches found, the functions does the following:
1193 * 1. if there are saved states present, try to ignore them and search
1194 * again only using the last command. If nothing was found, switch
1195 * to the STATE_READY state.
1196 * 2. if there are no saved states, switch to the STATE_READY state.
1197 *
1198 * RETURNS: -2 - no matched operations found.
1199 * -1 - several matches.
1200 * 0 - operation is found.
1201 */
a5602146 1202static int find_operation(struct nandsim *ns, uint32_t flag)
1da177e4
LT		 1203{
1204 int opsfound = 0;
1205 int i, j, idx = 0;
61b03bd7 1206
1da177e4
LT		 1207 for (i = 0; i < NS_OPER_NUM; i++) {
1208
1209 int found = 1;
61b03bd7 1210
1da177e4
LT		 1211 if (!(ns->options & ops[i].reqopts))
1212 /* Ignore operations we can't perform */
1213 continue;
61b03bd7 1214
1da177e4
LT		 1215 if (flag) {
1216 if (!(ops[i].states[ns->npstates] & STATE_ADDR_MASK))
1217 continue;
1218 } else {
1219 if (NS_STATE(ns->state) != NS_STATE(ops[i].states[ns->npstates]))
1220 continue;
1221 }
1222
61b03bd7 1223 for (j = 0; j < ns->npstates; j++)
1da177e4
LT		 1224 if (NS_STATE(ops[i].states[j]) != NS_STATE(ns->pstates[j])
1225 && (ns->options & ops[idx].reqopts)) {
1226 found = 0;
1227 break;
1228 }
1229
1230 if (found) {
1231 idx = i;
1232 opsfound += 1;
1233 }
1234 }
1235
1236 if (opsfound == 1) {
1237 /* Exact match */
1238 ns->op = &ops[idx].states[0];
1239 if (flag) {
61b03bd7 1240 /*
1da177e4
LT		 1241 * In this case the find_operation function was
1242 * called when address has just began input. But it isn't
1243 * yet fully input and the current state must
1244 * not be one of STATE_ADDR_*, but the STATE_ADDR_*
1245 * state must be the next state (ns->nxstate).
1246 */
1247 ns->stateidx = ns->npstates - 1;
1248 } else {
1249 ns->stateidx = ns->npstates;
1250 }
1251 ns->npstates = 0;
1252 ns->state = ns->op[ns->stateidx];
1253 ns->nxstate = ns->op[ns->stateidx + 1];
1254 NS_DBG("find_operation: operation found, index: %d, state: %s, nxstate %s\n",
1255 idx, get_state_name(ns->state), get_state_name(ns->nxstate));
1256 return 0;
1257 }
61b03bd7 1258
1da177e4
LT		 1259 if (opsfound == 0) {
1260 /* Nothing was found. Try to ignore previous commands (if any) and search again */
1261 if (ns->npstates != 0) {
1262 NS_DBG("find_operation: no operation found, try again with state %s\n",
1263 get_state_name(ns->state));
1264 ns->npstates = 0;
1265 return find_operation(ns, 0);
1266
1267 }
1268 NS_DBG("find_operation: no operations found\n");
1269 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1270 return -2;
1271 }
61b03bd7 1272
1da177e4
LT		 1273 if (flag) {
1274 /* This shouldn't happen */
1275 NS_DBG("find_operation: BUG, operation must be known if address is input\n");
1276 return -2;
1277 }
61b03bd7 1278
1da177e4
LT		 1279 NS_DBG("find_operation: there is still ambiguity\n");
1280
1281 ns->pstates[ns->npstates++] = ns->state;
1282
1283 return -1;
1284}
1285
a9fc8991
AH		 1286static void put_pages(struct nandsim *ns)
1287{
1288 int i;
1289
1290 for (i = 0; i < ns->held_cnt; i++)
1291 page_cache_release(ns->held_pages[i]);
1292}
1293
1294/* Get page cache pages in advance to provide NOFS memory allocation */
1295static int get_pages(struct nandsim *ns, struct file *file, size_t count, loff_t pos)
1296{
1297 pgoff_t index, start_index, end_index;
1298 struct page *page;
1299 struct address_space *mapping = file->f_mapping;
1300
1301 start_index = pos >> PAGE_CACHE_SHIFT;
1302 end_index = (pos + count - 1) >> PAGE_CACHE_SHIFT;
1303 if (end_index - start_index + 1 > NS_MAX_HELD_PAGES)
1304 return -EINVAL;
1305 ns->held_cnt = 0;
1306 for (index = start_index; index <= end_index; index++) {
1307 page = find_get_page(mapping, index);
1308 if (page == NULL) {
1309 page = find_or_create_page(mapping, index, GFP_NOFS);
1310 if (page == NULL) {
1311 write_inode_now(mapping->host, 1);
1312 page = find_or_create_page(mapping, index, GFP_NOFS);
1313 }
1314 if (page == NULL) {
1315 put_pages(ns);
1316 return -ENOMEM;
1317 }
1318 unlock_page(page);
1319 }
1320 ns->held_pages[ns->held_cnt++] = page;
1321 }
1322 return 0;
1323}
1324
1325static int set_memalloc(void)
1326{
1327 if (current->flags & PF_MEMALLOC)
1328 return 0;
1329 current->flags |= PF_MEMALLOC;
1330 return 1;
1331}
1332
1333static void clear_memalloc(int memalloc)
1334{
1335 if (memalloc)
1336 current->flags &= ~PF_MEMALLOC;
1337}
1338
1339static ssize_t read_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t *pos)
1340{
1341 mm_segment_t old_fs;
1342 ssize_t tx;
1343 int err, memalloc;
1344
1345 err = get_pages(ns, file, count, *pos);
1346 if (err)
1347 return err;
1348 old_fs = get_fs();
1349 set_fs(get_ds());
1350 memalloc = set_memalloc();
1351 tx = vfs_read(file, (char __user *)buf, count, pos);
1352 clear_memalloc(memalloc);
1353 set_fs(old_fs);
1354 put_pages(ns);
1355 return tx;
1356}
1357
1358static ssize_t write_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t *pos)
1359{
1360 mm_segment_t old_fs;
1361 ssize_t tx;
1362 int err, memalloc;
1363
1364 err = get_pages(ns, file, count, *pos);
1365 if (err)
1366 return err;
1367 old_fs = get_fs();
1368 set_fs(get_ds());
1369 memalloc = set_memalloc();
1370 tx = vfs_write(file, (char __user *)buf, count, pos);
1371 clear_memalloc(memalloc);
1372 set_fs(old_fs);
1373 put_pages(ns);
1374 return tx;
1375}
1376
d086d436
VK		 1377/*
1378 * Returns a pointer to the current page.
1379 */
1380static inline union ns_mem *NS_GET_PAGE(struct nandsim *ns)
1381{
1382 return &(ns->pages[ns->regs.row]);
1383}
1384
1385/*
1386 * Retuns a pointer to the current byte, within the current page.
1387 */
1388static inline u_char *NS_PAGE_BYTE_OFF(struct nandsim *ns)
1389{
1390 return NS_GET_PAGE(ns)->byte + ns->regs.column + ns->regs.off;
1391}
1392
a9fc8991
AH		 1393int do_read_error(struct nandsim *ns, int num)
1394{
1395 unsigned int page_no = ns->regs.row;
1396
1397 if (read_error(page_no)) {
1398 int i;
1399 memset(ns->buf.byte, 0xFF, num);
1400 for (i = 0; i < num; ++i)
1401 ns->buf.byte[i] = random32();
1402 NS_WARN("simulating read error in page %u\n", page_no);
1403 return 1;
1404 }
1405 return 0;
1406}
1407
1408void do_bit_flips(struct nandsim *ns, int num)
1409{
1410 if (bitflips && random32() < (1 << 22)) {
1411 int flips = 1;
1412 if (bitflips > 1)
1413 flips = (random32() % (int) bitflips) + 1;
1414 while (flips--) {
1415 int pos = random32() % (num * 8);
1416 ns->buf.byte[pos / 8] ^= (1 << (pos % 8));
1417 NS_WARN("read_page: flipping bit %d in page %d "
1418 "reading from %d ecc: corrected=%u failed=%u\n",
1419 pos, ns->regs.row, ns->regs.column + ns->regs.off,
1420 nsmtd->ecc_stats.corrected, nsmtd->ecc_stats.failed);
1421 }
1422 }
1423}
1424
d086d436
VK		 1425/*
1426 * Fill the NAND buffer with data read from the specified page.
1427 */
1428static void read_page(struct nandsim *ns, int num)
1429{
1430 union ns_mem *mypage;
1431
a9fc8991
AH		 1432 if (ns->cfile) {
1433 if (!ns->pages_written[ns->regs.row]) {
1434 NS_DBG("read_page: page %d not written\n", ns->regs.row);
1435 memset(ns->buf.byte, 0xFF, num);
1436 } else {
1437 loff_t pos;
1438 ssize_t tx;
1439
1440 NS_DBG("read_page: page %d written, reading from %d\n",
1441 ns->regs.row, ns->regs.column + ns->regs.off);
1442 if (do_read_error(ns, num))
1443 return;
1444 pos = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off;
1445 tx = read_file(ns, ns->cfile, ns->buf.byte, num, &pos);
1446 if (tx != num) {
1447 NS_ERR("read_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1448 return;
1449 }
1450 do_bit_flips(ns, num);
1451 }
1452 return;
1453 }
1454
d086d436
VK		 1455 mypage = NS_GET_PAGE(ns);
1456 if (mypage->byte == NULL) {
1457 NS_DBG("read_page: page %d not allocated\n", ns->regs.row);
1458 memset(ns->buf.byte, 0xFF, num);
1459 } else {
1460 NS_DBG("read_page: page %d allocated, reading from %d\n",
1461 ns->regs.row, ns->regs.column + ns->regs.off);
a9fc8991 1462 if (do_read_error(ns, num))
514087e7 1463 return;
d086d436 1464 memcpy(ns->buf.byte, NS_PAGE_BYTE_OFF(ns), num);
a9fc8991 1465 do_bit_flips(ns, num);
d086d436
VK		 1466 }
1467}
1468
1469/*
1470 * Erase all pages in the specified sector.
1471 */
1472static void erase_sector(struct nandsim *ns)
1473{
1474 union ns_mem *mypage;
1475 int i;
1476
a9fc8991
AH		 1477 if (ns->cfile) {
1478 for (i = 0; i < ns->geom.pgsec; i++)
1479 if (ns->pages_written[ns->regs.row + i]) {
1480 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row + i);
1481 ns->pages_written[ns->regs.row + i] = 0;
1482 }
1483 return;
1484 }
1485
d086d436
VK		 1486 mypage = NS_GET_PAGE(ns);
1487 for (i = 0; i < ns->geom.pgsec; i++) {
1488 if (mypage->byte != NULL) {
1489 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row+i);
8a4c2495 1490 kmem_cache_free(ns->nand_pages_slab, mypage->byte);
d086d436
VK		 1491 mypage->byte = NULL;
1492 }
1493 mypage++;
1494 }
1495}
1496
1497/*
1498 * Program the specified page with the contents from the NAND buffer.
1499 */
1500static int prog_page(struct nandsim *ns, int num)
1501{
82810b7b 1502 int i;
d086d436
VK		 1503 union ns_mem *mypage;
1504 u_char *pg_off;
1505
a9fc8991
AH		 1506 if (ns->cfile) {
1507 loff_t off, pos;
1508 ssize_t tx;
1509 int all;
1510
1511 NS_DBG("prog_page: writing page %d\n", ns->regs.row);
1512 pg_off = ns->file_buf + ns->regs.column + ns->regs.off;
1513 off = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off;
1514 if (!ns->pages_written[ns->regs.row]) {
1515 all = 1;
1516 memset(ns->file_buf, 0xff, ns->geom.pgszoob);
1517 } else {
1518 all = 0;
1519 pos = off;
1520 tx = read_file(ns, ns->cfile, pg_off, num, &pos);
1521 if (tx != num) {
1522 NS_ERR("prog_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1523 return -1;
1524 }
1525 }
1526 for (i = 0; i < num; i++)
1527 pg_off[i] &= ns->buf.byte[i];
1528 if (all) {
1529 pos = (loff_t)ns->regs.row * ns->geom.pgszoob;
1530 tx = write_file(ns, ns->cfile, ns->file_buf, ns->geom.pgszoob, &pos);
1531 if (tx != ns->geom.pgszoob) {
1532 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1533 return -1;
1534 }
1535 ns->pages_written[ns->regs.row] = 1;
1536 } else {
1537 pos = off;
1538 tx = write_file(ns, ns->cfile, pg_off, num, &pos);
1539 if (tx != num) {
1540 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1541 return -1;
1542 }
1543 }
1544 return 0;
1545 }
1546
d086d436
VK		 1547 mypage = NS_GET_PAGE(ns);
1548 if (mypage->byte == NULL) {
1549 NS_DBG("prog_page: allocating page %d\n", ns->regs.row);
98b830d2
AB		 1550 /*
1551 * We allocate memory with GFP_NOFS because a flash FS may
1552 * utilize this. If it is holding an FS lock, then gets here,
8a4c2495
AK		 1553 * then kernel memory alloc runs writeback which goes to the FS
1554 * again and deadlocks. This was seen in practice.
98b830d2 1555 */
8a4c2495 1556 mypage->byte = kmem_cache_alloc(ns->nand_pages_slab, GFP_NOFS);
d086d436
VK		 1557 if (mypage->byte == NULL) {
1558 NS_ERR("prog_page: error allocating memory for page %d\n", ns->regs.row);
1559 return -1;
1560 }
1561 memset(mypage->byte, 0xFF, ns->geom.pgszoob);
1562 }
1563
1564 pg_off = NS_PAGE_BYTE_OFF(ns);
82810b7b
AB		 1565 for (i = 0; i < num; i++)
1566 pg_off[i] &= ns->buf.byte[i];
d086d436
VK		 1567
1568 return 0;
1569}
1570
1da177e4
LT		 1571/*
1572 * If state has any action bit, perform this action.
1573 *
1574 * RETURNS: 0 if success, -1 if error.
1575 */
a5602146 1576static int do_state_action(struct nandsim *ns, uint32_t action)
1da177e4 1577{
d086d436 1578 int num;
1da177e4 1579 int busdiv = ns->busw == 8 ? 1 : 2;
514087e7 1580 unsigned int erase_block_no, page_no;
1da177e4
LT		 1581
1582 action &= ACTION_MASK;
61b03bd7 1583
1da177e4
LT		 1584 /* Check that page address input is correct */
1585 if (action != ACTION_SECERASE && ns->regs.row >= ns->geom.pgnum) {
1586 NS_WARN("do_state_action: wrong page number (%#x)\n", ns->regs.row);
1587 return -1;
1588 }
1589
1590 switch (action) {
1591
1592 case ACTION_CPY:
1593 /*
1594 * Copy page data to the internal buffer.
1595 */
1596
1597 /* Column shouldn't be very large */
1598 if (ns->regs.column >= (ns->geom.pgszoob - ns->regs.off)) {
1599 NS_ERR("do_state_action: column number is too large\n");
1600 break;
1601 }
1602 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
d086d436 1603 read_page(ns, num);
1da177e4
LT		 1604
1605 NS_DBG("do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d\n",
1606 num, NS_RAW_OFFSET(ns) + ns->regs.off);
61b03bd7 1607
1da177e4
LT		 1608 if (ns->regs.off == 0)
1609 NS_LOG("read page %d\n", ns->regs.row);
1610 else if (ns->regs.off < ns->geom.pgsz)
1611 NS_LOG("read page %d (second half)\n", ns->regs.row);
1612 else
1613 NS_LOG("read OOB of page %d\n", ns->regs.row);
61b03bd7 1614
1da177e4
LT		 1615 NS_UDELAY(access_delay);
1616 NS_UDELAY(input_cycle * ns->geom.pgsz / 1000 / busdiv);
1617
1618 break;
1619
1620 case ACTION_SECERASE:
1621 /*
1622 * Erase sector.
1623 */
61b03bd7 1624
1da177e4
LT		 1625 if (ns->lines.wp) {
1626 NS_ERR("do_state_action: device is write-protected, ignore sector erase\n");
1627 return -1;
1628 }
61b03bd7 1629
1da177e4
LT		 1630 if (ns->regs.row >= ns->geom.pgnum - ns->geom.pgsec
1631 || (ns->regs.row & ~(ns->geom.secsz - 1))) {
1632 NS_ERR("do_state_action: wrong sector address (%#x)\n", ns->regs.row);
1633 return -1;
1634 }
61b03bd7 1635
1da177e4
LT		 1636 ns->regs.row = (ns->regs.row <<
1637 8 * (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) | ns->regs.column;
1638 ns->regs.column = 0;
61b03bd7 1639
514087e7
AH		 1640 erase_block_no = ns->regs.row >> (ns->geom.secshift - ns->geom.pgshift);
1641
1da177e4
LT		 1642 NS_DBG("do_state_action: erase sector at address %#x, off = %d\n",
1643 ns->regs.row, NS_RAW_OFFSET(ns));
514087e7 1644 NS_LOG("erase sector %u\n", erase_block_no);
1da177e4 1645
d086d436 1646 erase_sector(ns);
61b03bd7 1647
1da177e4 1648 NS_MDELAY(erase_delay);
61b03bd7 1649
57aa6b54
AH		 1650 if (erase_block_wear)
1651 update_wear(erase_block_no);
1652
514087e7
AH		 1653 if (erase_error(erase_block_no)) {
1654 NS_WARN("simulating erase failure in erase block %u\n", erase_block_no);
1655 return -1;
1656 }
1657
1da177e4
LT		 1658 break;
1659
1660 case ACTION_PRGPAGE:
1661 /*
1662 * Programm page - move internal buffer data to the page.
1663 */
1664
1665 if (ns->lines.wp) {
1666 NS_WARN("do_state_action: device is write-protected, programm\n");
1667 return -1;
1668 }
1669
1670 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1671 if (num != ns->regs.count) {
1672 NS_ERR("do_state_action: too few bytes were input (%d instead of %d)\n",
1673 ns->regs.count, num);
1674 return -1;
1675 }
1676
d086d436
VK		 1677 if (prog_page(ns, num) == -1)
1678 return -1;
1da177e4 1679
514087e7
AH		 1680 page_no = ns->regs.row;
1681
1da177e4
LT		 1682 NS_DBG("do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d\n",
1683 num, ns->regs.row, ns->regs.column, NS_RAW_OFFSET(ns) + ns->regs.off);
1684 NS_LOG("programm page %d\n", ns->regs.row);
61b03bd7 1685
1da177e4
LT		 1686 NS_UDELAY(programm_delay);
1687 NS_UDELAY(output_cycle * ns->geom.pgsz / 1000 / busdiv);
61b03bd7 1688
514087e7
AH		 1689 if (write_error(page_no)) {
1690 NS_WARN("simulating write failure in page %u\n", page_no);
1691 return -1;
1692 }
1693
1da177e4 1694 break;
61b03bd7 1695
1da177e4
LT		 1696 case ACTION_ZEROOFF:
1697 NS_DBG("do_state_action: set internal offset to 0\n");
1698 ns->regs.off = 0;
1699 break;
1700
1701 case ACTION_HALFOFF:
1702 if (!(ns->options & OPT_PAGE512_8BIT)) {
1703 NS_ERR("do_state_action: BUG! can't skip half of page for non-512"
1704 "byte page size 8x chips\n");
1705 return -1;
1706 }
1707 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz/2);
1708 ns->regs.off = ns->geom.pgsz/2;
1709 break;
1710
1711 case ACTION_OOBOFF:
1712 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz);
1713 ns->regs.off = ns->geom.pgsz;
1714 break;
61b03bd7 1715
1da177e4
LT		 1716 default:
1717 NS_DBG("do_state_action: BUG! unknown action\n");
1718 }
1719
1720 return 0;
1721}
1722
1723/*
1724 * Switch simulator's state.
1725 */
a5602146 1726static void switch_state(struct nandsim *ns)
1da177e4
LT		 1727{
1728 if (ns->op) {
1729 /*
1730 * The current operation have already been identified.
1731 * Just follow the states chain.
1732 */
61b03bd7 1733
1da177e4
LT		 1734 ns->stateidx += 1;
1735 ns->state = ns->nxstate;
1736 ns->nxstate = ns->op[ns->stateidx + 1];
1737
1738 NS_DBG("switch_state: operation is known, switch to the next state, "
1739 "state: %s, nxstate: %s\n",
1740 get_state_name(ns->state), get_state_name(ns->nxstate));
1741
1742 /* See, whether we need to do some action */
1743 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1744 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1745 return;
1746 }
61b03bd7 1747
1da177e4
LT		 1748 } else {
1749 /*
1750 * We don't yet know which operation we perform.
1751 * Try to identify it.
1752 */
1753
61b03bd7 1754 /*
1da177e4
LT		 1755 * The only event causing the switch_state function to
1756 * be called with yet unknown operation is new command.
1757 */
1758 ns->state = get_state_by_command(ns->regs.command);
1759
1760 NS_DBG("switch_state: operation is unknown, try to find it\n");
1761
1762 if (find_operation(ns, 0) != 0)
1763 return;
1764
1765 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1766 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1767 return;
1768 }
1769 }
1770
1771 /* For 16x devices column means the page offset in words */
1772 if ((ns->nxstate & STATE_ADDR_MASK) && ns->busw == 16) {
1773 NS_DBG("switch_state: double the column number for 16x device\n");
1774 ns->regs.column <<= 1;
1775 }
1776
1777 if (NS_STATE(ns->nxstate) == STATE_READY) {
1778 /*
1779 * The current state is the last. Return to STATE_READY
1780 */
1781
1782 u_char status = NS_STATUS_OK(ns);
61b03bd7 1783
1da177e4
LT		 1784 /* In case of data states, see if all bytes were input/output */
1785 if ((ns->state & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK))
1786 && ns->regs.count != ns->regs.num) {
1787 NS_WARN("switch_state: not all bytes were processed, %d left\n",
1788 ns->regs.num - ns->regs.count);
1789 status = NS_STATUS_FAILED(ns);
1790 }
61b03bd7 1791
1da177e4
LT		 1792 NS_DBG("switch_state: operation complete, switch to STATE_READY state\n");
1793
1794 switch_to_ready_state(ns, status);
1795
1796 return;
1797 } else if (ns->nxstate & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK)) {
61b03bd7 1798 /*
1da177e4
LT		 1799 * If the next state is data input/output, switch to it now
1800 */
61b03bd7 1801
1da177e4
LT		 1802 ns->state = ns->nxstate;
1803 ns->nxstate = ns->op[++ns->stateidx + 1];
1804 ns->regs.num = ns->regs.count = 0;
1805
1806 NS_DBG("switch_state: the next state is data I/O, switch, "
1807 "state: %s, nxstate: %s\n",
1808 get_state_name(ns->state), get_state_name(ns->nxstate));
1809
1810 /*
1811 * Set the internal register to the count of bytes which
1812 * are expected to be input or output
1813 */
1814 switch (NS_STATE(ns->state)) {
1815 case STATE_DATAIN:
1816 case STATE_DATAOUT:
1817 ns->regs.num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1818 break;
61b03bd7 1819
1da177e4
LT		 1820 case STATE_DATAOUT_ID:
1821 ns->regs.num = ns->geom.idbytes;
1822 break;
61b03bd7 1823
1da177e4
LT		 1824 case STATE_DATAOUT_STATUS:
1825 case STATE_DATAOUT_STATUS_M:
1826 ns->regs.count = ns->regs.num = 0;
1827 break;
61b03bd7 1828
1da177e4
LT		 1829 default:
1830 NS_ERR("switch_state: BUG! unknown data state\n");
1831 }
1832
1833 } else if (ns->nxstate & STATE_ADDR_MASK) {
1834 /*
1835 * If the next state is address input, set the internal
1836 * register to the number of expected address bytes
1837 */
1838
1839 ns->regs.count = 0;
61b03bd7 1840
1da177e4
LT		 1841 switch (NS_STATE(ns->nxstate)) {
1842 case STATE_ADDR_PAGE:
1843 ns->regs.num = ns->geom.pgaddrbytes;
61b03bd7 1844
1da177e4
LT		 1845 break;
1846 case STATE_ADDR_SEC:
1847 ns->regs.num = ns->geom.secaddrbytes;
1848 break;
61b03bd7 1849
1da177e4
LT		 1850 case STATE_ADDR_ZERO:
1851 ns->regs.num = 1;
1852 break;
1853
74216be4
AB		 1854 case STATE_ADDR_COLUMN:
1855 /* Column address is always 2 bytes */
1856 ns->regs.num = ns->geom.pgaddrbytes - ns->geom.secaddrbytes;
1857 break;
1858
1da177e4
LT		 1859 default:
1860 NS_ERR("switch_state: BUG! unknown address state\n");
1861 }
1862 } else {
61b03bd7 1863 /*
1da177e4
LT		 1864 * Just reset internal counters.
1865 */
1866
1867 ns->regs.num = 0;
1868 ns->regs.count = 0;
1869 }
1870}
1871
a5602146 1872static u_char ns_nand_read_byte(struct mtd_info *mtd)
1da177e4
LT		 1873{
1874 struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv;
1875 u_char outb = 0x00;
1876
1877 /* Sanity and correctness checks */
1878 if (!ns->lines.ce) {
1879 NS_ERR("read_byte: chip is disabled, return %#x\n", (uint)outb);
1880 return outb;
1881 }
1882 if (ns->lines.ale || ns->lines.cle) {
1883 NS_ERR("read_byte: ALE or CLE pin is high, return %#x\n", (uint)outb);
1884 return outb;
1885 }
1886 if (!(ns->state & STATE_DATAOUT_MASK)) {
1887 NS_WARN("read_byte: unexpected data output cycle, state is %s "
1888 "return %#x\n", get_state_name(ns->state), (uint)outb);
1889 return outb;
1890 }
1891
1892 /* Status register may be read as many times as it is wanted */
1893 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS) {
1894 NS_DBG("read_byte: return %#x status\n", ns->regs.status);
1895 return ns->regs.status;
1896 }
1897
1898 /* Check if there is any data in the internal buffer which may be read */
1899 if (ns->regs.count == ns->regs.num) {
1900 NS_WARN("read_byte: no more data to output, return %#x\n", (uint)outb);
1901 return outb;
1902 }
1903
1904 switch (NS_STATE(ns->state)) {
1905 case STATE_DATAOUT:
1906 if (ns->busw == 8) {
1907 outb = ns->buf.byte[ns->regs.count];
1908 ns->regs.count += 1;
1909 } else {
1910 outb = (u_char)cpu_to_le16(ns->buf.word[ns->regs.count >> 1]);
1911 ns->regs.count += 2;
1912 }
1913 break;
1914 case STATE_DATAOUT_ID:
1915 NS_DBG("read_byte: read ID byte %d, total = %d\n", ns->regs.count, ns->regs.num);
1916 outb = ns->ids[ns->regs.count];
1917 ns->regs.count += 1;
1918 break;
1919 default:
1920 BUG();
1921 }
61b03bd7 1922
1da177e4
LT		 1923 if (ns->regs.count == ns->regs.num) {
1924 NS_DBG("read_byte: all bytes were read\n");
1925
1926 /*
1927 * The OPT_AUTOINCR allows to read next conseqitive pages without
1928 * new read operation cycle.
1929 */
1930 if ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT) {
1931 ns->regs.count = 0;
1932 if (ns->regs.row + 1 < ns->geom.pgnum)
1933 ns->regs.row += 1;
1934 NS_DBG("read_byte: switch to the next page (%#x)\n", ns->regs.row);
1935 do_state_action(ns, ACTION_CPY);
1936 }
1937 else if (NS_STATE(ns->nxstate) == STATE_READY)
1938 switch_state(ns);
61b03bd7 1939
1da177e4 1940 }
61b03bd7 1941
1da177e4
LT		 1942 return outb;
1943}
1944
a5602146 1945static void ns_nand_write_byte(struct mtd_info *mtd, u_char byte)
1da177e4
LT		 1946{
1947 struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv;
61b03bd7 1948
1da177e4
LT		 1949 /* Sanity and correctness checks */
1950 if (!ns->lines.ce) {
1951 NS_ERR("write_byte: chip is disabled, ignore write\n");
1952 return;
1953 }
1954 if (ns->lines.ale && ns->lines.cle) {
1955 NS_ERR("write_byte: ALE and CLE pins are high simultaneously, ignore write\n");
1956 return;
1957 }
61b03bd7 1958
1da177e4
LT		 1959 if (ns->lines.cle == 1) {
1960 /*
1961 * The byte written is a command.
1962 */
1963
1964 if (byte == NAND_CMD_RESET) {
1965 NS_LOG("reset chip\n");
1966 switch_to_ready_state(ns, NS_STATUS_OK(ns));
1967 return;
1968 }
1969
74216be4
AB		 1970 /* Check that the command byte is correct */
1971 if (check_command(byte)) {
1972 NS_ERR("write_byte: unknown command %#x\n", (uint)byte);
1973 return;
1974 }
1975
1da177e4
LT		 1976 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS
1977 || NS_STATE(ns->state) == STATE_DATAOUT_STATUS_M
74216be4
AB		 1978 || NS_STATE(ns->state) == STATE_DATAOUT) {
1979 int row = ns->regs.row;
1980
1da177e4 1981 switch_state(ns);
74216be4
AB		 1982 if (byte == NAND_CMD_RNDOUT)
1983 ns->regs.row = row;
1984 }
1da177e4
LT		 1985
1986 /* Check if chip is expecting command */
1987 if (NS_STATE(ns->nxstate) != STATE_UNKNOWN && !(ns->nxstate & STATE_CMD_MASK)) {
9359ea46
AH		 1988 /* Do not warn if only 2 id bytes are read */
1989 if (!(ns->regs.command == NAND_CMD_READID &&
1990 NS_STATE(ns->state) == STATE_DATAOUT_ID && ns->regs.count == 2)) {
1991 /*
1992 * We are in situation when something else (not command)
1993 * was expected but command was input. In this case ignore
1994 * previous command(s)/state(s) and accept the last one.
1995 */
1996 NS_WARN("write_byte: command (%#x) wasn't expected, expected state is %s, "
1997 "ignore previous states\n", (uint)byte, get_state_name(ns->nxstate));
1998 }
1da177e4
LT		 1999 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2000 }
61b03bd7 2001
1da177e4
LT		 2002 NS_DBG("command byte corresponding to %s state accepted\n",
2003 get_state_name(get_state_by_command(byte)));
2004 ns->regs.command = byte;
2005 switch_state(ns);
2006
2007 } else if (ns->lines.ale == 1) {
2008 /*
2009 * The byte written is an address.
2010 */
2011
2012 if (NS_STATE(ns->nxstate) == STATE_UNKNOWN) {
2013
2014 NS_DBG("write_byte: operation isn't known yet, identify it\n");
2015
2016 if (find_operation(ns, 1) < 0)
2017 return;
61b03bd7 2018
1da177e4
LT		 2019 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
2020 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2021 return;
2022 }
61b03bd7 2023
1da177e4
LT		 2024 ns->regs.count = 0;
2025 switch (NS_STATE(ns->nxstate)) {
2026 case STATE_ADDR_PAGE:
2027 ns->regs.num = ns->geom.pgaddrbytes;
2028 break;
2029 case STATE_ADDR_SEC:
2030 ns->regs.num = ns->geom.secaddrbytes;
2031 break;
2032 case STATE_ADDR_ZERO:
2033 ns->regs.num = 1;
2034 break;
2035 default:
2036 BUG();
2037 }
2038 }
2039
2040 /* Check that chip is expecting address */
2041 if (!(ns->nxstate & STATE_ADDR_MASK)) {
2042 NS_ERR("write_byte: address (%#x) isn't expected, expected state is %s, "
2043 "switch to STATE_READY\n", (uint)byte, get_state_name(ns->nxstate));
2044 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2045 return;
2046 }
61b03bd7 2047
1da177e4
LT		 2048 /* Check if this is expected byte */
2049 if (ns->regs.count == ns->regs.num) {
2050 NS_ERR("write_byte: no more address bytes expected\n");
2051 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2052 return;
2053 }
2054
2055 accept_addr_byte(ns, byte);
2056
2057 ns->regs.count += 1;
2058
2059 NS_DBG("write_byte: address byte %#x was accepted (%d bytes input, %d expected)\n",
2060 (uint)byte, ns->regs.count, ns->regs.num);
2061
2062 if (ns->regs.count == ns->regs.num) {
2063 NS_DBG("address (%#x, %#x) is accepted\n", ns->regs.row, ns->regs.column);
2064 switch_state(ns);
2065 }
61b03bd7 2066
1da177e4
LT		 2067 } else {
2068 /*
2069 * The byte written is an input data.
2070 */
61b03bd7 2071
1da177e4
LT		 2072 /* Check that chip is expecting data input */
2073 if (!(ns->state & STATE_DATAIN_MASK)) {
2074 NS_ERR("write_byte: data input (%#x) isn't expected, state is %s, "
2075 "switch to %s\n", (uint)byte,
2076 get_state_name(ns->state), get_state_name(STATE_READY));
2077 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2078 return;
2079 }
2080
2081 /* Check if this is expected byte */
2082 if (ns->regs.count == ns->regs.num) {
2083 NS_WARN("write_byte: %u input bytes has already been accepted, ignore write\n",
2084 ns->regs.num);
2085 return;
2086 }
2087
2088 if (ns->busw == 8) {
2089 ns->buf.byte[ns->regs.count] = byte;
2090 ns->regs.count += 1;
2091 } else {
2092 ns->buf.word[ns->regs.count >> 1] = cpu_to_le16((uint16_t)byte);
2093 ns->regs.count += 2;
2094 }
2095 }
2096
2097 return;
2098}
2099
7abd3ef9
TG		 2100static void ns_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int bitmask)
2101{
2102 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2103
2104 ns->lines.cle = bitmask & NAND_CLE ? 1 : 0;
2105 ns->lines.ale = bitmask & NAND_ALE ? 1 : 0;
2106 ns->lines.ce = bitmask & NAND_NCE ? 1 : 0;
2107
2108 if (cmd != NAND_CMD_NONE)
2109 ns_nand_write_byte(mtd, cmd);
2110}
2111
a5602146 2112static int ns_device_ready(struct mtd_info *mtd)
1da177e4
LT		 2113{
2114 NS_DBG("device_ready\n");
2115 return 1;
2116}
2117
a5602146 2118static uint16_t ns_nand_read_word(struct mtd_info *mtd)
1da177e4
LT		 2119{
2120 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
2121
2122 NS_DBG("read_word\n");
61b03bd7 2123
1da177e4
LT		 2124 return chip->read_byte(mtd) | (chip->read_byte(mtd) << 8);
2125}
2126
a5602146 2127static void ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
1da177e4
LT		 2128{
2129 struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv;
2130
2131 /* Check that chip is expecting data input */
2132 if (!(ns->state & STATE_DATAIN_MASK)) {
2133 NS_ERR("write_buf: data input isn't expected, state is %s, "
2134 "switch to STATE_READY\n", get_state_name(ns->state));
2135 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2136 return;
2137 }
2138
2139 /* Check if these are expected bytes */
2140 if (ns->regs.count + len > ns->regs.num) {
2141 NS_ERR("write_buf: too many input bytes\n");
2142 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2143 return;
2144 }
2145
2146 memcpy(ns->buf.byte + ns->regs.count, buf, len);
2147 ns->regs.count += len;
61b03bd7 2148
1da177e4
LT		 2149 if (ns->regs.count == ns->regs.num) {
2150 NS_DBG("write_buf: %d bytes were written\n", ns->regs.count);
2151 }
2152}
2153
a5602146 2154static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
1da177e4
LT		 2155{
2156 struct nandsim *ns = (struct nandsim *)((struct nand_chip *)mtd->priv)->priv;
2157
2158 /* Sanity and correctness checks */
2159 if (!ns->lines.ce) {
2160 NS_ERR("read_buf: chip is disabled\n");
2161 return;
2162 }
2163 if (ns->lines.ale || ns->lines.cle) {
2164 NS_ERR("read_buf: ALE or CLE pin is high\n");
2165 return;
2166 }
2167 if (!(ns->state & STATE_DATAOUT_MASK)) {
2168 NS_WARN("read_buf: unexpected data output cycle, current state is %s\n",
2169 get_state_name(ns->state));
2170 return;
2171 }
2172
2173 if (NS_STATE(ns->state) != STATE_DATAOUT) {
2174 int i;
2175
2176 for (i = 0; i < len; i++)
2177 buf[i] = ((struct nand_chip *)mtd->priv)->read_byte(mtd);
2178
2179 return;
2180 }
2181
2182 /* Check if these are expected bytes */
2183 if (ns->regs.count + len > ns->regs.num) {
2184 NS_ERR("read_buf: too many bytes to read\n");
2185 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2186 return;
2187 }
2188
2189 memcpy(buf, ns->buf.byte + ns->regs.count, len);
2190 ns->regs.count += len;
61b03bd7 2191
1da177e4
LT		 2192 if (ns->regs.count == ns->regs.num) {
2193 if ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT) {
2194 ns->regs.count = 0;
2195 if (ns->regs.row + 1 < ns->geom.pgnum)
2196 ns->regs.row += 1;
2197 NS_DBG("read_buf: switch to the next page (%#x)\n", ns->regs.row);
2198 do_state_action(ns, ACTION_CPY);
2199 }
2200 else if (NS_STATE(ns->nxstate) == STATE_READY)
2201 switch_state(ns);
2202 }
61b03bd7 2203
1da177e4
LT		 2204 return;
2205}
2206
a5602146 2207static int ns_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
1da177e4
LT		 2208{
2209 ns_nand_read_buf(mtd, (u_char *)&ns_verify_buf[0], len);
2210
2211 if (!memcmp(buf, &ns_verify_buf[0], len)) {
2212 NS_DBG("verify_buf: the buffer is OK\n");
2213 return 0;
2214 } else {
2215 NS_DBG("verify_buf: the buffer is wrong\n");
2216 return -EFAULT;
2217 }
2218}
2219
1da177e4
LT		 2220/*
2221 * Module initialization function
2222 */
2b9175c1 2223static int __init ns_init_module(void)
1da177e4
LT		 2224{
2225 struct nand_chip *chip;
2226 struct nandsim *nand;
2b77a0ed 2227 int retval = -ENOMEM, i;
1da177e4
LT		 2228
2229 if (bus_width != 8 && bus_width != 16) {
2230 NS_ERR("wrong bus width (%d), use only 8 or 16\n", bus_width);
2231 return -EINVAL;
2232 }
61b03bd7 2233
1da177e4 2234 /* Allocate and initialize mtd_info, nand_chip and nandsim structures */
95b93a0c 2235 nsmtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip)
1da177e4
LT		 2236 + sizeof(struct nandsim), GFP_KERNEL);
2237 if (!nsmtd) {
2238 NS_ERR("unable to allocate core structures.\n");
2239 return -ENOMEM;
2240 }
1da177e4
LT		 2241 chip = (struct nand_chip *)(nsmtd + 1);
2242 nsmtd->priv = (void *)chip;
2243 nand = (struct nandsim *)(chip + 1);
61b03bd7 2244 chip->priv = (void *)nand;
1da177e4
LT		 2245
2246 /*
2247 * Register simulator's callbacks.
2248 */
7abd3ef9 2249 chip->cmd_ctrl = ns_hwcontrol;
1da177e4
LT		 2250 chip->read_byte = ns_nand_read_byte;
2251 chip->dev_ready = ns_device_ready;
1da177e4
LT		 2252 chip->write_buf = ns_nand_write_buf;
2253 chip->read_buf = ns_nand_read_buf;
2254 chip->verify_buf = ns_nand_verify_buf;
1da177e4 2255 chip->read_word = ns_nand_read_word;
6dfc6d25 2256 chip->ecc.mode = NAND_ECC_SOFT;
a5ac8aeb
AH		 2257 /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */
2258 /* and 'badblocks' parameters to work */
51502287 2259 chip->options |= NAND_SKIP_BBTSCAN;
1da177e4 2260
61b03bd7 2261 /*
1da177e4 2262 * Perform minimum nandsim structure initialization to handle
61b03bd7 2263 * the initial ID read command correctly
1da177e4
LT		 2264 */
2265 if (third_id_byte != 0xFF || fourth_id_byte != 0xFF)
2266 nand->geom.idbytes = 4;
2267 else
2268 nand->geom.idbytes = 2;
2269 nand->regs.status = NS_STATUS_OK(nand);
2270 nand->nxstate = STATE_UNKNOWN;
2271 nand->options |= OPT_PAGE256; /* temporary value */
2272 nand->ids[0] = first_id_byte;
2273 nand->ids[1] = second_id_byte;
2274 nand->ids[2] = third_id_byte;
2275 nand->ids[3] = fourth_id_byte;
2276 if (bus_width == 16) {
2277 nand->busw = 16;
2278 chip->options |= NAND_BUSWIDTH_16;
2279 }
2280
552d9205
DW		 2281 nsmtd->owner = THIS_MODULE;
2282
514087e7
AH		 2283 if ((retval = parse_weakblocks()) != 0)
2284 goto error;
2285
2286 if ((retval = parse_weakpages()) != 0)
2287 goto error;
2288
2289 if ((retval = parse_gravepages()) != 0)
2290 goto error;
2291
1da177e4
LT		 2292 if ((retval = nand_scan(nsmtd, 1)) != 0) {
2293 NS_ERR("can't register NAND Simulator\n");
2294 if (retval > 0)
2295 retval = -ENXIO;
2296 goto error;
2297 }
2298
a5ac8aeb 2299 if (overridesize) {
0f07a0be 2300 uint64_t new_size = (uint64_t)nsmtd->erasesize << overridesize;
a5ac8aeb
AH		 2301 if (new_size >> overridesize != nsmtd->erasesize) {
2302 NS_ERR("overridesize is too big\n");
2303 goto err_exit;
2304 }
2305 /* N.B. This relies on nand_scan not doing anything with the size before we change it */
2306 nsmtd->size = new_size;
2307 chip->chipsize = new_size;
6eda7a55 2308 chip->chip_shift = ffs(nsmtd->erasesize) + overridesize - 1;
07293b20 2309 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
a5ac8aeb
AH		 2310 }
2311
57aa6b54
AH		 2312 if ((retval = setup_wear_reporting(nsmtd)) != 0)
2313 goto err_exit;
2314
2b77a0ed
AH		 2315 if ((retval = init_nandsim(nsmtd)) != 0)
2316 goto err_exit;
61b03bd7 2317
514087e7
AH		 2318 if ((retval = parse_badblocks(nand, nsmtd)) != 0)
2319 goto err_exit;
2320
2b77a0ed
AH		 2321 if ((retval = nand_default_bbt(nsmtd)) != 0)
2322 goto err_exit;
51502287 2323
2b77a0ed
AH		 2324 /* Register NAND partitions */
2325 if ((retval = add_mtd_partitions(nsmtd, &nand->partitions[0], nand->nbparts)) != 0)
2326 goto err_exit;
1da177e4
LT		 2327
2328 return 0;
2329
2b77a0ed
AH		 2330err_exit:
2331 free_nandsim(nand);
2332 nand_release(nsmtd);
2333 for (i = 0;i < ARRAY_SIZE(nand->partitions); ++i)
2334 kfree(nand->partitions[i].name);
1da177e4
LT		 2335error:
2336 kfree(nsmtd);
514087e7 2337 free_lists();
1da177e4
LT		 2338
2339 return retval;
2340}
2341
2342module_init(ns_init_module);
2343
2344/*
2345 * Module clean-up function
2346 */
2347static void __exit ns_cleanup_module(void)
2348{
2349 struct nandsim *ns = (struct nandsim *)(((struct nand_chip *)nsmtd->priv)->priv);
2b77a0ed 2350 int i;
1da177e4
LT		 2351
2352 free_nandsim(ns); /* Free nandsim private resources */
2b77a0ed
AH		 2353 nand_release(nsmtd); /* Unregister driver */
2354 for (i = 0;i < ARRAY_SIZE(ns->partitions); ++i)
2355 kfree(ns->partitions[i].name);
1da177e4 2356 kfree(nsmtd); /* Free other structures */
514087e7 2357 free_lists();
1da177e4
LT		 2358}
2359
2360module_exit(ns_cleanup_module);
2361
2362MODULE_LICENSE ("GPL");
2363MODULE_AUTHOR ("Artem B. Bityuckiy");
2364MODULE_DESCRIPTION ("The NAND flash simulator");
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