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Merge branch 'upstream/core' of git://git.kernel.org/pub/scm/linux/kernel/git/jeremy/xen
[net-next-2.6.git] / drivers / mtd / nand / nandsim.c
CommitLineData
1da177e4
LT		 1/*
2 * NAND flash simulator.
3 *
4 * Author: Artem B. Bityuckiy <dedekind@oktetlabs.ru>, <dedekind@infradead.org>
5 *
61b03bd7 6 * Copyright (C) 2004 Nokia Corporation
1da177e4
LT		 7 *
8 * Note: NS means "NAND Simulator".
9 * Note: Input means input TO flash chip, output means output FROM chip.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2, or (at your option) any later
14 * version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
19 * Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
1da177e4
LT		 24 */
25
1da177e4
LT		 26#include <linux/init.h>
27#include <linux/types.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/vmalloc.h>
fc1f397b 31#include <asm/div64.h>
1da177e4
LT		 32#include <linux/slab.h>
33#include <linux/errno.h>
34#include <linux/string.h>
35#include <linux/mtd/mtd.h>
36#include <linux/mtd/nand.h>
37#include <linux/mtd/partitions.h>
38#include <linux/delay.h>
2b77a0ed 39#include <linux/list.h>
514087e7 40#include <linux/random.h>
a5cce42f 41#include <linux/sched.h>
a9fc8991
AH		 42#include <linux/fs.h>
43#include <linux/pagemap.h>
1da177e4
LT		 44
45/* Default simulator parameters values */
46#if !defined(CONFIG_NANDSIM_FIRST_ID_BYTE) || \
47 !defined(CONFIG_NANDSIM_SECOND_ID_BYTE) || \
48 !defined(CONFIG_NANDSIM_THIRD_ID_BYTE) || \
49 !defined(CONFIG_NANDSIM_FOURTH_ID_BYTE)
50#define CONFIG_NANDSIM_FIRST_ID_BYTE 0x98
51#define CONFIG_NANDSIM_SECOND_ID_BYTE 0x39
52#define CONFIG_NANDSIM_THIRD_ID_BYTE 0xFF /* No byte */
53#define CONFIG_NANDSIM_FOURTH_ID_BYTE 0xFF /* No byte */
54#endif
55
56#ifndef CONFIG_NANDSIM_ACCESS_DELAY
57#define CONFIG_NANDSIM_ACCESS_DELAY 25
58#endif
59#ifndef CONFIG_NANDSIM_PROGRAMM_DELAY
60#define CONFIG_NANDSIM_PROGRAMM_DELAY 200
61#endif
62#ifndef CONFIG_NANDSIM_ERASE_DELAY
63#define CONFIG_NANDSIM_ERASE_DELAY 2
64#endif
65#ifndef CONFIG_NANDSIM_OUTPUT_CYCLE
66#define CONFIG_NANDSIM_OUTPUT_CYCLE 40
67#endif
68#ifndef CONFIG_NANDSIM_INPUT_CYCLE
69#define CONFIG_NANDSIM_INPUT_CYCLE 50
70#endif
71#ifndef CONFIG_NANDSIM_BUS_WIDTH
72#define CONFIG_NANDSIM_BUS_WIDTH 8
73#endif
74#ifndef CONFIG_NANDSIM_DO_DELAYS
75#define CONFIG_NANDSIM_DO_DELAYS 0
76#endif
77#ifndef CONFIG_NANDSIM_LOG
78#define CONFIG_NANDSIM_LOG 0
79#endif
80#ifndef CONFIG_NANDSIM_DBG
81#define CONFIG_NANDSIM_DBG 0
82#endif
e99e90ae
BH		 83#ifndef CONFIG_NANDSIM_MAX_PARTS
84#define CONFIG_NANDSIM_MAX_PARTS 32
85#endif
1da177e4
LT		 86
87static uint first_id_byte = CONFIG_NANDSIM_FIRST_ID_BYTE;
88static uint second_id_byte = CONFIG_NANDSIM_SECOND_ID_BYTE;
89static uint third_id_byte = CONFIG_NANDSIM_THIRD_ID_BYTE;
90static uint fourth_id_byte = CONFIG_NANDSIM_FOURTH_ID_BYTE;
91static uint access_delay = CONFIG_NANDSIM_ACCESS_DELAY;
92static uint programm_delay = CONFIG_NANDSIM_PROGRAMM_DELAY;
93static uint erase_delay = CONFIG_NANDSIM_ERASE_DELAY;
94static uint output_cycle = CONFIG_NANDSIM_OUTPUT_CYCLE;
95static uint input_cycle = CONFIG_NANDSIM_INPUT_CYCLE;
96static uint bus_width = CONFIG_NANDSIM_BUS_WIDTH;
97static uint do_delays = CONFIG_NANDSIM_DO_DELAYS;
98static uint log = CONFIG_NANDSIM_LOG;
99static uint dbg = CONFIG_NANDSIM_DBG;
e99e90ae 100static unsigned long parts[CONFIG_NANDSIM_MAX_PARTS];
2b77a0ed 101static unsigned int parts_num;
514087e7
AH		 102static char *badblocks = NULL;
103static char *weakblocks = NULL;
104static char *weakpages = NULL;
105static unsigned int bitflips = 0;
106static char *gravepages = NULL;
57aa6b54 107static unsigned int rptwear = 0;
a5ac8aeb 108static unsigned int overridesize = 0;
a9fc8991 109static char *cache_file = NULL;
ce85b79f 110static unsigned int bbt;
1da177e4
LT		 111
112module_param(first_id_byte, uint, 0400);
113module_param(second_id_byte, uint, 0400);
114module_param(third_id_byte, uint, 0400);
115module_param(fourth_id_byte, uint, 0400);
116module_param(access_delay, uint, 0400);
117module_param(programm_delay, uint, 0400);
118module_param(erase_delay, uint, 0400);
119module_param(output_cycle, uint, 0400);
120module_param(input_cycle, uint, 0400);
121module_param(bus_width, uint, 0400);
122module_param(do_delays, uint, 0400);
123module_param(log, uint, 0400);
124module_param(dbg, uint, 0400);
2b77a0ed 125module_param_array(parts, ulong, &parts_num, 0400);
514087e7
AH		 126module_param(badblocks, charp, 0400);
127module_param(weakblocks, charp, 0400);
128module_param(weakpages, charp, 0400);
129module_param(bitflips, uint, 0400);
130module_param(gravepages, charp, 0400);
57aa6b54 131module_param(rptwear, uint, 0400);
a5ac8aeb 132module_param(overridesize, uint, 0400);
a9fc8991 133module_param(cache_file, charp, 0400);
ce85b79f 134module_param(bbt, uint, 0400);
1da177e4 135
a5ac8aeb 136MODULE_PARM_DESC(first_id_byte, "The first byte returned by NAND Flash 'read ID' command (manufacturer ID)");
1da177e4
LT		 137MODULE_PARM_DESC(second_id_byte, "The second byte returned by NAND Flash 'read ID' command (chip ID)");
138MODULE_PARM_DESC(third_id_byte, "The third byte returned by NAND Flash 'read ID' command");
139MODULE_PARM_DESC(fourth_id_byte, "The fourth byte returned by NAND Flash 'read ID' command");
a9fc8991 140MODULE_PARM_DESC(access_delay, "Initial page access delay (microseconds)");
1da177e4
LT		 141MODULE_PARM_DESC(programm_delay, "Page programm delay (microseconds");
142MODULE_PARM_DESC(erase_delay, "Sector erase delay (milliseconds)");
6029a3a4
AY		 143MODULE_PARM_DESC(output_cycle, "Word output (from flash) time (nanoseconds)");
144MODULE_PARM_DESC(input_cycle, "Word input (to flash) time (nanoseconds)");
1da177e4
LT		 145MODULE_PARM_DESC(bus_width, "Chip's bus width (8- or 16-bit)");
146MODULE_PARM_DESC(do_delays, "Simulate NAND delays using busy-waits if not zero");
147MODULE_PARM_DESC(log, "Perform logging if not zero");
148MODULE_PARM_DESC(dbg, "Output debug information if not zero");
2b77a0ed 149MODULE_PARM_DESC(parts, "Partition sizes (in erase blocks) separated by commas");
514087e7
AH		 150/* Page and erase block positions for the following parameters are independent of any partitions */
151MODULE_PARM_DESC(badblocks, "Erase blocks that are initially marked bad, separated by commas");
152MODULE_PARM_DESC(weakblocks, "Weak erase blocks [: remaining erase cycles (defaults to 3)]"
153 " separated by commas e.g. 113:2 means eb 113"
154 " can be erased only twice before failing");
155MODULE_PARM_DESC(weakpages, "Weak pages [: maximum writes (defaults to 3)]"
156 " separated by commas e.g. 1401:2 means page 1401"
157 " can be written only twice before failing");
158MODULE_PARM_DESC(bitflips, "Maximum number of random bit flips per page (zero by default)");
159MODULE_PARM_DESC(gravepages, "Pages that lose data [: maximum reads (defaults to 3)]"
160 " separated by commas e.g. 1401:2 means page 1401"
161 " can be read only twice before failing");
57aa6b54 162MODULE_PARM_DESC(rptwear, "Number of erases inbetween reporting wear, if not zero");
a5ac8aeb
AH		 163MODULE_PARM_DESC(overridesize, "Specifies the NAND Flash size overriding the ID bytes. "
164 "The size is specified in erase blocks and as the exponent of a power of two"
165 " e.g. 5 means a size of 32 erase blocks");
a9fc8991 166MODULE_PARM_DESC(cache_file, "File to use to cache nand pages instead of memory");
ce85b79f 167MODULE_PARM_DESC(bbt, "0 OOB, 1 BBT with marker in OOB, 2 BBT with marker in data area");
1da177e4
LT		 168
169/* The largest possible page size */
75352662 170#define NS_LARGEST_PAGE_SIZE 4096
61b03bd7 171
1da177e4
LT		 172/* The prefix for simulator output */
173#define NS_OUTPUT_PREFIX "[nandsim]"
174
175/* Simulator's output macros (logging, debugging, warning, error) */
176#define NS_LOG(args...) \
177 do { if (log) printk(KERN_DEBUG NS_OUTPUT_PREFIX " log: " args); } while(0)
178#define NS_DBG(args...) \
179 do { if (dbg) printk(KERN_DEBUG NS_OUTPUT_PREFIX " debug: " args); } while(0)
180#define NS_WARN(args...) \
2b77a0ed 181 do { printk(KERN_WARNING NS_OUTPUT_PREFIX " warning: " args); } while(0)
1da177e4 182#define NS_ERR(args...) \
2b77a0ed 183 do { printk(KERN_ERR NS_OUTPUT_PREFIX " error: " args); } while(0)
57aa6b54
AH		 184#define NS_INFO(args...) \
185 do { printk(KERN_INFO NS_OUTPUT_PREFIX " " args); } while(0)
1da177e4
LT		 186
187/* Busy-wait delay macros (microseconds, milliseconds) */
188#define NS_UDELAY(us) \
189 do { if (do_delays) udelay(us); } while(0)
190#define NS_MDELAY(us) \
191 do { if (do_delays) mdelay(us); } while(0)
61b03bd7 192
1da177e4
LT		 193/* Is the nandsim structure initialized ? */
194#define NS_IS_INITIALIZED(ns) ((ns)->geom.totsz != 0)
195
196/* Good operation completion status */
197#define NS_STATUS_OK(ns) (NAND_STATUS_READY | (NAND_STATUS_WP * ((ns)->lines.wp == 0)))
198
199/* Operation failed completion status */
61b03bd7 200#define NS_STATUS_FAILED(ns) (NAND_STATUS_FAIL | NS_STATUS_OK(ns))
1da177e4
LT		 201
202/* Calculate the page offset in flash RAM image by (row, column) address */
203#define NS_RAW_OFFSET(ns) \
204 (((ns)->regs.row << (ns)->geom.pgshift) + ((ns)->regs.row * (ns)->geom.oobsz) + (ns)->regs.column)
61b03bd7 205
1da177e4
LT		 206/* Calculate the OOB offset in flash RAM image by (row, column) address */
207#define NS_RAW_OFFSET_OOB(ns) (NS_RAW_OFFSET(ns) + ns->geom.pgsz)
208
209/* After a command is input, the simulator goes to one of the following states */
210#define STATE_CMD_READ0 0x00000001 /* read data from the beginning of page */
211#define STATE_CMD_READ1 0x00000002 /* read data from the second half of page */
4a0c50c0 212#define STATE_CMD_READSTART 0x00000003 /* read data second command (large page devices) */
1da177e4
LT		 213#define STATE_CMD_PAGEPROG 0x00000004 /* start page programm */
214#define STATE_CMD_READOOB 0x00000005 /* read OOB area */
215#define STATE_CMD_ERASE1 0x00000006 /* sector erase first command */
216#define STATE_CMD_STATUS 0x00000007 /* read status */
217#define STATE_CMD_STATUS_M 0x00000008 /* read multi-plane status (isn't implemented) */
218#define STATE_CMD_SEQIN 0x00000009 /* sequential data imput */
219#define STATE_CMD_READID 0x0000000A /* read ID */
220#define STATE_CMD_ERASE2 0x0000000B /* sector erase second command */
221#define STATE_CMD_RESET 0x0000000C /* reset */
74216be4
AB		 222#define STATE_CMD_RNDOUT 0x0000000D /* random output command */
223#define STATE_CMD_RNDOUTSTART 0x0000000E /* random output start command */
1da177e4
LT		 224#define STATE_CMD_MASK 0x0000000F /* command states mask */
225
8e87d782 226/* After an address is input, the simulator goes to one of these states */
1da177e4
LT		 227#define STATE_ADDR_PAGE 0x00000010 /* full (row, column) address is accepted */
228#define STATE_ADDR_SEC 0x00000020 /* sector address was accepted */
74216be4
AB		 229#define STATE_ADDR_COLUMN 0x00000030 /* column address was accepted */
230#define STATE_ADDR_ZERO 0x00000040 /* one byte zero address was accepted */
231#define STATE_ADDR_MASK 0x00000070 /* address states mask */
1da177e4
LT		 232
233/* Durind data input/output the simulator is in these states */
234#define STATE_DATAIN 0x00000100 /* waiting for data input */
235#define STATE_DATAIN_MASK 0x00000100 /* data input states mask */
236
237#define STATE_DATAOUT 0x00001000 /* waiting for page data output */
238#define STATE_DATAOUT_ID 0x00002000 /* waiting for ID bytes output */
239#define STATE_DATAOUT_STATUS 0x00003000 /* waiting for status output */
240#define STATE_DATAOUT_STATUS_M 0x00004000 /* waiting for multi-plane status output */
241#define STATE_DATAOUT_MASK 0x00007000 /* data output states mask */
242
243/* Previous operation is done, ready to accept new requests */
244#define STATE_READY 0x00000000
245
246/* This state is used to mark that the next state isn't known yet */
247#define STATE_UNKNOWN 0x10000000
248
249/* Simulator's actions bit masks */
250#define ACTION_CPY 0x00100000 /* copy page/OOB to the internal buffer */
251#define ACTION_PRGPAGE 0x00200000 /* programm the internal buffer to flash */
252#define ACTION_SECERASE 0x00300000 /* erase sector */
253#define ACTION_ZEROOFF 0x00400000 /* don't add any offset to address */
254#define ACTION_HALFOFF 0x00500000 /* add to address half of page */
255#define ACTION_OOBOFF 0x00600000 /* add to address OOB offset */
256#define ACTION_MASK 0x00700000 /* action mask */
257
74216be4 258#define NS_OPER_NUM 13 /* Number of operations supported by the simulator */
1da177e4
LT		 259#define NS_OPER_STATES 6 /* Maximum number of states in operation */
260
261#define OPT_ANY 0xFFFFFFFF /* any chip supports this operation */
262#define OPT_PAGE256 0x00000001 /* 256-byte page chips */
263#define OPT_PAGE512 0x00000002 /* 512-byte page chips */
264#define OPT_PAGE2048 0x00000008 /* 2048-byte page chips */
265#define OPT_SMARTMEDIA 0x00000010 /* SmartMedia technology chips */
266#define OPT_AUTOINCR 0x00000020 /* page number auto inctimentation is possible */
267#define OPT_PAGE512_8BIT 0x00000040 /* 512-byte page chips with 8-bit bus width */
75352662
SAS		 268#define OPT_PAGE4096 0x00000080 /* 4096-byte page chips */
269#define OPT_LARGEPAGE (OPT_PAGE2048 | OPT_PAGE4096) /* 2048 & 4096-byte page chips */
1da177e4
LT		 270#define OPT_SMALLPAGE (OPT_PAGE256 | OPT_PAGE512) /* 256 and 512-byte page chips */
271
272/* Remove action bits ftom state */
273#define NS_STATE(x) ((x) & ~ACTION_MASK)
61b03bd7
TG		 274
275/*
1da177e4
LT		 276 * Maximum previous states which need to be saved. Currently saving is
277 * only needed for page programm operation with preceeded read command
278 * (which is only valid for 512-byte pages).
279 */
280#define NS_MAX_PREVSTATES 1
281
a9fc8991
AH		 282/* Maximum page cache pages needed to read or write a NAND page to the cache_file */
283#define NS_MAX_HELD_PAGES 16
284
d086d436
VK		 285/*
286 * A union to represent flash memory contents and flash buffer.
287 */
288union ns_mem {
289 u_char *byte; /* for byte access */
290 uint16_t *word; /* for 16-bit word access */
291};
292
61b03bd7 293/*
1da177e4
LT		 294 * The structure which describes all the internal simulator data.
295 */
296struct nandsim {
e99e90ae 297 struct mtd_partition partitions[CONFIG_NANDSIM_MAX_PARTS];
2b77a0ed 298 unsigned int nbparts;
1da177e4
LT		 299
300 uint busw; /* flash chip bus width (8 or 16) */
301 u_char ids[4]; /* chip's ID bytes */
302 uint32_t options; /* chip's characteristic bits */
303 uint32_t state; /* current chip state */
304 uint32_t nxstate; /* next expected state */
61b03bd7 305
1da177e4
LT		 306 uint32_t *op; /* current operation, NULL operations isn't known yet */
307 uint32_t pstates[NS_MAX_PREVSTATES]; /* previous states */
308 uint16_t npstates; /* number of previous states saved */
309 uint16_t stateidx; /* current state index */
310
d086d436
VK		 311 /* The simulated NAND flash pages array */
312 union ns_mem *pages;
1da177e4 313
8a4c2495
AK		 314 /* Slab allocator for nand pages */
315 struct kmem_cache *nand_pages_slab;
316
1da177e4 317 /* Internal buffer of page + OOB size bytes */
d086d436 318 union ns_mem buf;
1da177e4
LT		 319
320 /* NAND flash "geometry" */
0bfa4df2 321 struct {
6eda7a55 322 uint64_t totsz; /* total flash size, bytes */
1da177e4
LT		 323 uint32_t secsz; /* flash sector (erase block) size, bytes */
324 uint pgsz; /* NAND flash page size, bytes */
325 uint oobsz; /* page OOB area size, bytes */
6eda7a55 326 uint64_t totszoob; /* total flash size including OOB, bytes */
1da177e4
LT		 327 uint pgszoob; /* page size including OOB , bytes*/
328 uint secszoob; /* sector size including OOB, bytes */
329 uint pgnum; /* total number of pages */
330 uint pgsec; /* number of pages per sector */
331 uint secshift; /* bits number in sector size */
332 uint pgshift; /* bits number in page size */
333 uint oobshift; /* bits number in OOB size */
334 uint pgaddrbytes; /* bytes per page address */
335 uint secaddrbytes; /* bytes per sector address */
336 uint idbytes; /* the number ID bytes that this chip outputs */
337 } geom;
338
339 /* NAND flash internal registers */
0bfa4df2 340 struct {
1da177e4
LT		 341 unsigned command; /* the command register */
342 u_char status; /* the status register */
343 uint row; /* the page number */
344 uint column; /* the offset within page */
345 uint count; /* internal counter */
346 uint num; /* number of bytes which must be processed */
347 uint off; /* fixed page offset */
348 } regs;
349
350 /* NAND flash lines state */
0bfa4df2 351 struct {
1da177e4
LT		 352 int ce; /* chip Enable */
353 int cle; /* command Latch Enable */
354 int ale; /* address Latch Enable */
355 int wp; /* write Protect */
356 } lines;
a9fc8991
AH		 357
358 /* Fields needed when using a cache file */
359 struct file *cfile; /* Open file */
360 unsigned char *pages_written; /* Which pages have been written */
361 void *file_buf;
362 struct page *held_pages[NS_MAX_HELD_PAGES];
363 int held_cnt;
1da177e4
LT		 364};
365
366/*
367 * Operations array. To perform any operation the simulator must pass
368 * through the correspondent states chain.
369 */
370static struct nandsim_operations {
371 uint32_t reqopts; /* options which are required to perform the operation */
372 uint32_t states[NS_OPER_STATES]; /* operation's states */
373} ops[NS_OPER_NUM] = {
374 /* Read page + OOB from the beginning */
375 {OPT_SMALLPAGE, {STATE_CMD_READ0 | ACTION_ZEROOFF, STATE_ADDR_PAGE | ACTION_CPY,
376 STATE_DATAOUT, STATE_READY}},
377 /* Read page + OOB from the second half */
378 {OPT_PAGE512_8BIT, {STATE_CMD_READ1 | ACTION_HALFOFF, STATE_ADDR_PAGE | ACTION_CPY,
379 STATE_DATAOUT, STATE_READY}},
380 /* Read OOB */
381 {OPT_SMALLPAGE, {STATE_CMD_READOOB | ACTION_OOBOFF, STATE_ADDR_PAGE | ACTION_CPY,
382 STATE_DATAOUT, STATE_READY}},
383 /* Programm page starting from the beginning */
384 {OPT_ANY, {STATE_CMD_SEQIN, STATE_ADDR_PAGE, STATE_DATAIN,
385 STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
386 /* Programm page starting from the beginning */
387 {OPT_SMALLPAGE, {STATE_CMD_READ0, STATE_CMD_SEQIN | ACTION_ZEROOFF, STATE_ADDR_PAGE,
388 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
389 /* Programm page starting from the second half */
390 {OPT_PAGE512, {STATE_CMD_READ1, STATE_CMD_SEQIN | ACTION_HALFOFF, STATE_ADDR_PAGE,
391 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
392 /* Programm OOB */
393 {OPT_SMALLPAGE, {STATE_CMD_READOOB, STATE_CMD_SEQIN | ACTION_OOBOFF, STATE_ADDR_PAGE,
394 STATE_DATAIN, STATE_CMD_PAGEPROG | ACTION_PRGPAGE, STATE_READY}},
395 /* Erase sector */
396 {OPT_ANY, {STATE_CMD_ERASE1, STATE_ADDR_SEC, STATE_CMD_ERASE2 | ACTION_SECERASE, STATE_READY}},
397 /* Read status */
398 {OPT_ANY, {STATE_CMD_STATUS, STATE_DATAOUT_STATUS, STATE_READY}},
399 /* Read multi-plane status */
400 {OPT_SMARTMEDIA, {STATE_CMD_STATUS_M, STATE_DATAOUT_STATUS_M, STATE_READY}},
401 /* Read ID */
402 {OPT_ANY, {STATE_CMD_READID, STATE_ADDR_ZERO, STATE_DATAOUT_ID, STATE_READY}},
403 /* Large page devices read page */
404 {OPT_LARGEPAGE, {STATE_CMD_READ0, STATE_ADDR_PAGE, STATE_CMD_READSTART | ACTION_CPY,
74216be4
AB		 405 STATE_DATAOUT, STATE_READY}},
406 /* Large page devices random page read */
407 {OPT_LARGEPAGE, {STATE_CMD_RNDOUT, STATE_ADDR_COLUMN, STATE_CMD_RNDOUTSTART | ACTION_CPY,
408 STATE_DATAOUT, STATE_READY}},
1da177e4
LT		 409};
410
514087e7
AH		 411struct weak_block {
412 struct list_head list;
413 unsigned int erase_block_no;
414 unsigned int max_erases;
415 unsigned int erases_done;
416};
417
418static LIST_HEAD(weak_blocks);
419
420struct weak_page {
421 struct list_head list;
422 unsigned int page_no;
423 unsigned int max_writes;
424 unsigned int writes_done;
425};
426
427static LIST_HEAD(weak_pages);
428
429struct grave_page {
430 struct list_head list;
431 unsigned int page_no;
432 unsigned int max_reads;
433 unsigned int reads_done;
434};
435
436static LIST_HEAD(grave_pages);
437
57aa6b54
AH		 438static unsigned long *erase_block_wear = NULL;
439static unsigned int wear_eb_count = 0;
440static unsigned long total_wear = 0;
441static unsigned int rptwear_cnt = 0;
442
1da177e4
LT		 443/* MTD structure for NAND controller */
444static struct mtd_info *nsmtd;
445
446static u_char ns_verify_buf[NS_LARGEST_PAGE_SIZE];
447
d086d436 448/*
8a4c2495
AK		 449 * Allocate array of page pointers, create slab allocation for an array
450 * and initialize the array by NULL pointers.
d086d436
VK		 451 *
452 * RETURNS: 0 if success, -ENOMEM if memory alloc fails.
453 */
a5602146 454static int alloc_device(struct nandsim *ns)
d086d436 455{
a9fc8991
AH		 456 struct file *cfile;
457 int i, err;
458
459 if (cache_file) {
460 cfile = filp_open(cache_file, O_CREAT | O_RDWR | O_LARGEFILE, 0600);
461 if (IS_ERR(cfile))
462 return PTR_ERR(cfile);
463 if (!cfile->f_op || (!cfile->f_op->read && !cfile->f_op->aio_read)) {
464 NS_ERR("alloc_device: cache file not readable\n");
465 err = -EINVAL;
466 goto err_close;
467 }
468 if (!cfile->f_op->write && !cfile->f_op->aio_write) {
469 NS_ERR("alloc_device: cache file not writeable\n");
470 err = -EINVAL;
471 goto err_close;
472 }
473 ns->pages_written = vmalloc(ns->geom.pgnum);
474 if (!ns->pages_written) {
475 NS_ERR("alloc_device: unable to allocate pages written array\n");
476 err = -ENOMEM;
477 goto err_close;
478 }
479 ns->file_buf = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
480 if (!ns->file_buf) {
481 NS_ERR("alloc_device: unable to allocate file buf\n");
482 err = -ENOMEM;
483 goto err_free;
484 }
485 ns->cfile = cfile;
486 memset(ns->pages_written, 0, ns->geom.pgnum);
487 return 0;
488 }
d086d436
VK		 489
490 ns->pages = vmalloc(ns->geom.pgnum * sizeof(union ns_mem));
491 if (!ns->pages) {
a9fc8991 492 NS_ERR("alloc_device: unable to allocate page array\n");
d086d436
VK		 493 return -ENOMEM;
494 }
495 for (i = 0; i < ns->geom.pgnum; i++) {
496 ns->pages[i].byte = NULL;
497 }
8a4c2495
AK		 498 ns->nand_pages_slab = kmem_cache_create("nandsim",
499 ns->geom.pgszoob, 0, 0, NULL);
500 if (!ns->nand_pages_slab) {
501 NS_ERR("cache_create: unable to create kmem_cache\n");
502 return -ENOMEM;
503 }
d086d436
VK		 504
505 return 0;
a9fc8991
AH		 506
507err_free:
508 vfree(ns->pages_written);
509err_close:
510 filp_close(cfile, NULL);
511 return err;
d086d436
VK		 512}
513
514/*
515 * Free any allocated pages, and free the array of page pointers.
516 */
a5602146 517static void free_device(struct nandsim *ns)
d086d436
VK		 518{
519 int i;
520
a9fc8991
AH		 521 if (ns->cfile) {
522 kfree(ns->file_buf);
523 vfree(ns->pages_written);
524 filp_close(ns->cfile, NULL);
525 return;
526 }
527
d086d436
VK		 528 if (ns->pages) {
529 for (i = 0; i < ns->geom.pgnum; i++) {
530 if (ns->pages[i].byte)
8a4c2495
AK		 531 kmem_cache_free(ns->nand_pages_slab,
532 ns->pages[i].byte);
d086d436 533 }
8a4c2495 534 kmem_cache_destroy(ns->nand_pages_slab);
d086d436
VK		 535 vfree(ns->pages);
536 }
537}
538
2b77a0ed
AH		 539static char *get_partition_name(int i)
540{
541 char buf[64];
542 sprintf(buf, "NAND simulator partition %d", i);
543 return kstrdup(buf, GFP_KERNEL);
544}
545
0f07a0be 546static uint64_t divide(uint64_t n, uint32_t d)
6eda7a55
AH		 547{
548 do_div(n, d);
549 return n;
550}
551
1da177e4
LT		 552/*
553 * Initialize the nandsim structure.
554 *
555 * RETURNS: 0 if success, -ERRNO if failure.
556 */
a5602146 557static int init_nandsim(struct mtd_info *mtd)
1da177e4 558{
7b8516b7
KV		 559 struct nand_chip *chip = mtd->priv;
560 struct nandsim *ns = chip->priv;
2b77a0ed 561 int i, ret = 0;
0f07a0be
DW		 562 uint64_t remains;
563 uint64_t next_offset;
1da177e4
LT		 564
565 if (NS_IS_INITIALIZED(ns)) {
566 NS_ERR("init_nandsim: nandsim is already initialized\n");
567 return -EIO;
568 }
569
570 /* Force mtd to not do delays */
571 chip->chip_delay = 0;
572
573 /* Initialize the NAND flash parameters */
574 ns->busw = chip->options & NAND_BUSWIDTH_16 ? 16 : 8;
575 ns->geom.totsz = mtd->size;
28318776 576 ns->geom.pgsz = mtd->writesize;
1da177e4
LT		 577 ns->geom.oobsz = mtd->oobsize;
578 ns->geom.secsz = mtd->erasesize;
579 ns->geom.pgszoob = ns->geom.pgsz + ns->geom.oobsz;
6eda7a55
AH		 580 ns->geom.pgnum = divide(ns->geom.totsz, ns->geom.pgsz);
581 ns->geom.totszoob = ns->geom.totsz + (uint64_t)ns->geom.pgnum * ns->geom.oobsz;
1da177e4
LT		 582 ns->geom.secshift = ffs(ns->geom.secsz) - 1;
583 ns->geom.pgshift = chip->page_shift;
584 ns->geom.oobshift = ffs(ns->geom.oobsz) - 1;
585 ns->geom.pgsec = ns->geom.secsz / ns->geom.pgsz;
586 ns->geom.secszoob = ns->geom.secsz + ns->geom.oobsz * ns->geom.pgsec;
587 ns->options = 0;
588
589 if (ns->geom.pgsz == 256) {
590 ns->options |= OPT_PAGE256;
591 }
592 else if (ns->geom.pgsz == 512) {
593 ns->options |= (OPT_PAGE512 | OPT_AUTOINCR);
594 if (ns->busw == 8)
595 ns->options |= OPT_PAGE512_8BIT;
596 } else if (ns->geom.pgsz == 2048) {
597 ns->options |= OPT_PAGE2048;
75352662
SAS		 598 } else if (ns->geom.pgsz == 4096) {
599 ns->options |= OPT_PAGE4096;
1da177e4
LT		 600 } else {
601 NS_ERR("init_nandsim: unknown page size %u\n", ns->geom.pgsz);
602 return -EIO;
603 }
604
605 if (ns->options & OPT_SMALLPAGE) {
af3deccf 606 if (ns->geom.totsz <= (32 << 20)) {
1da177e4
LT		 607 ns->geom.pgaddrbytes = 3;
608 ns->geom.secaddrbytes = 2;
609 } else {
610 ns->geom.pgaddrbytes = 4;
611 ns->geom.secaddrbytes = 3;
612 }
613 } else {
614 if (ns->geom.totsz <= (128 << 20)) {
4a0c50c0 615 ns->geom.pgaddrbytes = 4;
1da177e4
LT		 616 ns->geom.secaddrbytes = 2;
617 } else {
618 ns->geom.pgaddrbytes = 5;
619 ns->geom.secaddrbytes = 3;
620 }
621 }
61b03bd7 622
2b77a0ed
AH		 623 /* Fill the partition_info structure */
624 if (parts_num > ARRAY_SIZE(ns->partitions)) {
625 NS_ERR("too many partitions.\n");
626 ret = -EINVAL;
627 goto error;
628 }
629 remains = ns->geom.totsz;
630 next_offset = 0;
631 for (i = 0; i < parts_num; ++i) {
0f07a0be 632 uint64_t part_sz = (uint64_t)parts[i] * ns->geom.secsz;
6eda7a55
AH		 633
634 if (!part_sz || part_sz > remains) {
2b77a0ed
AH		 635 NS_ERR("bad partition size.\n");
636 ret = -EINVAL;
637 goto error;
638 }
639 ns->partitions[i].name = get_partition_name(i);
640 ns->partitions[i].offset = next_offset;
6eda7a55 641 ns->partitions[i].size = part_sz;
2b77a0ed
AH		 642 next_offset += ns->partitions[i].size;
643 remains -= ns->partitions[i].size;
644 }
645 ns->nbparts = parts_num;
646 if (remains) {
647 if (parts_num + 1 > ARRAY_SIZE(ns->partitions)) {
648 NS_ERR("too many partitions.\n");
649 ret = -EINVAL;
650 goto error;
651 }
652 ns->partitions[i].name = get_partition_name(i);
653 ns->partitions[i].offset = next_offset;
654 ns->partitions[i].size = remains;
655 ns->nbparts += 1;
656 }
657
1da177e4
LT		 658 /* Detect how many ID bytes the NAND chip outputs */
659 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
660 if (second_id_byte != nand_flash_ids[i].id)
661 continue;
662 if (!(nand_flash_ids[i].options & NAND_NO_AUTOINCR))
663 ns->options |= OPT_AUTOINCR;
664 }
665
666 if (ns->busw == 16)
667 NS_WARN("16-bit flashes support wasn't tested\n");
668
e4c094a5
AM		 669 printk("flash size: %llu MiB\n",
670 (unsigned long long)ns->geom.totsz >> 20);
1da177e4
LT		 671 printk("page size: %u bytes\n", ns->geom.pgsz);
672 printk("OOB area size: %u bytes\n", ns->geom.oobsz);
673 printk("sector size: %u KiB\n", ns->geom.secsz >> 10);
674 printk("pages number: %u\n", ns->geom.pgnum);
675 printk("pages per sector: %u\n", ns->geom.pgsec);
676 printk("bus width: %u\n", ns->busw);
677 printk("bits in sector size: %u\n", ns->geom.secshift);
678 printk("bits in page size: %u\n", ns->geom.pgshift);
e4c094a5
AM		 679 printk("bits in OOB size: %u\n", ns->geom.oobshift);
680 printk("flash size with OOB: %llu KiB\n",
681 (unsigned long long)ns->geom.totszoob >> 10);
1da177e4
LT		 682 printk("page address bytes: %u\n", ns->geom.pgaddrbytes);
683 printk("sector address bytes: %u\n", ns->geom.secaddrbytes);
684 printk("options: %#x\n", ns->options);
685
2b77a0ed 686 if ((ret = alloc_device(ns)) != 0)
d086d436 687 goto error;
1da177e4
LT		 688
689 /* Allocate / initialize the internal buffer */
690 ns->buf.byte = kmalloc(ns->geom.pgszoob, GFP_KERNEL);
691 if (!ns->buf.byte) {
692 NS_ERR("init_nandsim: unable to allocate %u bytes for the internal buffer\n",
693 ns->geom.pgszoob);
2b77a0ed 694 ret = -ENOMEM;
1da177e4
LT		 695 goto error;
696 }
697 memset(ns->buf.byte, 0xFF, ns->geom.pgszoob);
698
1da177e4
LT		 699 return 0;
700
701error:
d086d436 702 free_device(ns);
1da177e4 703
2b77a0ed 704 return ret;
1da177e4
LT		 705}
706
707/*
708 * Free the nandsim structure.
709 */
a5602146 710static void free_nandsim(struct nandsim *ns)
1da177e4
LT		 711{
712 kfree(ns->buf.byte);
d086d436 713 free_device(ns);
1da177e4
LT		 714
715 return;
716}
717
514087e7
AH		 718static int parse_badblocks(struct nandsim *ns, struct mtd_info *mtd)
719{
720 char *w;
721 int zero_ok;
722 unsigned int erase_block_no;
723 loff_t offset;
724
725 if (!badblocks)
726 return 0;
727 w = badblocks;
728 do {
729 zero_ok = (*w == '0' ? 1 : 0);
730 erase_block_no = simple_strtoul(w, &w, 0);
731 if (!zero_ok && !erase_block_no) {
732 NS_ERR("invalid badblocks.\n");
733 return -EINVAL;
734 }
735 offset = erase_block_no * ns->geom.secsz;
736 if (mtd->block_markbad(mtd, offset)) {
737 NS_ERR("invalid badblocks.\n");
738 return -EINVAL;
739 }
740 if (*w == ',')
741 w += 1;
742 } while (*w);
743 return 0;
744}
745
746static int parse_weakblocks(void)
747{
748 char *w;
749 int zero_ok;
750 unsigned int erase_block_no;
751 unsigned int max_erases;
752 struct weak_block *wb;
753
754 if (!weakblocks)
755 return 0;
756 w = weakblocks;
757 do {
758 zero_ok = (*w == '0' ? 1 : 0);
759 erase_block_no = simple_strtoul(w, &w, 0);
760 if (!zero_ok && !erase_block_no) {
761 NS_ERR("invalid weakblocks.\n");
762 return -EINVAL;
763 }
764 max_erases = 3;
765 if (*w == ':') {
766 w += 1;
767 max_erases = simple_strtoul(w, &w, 0);
768 }
769 if (*w == ',')
770 w += 1;
771 wb = kzalloc(sizeof(*wb), GFP_KERNEL);
772 if (!wb) {
773 NS_ERR("unable to allocate memory.\n");
774 return -ENOMEM;
775 }
776 wb->erase_block_no = erase_block_no;
777 wb->max_erases = max_erases;
778 list_add(&wb->list, &weak_blocks);
779 } while (*w);
780 return 0;
781}
782
783static int erase_error(unsigned int erase_block_no)
784{
785 struct weak_block *wb;
786
787 list_for_each_entry(wb, &weak_blocks, list)
788 if (wb->erase_block_no == erase_block_no) {
789 if (wb->erases_done >= wb->max_erases)
790 return 1;
791 wb->erases_done += 1;
792 return 0;
793 }
794 return 0;
795}
796
797static int parse_weakpages(void)
798{
799 char *w;
800 int zero_ok;
801 unsigned int page_no;
802 unsigned int max_writes;
803 struct weak_page *wp;
804
805 if (!weakpages)
806 return 0;
807 w = weakpages;
808 do {
809 zero_ok = (*w == '0' ? 1 : 0);
810 page_no = simple_strtoul(w, &w, 0);
811 if (!zero_ok && !page_no) {
812 NS_ERR("invalid weakpagess.\n");
813 return -EINVAL;
814 }
815 max_writes = 3;
816 if (*w == ':') {
817 w += 1;
818 max_writes = simple_strtoul(w, &w, 0);
819 }
820 if (*w == ',')
821 w += 1;
822 wp = kzalloc(sizeof(*wp), GFP_KERNEL);
823 if (!wp) {
824 NS_ERR("unable to allocate memory.\n");
825 return -ENOMEM;
826 }
827 wp->page_no = page_no;
828 wp->max_writes = max_writes;
829 list_add(&wp->list, &weak_pages);
830 } while (*w);
831 return 0;
832}
833
834static int write_error(unsigned int page_no)
835{
836 struct weak_page *wp;
837
838 list_for_each_entry(wp, &weak_pages, list)
839 if (wp->page_no == page_no) {
840 if (wp->writes_done >= wp->max_writes)
841 return 1;
842 wp->writes_done += 1;
843 return 0;
844 }
845 return 0;
846}
847
848static int parse_gravepages(void)
849{
850 char *g;
851 int zero_ok;
852 unsigned int page_no;
853 unsigned int max_reads;
854 struct grave_page *gp;
855
856 if (!gravepages)
857 return 0;
858 g = gravepages;
859 do {
860 zero_ok = (*g == '0' ? 1 : 0);
861 page_no = simple_strtoul(g, &g, 0);
862 if (!zero_ok && !page_no) {
863 NS_ERR("invalid gravepagess.\n");
864 return -EINVAL;
865 }
866 max_reads = 3;
867 if (*g == ':') {
868 g += 1;
869 max_reads = simple_strtoul(g, &g, 0);
870 }
871 if (*g == ',')
872 g += 1;
873 gp = kzalloc(sizeof(*gp), GFP_KERNEL);
874 if (!gp) {
875 NS_ERR("unable to allocate memory.\n");
876 return -ENOMEM;
877 }
878 gp->page_no = page_no;
879 gp->max_reads = max_reads;
880 list_add(&gp->list, &grave_pages);
881 } while (*g);
882 return 0;
883}
884
885static int read_error(unsigned int page_no)
886{
887 struct grave_page *gp;
888
889 list_for_each_entry(gp, &grave_pages, list)
890 if (gp->page_no == page_no) {
891 if (gp->reads_done >= gp->max_reads)
892 return 1;
893 gp->reads_done += 1;
894 return 0;
895 }
896 return 0;
897}
898
899static void free_lists(void)
900{
901 struct list_head *pos, *n;
902 list_for_each_safe(pos, n, &weak_blocks) {
903 list_del(pos);
904 kfree(list_entry(pos, struct weak_block, list));
905 }
906 list_for_each_safe(pos, n, &weak_pages) {
907 list_del(pos);
908 kfree(list_entry(pos, struct weak_page, list));
909 }
910 list_for_each_safe(pos, n, &grave_pages) {
911 list_del(pos);
912 kfree(list_entry(pos, struct grave_page, list));
913 }
57aa6b54
AH		 914 kfree(erase_block_wear);
915}
916
917static int setup_wear_reporting(struct mtd_info *mtd)
918{
919 size_t mem;
920
921 if (!rptwear)
922 return 0;
6eda7a55 923 wear_eb_count = divide(mtd->size, mtd->erasesize);
57aa6b54
AH		 924 mem = wear_eb_count * sizeof(unsigned long);
925 if (mem / sizeof(unsigned long) != wear_eb_count) {
926 NS_ERR("Too many erase blocks for wear reporting\n");
927 return -ENOMEM;
928 }
929 erase_block_wear = kzalloc(mem, GFP_KERNEL);
930 if (!erase_block_wear) {
931 NS_ERR("Too many erase blocks for wear reporting\n");
932 return -ENOMEM;
933 }
934 return 0;
935}
936
937static void update_wear(unsigned int erase_block_no)
938{
939 unsigned long wmin = -1, wmax = 0, avg;
940 unsigned long deciles[10], decile_max[10], tot = 0;
941 unsigned int i;
942
943 if (!erase_block_wear)
944 return;
945 total_wear += 1;
946 if (total_wear == 0)
947 NS_ERR("Erase counter total overflow\n");
948 erase_block_wear[erase_block_no] += 1;
949 if (erase_block_wear[erase_block_no] == 0)
950 NS_ERR("Erase counter overflow for erase block %u\n", erase_block_no);
951 rptwear_cnt += 1;
952 if (rptwear_cnt < rptwear)
953 return;
954 rptwear_cnt = 0;
955 /* Calc wear stats */
956 for (i = 0; i < wear_eb_count; ++i) {
957 unsigned long wear = erase_block_wear[i];
958 if (wear < wmin)
959 wmin = wear;
960 if (wear > wmax)
961 wmax = wear;
962 tot += wear;
963 }
964 for (i = 0; i < 9; ++i) {
965 deciles[i] = 0;
966 decile_max[i] = (wmax * (i + 1) + 5) / 10;
967 }
968 deciles[9] = 0;
969 decile_max[9] = wmax;
970 for (i = 0; i < wear_eb_count; ++i) {
971 int d;
972 unsigned long wear = erase_block_wear[i];
973 for (d = 0; d < 10; ++d)
974 if (wear <= decile_max[d]) {
975 deciles[d] += 1;
976 break;
977 }
978 }
979 avg = tot / wear_eb_count;
980 /* Output wear report */
981 NS_INFO("*** Wear Report ***\n");
982 NS_INFO("Total numbers of erases: %lu\n", tot);
983 NS_INFO("Number of erase blocks: %u\n", wear_eb_count);
984 NS_INFO("Average number of erases: %lu\n", avg);
985 NS_INFO("Maximum number of erases: %lu\n", wmax);
986 NS_INFO("Minimum number of erases: %lu\n", wmin);
987 for (i = 0; i < 10; ++i) {
988 unsigned long from = (i ? decile_max[i - 1] + 1 : 0);
989 if (from > decile_max[i])
990 continue;
991 NS_INFO("Number of ebs with erase counts from %lu to %lu : %lu\n",
992 from,
993 decile_max[i],
994 deciles[i]);
995 }
996 NS_INFO("*** End of Wear Report ***\n");
514087e7
AH		 997}
998
1da177e4
LT		 999/*
1000 * Returns the string representation of 'state' state.
1001 */
a5602146 1002static char *get_state_name(uint32_t state)
1da177e4
LT		 1003{
1004 switch (NS_STATE(state)) {
1005 case STATE_CMD_READ0:
1006 return "STATE_CMD_READ0";
1007 case STATE_CMD_READ1:
1008 return "STATE_CMD_READ1";
1009 case STATE_CMD_PAGEPROG:
1010 return "STATE_CMD_PAGEPROG";
1011 case STATE_CMD_READOOB:
1012 return "STATE_CMD_READOOB";
1013 case STATE_CMD_READSTART:
1014 return "STATE_CMD_READSTART";
1015 case STATE_CMD_ERASE1:
1016 return "STATE_CMD_ERASE1";
1017 case STATE_CMD_STATUS:
1018 return "STATE_CMD_STATUS";
1019 case STATE_CMD_STATUS_M:
1020 return "STATE_CMD_STATUS_M";
1021 case STATE_CMD_SEQIN:
1022 return "STATE_CMD_SEQIN";
1023 case STATE_CMD_READID:
1024 return "STATE_CMD_READID";
1025 case STATE_CMD_ERASE2:
1026 return "STATE_CMD_ERASE2";
1027 case STATE_CMD_RESET:
1028 return "STATE_CMD_RESET";
74216be4
AB		 1029 case STATE_CMD_RNDOUT:
1030 return "STATE_CMD_RNDOUT";
1031 case STATE_CMD_RNDOUTSTART:
1032 return "STATE_CMD_RNDOUTSTART";
1da177e4
LT		 1033 case STATE_ADDR_PAGE:
1034 return "STATE_ADDR_PAGE";
1035 case STATE_ADDR_SEC:
1036 return "STATE_ADDR_SEC";
1037 case STATE_ADDR_ZERO:
1038 return "STATE_ADDR_ZERO";
74216be4
AB		 1039 case STATE_ADDR_COLUMN:
1040 return "STATE_ADDR_COLUMN";
1da177e4
LT		 1041 case STATE_DATAIN:
1042 return "STATE_DATAIN";
1043 case STATE_DATAOUT:
1044 return "STATE_DATAOUT";
1045 case STATE_DATAOUT_ID:
1046 return "STATE_DATAOUT_ID";
1047 case STATE_DATAOUT_STATUS:
1048 return "STATE_DATAOUT_STATUS";
1049 case STATE_DATAOUT_STATUS_M:
1050 return "STATE_DATAOUT_STATUS_M";
1051 case STATE_READY:
1052 return "STATE_READY";
1053 case STATE_UNKNOWN:
1054 return "STATE_UNKNOWN";
1055 }
1056
1057 NS_ERR("get_state_name: unknown state, BUG\n");
1058 return NULL;
1059}
1060
1061/*
1062 * Check if command is valid.
1063 *
1064 * RETURNS: 1 if wrong command, 0 if right.
1065 */
a5602146 1066static int check_command(int cmd)
1da177e4
LT		 1067{
1068 switch (cmd) {
61b03bd7 1069
1da177e4 1070 case NAND_CMD_READ0:
74216be4 1071 case NAND_CMD_READ1:
1da177e4
LT		 1072 case NAND_CMD_READSTART:
1073 case NAND_CMD_PAGEPROG:
1074 case NAND_CMD_READOOB:
1075 case NAND_CMD_ERASE1:
1076 case NAND_CMD_STATUS:
1077 case NAND_CMD_SEQIN:
1078 case NAND_CMD_READID:
1079 case NAND_CMD_ERASE2:
1080 case NAND_CMD_RESET:
74216be4
AB		 1081 case NAND_CMD_RNDOUT:
1082 case NAND_CMD_RNDOUTSTART:
1da177e4 1083 return 0;
61b03bd7 1084
1da177e4
LT		 1085 case NAND_CMD_STATUS_MULTI:
1086 default:
1087 return 1;
1088 }
1089}
1090
1091/*
1092 * Returns state after command is accepted by command number.
1093 */
a5602146 1094static uint32_t get_state_by_command(unsigned command)
1da177e4
LT		 1095{
1096 switch (command) {
1097 case NAND_CMD_READ0:
1098 return STATE_CMD_READ0;
1099 case NAND_CMD_READ1:
1100 return STATE_CMD_READ1;
1101 case NAND_CMD_PAGEPROG:
1102 return STATE_CMD_PAGEPROG;
1103 case NAND_CMD_READSTART:
1104 return STATE_CMD_READSTART;
1105 case NAND_CMD_READOOB:
1106 return STATE_CMD_READOOB;
1107 case NAND_CMD_ERASE1:
1108 return STATE_CMD_ERASE1;
1109 case NAND_CMD_STATUS:
1110 return STATE_CMD_STATUS;
1111 case NAND_CMD_STATUS_MULTI:
1112 return STATE_CMD_STATUS_M;
1113 case NAND_CMD_SEQIN:
1114 return STATE_CMD_SEQIN;
1115 case NAND_CMD_READID:
1116 return STATE_CMD_READID;
1117 case NAND_CMD_ERASE2:
1118 return STATE_CMD_ERASE2;
1119 case NAND_CMD_RESET:
1120 return STATE_CMD_RESET;
74216be4
AB		 1121 case NAND_CMD_RNDOUT:
1122 return STATE_CMD_RNDOUT;
1123 case NAND_CMD_RNDOUTSTART:
1124 return STATE_CMD_RNDOUTSTART;
1da177e4
LT		 1125 }
1126
1127 NS_ERR("get_state_by_command: unknown command, BUG\n");
1128 return 0;
1129}
1130
1131/*
1132 * Move an address byte to the correspondent internal register.
1133 */
a5602146 1134static inline void accept_addr_byte(struct nandsim *ns, u_char bt)
1da177e4
LT		 1135{
1136 uint byte = (uint)bt;
61b03bd7 1137
1da177e4
LT		 1138 if (ns->regs.count < (ns->geom.pgaddrbytes - ns->geom.secaddrbytes))
1139 ns->regs.column |= (byte << 8 * ns->regs.count);
1140 else {
1141 ns->regs.row |= (byte << 8 * (ns->regs.count -
1142 ns->geom.pgaddrbytes +
1143 ns->geom.secaddrbytes));
1144 }
1145
1146 return;
1147}
61b03bd7 1148
1da177e4
LT		 1149/*
1150 * Switch to STATE_READY state.
1151 */
a5602146 1152static inline void switch_to_ready_state(struct nandsim *ns, u_char status)
1da177e4
LT		 1153{
1154 NS_DBG("switch_to_ready_state: switch to %s state\n", get_state_name(STATE_READY));
1155
1156 ns->state = STATE_READY;
1157 ns->nxstate = STATE_UNKNOWN;
1158 ns->op = NULL;
1159 ns->npstates = 0;
1160 ns->stateidx = 0;
1161 ns->regs.num = 0;
1162 ns->regs.count = 0;
1163 ns->regs.off = 0;
1164 ns->regs.row = 0;
1165 ns->regs.column = 0;
1166 ns->regs.status = status;
1167}
1168
1169/*
1170 * If the operation isn't known yet, try to find it in the global array
1171 * of supported operations.
1172 *
1173 * Operation can be unknown because of the following.
1174 * 1. New command was accepted and this is the firs call to find the
1175 * correspondent states chain. In this case ns->npstates = 0;
1176 * 2. There is several operations which begin with the same command(s)
1177 * (for example program from the second half and read from the
1178 * second half operations both begin with the READ1 command). In this
1179 * case the ns->pstates[] array contains previous states.
61b03bd7 1180 *
1da177e4
LT		 1181 * Thus, the function tries to find operation containing the following
1182 * states (if the 'flag' parameter is 0):
1183 * ns->pstates[0], ... ns->pstates[ns->npstates], ns->state
1184 *
1185 * If (one and only one) matching operation is found, it is accepted (
1186 * ns->ops, ns->state, ns->nxstate are initialized, ns->npstate is
1187 * zeroed).
61b03bd7 1188 *
1da177e4
LT		 1189 * If there are several maches, the current state is pushed to the
1190 * ns->pstates.
1191 *
1192 * The operation can be unknown only while commands are input to the chip.
1193 * As soon as address command is accepted, the operation must be known.
1194 * In such situation the function is called with 'flag' != 0, and the
1195 * operation is searched using the following pattern:
1196 * ns->pstates[0], ... ns->pstates[ns->npstates], <address input>
61b03bd7 1197 *
1da177e4
LT		 1198 * It is supposed that this pattern must either match one operation on
1199 * none. There can't be ambiguity in that case.
1200 *
1201 * If no matches found, the functions does the following:
1202 * 1. if there are saved states present, try to ignore them and search
1203 * again only using the last command. If nothing was found, switch
1204 * to the STATE_READY state.
1205 * 2. if there are no saved states, switch to the STATE_READY state.
1206 *
1207 * RETURNS: -2 - no matched operations found.
1208 * -1 - several matches.
1209 * 0 - operation is found.
1210 */
a5602146 1211static int find_operation(struct nandsim *ns, uint32_t flag)
1da177e4
LT		 1212{
1213 int opsfound = 0;
1214 int i, j, idx = 0;
61b03bd7 1215
1da177e4
LT		 1216 for (i = 0; i < NS_OPER_NUM; i++) {
1217
1218 int found = 1;
61b03bd7 1219
1da177e4
LT		 1220 if (!(ns->options & ops[i].reqopts))
1221 /* Ignore operations we can't perform */
1222 continue;
61b03bd7 1223
1da177e4
LT		 1224 if (flag) {
1225 if (!(ops[i].states[ns->npstates] & STATE_ADDR_MASK))
1226 continue;
1227 } else {
1228 if (NS_STATE(ns->state) != NS_STATE(ops[i].states[ns->npstates]))
1229 continue;
1230 }
1231
61b03bd7 1232 for (j = 0; j < ns->npstates; j++)
1da177e4
LT		 1233 if (NS_STATE(ops[i].states[j]) != NS_STATE(ns->pstates[j])
1234 && (ns->options & ops[idx].reqopts)) {
1235 found = 0;
1236 break;
1237 }
1238
1239 if (found) {
1240 idx = i;
1241 opsfound += 1;
1242 }
1243 }
1244
1245 if (opsfound == 1) {
1246 /* Exact match */
1247 ns->op = &ops[idx].states[0];
1248 if (flag) {
61b03bd7 1249 /*
1da177e4
LT		 1250 * In this case the find_operation function was
1251 * called when address has just began input. But it isn't
1252 * yet fully input and the current state must
1253 * not be one of STATE_ADDR_*, but the STATE_ADDR_*
1254 * state must be the next state (ns->nxstate).
1255 */
1256 ns->stateidx = ns->npstates - 1;
1257 } else {
1258 ns->stateidx = ns->npstates;
1259 }
1260 ns->npstates = 0;
1261 ns->state = ns->op[ns->stateidx];
1262 ns->nxstate = ns->op[ns->stateidx + 1];
1263 NS_DBG("find_operation: operation found, index: %d, state: %s, nxstate %s\n",
1264 idx, get_state_name(ns->state), get_state_name(ns->nxstate));
1265 return 0;
1266 }
61b03bd7 1267
1da177e4
LT		 1268 if (opsfound == 0) {
1269 /* Nothing was found. Try to ignore previous commands (if any) and search again */
1270 if (ns->npstates != 0) {
1271 NS_DBG("find_operation: no operation found, try again with state %s\n",
1272 get_state_name(ns->state));
1273 ns->npstates = 0;
1274 return find_operation(ns, 0);
1275
1276 }
1277 NS_DBG("find_operation: no operations found\n");
1278 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1279 return -2;
1280 }
61b03bd7 1281
1da177e4
LT		 1282 if (flag) {
1283 /* This shouldn't happen */
1284 NS_DBG("find_operation: BUG, operation must be known if address is input\n");
1285 return -2;
1286 }
61b03bd7 1287
1da177e4
LT		 1288 NS_DBG("find_operation: there is still ambiguity\n");
1289
1290 ns->pstates[ns->npstates++] = ns->state;
1291
1292 return -1;
1293}
1294
a9fc8991
AH		 1295static void put_pages(struct nandsim *ns)
1296{
1297 int i;
1298
1299 for (i = 0; i < ns->held_cnt; i++)
1300 page_cache_release(ns->held_pages[i]);
1301}
1302
1303/* Get page cache pages in advance to provide NOFS memory allocation */
1304static int get_pages(struct nandsim *ns, struct file *file, size_t count, loff_t pos)
1305{
1306 pgoff_t index, start_index, end_index;
1307 struct page *page;
1308 struct address_space *mapping = file->f_mapping;
1309
1310 start_index = pos >> PAGE_CACHE_SHIFT;
1311 end_index = (pos + count - 1) >> PAGE_CACHE_SHIFT;
1312 if (end_index - start_index + 1 > NS_MAX_HELD_PAGES)
1313 return -EINVAL;
1314 ns->held_cnt = 0;
1315 for (index = start_index; index <= end_index; index++) {
1316 page = find_get_page(mapping, index);
1317 if (page == NULL) {
1318 page = find_or_create_page(mapping, index, GFP_NOFS);
1319 if (page == NULL) {
1320 write_inode_now(mapping->host, 1);
1321 page = find_or_create_page(mapping, index, GFP_NOFS);
1322 }
1323 if (page == NULL) {
1324 put_pages(ns);
1325 return -ENOMEM;
1326 }
1327 unlock_page(page);
1328 }
1329 ns->held_pages[ns->held_cnt++] = page;
1330 }
1331 return 0;
1332}
1333
1334static int set_memalloc(void)
1335{
1336 if (current->flags & PF_MEMALLOC)
1337 return 0;
1338 current->flags |= PF_MEMALLOC;
1339 return 1;
1340}
1341
1342static void clear_memalloc(int memalloc)
1343{
1344 if (memalloc)
1345 current->flags &= ~PF_MEMALLOC;
1346}
1347
1348static ssize_t read_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t *pos)
1349{
1350 mm_segment_t old_fs;
1351 ssize_t tx;
1352 int err, memalloc;
1353
1354 err = get_pages(ns, file, count, *pos);
1355 if (err)
1356 return err;
1357 old_fs = get_fs();
1358 set_fs(get_ds());
1359 memalloc = set_memalloc();
1360 tx = vfs_read(file, (char __user *)buf, count, pos);
1361 clear_memalloc(memalloc);
1362 set_fs(old_fs);
1363 put_pages(ns);
1364 return tx;
1365}
1366
1367static ssize_t write_file(struct nandsim *ns, struct file *file, void *buf, size_t count, loff_t *pos)
1368{
1369 mm_segment_t old_fs;
1370 ssize_t tx;
1371 int err, memalloc;
1372
1373 err = get_pages(ns, file, count, *pos);
1374 if (err)
1375 return err;
1376 old_fs = get_fs();
1377 set_fs(get_ds());
1378 memalloc = set_memalloc();
1379 tx = vfs_write(file, (char __user *)buf, count, pos);
1380 clear_memalloc(memalloc);
1381 set_fs(old_fs);
1382 put_pages(ns);
1383 return tx;
1384}
1385
d086d436
VK		 1386/*
1387 * Returns a pointer to the current page.
1388 */
1389static inline union ns_mem *NS_GET_PAGE(struct nandsim *ns)
1390{
1391 return &(ns->pages[ns->regs.row]);
1392}
1393
1394/*
1395 * Retuns a pointer to the current byte, within the current page.
1396 */
1397static inline u_char *NS_PAGE_BYTE_OFF(struct nandsim *ns)
1398{
1399 return NS_GET_PAGE(ns)->byte + ns->regs.column + ns->regs.off;
1400}
1401
a9fc8991
AH		 1402int do_read_error(struct nandsim *ns, int num)
1403{
1404 unsigned int page_no = ns->regs.row;
1405
1406 if (read_error(page_no)) {
1407 int i;
1408 memset(ns->buf.byte, 0xFF, num);
1409 for (i = 0; i < num; ++i)
1410 ns->buf.byte[i] = random32();
1411 NS_WARN("simulating read error in page %u\n", page_no);
1412 return 1;
1413 }
1414 return 0;
1415}
1416
1417void do_bit_flips(struct nandsim *ns, int num)
1418{
1419 if (bitflips && random32() < (1 << 22)) {
1420 int flips = 1;
1421 if (bitflips > 1)
1422 flips = (random32() % (int) bitflips) + 1;
1423 while (flips--) {
1424 int pos = random32() % (num * 8);
1425 ns->buf.byte[pos / 8] ^= (1 << (pos % 8));
1426 NS_WARN("read_page: flipping bit %d in page %d "
1427 "reading from %d ecc: corrected=%u failed=%u\n",
1428 pos, ns->regs.row, ns->regs.column + ns->regs.off,
1429 nsmtd->ecc_stats.corrected, nsmtd->ecc_stats.failed);
1430 }
1431 }
1432}
1433
d086d436
VK		 1434/*
1435 * Fill the NAND buffer with data read from the specified page.
1436 */
1437static void read_page(struct nandsim *ns, int num)
1438{
1439 union ns_mem *mypage;
1440
a9fc8991
AH		 1441 if (ns->cfile) {
1442 if (!ns->pages_written[ns->regs.row]) {
1443 NS_DBG("read_page: page %d not written\n", ns->regs.row);
1444 memset(ns->buf.byte, 0xFF, num);
1445 } else {
1446 loff_t pos;
1447 ssize_t tx;
1448
1449 NS_DBG("read_page: page %d written, reading from %d\n",
1450 ns->regs.row, ns->regs.column + ns->regs.off);
1451 if (do_read_error(ns, num))
1452 return;
1453 pos = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off;
1454 tx = read_file(ns, ns->cfile, ns->buf.byte, num, &pos);
1455 if (tx != num) {
1456 NS_ERR("read_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1457 return;
1458 }
1459 do_bit_flips(ns, num);
1460 }
1461 return;
1462 }
1463
d086d436
VK		 1464 mypage = NS_GET_PAGE(ns);
1465 if (mypage->byte == NULL) {
1466 NS_DBG("read_page: page %d not allocated\n", ns->regs.row);
1467 memset(ns->buf.byte, 0xFF, num);
1468 } else {
1469 NS_DBG("read_page: page %d allocated, reading from %d\n",
1470 ns->regs.row, ns->regs.column + ns->regs.off);
a9fc8991 1471 if (do_read_error(ns, num))
514087e7 1472 return;
d086d436 1473 memcpy(ns->buf.byte, NS_PAGE_BYTE_OFF(ns), num);
a9fc8991 1474 do_bit_flips(ns, num);
d086d436
VK		 1475 }
1476}
1477
1478/*
1479 * Erase all pages in the specified sector.
1480 */
1481static void erase_sector(struct nandsim *ns)
1482{
1483 union ns_mem *mypage;
1484 int i;
1485
a9fc8991
AH		 1486 if (ns->cfile) {
1487 for (i = 0; i < ns->geom.pgsec; i++)
1488 if (ns->pages_written[ns->regs.row + i]) {
1489 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row + i);
1490 ns->pages_written[ns->regs.row + i] = 0;
1491 }
1492 return;
1493 }
1494
d086d436
VK		 1495 mypage = NS_GET_PAGE(ns);
1496 for (i = 0; i < ns->geom.pgsec; i++) {
1497 if (mypage->byte != NULL) {
1498 NS_DBG("erase_sector: freeing page %d\n", ns->regs.row+i);
8a4c2495 1499 kmem_cache_free(ns->nand_pages_slab, mypage->byte);
d086d436
VK		 1500 mypage->byte = NULL;
1501 }
1502 mypage++;
1503 }
1504}
1505
1506/*
1507 * Program the specified page with the contents from the NAND buffer.
1508 */
1509static int prog_page(struct nandsim *ns, int num)
1510{
82810b7b 1511 int i;
d086d436
VK		 1512 union ns_mem *mypage;
1513 u_char *pg_off;
1514
a9fc8991
AH		 1515 if (ns->cfile) {
1516 loff_t off, pos;
1517 ssize_t tx;
1518 int all;
1519
1520 NS_DBG("prog_page: writing page %d\n", ns->regs.row);
1521 pg_off = ns->file_buf + ns->regs.column + ns->regs.off;
1522 off = (loff_t)ns->regs.row * ns->geom.pgszoob + ns->regs.column + ns->regs.off;
1523 if (!ns->pages_written[ns->regs.row]) {
1524 all = 1;
1525 memset(ns->file_buf, 0xff, ns->geom.pgszoob);
1526 } else {
1527 all = 0;
1528 pos = off;
1529 tx = read_file(ns, ns->cfile, pg_off, num, &pos);
1530 if (tx != num) {
1531 NS_ERR("prog_page: read error for page %d ret %ld\n", ns->regs.row, (long)tx);
1532 return -1;
1533 }
1534 }
1535 for (i = 0; i < num; i++)
1536 pg_off[i] &= ns->buf.byte[i];
1537 if (all) {
1538 pos = (loff_t)ns->regs.row * ns->geom.pgszoob;
1539 tx = write_file(ns, ns->cfile, ns->file_buf, ns->geom.pgszoob, &pos);
1540 if (tx != ns->geom.pgszoob) {
1541 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1542 return -1;
1543 }
1544 ns->pages_written[ns->regs.row] = 1;
1545 } else {
1546 pos = off;
1547 tx = write_file(ns, ns->cfile, pg_off, num, &pos);
1548 if (tx != num) {
1549 NS_ERR("prog_page: write error for page %d ret %ld\n", ns->regs.row, (long)tx);
1550 return -1;
1551 }
1552 }
1553 return 0;
1554 }
1555
d086d436
VK		 1556 mypage = NS_GET_PAGE(ns);
1557 if (mypage->byte == NULL) {
1558 NS_DBG("prog_page: allocating page %d\n", ns->regs.row);
98b830d2
AB		 1559 /*
1560 * We allocate memory with GFP_NOFS because a flash FS may
1561 * utilize this. If it is holding an FS lock, then gets here,
8a4c2495
AK		 1562 * then kernel memory alloc runs writeback which goes to the FS
1563 * again and deadlocks. This was seen in practice.
98b830d2 1564 */
8a4c2495 1565 mypage->byte = kmem_cache_alloc(ns->nand_pages_slab, GFP_NOFS);
d086d436
VK		 1566 if (mypage->byte == NULL) {
1567 NS_ERR("prog_page: error allocating memory for page %d\n", ns->regs.row);
1568 return -1;
1569 }
1570 memset(mypage->byte, 0xFF, ns->geom.pgszoob);
1571 }
1572
1573 pg_off = NS_PAGE_BYTE_OFF(ns);
82810b7b
AB		 1574 for (i = 0; i < num; i++)
1575 pg_off[i] &= ns->buf.byte[i];
d086d436
VK		 1576
1577 return 0;
1578}
1579
1da177e4
LT		 1580/*
1581 * If state has any action bit, perform this action.
1582 *
1583 * RETURNS: 0 if success, -1 if error.
1584 */
a5602146 1585static int do_state_action(struct nandsim *ns, uint32_t action)
1da177e4 1586{
d086d436 1587 int num;
1da177e4 1588 int busdiv = ns->busw == 8 ? 1 : 2;
514087e7 1589 unsigned int erase_block_no, page_no;
1da177e4
LT		 1590
1591 action &= ACTION_MASK;
61b03bd7 1592
1da177e4
LT		 1593 /* Check that page address input is correct */
1594 if (action != ACTION_SECERASE && ns->regs.row >= ns->geom.pgnum) {
1595 NS_WARN("do_state_action: wrong page number (%#x)\n", ns->regs.row);
1596 return -1;
1597 }
1598
1599 switch (action) {
1600
1601 case ACTION_CPY:
1602 /*
1603 * Copy page data to the internal buffer.
1604 */
1605
1606 /* Column shouldn't be very large */
1607 if (ns->regs.column >= (ns->geom.pgszoob - ns->regs.off)) {
1608 NS_ERR("do_state_action: column number is too large\n");
1609 break;
1610 }
1611 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
d086d436 1612 read_page(ns, num);
1da177e4
LT		 1613
1614 NS_DBG("do_state_action: (ACTION_CPY:) copy %d bytes to int buf, raw offset %d\n",
1615 num, NS_RAW_OFFSET(ns) + ns->regs.off);
61b03bd7 1616
1da177e4
LT		 1617 if (ns->regs.off == 0)
1618 NS_LOG("read page %d\n", ns->regs.row);
1619 else if (ns->regs.off < ns->geom.pgsz)
1620 NS_LOG("read page %d (second half)\n", ns->regs.row);
1621 else
1622 NS_LOG("read OOB of page %d\n", ns->regs.row);
61b03bd7 1623
1da177e4
LT		 1624 NS_UDELAY(access_delay);
1625 NS_UDELAY(input_cycle * ns->geom.pgsz / 1000 / busdiv);
1626
1627 break;
1628
1629 case ACTION_SECERASE:
1630 /*
1631 * Erase sector.
1632 */
61b03bd7 1633
1da177e4
LT		 1634 if (ns->lines.wp) {
1635 NS_ERR("do_state_action: device is write-protected, ignore sector erase\n");
1636 return -1;
1637 }
61b03bd7 1638
1da177e4
LT		 1639 if (ns->regs.row >= ns->geom.pgnum - ns->geom.pgsec
1640 || (ns->regs.row & ~(ns->geom.secsz - 1))) {
1641 NS_ERR("do_state_action: wrong sector address (%#x)\n", ns->regs.row);
1642 return -1;
1643 }
61b03bd7 1644
1da177e4
LT		 1645 ns->regs.row = (ns->regs.row <<
1646 8 * (ns->geom.pgaddrbytes - ns->geom.secaddrbytes)) | ns->regs.column;
1647 ns->regs.column = 0;
61b03bd7 1648
514087e7
AH		 1649 erase_block_no = ns->regs.row >> (ns->geom.secshift - ns->geom.pgshift);
1650
1da177e4
LT		 1651 NS_DBG("do_state_action: erase sector at address %#x, off = %d\n",
1652 ns->regs.row, NS_RAW_OFFSET(ns));
514087e7 1653 NS_LOG("erase sector %u\n", erase_block_no);
1da177e4 1654
d086d436 1655 erase_sector(ns);
61b03bd7 1656
1da177e4 1657 NS_MDELAY(erase_delay);
61b03bd7 1658
57aa6b54
AH		 1659 if (erase_block_wear)
1660 update_wear(erase_block_no);
1661
514087e7
AH		 1662 if (erase_error(erase_block_no)) {
1663 NS_WARN("simulating erase failure in erase block %u\n", erase_block_no);
1664 return -1;
1665 }
1666
1da177e4
LT		 1667 break;
1668
1669 case ACTION_PRGPAGE:
1670 /*
1671 * Programm page - move internal buffer data to the page.
1672 */
1673
1674 if (ns->lines.wp) {
1675 NS_WARN("do_state_action: device is write-protected, programm\n");
1676 return -1;
1677 }
1678
1679 num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1680 if (num != ns->regs.count) {
1681 NS_ERR("do_state_action: too few bytes were input (%d instead of %d)\n",
1682 ns->regs.count, num);
1683 return -1;
1684 }
1685
d086d436
VK		 1686 if (prog_page(ns, num) == -1)
1687 return -1;
1da177e4 1688
514087e7
AH		 1689 page_no = ns->regs.row;
1690
1da177e4
LT		 1691 NS_DBG("do_state_action: copy %d bytes from int buf to (%#x, %#x), raw off = %d\n",
1692 num, ns->regs.row, ns->regs.column, NS_RAW_OFFSET(ns) + ns->regs.off);
1693 NS_LOG("programm page %d\n", ns->regs.row);
61b03bd7 1694
1da177e4
LT		 1695 NS_UDELAY(programm_delay);
1696 NS_UDELAY(output_cycle * ns->geom.pgsz / 1000 / busdiv);
61b03bd7 1697
514087e7
AH		 1698 if (write_error(page_no)) {
1699 NS_WARN("simulating write failure in page %u\n", page_no);
1700 return -1;
1701 }
1702
1da177e4 1703 break;
61b03bd7 1704
1da177e4
LT		 1705 case ACTION_ZEROOFF:
1706 NS_DBG("do_state_action: set internal offset to 0\n");
1707 ns->regs.off = 0;
1708 break;
1709
1710 case ACTION_HALFOFF:
1711 if (!(ns->options & OPT_PAGE512_8BIT)) {
1712 NS_ERR("do_state_action: BUG! can't skip half of page for non-512"
1713 "byte page size 8x chips\n");
1714 return -1;
1715 }
1716 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz/2);
1717 ns->regs.off = ns->geom.pgsz/2;
1718 break;
1719
1720 case ACTION_OOBOFF:
1721 NS_DBG("do_state_action: set internal offset to %d\n", ns->geom.pgsz);
1722 ns->regs.off = ns->geom.pgsz;
1723 break;
61b03bd7 1724
1da177e4
LT		 1725 default:
1726 NS_DBG("do_state_action: BUG! unknown action\n");
1727 }
1728
1729 return 0;
1730}
1731
1732/*
1733 * Switch simulator's state.
1734 */
a5602146 1735static void switch_state(struct nandsim *ns)
1da177e4
LT		 1736{
1737 if (ns->op) {
1738 /*
1739 * The current operation have already been identified.
1740 * Just follow the states chain.
1741 */
61b03bd7 1742
1da177e4
LT		 1743 ns->stateidx += 1;
1744 ns->state = ns->nxstate;
1745 ns->nxstate = ns->op[ns->stateidx + 1];
1746
1747 NS_DBG("switch_state: operation is known, switch to the next state, "
1748 "state: %s, nxstate: %s\n",
1749 get_state_name(ns->state), get_state_name(ns->nxstate));
1750
1751 /* See, whether we need to do some action */
1752 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1753 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1754 return;
1755 }
61b03bd7 1756
1da177e4
LT		 1757 } else {
1758 /*
1759 * We don't yet know which operation we perform.
1760 * Try to identify it.
1761 */
1762
61b03bd7 1763 /*
1da177e4
LT		 1764 * The only event causing the switch_state function to
1765 * be called with yet unknown operation is new command.
1766 */
1767 ns->state = get_state_by_command(ns->regs.command);
1768
1769 NS_DBG("switch_state: operation is unknown, try to find it\n");
1770
1771 if (find_operation(ns, 0) != 0)
1772 return;
1773
1774 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
1775 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
1776 return;
1777 }
1778 }
1779
1780 /* For 16x devices column means the page offset in words */
1781 if ((ns->nxstate & STATE_ADDR_MASK) && ns->busw == 16) {
1782 NS_DBG("switch_state: double the column number for 16x device\n");
1783 ns->regs.column <<= 1;
1784 }
1785
1786 if (NS_STATE(ns->nxstate) == STATE_READY) {
1787 /*
1788 * The current state is the last. Return to STATE_READY
1789 */
1790
1791 u_char status = NS_STATUS_OK(ns);
61b03bd7 1792
1da177e4
LT		 1793 /* In case of data states, see if all bytes were input/output */
1794 if ((ns->state & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK))
1795 && ns->regs.count != ns->regs.num) {
1796 NS_WARN("switch_state: not all bytes were processed, %d left\n",
1797 ns->regs.num - ns->regs.count);
1798 status = NS_STATUS_FAILED(ns);
1799 }
61b03bd7 1800
1da177e4
LT		 1801 NS_DBG("switch_state: operation complete, switch to STATE_READY state\n");
1802
1803 switch_to_ready_state(ns, status);
1804
1805 return;
1806 } else if (ns->nxstate & (STATE_DATAIN_MASK | STATE_DATAOUT_MASK)) {
61b03bd7 1807 /*
1da177e4
LT		 1808 * If the next state is data input/output, switch to it now
1809 */
61b03bd7 1810
1da177e4
LT		 1811 ns->state = ns->nxstate;
1812 ns->nxstate = ns->op[++ns->stateidx + 1];
1813 ns->regs.num = ns->regs.count = 0;
1814
1815 NS_DBG("switch_state: the next state is data I/O, switch, "
1816 "state: %s, nxstate: %s\n",
1817 get_state_name(ns->state), get_state_name(ns->nxstate));
1818
1819 /*
1820 * Set the internal register to the count of bytes which
1821 * are expected to be input or output
1822 */
1823 switch (NS_STATE(ns->state)) {
1824 case STATE_DATAIN:
1825 case STATE_DATAOUT:
1826 ns->regs.num = ns->geom.pgszoob - ns->regs.off - ns->regs.column;
1827 break;
61b03bd7 1828
1da177e4
LT		 1829 case STATE_DATAOUT_ID:
1830 ns->regs.num = ns->geom.idbytes;
1831 break;
61b03bd7 1832
1da177e4
LT		 1833 case STATE_DATAOUT_STATUS:
1834 case STATE_DATAOUT_STATUS_M:
1835 ns->regs.count = ns->regs.num = 0;
1836 break;
61b03bd7 1837
1da177e4
LT		 1838 default:
1839 NS_ERR("switch_state: BUG! unknown data state\n");
1840 }
1841
1842 } else if (ns->nxstate & STATE_ADDR_MASK) {
1843 /*
1844 * If the next state is address input, set the internal
1845 * register to the number of expected address bytes
1846 */
1847
1848 ns->regs.count = 0;
61b03bd7 1849
1da177e4
LT		 1850 switch (NS_STATE(ns->nxstate)) {
1851 case STATE_ADDR_PAGE:
1852 ns->regs.num = ns->geom.pgaddrbytes;
61b03bd7 1853
1da177e4
LT		 1854 break;
1855 case STATE_ADDR_SEC:
1856 ns->regs.num = ns->geom.secaddrbytes;
1857 break;
61b03bd7 1858
1da177e4
LT		 1859 case STATE_ADDR_ZERO:
1860 ns->regs.num = 1;
1861 break;
1862
74216be4
AB		 1863 case STATE_ADDR_COLUMN:
1864 /* Column address is always 2 bytes */
1865 ns->regs.num = ns->geom.pgaddrbytes - ns->geom.secaddrbytes;
1866 break;
1867
1da177e4
LT		 1868 default:
1869 NS_ERR("switch_state: BUG! unknown address state\n");
1870 }
1871 } else {
61b03bd7 1872 /*
1da177e4
LT		 1873 * Just reset internal counters.
1874 */
1875
1876 ns->regs.num = 0;
1877 ns->regs.count = 0;
1878 }
1879}
1880
a5602146 1881static u_char ns_nand_read_byte(struct mtd_info *mtd)
1da177e4 1882{
7b8516b7 1883 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
1da177e4
LT		 1884 u_char outb = 0x00;
1885
1886 /* Sanity and correctness checks */
1887 if (!ns->lines.ce) {
1888 NS_ERR("read_byte: chip is disabled, return %#x\n", (uint)outb);
1889 return outb;
1890 }
1891 if (ns->lines.ale || ns->lines.cle) {
1892 NS_ERR("read_byte: ALE or CLE pin is high, return %#x\n", (uint)outb);
1893 return outb;
1894 }
1895 if (!(ns->state & STATE_DATAOUT_MASK)) {
1896 NS_WARN("read_byte: unexpected data output cycle, state is %s "
1897 "return %#x\n", get_state_name(ns->state), (uint)outb);
1898 return outb;
1899 }
1900
1901 /* Status register may be read as many times as it is wanted */
1902 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS) {
1903 NS_DBG("read_byte: return %#x status\n", ns->regs.status);
1904 return ns->regs.status;
1905 }
1906
1907 /* Check if there is any data in the internal buffer which may be read */
1908 if (ns->regs.count == ns->regs.num) {
1909 NS_WARN("read_byte: no more data to output, return %#x\n", (uint)outb);
1910 return outb;
1911 }
1912
1913 switch (NS_STATE(ns->state)) {
1914 case STATE_DATAOUT:
1915 if (ns->busw == 8) {
1916 outb = ns->buf.byte[ns->regs.count];
1917 ns->regs.count += 1;
1918 } else {
1919 outb = (u_char)cpu_to_le16(ns->buf.word[ns->regs.count >> 1]);
1920 ns->regs.count += 2;
1921 }
1922 break;
1923 case STATE_DATAOUT_ID:
1924 NS_DBG("read_byte: read ID byte %d, total = %d\n", ns->regs.count, ns->regs.num);
1925 outb = ns->ids[ns->regs.count];
1926 ns->regs.count += 1;
1927 break;
1928 default:
1929 BUG();
1930 }
61b03bd7 1931
1da177e4
LT		 1932 if (ns->regs.count == ns->regs.num) {
1933 NS_DBG("read_byte: all bytes were read\n");
1934
1935 /*
1936 * The OPT_AUTOINCR allows to read next conseqitive pages without
1937 * new read operation cycle.
1938 */
1939 if ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT) {
1940 ns->regs.count = 0;
1941 if (ns->regs.row + 1 < ns->geom.pgnum)
1942 ns->regs.row += 1;
1943 NS_DBG("read_byte: switch to the next page (%#x)\n", ns->regs.row);
1944 do_state_action(ns, ACTION_CPY);
1945 }
1946 else if (NS_STATE(ns->nxstate) == STATE_READY)
1947 switch_state(ns);
61b03bd7 1948
1da177e4 1949 }
61b03bd7 1950
1da177e4
LT		 1951 return outb;
1952}
1953
a5602146 1954static void ns_nand_write_byte(struct mtd_info *mtd, u_char byte)
1da177e4 1955{
7b8516b7 1956 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
61b03bd7 1957
1da177e4
LT		 1958 /* Sanity and correctness checks */
1959 if (!ns->lines.ce) {
1960 NS_ERR("write_byte: chip is disabled, ignore write\n");
1961 return;
1962 }
1963 if (ns->lines.ale && ns->lines.cle) {
1964 NS_ERR("write_byte: ALE and CLE pins are high simultaneously, ignore write\n");
1965 return;
1966 }
61b03bd7 1967
1da177e4
LT		 1968 if (ns->lines.cle == 1) {
1969 /*
1970 * The byte written is a command.
1971 */
1972
1973 if (byte == NAND_CMD_RESET) {
1974 NS_LOG("reset chip\n");
1975 switch_to_ready_state(ns, NS_STATUS_OK(ns));
1976 return;
1977 }
1978
74216be4
AB		 1979 /* Check that the command byte is correct */
1980 if (check_command(byte)) {
1981 NS_ERR("write_byte: unknown command %#x\n", (uint)byte);
1982 return;
1983 }
1984
1da177e4
LT		 1985 if (NS_STATE(ns->state) == STATE_DATAOUT_STATUS
1986 || NS_STATE(ns->state) == STATE_DATAOUT_STATUS_M
74216be4
AB		 1987 || NS_STATE(ns->state) == STATE_DATAOUT) {
1988 int row = ns->regs.row;
1989
1da177e4 1990 switch_state(ns);
74216be4
AB		 1991 if (byte == NAND_CMD_RNDOUT)
1992 ns->regs.row = row;
1993 }
1da177e4
LT		 1994
1995 /* Check if chip is expecting command */
1996 if (NS_STATE(ns->nxstate) != STATE_UNKNOWN && !(ns->nxstate & STATE_CMD_MASK)) {
9359ea46
AH		 1997 /* Do not warn if only 2 id bytes are read */
1998 if (!(ns->regs.command == NAND_CMD_READID &&
1999 NS_STATE(ns->state) == STATE_DATAOUT_ID && ns->regs.count == 2)) {
2000 /*
2001 * We are in situation when something else (not command)
2002 * was expected but command was input. In this case ignore
2003 * previous command(s)/state(s) and accept the last one.
2004 */
2005 NS_WARN("write_byte: command (%#x) wasn't expected, expected state is %s, "
2006 "ignore previous states\n", (uint)byte, get_state_name(ns->nxstate));
2007 }
1da177e4
LT		 2008 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2009 }
61b03bd7 2010
1da177e4
LT		 2011 NS_DBG("command byte corresponding to %s state accepted\n",
2012 get_state_name(get_state_by_command(byte)));
2013 ns->regs.command = byte;
2014 switch_state(ns);
2015
2016 } else if (ns->lines.ale == 1) {
2017 /*
2018 * The byte written is an address.
2019 */
2020
2021 if (NS_STATE(ns->nxstate) == STATE_UNKNOWN) {
2022
2023 NS_DBG("write_byte: operation isn't known yet, identify it\n");
2024
2025 if (find_operation(ns, 1) < 0)
2026 return;
61b03bd7 2027
1da177e4
LT		 2028 if ((ns->state & ACTION_MASK) && do_state_action(ns, ns->state) < 0) {
2029 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2030 return;
2031 }
61b03bd7 2032
1da177e4
LT		 2033 ns->regs.count = 0;
2034 switch (NS_STATE(ns->nxstate)) {
2035 case STATE_ADDR_PAGE:
2036 ns->regs.num = ns->geom.pgaddrbytes;
2037 break;
2038 case STATE_ADDR_SEC:
2039 ns->regs.num = ns->geom.secaddrbytes;
2040 break;
2041 case STATE_ADDR_ZERO:
2042 ns->regs.num = 1;
2043 break;
2044 default:
2045 BUG();
2046 }
2047 }
2048
2049 /* Check that chip is expecting address */
2050 if (!(ns->nxstate & STATE_ADDR_MASK)) {
2051 NS_ERR("write_byte: address (%#x) isn't expected, expected state is %s, "
2052 "switch to STATE_READY\n", (uint)byte, get_state_name(ns->nxstate));
2053 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2054 return;
2055 }
61b03bd7 2056
1da177e4
LT		 2057 /* Check if this is expected byte */
2058 if (ns->regs.count == ns->regs.num) {
2059 NS_ERR("write_byte: no more address bytes expected\n");
2060 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2061 return;
2062 }
2063
2064 accept_addr_byte(ns, byte);
2065
2066 ns->regs.count += 1;
2067
2068 NS_DBG("write_byte: address byte %#x was accepted (%d bytes input, %d expected)\n",
2069 (uint)byte, ns->regs.count, ns->regs.num);
2070
2071 if (ns->regs.count == ns->regs.num) {
2072 NS_DBG("address (%#x, %#x) is accepted\n", ns->regs.row, ns->regs.column);
2073 switch_state(ns);
2074 }
61b03bd7 2075
1da177e4
LT		 2076 } else {
2077 /*
2078 * The byte written is an input data.
2079 */
61b03bd7 2080
1da177e4
LT		 2081 /* Check that chip is expecting data input */
2082 if (!(ns->state & STATE_DATAIN_MASK)) {
2083 NS_ERR("write_byte: data input (%#x) isn't expected, state is %s, "
2084 "switch to %s\n", (uint)byte,
2085 get_state_name(ns->state), get_state_name(STATE_READY));
2086 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2087 return;
2088 }
2089
2090 /* Check if this is expected byte */
2091 if (ns->regs.count == ns->regs.num) {
2092 NS_WARN("write_byte: %u input bytes has already been accepted, ignore write\n",
2093 ns->regs.num);
2094 return;
2095 }
2096
2097 if (ns->busw == 8) {
2098 ns->buf.byte[ns->regs.count] = byte;
2099 ns->regs.count += 1;
2100 } else {
2101 ns->buf.word[ns->regs.count >> 1] = cpu_to_le16((uint16_t)byte);
2102 ns->regs.count += 2;
2103 }
2104 }
2105
2106 return;
2107}
2108
7abd3ef9
TG		 2109static void ns_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int bitmask)
2110{
2111 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
2112
2113 ns->lines.cle = bitmask & NAND_CLE ? 1 : 0;
2114 ns->lines.ale = bitmask & NAND_ALE ? 1 : 0;
2115 ns->lines.ce = bitmask & NAND_NCE ? 1 : 0;
2116
2117 if (cmd != NAND_CMD_NONE)
2118 ns_nand_write_byte(mtd, cmd);
2119}
2120
a5602146 2121static int ns_device_ready(struct mtd_info *mtd)
1da177e4
LT		 2122{
2123 NS_DBG("device_ready\n");
2124 return 1;
2125}
2126
a5602146 2127static uint16_t ns_nand_read_word(struct mtd_info *mtd)
1da177e4
LT		 2128{
2129 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
2130
2131 NS_DBG("read_word\n");
61b03bd7 2132
1da177e4
LT		 2133 return chip->read_byte(mtd) | (chip->read_byte(mtd) << 8);
2134}
2135
a5602146 2136static void ns_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
1da177e4 2137{
7b8516b7 2138 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
1da177e4
LT		 2139
2140 /* Check that chip is expecting data input */
2141 if (!(ns->state & STATE_DATAIN_MASK)) {
2142 NS_ERR("write_buf: data input isn't expected, state is %s, "
2143 "switch to STATE_READY\n", get_state_name(ns->state));
2144 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2145 return;
2146 }
2147
2148 /* Check if these are expected bytes */
2149 if (ns->regs.count + len > ns->regs.num) {
2150 NS_ERR("write_buf: too many input bytes\n");
2151 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2152 return;
2153 }
2154
2155 memcpy(ns->buf.byte + ns->regs.count, buf, len);
2156 ns->regs.count += len;
61b03bd7 2157
1da177e4
LT		 2158 if (ns->regs.count == ns->regs.num) {
2159 NS_DBG("write_buf: %d bytes were written\n", ns->regs.count);
2160 }
2161}
2162
a5602146 2163static void ns_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
1da177e4 2164{
7b8516b7 2165 struct nandsim *ns = ((struct nand_chip *)mtd->priv)->priv;
1da177e4
LT		 2166
2167 /* Sanity and correctness checks */
2168 if (!ns->lines.ce) {
2169 NS_ERR("read_buf: chip is disabled\n");
2170 return;
2171 }
2172 if (ns->lines.ale || ns->lines.cle) {
2173 NS_ERR("read_buf: ALE or CLE pin is high\n");
2174 return;
2175 }
2176 if (!(ns->state & STATE_DATAOUT_MASK)) {
2177 NS_WARN("read_buf: unexpected data output cycle, current state is %s\n",
2178 get_state_name(ns->state));
2179 return;
2180 }
2181
2182 if (NS_STATE(ns->state) != STATE_DATAOUT) {
2183 int i;
2184
2185 for (i = 0; i < len; i++)
2186 buf[i] = ((struct nand_chip *)mtd->priv)->read_byte(mtd);
2187
2188 return;
2189 }
2190
2191 /* Check if these are expected bytes */
2192 if (ns->regs.count + len > ns->regs.num) {
2193 NS_ERR("read_buf: too many bytes to read\n");
2194 switch_to_ready_state(ns, NS_STATUS_FAILED(ns));
2195 return;
2196 }
2197
2198 memcpy(buf, ns->buf.byte + ns->regs.count, len);
2199 ns->regs.count += len;
61b03bd7 2200
1da177e4
LT		 2201 if (ns->regs.count == ns->regs.num) {
2202 if ((ns->options & OPT_AUTOINCR) && NS_STATE(ns->state) == STATE_DATAOUT) {
2203 ns->regs.count = 0;
2204 if (ns->regs.row + 1 < ns->geom.pgnum)
2205 ns->regs.row += 1;
2206 NS_DBG("read_buf: switch to the next page (%#x)\n", ns->regs.row);
2207 do_state_action(ns, ACTION_CPY);
2208 }
2209 else if (NS_STATE(ns->nxstate) == STATE_READY)
2210 switch_state(ns);
2211 }
61b03bd7 2212
1da177e4
LT		 2213 return;
2214}
2215
a5602146 2216static int ns_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
1da177e4
LT		 2217{
2218 ns_nand_read_buf(mtd, (u_char *)&ns_verify_buf[0], len);
2219
2220 if (!memcmp(buf, &ns_verify_buf[0], len)) {
2221 NS_DBG("verify_buf: the buffer is OK\n");
2222 return 0;
2223 } else {
2224 NS_DBG("verify_buf: the buffer is wrong\n");
2225 return -EFAULT;
2226 }
2227}
2228
1da177e4
LT		 2229/*
2230 * Module initialization function
2231 */
2b9175c1 2232static int __init ns_init_module(void)
1da177e4
LT		 2233{
2234 struct nand_chip *chip;
2235 struct nandsim *nand;
2b77a0ed 2236 int retval = -ENOMEM, i;
1da177e4
LT		 2237
2238 if (bus_width != 8 && bus_width != 16) {
2239 NS_ERR("wrong bus width (%d), use only 8 or 16\n", bus_width);
2240 return -EINVAL;
2241 }
61b03bd7 2242
1da177e4 2243 /* Allocate and initialize mtd_info, nand_chip and nandsim structures */
95b93a0c 2244 nsmtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip)
1da177e4
LT		 2245 + sizeof(struct nandsim), GFP_KERNEL);
2246 if (!nsmtd) {
2247 NS_ERR("unable to allocate core structures.\n");
2248 return -ENOMEM;
2249 }
1da177e4
LT		 2250 chip = (struct nand_chip *)(nsmtd + 1);
2251 nsmtd->priv = (void *)chip;
2252 nand = (struct nandsim *)(chip + 1);
61b03bd7 2253 chip->priv = (void *)nand;
1da177e4
LT		 2254
2255 /*
2256 * Register simulator's callbacks.
2257 */
7abd3ef9 2258 chip->cmd_ctrl = ns_hwcontrol;
1da177e4
LT		 2259 chip->read_byte = ns_nand_read_byte;
2260 chip->dev_ready = ns_device_ready;
1da177e4
LT		 2261 chip->write_buf = ns_nand_write_buf;
2262 chip->read_buf = ns_nand_read_buf;
2263 chip->verify_buf = ns_nand_verify_buf;
1da177e4 2264 chip->read_word = ns_nand_read_word;
6dfc6d25 2265 chip->ecc.mode = NAND_ECC_SOFT;
a5ac8aeb
AH		 2266 /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */
2267 /* and 'badblocks' parameters to work */
51502287 2268 chip->options |= NAND_SKIP_BBTSCAN;
1da177e4 2269
ce85b79f
SAS		 2270 switch (bbt) {
2271 case 2:
2272 chip->options |= NAND_USE_FLASH_BBT_NO_OOB;
2273 case 1:
2274 chip->options |= NAND_USE_FLASH_BBT;
2275 case 0:
2276 break;
2277 default:
2278 NS_ERR("bbt has to be 0..2\n");
2279 retval = -EINVAL;
2280 goto error;
2281 }
61b03bd7 2282 /*
1da177e4 2283 * Perform minimum nandsim structure initialization to handle
61b03bd7 2284 * the initial ID read command correctly
1da177e4
LT		 2285 */
2286 if (third_id_byte != 0xFF || fourth_id_byte != 0xFF)
2287 nand->geom.idbytes = 4;
2288 else
2289 nand->geom.idbytes = 2;
2290 nand->regs.status = NS_STATUS_OK(nand);
2291 nand->nxstate = STATE_UNKNOWN;
2292 nand->options |= OPT_PAGE256; /* temporary value */
2293 nand->ids[0] = first_id_byte;
2294 nand->ids[1] = second_id_byte;
2295 nand->ids[2] = third_id_byte;
2296 nand->ids[3] = fourth_id_byte;
2297 if (bus_width == 16) {
2298 nand->busw = 16;
2299 chip->options |= NAND_BUSWIDTH_16;
2300 }
2301
552d9205
DW		 2302 nsmtd->owner = THIS_MODULE;
2303
514087e7
AH		 2304 if ((retval = parse_weakblocks()) != 0)
2305 goto error;
2306
2307 if ((retval = parse_weakpages()) != 0)
2308 goto error;
2309
2310 if ((retval = parse_gravepages()) != 0)
2311 goto error;
2312
1da177e4
LT		 2313 if ((retval = nand_scan(nsmtd, 1)) != 0) {
2314 NS_ERR("can't register NAND Simulator\n");
2315 if (retval > 0)
2316 retval = -ENXIO;
2317 goto error;
2318 }
2319
a5ac8aeb 2320 if (overridesize) {
0f07a0be 2321 uint64_t new_size = (uint64_t)nsmtd->erasesize << overridesize;
a5ac8aeb
AH		 2322 if (new_size >> overridesize != nsmtd->erasesize) {
2323 NS_ERR("overridesize is too big\n");
2324 goto err_exit;
2325 }
2326 /* N.B. This relies on nand_scan not doing anything with the size before we change it */
2327 nsmtd->size = new_size;
2328 chip->chipsize = new_size;
6eda7a55 2329 chip->chip_shift = ffs(nsmtd->erasesize) + overridesize - 1;
07293b20 2330 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
a5ac8aeb
AH		 2331 }
2332
57aa6b54
AH		 2333 if ((retval = setup_wear_reporting(nsmtd)) != 0)
2334 goto err_exit;
2335
2b77a0ed
AH		 2336 if ((retval = init_nandsim(nsmtd)) != 0)
2337 goto err_exit;
61b03bd7 2338
ce85b79f 2339 if ((retval = nand_default_bbt(nsmtd)) != 0)
514087e7
AH		 2340 goto err_exit;
2341
ce85b79f 2342 if ((retval = parse_badblocks(nand, nsmtd)) != 0)
2b77a0ed 2343 goto err_exit;
51502287 2344
2b77a0ed
AH		 2345 /* Register NAND partitions */
2346 if ((retval = add_mtd_partitions(nsmtd, &nand->partitions[0], nand->nbparts)) != 0)
2347 goto err_exit;
1da177e4
LT		 2348
2349 return 0;
2350
2b77a0ed
AH		 2351err_exit:
2352 free_nandsim(nand);
2353 nand_release(nsmtd);
2354 for (i = 0;i < ARRAY_SIZE(nand->partitions); ++i)
2355 kfree(nand->partitions[i].name);
1da177e4
LT		 2356error:
2357 kfree(nsmtd);
514087e7 2358 free_lists();
1da177e4
LT		 2359
2360 return retval;
2361}
2362
2363module_init(ns_init_module);
2364
2365/*
2366 * Module clean-up function
2367 */
2368static void __exit ns_cleanup_module(void)
2369{
7b8516b7 2370 struct nandsim *ns = ((struct nand_chip *)nsmtd->priv)->priv;
2b77a0ed 2371 int i;
1da177e4
LT		 2372
2373 free_nandsim(ns); /* Free nandsim private resources */
2b77a0ed
AH		 2374 nand_release(nsmtd); /* Unregister driver */
2375 for (i = 0;i < ARRAY_SIZE(ns->partitions); ++i)
2376 kfree(ns->partitions[i].name);
1da177e4 2377 kfree(nsmtd); /* Free other structures */
514087e7 2378 free_lists();
1da177e4
LT		 2379}
2380
2381module_exit(ns_cleanup_module);
2382
2383MODULE_LICENSE ("GPL");
2384MODULE_AUTHOR ("Artem B. Bityuckiy");
2385MODULE_DESCRIPTION ("The NAND flash simulator");
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