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mtd: fix all checkpatch errors in nand_base.c
[net-next-2.6.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
1da177e4
LT		 45#include <linux/interrupt.h>
46#include <linux/bitops.h>
8fe833c1 47#include <linux/leds.h>
1da177e4
LT		 48#include <asm/io.h>
49
50#ifdef CONFIG_MTD_PARTITIONS
51#include <linux/mtd/partitions.h>
52#endif
53
54/* Define default oob placement schemes for large and small page devices */
5bd34c09 55static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 56 .eccbytes = 3,
57 .eccpos = {0, 1, 2},
5bd34c09
TG		 58 .oobfree = {
59 {.offset = 3,
60 .length = 2},
61 {.offset = 6,
f8ac0414 62 .length = 2} }
1da177e4
LT		 63};
64
5bd34c09 65static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 66 .eccbytes = 6,
67 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 68 .oobfree = {
69 {.offset = 8,
f8ac0414 70 . length = 8} }
1da177e4
LT		 71};
72
5bd34c09 73static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 74 .eccbytes = 24,
75 .eccpos = {
e0c7d767
DW		 76 40, 41, 42, 43, 44, 45, 46, 47,
77 48, 49, 50, 51, 52, 53, 54, 55,
78 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 79 .oobfree = {
80 {.offset = 2,
f8ac0414 81 .length = 38} }
1da177e4
LT		 82};
83
81ec5364
TG		 84static struct nand_ecclayout nand_oob_128 = {
85 .eccbytes = 48,
86 .eccpos = {
87 80, 81, 82, 83, 84, 85, 86, 87,
88 88, 89, 90, 91, 92, 93, 94, 95,
89 96, 97, 98, 99, 100, 101, 102, 103,
90 104, 105, 106, 107, 108, 109, 110, 111,
91 112, 113, 114, 115, 116, 117, 118, 119,
92 120, 121, 122, 123, 124, 125, 126, 127},
93 .oobfree = {
94 {.offset = 2,
f8ac0414 95 .length = 78} }
81ec5364
TG		 96};
97
ace4dfee 98static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 99 int new_state);
1da177e4 100
8593fbc6
TG		 101static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
102 struct mtd_oob_ops *ops);
103
d470a97c 104/*
8e87d782 105 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 106 * compiled away when LED support is disabled.
107 */
108DEFINE_LED_TRIGGER(nand_led_trigger);
109
6fe5a6ac
VS		 110static int check_offs_len(struct mtd_info *mtd,
111 loff_t ofs, uint64_t len)
112{
113 struct nand_chip *chip = mtd->priv;
114 int ret = 0;
115
116 /* Start address must align on block boundary */
117 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
118 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
119 ret = -EINVAL;
120 }
121
122 /* Length must align on block boundary */
123 if (len & ((1 << chip->phys_erase_shift) - 1)) {
124 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
125 __func__);
126 ret = -EINVAL;
127 }
128
129 /* Do not allow past end of device */
130 if (ofs + len > mtd->size) {
131 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
132 __func__);
133 ret = -EINVAL;
134 }
135
136 return ret;
137}
138
1da177e4
LT		 139/**
140 * nand_release_device - [GENERIC] release chip
141 * @mtd: MTD device structure
61b03bd7
TG		 142 *
143 * Deselect, release chip lock and wake up anyone waiting on the device
1da177e4 144 */
e0c7d767 145static void nand_release_device(struct mtd_info *mtd)
1da177e4 146{
ace4dfee 147 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 148
149 /* De-select the NAND device */
ace4dfee 150 chip->select_chip(mtd, -1);
0dfc6246 151
a36ed299 152 /* Release the controller and the chip */
ace4dfee
TG		 153 spin_lock(&chip->controller->lock);
154 chip->controller->active = NULL;
155 chip->state = FL_READY;
156 wake_up(&chip->controller->wq);
157 spin_unlock(&chip->controller->lock);
1da177e4
LT		 158}
159
160/**
161 * nand_read_byte - [DEFAULT] read one byte from the chip
162 * @mtd: MTD device structure
163 *
164 * Default read function for 8bit buswith
165 */
58dd8f2b 166static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 167{
ace4dfee
TG		 168 struct nand_chip *chip = mtd->priv;
169 return readb(chip->IO_ADDR_R);
1da177e4
LT		 170}
171
1da177e4
LT		 172/**
173 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
174 * @mtd: MTD device structure
175 *
61b03bd7 176 * Default read function for 16bit buswith with
1da177e4
LT		 177 * endianess conversion
178 */
58dd8f2b 179static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 180{
ace4dfee
TG		 181 struct nand_chip *chip = mtd->priv;
182 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 183}
184
1da177e4
LT		 185/**
186 * nand_read_word - [DEFAULT] read one word from the chip
187 * @mtd: MTD device structure
188 *
61b03bd7 189 * Default read function for 16bit buswith without
1da177e4
LT		 190 * endianess conversion
191 */
192static u16 nand_read_word(struct mtd_info *mtd)
193{
ace4dfee
TG		 194 struct nand_chip *chip = mtd->priv;
195 return readw(chip->IO_ADDR_R);
1da177e4
LT		 196}
197
1da177e4
LT		 198/**
199 * nand_select_chip - [DEFAULT] control CE line
200 * @mtd: MTD device structure
844d3b42 201 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 202 *
203 * Default select function for 1 chip devices.
204 */
ace4dfee 205static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 206{
ace4dfee
TG		 207 struct nand_chip *chip = mtd->priv;
208
209 switch (chipnr) {
1da177e4 210 case -1:
ace4dfee 211 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 212 break;
213 case 0:
1da177e4
LT		 214 break;
215
216 default:
217 BUG();
218 }
219}
220
221/**
222 * nand_write_buf - [DEFAULT] write buffer to chip
223 * @mtd: MTD device structure
224 * @buf: data buffer
225 * @len: number of bytes to write
226 *
227 * Default write function for 8bit buswith
228 */
58dd8f2b 229static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 230{
231 int i;
ace4dfee 232 struct nand_chip *chip = mtd->priv;
1da177e4 233
e0c7d767 234 for (i = 0; i < len; i++)
ace4dfee 235 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 236}
237
238/**
61b03bd7 239 * nand_read_buf - [DEFAULT] read chip data into buffer
1da177e4
LT		 240 * @mtd: MTD device structure
241 * @buf: buffer to store date
242 * @len: number of bytes to read
243 *
244 * Default read function for 8bit buswith
245 */
58dd8f2b 246static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 247{
248 int i;
ace4dfee 249 struct nand_chip *chip = mtd->priv;
1da177e4 250
e0c7d767 251 for (i = 0; i < len; i++)
ace4dfee 252 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 253}
254
255/**
61b03bd7 256 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 257 * @mtd: MTD device structure
258 * @buf: buffer containing the data to compare
259 * @len: number of bytes to compare
260 *
261 * Default verify function for 8bit buswith
262 */
58dd8f2b 263static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 264{
265 int i;
ace4dfee 266 struct nand_chip *chip = mtd->priv;
1da177e4 267
e0c7d767 268 for (i = 0; i < len; i++)
ace4dfee 269 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 270 return -EFAULT;
1da177e4
LT		 271 return 0;
272}
273
274/**
275 * nand_write_buf16 - [DEFAULT] write buffer to chip
276 * @mtd: MTD device structure
277 * @buf: data buffer
278 * @len: number of bytes to write
279 *
280 * Default write function for 16bit buswith
281 */
58dd8f2b 282static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 283{
284 int i;
ace4dfee 285 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 286 u16 *p = (u16 *) buf;
287 len >>= 1;
61b03bd7 288
e0c7d767 289 for (i = 0; i < len; i++)
ace4dfee 290 writew(p[i], chip->IO_ADDR_W);
61b03bd7 291
1da177e4
LT		 292}
293
294/**
61b03bd7 295 * nand_read_buf16 - [DEFAULT] read chip data into buffer
1da177e4
LT		 296 * @mtd: MTD device structure
297 * @buf: buffer to store date
298 * @len: number of bytes to read
299 *
300 * Default read function for 16bit buswith
301 */
58dd8f2b 302static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 303{
304 int i;
ace4dfee 305 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 306 u16 *p = (u16 *) buf;
307 len >>= 1;
308
e0c7d767 309 for (i = 0; i < len; i++)
ace4dfee 310 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 311}
312
313/**
61b03bd7 314 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 315 * @mtd: MTD device structure
316 * @buf: buffer containing the data to compare
317 * @len: number of bytes to compare
318 *
319 * Default verify function for 16bit buswith
320 */
58dd8f2b 321static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 322{
323 int i;
ace4dfee 324 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 325 u16 *p = (u16 *) buf;
326 len >>= 1;
327
e0c7d767 328 for (i = 0; i < len; i++)
ace4dfee 329 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 330 return -EFAULT;
331
332 return 0;
333}
334
335/**
336 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
337 * @mtd: MTD device structure
338 * @ofs: offset from device start
339 * @getchip: 0, if the chip is already selected
340 *
61b03bd7 341 * Check, if the block is bad.
1da177e4
LT		 342 */
343static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
344{
345 int page, chipnr, res = 0;
ace4dfee 346 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 347 u16 bad;
348
30fe8115 349 if (chip->options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 350 ofs += mtd->erasesize - mtd->writesize;
351
1a12f46a
TK		 352 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
353
1da177e4 354 if (getchip) {
ace4dfee 355 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 356
ace4dfee 357 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 358
359 /* Select the NAND device */
ace4dfee 360 chip->select_chip(mtd, chipnr);
1a12f46a 361 }
1da177e4 362
ace4dfee
TG		 363 if (chip->options & NAND_BUSWIDTH_16) {
364 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
1a12f46a 365 page);
ace4dfee
TG		 366 bad = cpu_to_le16(chip->read_word(mtd));
367 if (chip->badblockpos & 0x1)
49196f33 368 bad >>= 8;
e0b58d0a
ML		 369 else
370 bad &= 0xFF;
1da177e4 371 } else {
1a12f46a 372 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
e0b58d0a 373 bad = chip->read_byte(mtd);
1da177e4 374 }
61b03bd7 375
e0b58d0a
ML		 376 if (likely(chip->badblockbits == 8))
377 res = bad != 0xFF;
378 else
379 res = hweight8(bad) < chip->badblockbits;
380
ace4dfee 381 if (getchip)
1da177e4 382 nand_release_device(mtd);
61b03bd7 383
1da177e4
LT		 384 return res;
385}
386
387/**
388 * nand_default_block_markbad - [DEFAULT] mark a block bad
389 * @mtd: MTD device structure
390 * @ofs: offset from device start
391 *
392 * This is the default implementation, which can be overridden by
393 * a hardware specific driver.
394*/
395static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
396{
ace4dfee 397 struct nand_chip *chip = mtd->priv;
58dd8f2b 398 uint8_t buf[2] = { 0, 0 };
02ed70bb 399 int block, ret, i = 0;
61b03bd7 400
30fe8115 401 if (chip->options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 402 ofs += mtd->erasesize - mtd->writesize;
403
1da177e4 404 /* Get block number */
4226b510 405 block = (int)(ofs >> chip->bbt_erase_shift);
ace4dfee
TG		 406 if (chip->bbt)
407 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4
LT		 408
409 /* Do we have a flash based bad block table ? */
ace4dfee 410 if (chip->options & NAND_USE_FLASH_BBT)
f1a28c02
TG		 411 ret = nand_update_bbt(mtd, ofs);
412 else {
c0b8ba7b 413 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 414
02ed70bb
BN		 415 /* Write to first two pages and to byte 1 and 6 if necessary.
416 * If we write to more than one location, the first error
417 * encountered quits the procedure. We write two bytes per
418 * location, so we dont have to mess with 16 bit access.
419 */
420 do {
421 chip->ops.len = chip->ops.ooblen = 2;
422 chip->ops.datbuf = NULL;
423 chip->ops.oobbuf = buf;
424 chip->ops.ooboffs = chip->badblockpos & ~0x01;
425
426 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
427
428 if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) {
429 chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS
430 & ~0x01;
431 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
432 }
433 i++;
434 ofs += mtd->writesize;
435 } while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) &&
436 i < 2);
437
c0b8ba7b 438 nand_release_device(mtd);
f1a28c02
TG		 439 }
440 if (!ret)
441 mtd->ecc_stats.badblocks++;
c0b8ba7b 442
f1a28c02 443 return ret;
1da177e4
LT		 444}
445
61b03bd7 446/**
1da177e4
LT		 447 * nand_check_wp - [GENERIC] check if the chip is write protected
448 * @mtd: MTD device structure
61b03bd7 449 * Check, if the device is write protected
1da177e4 450 *
61b03bd7 451 * The function expects, that the device is already selected
1da177e4 452 */
e0c7d767 453static int nand_check_wp(struct mtd_info *mtd)
1da177e4 454{
ace4dfee 455 struct nand_chip *chip = mtd->priv;
93edbad6
ML		 456
457 /* broken xD cards report WP despite being writable */
458 if (chip->options & NAND_BROKEN_XD)
459 return 0;
460
1da177e4 461 /* Check the WP bit */
ace4dfee
TG		 462 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
463 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 464}
465
466/**
467 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
468 * @mtd: MTD device structure
469 * @ofs: offset from device start
470 * @getchip: 0, if the chip is already selected
471 * @allowbbt: 1, if its allowed to access the bbt area
472 *
473 * Check, if the block is bad. Either by reading the bad block table or
474 * calling of the scan function.
475 */
2c0a2bed
TG		 476static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
477 int allowbbt)
1da177e4 478{
ace4dfee 479 struct nand_chip *chip = mtd->priv;
61b03bd7 480
ace4dfee
TG		 481 if (!chip->bbt)
482 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 483
1da177e4 484 /* Return info from the table */
e0c7d767 485 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 486}
487
2af7c653
SK		 488/**
489 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
490 * @mtd: MTD device structure
491 * @timeo: Timeout
492 *
493 * Helper function for nand_wait_ready used when needing to wait in interrupt
494 * context.
495 */
496static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
497{
498 struct nand_chip *chip = mtd->priv;
499 int i;
500
501 /* Wait for the device to get ready */
502 for (i = 0; i < timeo; i++) {
503 if (chip->dev_ready(mtd))
504 break;
505 touch_softlockup_watchdog();
506 mdelay(1);
507 }
508}
509
61b03bd7 510/*
3b88775c
TG		 511 * Wait for the ready pin, after a command
512 * The timeout is catched later.
513 */
4b648b02 514void nand_wait_ready(struct mtd_info *mtd)
3b88775c 515{
ace4dfee 516 struct nand_chip *chip = mtd->priv;
e0c7d767 517 unsigned long timeo = jiffies + 2;
3b88775c 518
2af7c653
SK		 519 /* 400ms timeout */
520 if (in_interrupt() || oops_in_progress)
521 return panic_nand_wait_ready(mtd, 400);
522
8fe833c1 523 led_trigger_event(nand_led_trigger, LED_FULL);
3b88775c
TG		 524 /* wait until command is processed or timeout occures */
525 do {
ace4dfee 526 if (chip->dev_ready(mtd))
8fe833c1 527 break;
8446f1d3 528 touch_softlockup_watchdog();
61b03bd7 529 } while (time_before(jiffies, timeo));
8fe833c1 530 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 531}
4b648b02 532EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 533
1da177e4
LT		 534/**
535 * nand_command - [DEFAULT] Send command to NAND device
536 * @mtd: MTD device structure
537 * @command: the command to be sent
538 * @column: the column address for this command, -1 if none
539 * @page_addr: the page address for this command, -1 if none
540 *
541 * Send command to NAND device. This function is used for small page
542 * devices (256/512 Bytes per page)
543 */
7abd3ef9
TG		 544static void nand_command(struct mtd_info *mtd, unsigned int command,
545 int column, int page_addr)
1da177e4 546{
ace4dfee 547 register struct nand_chip *chip = mtd->priv;
7abd3ef9 548 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 549
1da177e4
LT		 550 /*
551 * Write out the command to the device.
552 */
553 if (command == NAND_CMD_SEQIN) {
554 int readcmd;
555
28318776 556 if (column >= mtd->writesize) {
1da177e4 557 /* OOB area */
28318776 558 column -= mtd->writesize;
1da177e4
LT		 559 readcmd = NAND_CMD_READOOB;
560 } else if (column < 256) {
561 /* First 256 bytes --> READ0 */
562 readcmd = NAND_CMD_READ0;
563 } else {
564 column -= 256;
565 readcmd = NAND_CMD_READ1;
566 }
ace4dfee 567 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 568 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 569 }
ace4dfee 570 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 571
7abd3ef9
TG		 572 /*
573 * Address cycle, when necessary
574 */
575 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
576 /* Serially input address */
577 if (column != -1) {
578 /* Adjust columns for 16 bit buswidth */
ace4dfee 579 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 580 column >>= 1;
ace4dfee 581 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 582 ctrl &= ~NAND_CTRL_CHANGE;
583 }
584 if (page_addr != -1) {
ace4dfee 585 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 586 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 587 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 588 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 589 if (chip->chipsize > (32 << 20))
590 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 591 }
ace4dfee 592 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 593
594 /*
595 * program and erase have their own busy handlers
1da177e4 596 * status and sequential in needs no delay
e0c7d767 597 */
1da177e4 598 switch (command) {
61b03bd7 599
1da177e4
LT		 600 case NAND_CMD_PAGEPROG:
601 case NAND_CMD_ERASE1:
602 case NAND_CMD_ERASE2:
603 case NAND_CMD_SEQIN:
604 case NAND_CMD_STATUS:
605 return;
606
607 case NAND_CMD_RESET:
ace4dfee 608 if (chip->dev_ready)
1da177e4 609 break;
ace4dfee
TG		 610 udelay(chip->chip_delay);
611 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 612 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 613 chip->cmd_ctrl(mtd,
614 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 615 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
616 ;
1da177e4
LT		 617 return;
618
e0c7d767 619 /* This applies to read commands */
1da177e4 620 default:
61b03bd7 621 /*
1da177e4
LT		 622 * If we don't have access to the busy pin, we apply the given
623 * command delay
e0c7d767 624 */
ace4dfee
TG		 625 if (!chip->dev_ready) {
626 udelay(chip->chip_delay);
1da177e4 627 return;
61b03bd7 628 }
1da177e4 629 }
1da177e4
LT		 630 /* Apply this short delay always to ensure that we do wait tWB in
631 * any case on any machine. */
e0c7d767 632 ndelay(100);
3b88775c
TG		 633
634 nand_wait_ready(mtd);
1da177e4
LT		 635}
636
637/**
638 * nand_command_lp - [DEFAULT] Send command to NAND large page device
639 * @mtd: MTD device structure
640 * @command: the command to be sent
641 * @column: the column address for this command, -1 if none
642 * @page_addr: the page address for this command, -1 if none
643 *
7abd3ef9
TG		 644 * Send command to NAND device. This is the version for the new large page
645 * devices We dont have the separate regions as we have in the small page
646 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 647 */
7abd3ef9
TG		 648static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
649 int column, int page_addr)
1da177e4 650{
ace4dfee 651 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 652
653 /* Emulate NAND_CMD_READOOB */
654 if (command == NAND_CMD_READOOB) {
28318776 655 column += mtd->writesize;
1da177e4
LT		 656 command = NAND_CMD_READ0;
657 }
61b03bd7 658
7abd3ef9 659 /* Command latch cycle */
ace4dfee 660 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 661 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 662
663 if (column != -1 || page_addr != -1) {
7abd3ef9 664 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 665
666 /* Serially input address */
667 if (column != -1) {
668 /* Adjust columns for 16 bit buswidth */
ace4dfee 669 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 670 column >>= 1;
ace4dfee 671 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 672 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 673 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 674 }
1da177e4 675 if (page_addr != -1) {
ace4dfee
TG		 676 chip->cmd_ctrl(mtd, page_addr, ctrl);
677 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 678 NAND_NCE | NAND_ALE);
1da177e4 679 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 680 if (chip->chipsize > (128 << 20))
681 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 682 NAND_NCE | NAND_ALE);
1da177e4 683 }
1da177e4 684 }
ace4dfee 685 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 686
687 /*
688 * program and erase have their own busy handlers
30f464b7
DM		 689 * status, sequential in, and deplete1 need no delay
690 */
1da177e4 691 switch (command) {
61b03bd7 692
1da177e4
LT		 693 case NAND_CMD_CACHEDPROG:
694 case NAND_CMD_PAGEPROG:
695 case NAND_CMD_ERASE1:
696 case NAND_CMD_ERASE2:
697 case NAND_CMD_SEQIN:
7bc3312b 698 case NAND_CMD_RNDIN:
1da177e4 699 case NAND_CMD_STATUS:
30f464b7 700 case NAND_CMD_DEPLETE1:
1da177e4
LT		 701 return;
702
e0c7d767
DW		 703 /*
704 * read error status commands require only a short delay
705 */
30f464b7
DM		 706 case NAND_CMD_STATUS_ERROR:
707 case NAND_CMD_STATUS_ERROR0:
708 case NAND_CMD_STATUS_ERROR1:
709 case NAND_CMD_STATUS_ERROR2:
710 case NAND_CMD_STATUS_ERROR3:
ace4dfee 711 udelay(chip->chip_delay);
30f464b7 712 return;
1da177e4
LT		 713
714 case NAND_CMD_RESET:
ace4dfee 715 if (chip->dev_ready)
1da177e4 716 break;
ace4dfee 717 udelay(chip->chip_delay);
12efdde3
TG		 718 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
719 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
720 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
721 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 722 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
723 ;
1da177e4
LT		 724 return;
725
7bc3312b
TG		 726 case NAND_CMD_RNDOUT:
727 /* No ready / busy check necessary */
728 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
729 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
730 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
731 NAND_NCE | NAND_CTRL_CHANGE);
732 return;
733
1da177e4 734 case NAND_CMD_READ0:
12efdde3
TG		 735 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
736 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
737 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
738 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 739
e0c7d767 740 /* This applies to read commands */
1da177e4 741 default:
61b03bd7 742 /*
1da177e4
LT		 743 * If we don't have access to the busy pin, we apply the given
744 * command delay
e0c7d767 745 */
ace4dfee
TG		 746 if (!chip->dev_ready) {
747 udelay(chip->chip_delay);
1da177e4 748 return;
61b03bd7 749 }
1da177e4 750 }
3b88775c 751
1da177e4
LT		 752 /* Apply this short delay always to ensure that we do wait tWB in
753 * any case on any machine. */
e0c7d767 754 ndelay(100);
3b88775c
TG		 755
756 nand_wait_ready(mtd);
1da177e4
LT		 757}
758
2af7c653
SK		 759/**
760 * panic_nand_get_device - [GENERIC] Get chip for selected access
761 * @chip: the nand chip descriptor
762 * @mtd: MTD device structure
763 * @new_state: the state which is requested
764 *
765 * Used when in panic, no locks are taken.
766 */
767static void panic_nand_get_device(struct nand_chip *chip,
768 struct mtd_info *mtd, int new_state)
769{
770 /* Hardware controller shared among independend devices */
771 chip->controller->active = chip;
772 chip->state = new_state;
773}
774
1da177e4
LT		 775/**
776 * nand_get_device - [GENERIC] Get chip for selected access
844d3b42 777 * @chip: the nand chip descriptor
1da177e4 778 * @mtd: MTD device structure
61b03bd7 779 * @new_state: the state which is requested
1da177e4
LT		 780 *
781 * Get the device and lock it for exclusive access
782 */
2c0a2bed 783static int
ace4dfee 784nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 785{
ace4dfee
TG		 786 spinlock_t *lock = &chip->controller->lock;
787 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 788 DECLARE_WAITQUEUE(wait, current);
e0c7d767 789 retry:
0dfc6246
TG		 790 spin_lock(lock);
791
b8b3ee9a 792 /* Hardware controller shared among independent devices */
ace4dfee
TG		 793 if (!chip->controller->active)
794 chip->controller->active = chip;
a36ed299 795
ace4dfee
TG		 796 if (chip->controller->active == chip && chip->state == FL_READY) {
797 chip->state = new_state;
0dfc6246 798 spin_unlock(lock);
962034f4
VW		 799 return 0;
800 }
801 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 802 if (chip->controller->active->state == FL_PM_SUSPENDED) {
803 chip->state = FL_PM_SUSPENDED;
804 spin_unlock(lock);
805 return 0;
6b0d9a84 806 }
0dfc6246
TG		 807 }
808 set_current_state(TASK_UNINTERRUPTIBLE);
809 add_wait_queue(wq, &wait);
810 spin_unlock(lock);
811 schedule();
812 remove_wait_queue(wq, &wait);
1da177e4
LT		 813 goto retry;
814}
815
2af7c653
SK		 816/**
817 * panic_nand_wait - [GENERIC] wait until the command is done
818 * @mtd: MTD device structure
819 * @chip: NAND chip structure
820 * @timeo: Timeout
821 *
822 * Wait for command done. This is a helper function for nand_wait used when
823 * we are in interrupt context. May happen when in panic and trying to write
824 * an oops trough mtdoops.
825 */
826static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
827 unsigned long timeo)
828{
829 int i;
830 for (i = 0; i < timeo; i++) {
831 if (chip->dev_ready) {
832 if (chip->dev_ready(mtd))
833 break;
834 } else {
835 if (chip->read_byte(mtd) & NAND_STATUS_READY)
836 break;
837 }
838 mdelay(1);
f8ac0414 839 }
2af7c653
SK		 840}
841
1da177e4
LT		 842/**
843 * nand_wait - [DEFAULT] wait until the command is done
844 * @mtd: MTD device structure
844d3b42 845 * @chip: NAND chip structure
1da177e4
LT		 846 *
847 * Wait for command done. This applies to erase and program only
61b03bd7 848 * Erase can take up to 400ms and program up to 20ms according to
1da177e4 849 * general NAND and SmartMedia specs
844d3b42 850 */
7bc3312b 851static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 852{
853
e0c7d767 854 unsigned long timeo = jiffies;
7bc3312b 855 int status, state = chip->state;
61b03bd7 856
1da177e4 857 if (state == FL_ERASING)
e0c7d767 858 timeo += (HZ * 400) / 1000;
1da177e4 859 else
e0c7d767 860 timeo += (HZ * 20) / 1000;
1da177e4 861
8fe833c1
RP		 862 led_trigger_event(nand_led_trigger, LED_FULL);
863
1da177e4
LT		 864 /* Apply this short delay always to ensure that we do wait tWB in
865 * any case on any machine. */
e0c7d767 866 ndelay(100);
1da177e4 867
ace4dfee
TG		 868 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
869 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 870 else
ace4dfee 871 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 872
2af7c653
SK		 873 if (in_interrupt() || oops_in_progress)
874 panic_nand_wait(mtd, chip, timeo);
875 else {
876 while (time_before(jiffies, timeo)) {
877 if (chip->dev_ready) {
878 if (chip->dev_ready(mtd))
879 break;
880 } else {
881 if (chip->read_byte(mtd) & NAND_STATUS_READY)
882 break;
883 }
884 cond_resched();
1da177e4 885 }
1da177e4 886 }
8fe833c1
RP		 887 led_trigger_event(nand_led_trigger, LED_OFF);
888
ace4dfee 889 status = (int)chip->read_byte(mtd);
1da177e4
LT		 890 return status;
891}
892
7d70f334 893/**
b6d676db 894 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
7d70f334 895 *
b6d676db
RD		 896 * @mtd: mtd info
897 * @ofs: offset to start unlock from
898 * @len: length to unlock
899 * @invert: when = 0, unlock the range of blocks within the lower and
7d70f334 900 * upper boundary address
b6d676db 901 * when = 1, unlock the range of blocks outside the boundaries
7d70f334
VS		 902 * of the lower and upper boundary address
903 *
b6d676db 904 * return - unlock status
7d70f334
VS		 905 */
906static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
907 uint64_t len, int invert)
908{
909 int ret = 0;
910 int status, page;
911 struct nand_chip *chip = mtd->priv;
912
913 /* Submit address of first page to unlock */
914 page = ofs >> chip->page_shift;
915 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
916
917 /* Submit address of last page to unlock */
918 page = (ofs + len) >> chip->page_shift;
919 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
920 (page | invert) & chip->pagemask);
921
922 /* Call wait ready function */
923 status = chip->waitfunc(mtd, chip);
924 udelay(1000);
925 /* See if device thinks it succeeded */
926 if (status & 0x01) {
927 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
928 __func__, status);
929 ret = -EIO;
930 }
931
932 return ret;
933}
934
935/**
b6d676db 936 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
7d70f334 937 *
b6d676db
RD		 938 * @mtd: mtd info
939 * @ofs: offset to start unlock from
940 * @len: length to unlock
7d70f334 941 *
b6d676db 942 * return - unlock status
7d70f334
VS		 943 */
944int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
945{
946 int ret = 0;
947 int chipnr;
948 struct nand_chip *chip = mtd->priv;
949
950 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
951 __func__, (unsigned long long)ofs, len);
952
953 if (check_offs_len(mtd, ofs, len))
954 ret = -EINVAL;
955
956 /* Align to last block address if size addresses end of the device */
957 if (ofs + len == mtd->size)
958 len -= mtd->erasesize;
959
960 nand_get_device(chip, mtd, FL_UNLOCKING);
961
962 /* Shift to get chip number */
963 chipnr = ofs >> chip->chip_shift;
964
965 chip->select_chip(mtd, chipnr);
966
967 /* Check, if it is write protected */
968 if (nand_check_wp(mtd)) {
969 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
970 __func__);
971 ret = -EIO;
972 goto out;
973 }
974
975 ret = __nand_unlock(mtd, ofs, len, 0);
976
977out:
978 /* de-select the NAND device */
979 chip->select_chip(mtd, -1);
980
981 nand_release_device(mtd);
982
983 return ret;
984}
985
986/**
b6d676db 987 * nand_lock - [REPLACEABLE] locks all blocks present in the device
7d70f334 988 *
b6d676db
RD		 989 * @mtd: mtd info
990 * @ofs: offset to start unlock from
991 * @len: length to unlock
7d70f334 992 *
b6d676db 993 * return - lock status
7d70f334 994 *
b6d676db
RD		 995 * This feature is not supported in many NAND parts. 'Micron' NAND parts
996 * do have this feature, but it allows only to lock all blocks, not for
7d70f334
VS		 997 * specified range for block.
998 *
999 * Implementing 'lock' feature by making use of 'unlock', for now.
1000 */
1001int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1002{
1003 int ret = 0;
1004 int chipnr, status, page;
1005 struct nand_chip *chip = mtd->priv;
1006
1007 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
1008 __func__, (unsigned long long)ofs, len);
1009
1010 if (check_offs_len(mtd, ofs, len))
1011 ret = -EINVAL;
1012
1013 nand_get_device(chip, mtd, FL_LOCKING);
1014
1015 /* Shift to get chip number */
1016 chipnr = ofs >> chip->chip_shift;
1017
1018 chip->select_chip(mtd, chipnr);
1019
1020 /* Check, if it is write protected */
1021 if (nand_check_wp(mtd)) {
1022 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
1023 __func__);
1024 status = MTD_ERASE_FAILED;
1025 ret = -EIO;
1026 goto out;
1027 }
1028
1029 /* Submit address of first page to lock */
1030 page = ofs >> chip->page_shift;
1031 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1032
1033 /* Call wait ready function */
1034 status = chip->waitfunc(mtd, chip);
1035 udelay(1000);
1036 /* See if device thinks it succeeded */
1037 if (status & 0x01) {
1038 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1039 __func__, status);
1040 ret = -EIO;
1041 goto out;
1042 }
1043
1044 ret = __nand_unlock(mtd, ofs, len, 0x1);
1045
1046out:
1047 /* de-select the NAND device */
1048 chip->select_chip(mtd, -1);
1049
1050 nand_release_device(mtd);
1051
1052 return ret;
1053}
1054
8593fbc6
TG		 1055/**
1056 * nand_read_page_raw - [Intern] read raw page data without ecc
1057 * @mtd: mtd info structure
1058 * @chip: nand chip info structure
1059 * @buf: buffer to store read data
58475fb9 1060 * @page: page number to read
52ff49df
DB		 1061 *
1062 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1063 */
1064static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1065 uint8_t *buf, int page)
8593fbc6
TG		 1066{
1067 chip->read_buf(mtd, buf, mtd->writesize);
1068 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1069 return 0;
1070}
1071
52ff49df
DB		 1072/**
1073 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1074 * @mtd: mtd info structure
1075 * @chip: nand chip info structure
1076 * @buf: buffer to store read data
58475fb9 1077 * @page: page number to read
52ff49df
DB		 1078 *
1079 * We need a special oob layout and handling even when OOB isn't used.
1080 */
1081static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1082 uint8_t *buf, int page)
52ff49df
DB		 1083{
1084 int eccsize = chip->ecc.size;
1085 int eccbytes = chip->ecc.bytes;
1086 uint8_t *oob = chip->oob_poi;
1087 int steps, size;
1088
1089 for (steps = chip->ecc.steps; steps > 0; steps--) {
1090 chip->read_buf(mtd, buf, eccsize);
1091 buf += eccsize;
1092
1093 if (chip->ecc.prepad) {
1094 chip->read_buf(mtd, oob, chip->ecc.prepad);
1095 oob += chip->ecc.prepad;
1096 }
1097
1098 chip->read_buf(mtd, oob, eccbytes);
1099 oob += eccbytes;
1100
1101 if (chip->ecc.postpad) {
1102 chip->read_buf(mtd, oob, chip->ecc.postpad);
1103 oob += chip->ecc.postpad;
1104 }
1105 }
1106
1107 size = mtd->oobsize - (oob - chip->oob_poi);
1108 if (size)
1109 chip->read_buf(mtd, oob, size);
1110
1111 return 0;
1112}
1113
1da177e4 1114/**
d29ebdbe 1115 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
f5bbdacc
TG		 1116 * @mtd: mtd info structure
1117 * @chip: nand chip info structure
1118 * @buf: buffer to store read data
58475fb9 1119 * @page: page number to read
068e3c0a 1120 */
f5bbdacc 1121static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1122 uint8_t *buf, int page)
1da177e4 1123{
f5bbdacc
TG		 1124 int i, eccsize = chip->ecc.size;
1125 int eccbytes = chip->ecc.bytes;
1126 int eccsteps = chip->ecc.steps;
1127 uint8_t *p = buf;
4bf63fcb
DW		 1128 uint8_t *ecc_calc = chip->buffers->ecccalc;
1129 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1130 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc 1131
46a8cf2d 1132 chip->ecc.read_page_raw(mtd, chip, buf, page);
f5bbdacc
TG		 1133
1134 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1135 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1136
1137 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1138 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1139
1140 eccsteps = chip->ecc.steps;
1141 p = buf;
1142
1143 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1144 int stat;
1145
1146 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1147 if (stat < 0)
f5bbdacc
TG		 1148 mtd->ecc_stats.failed++;
1149 else
1150 mtd->ecc_stats.corrected += stat;
1151 }
1152 return 0;
22c60f5f 1153}
1da177e4 1154
3d459559
AK		 1155/**
1156 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1157 * @mtd: mtd info structure
1158 * @chip: nand chip info structure
17c1d2be
AK		 1159 * @data_offs: offset of requested data within the page
1160 * @readlen: data length
1161 * @bufpoi: buffer to store read data
3d459559
AK		 1162 */
1163static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1164{
1165 int start_step, end_step, num_steps;
1166 uint32_t *eccpos = chip->ecc.layout->eccpos;
1167 uint8_t *p;
1168 int data_col_addr, i, gaps = 0;
1169 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1170 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1171
1172 /* Column address wihin the page aligned to ECC size (256bytes). */
1173 start_step = data_offs / chip->ecc.size;
1174 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1175 num_steps = end_step - start_step + 1;
1176
1177 /* Data size aligned to ECC ecc.size*/
1178 datafrag_len = num_steps * chip->ecc.size;
1179 eccfrag_len = num_steps * chip->ecc.bytes;
1180
1181 data_col_addr = start_step * chip->ecc.size;
1182 /* If we read not a page aligned data */
1183 if (data_col_addr != 0)
1184 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1185
1186 p = bufpoi + data_col_addr;
1187 chip->read_buf(mtd, p, datafrag_len);
1188
1189 /* Calculate ECC */
1190 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1191 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1192
1193 /* The performance is faster if to position offsets
1194 according to ecc.pos. Let make sure here that
1195 there are no gaps in ecc positions */
1196 for (i = 0; i < eccfrag_len - 1; i++) {
1197 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1198 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1199 gaps = 1;
1200 break;
1201 }
1202 }
1203 if (gaps) {
1204 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1205 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1206 } else {
1207 /* send the command to read the particular ecc bytes */
1208 /* take care about buswidth alignment in read_buf */
1209 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
1210 aligned_len = eccfrag_len;
1211 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
1212 aligned_len++;
1213 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1214 aligned_len++;
1215
1216 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1217 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1218 }
1219
1220 for (i = 0; i < eccfrag_len; i++)
1221 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1222
1223 p = bufpoi + data_col_addr;
1224 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1225 int stat;
1226
1227 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
12c8eb98 1228 if (stat < 0)
3d459559
AK		 1229 mtd->ecc_stats.failed++;
1230 else
1231 mtd->ecc_stats.corrected += stat;
1232 }
1233 return 0;
1234}
1235
068e3c0a 1236/**
d29ebdbe 1237 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
f5bbdacc
TG		 1238 * @mtd: mtd info structure
1239 * @chip: nand chip info structure
1240 * @buf: buffer to store read data
58475fb9 1241 * @page: page number to read
068e3c0a 1242 *
f5bbdacc 1243 * Not for syndrome calculating ecc controllers which need a special oob layout
068e3c0a 1244 */
f5bbdacc 1245static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1246 uint8_t *buf, int page)
1da177e4 1247{
f5bbdacc
TG		 1248 int i, eccsize = chip->ecc.size;
1249 int eccbytes = chip->ecc.bytes;
1250 int eccsteps = chip->ecc.steps;
1251 uint8_t *p = buf;
4bf63fcb
DW		 1252 uint8_t *ecc_calc = chip->buffers->ecccalc;
1253 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1254 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc
TG		 1255
1256 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1257 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1258 chip->read_buf(mtd, p, eccsize);
1259 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1260 }
f75e5097 1261 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1262
f5bbdacc 1263 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1264 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1265
f5bbdacc
TG		 1266 eccsteps = chip->ecc.steps;
1267 p = buf;
61b03bd7 1268
f5bbdacc
TG		 1269 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1270 int stat;
1da177e4 1271
f5bbdacc 1272 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1273 if (stat < 0)
f5bbdacc
TG		 1274 mtd->ecc_stats.failed++;
1275 else
1276 mtd->ecc_stats.corrected += stat;
1277 }
1278 return 0;
1279}
1da177e4 1280
6e0cb135
SN		 1281/**
1282 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1283 * @mtd: mtd info structure
1284 * @chip: nand chip info structure
1285 * @buf: buffer to store read data
58475fb9 1286 * @page: page number to read
6e0cb135
SN		 1287 *
1288 * Hardware ECC for large page chips, require OOB to be read first.
1289 * For this ECC mode, the write_page method is re-used from ECC_HW.
1290 * These methods read/write ECC from the OOB area, unlike the
1291 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1292 * "infix ECC" scheme and reads/writes ECC from the data area, by
1293 * overwriting the NAND manufacturer bad block markings.
1294 */
1295static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1296 struct nand_chip *chip, uint8_t *buf, int page)
1297{
1298 int i, eccsize = chip->ecc.size;
1299 int eccbytes = chip->ecc.bytes;
1300 int eccsteps = chip->ecc.steps;
1301 uint8_t *p = buf;
1302 uint8_t *ecc_code = chip->buffers->ecccode;
1303 uint32_t *eccpos = chip->ecc.layout->eccpos;
1304 uint8_t *ecc_calc = chip->buffers->ecccalc;
1305
1306 /* Read the OOB area first */
1307 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1308 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1309 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1310
1311 for (i = 0; i < chip->ecc.total; i++)
1312 ecc_code[i] = chip->oob_poi[eccpos[i]];
1313
1314 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1315 int stat;
1316
1317 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1318 chip->read_buf(mtd, p, eccsize);
1319 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1320
1321 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1322 if (stat < 0)
1323 mtd->ecc_stats.failed++;
1324 else
1325 mtd->ecc_stats.corrected += stat;
1326 }
1327 return 0;
1328}
1329
f5bbdacc 1330/**
d29ebdbe 1331 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
f5bbdacc
TG		 1332 * @mtd: mtd info structure
1333 * @chip: nand chip info structure
1334 * @buf: buffer to store read data
58475fb9 1335 * @page: page number to read
f5bbdacc
TG		 1336 *
1337 * The hw generator calculates the error syndrome automatically. Therefor
f75e5097 1338 * we need a special oob layout and handling.
f5bbdacc
TG		 1339 */
1340static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1341 uint8_t *buf, int page)
f5bbdacc
TG		 1342{
1343 int i, eccsize = chip->ecc.size;
1344 int eccbytes = chip->ecc.bytes;
1345 int eccsteps = chip->ecc.steps;
1346 uint8_t *p = buf;
f75e5097 1347 uint8_t *oob = chip->oob_poi;
1da177e4 1348
f5bbdacc
TG		 1349 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1350 int stat;
61b03bd7 1351
f5bbdacc
TG		 1352 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1353 chip->read_buf(mtd, p, eccsize);
1da177e4 1354
f5bbdacc
TG		 1355 if (chip->ecc.prepad) {
1356 chip->read_buf(mtd, oob, chip->ecc.prepad);
1357 oob += chip->ecc.prepad;
1358 }
1da177e4 1359
f5bbdacc
TG		 1360 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1361 chip->read_buf(mtd, oob, eccbytes);
1362 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1363
c32b8dcc 1364 if (stat < 0)
f5bbdacc 1365 mtd->ecc_stats.failed++;
61b03bd7 1366 else
f5bbdacc 1367 mtd->ecc_stats.corrected += stat;
61b03bd7 1368
f5bbdacc 1369 oob += eccbytes;
1da177e4 1370
f5bbdacc
TG		 1371 if (chip->ecc.postpad) {
1372 chip->read_buf(mtd, oob, chip->ecc.postpad);
1373 oob += chip->ecc.postpad;
61b03bd7 1374 }
f5bbdacc 1375 }
1da177e4 1376
f5bbdacc 1377 /* Calculate remaining oob bytes */
7e4178f9 1378 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1379 if (i)
1380 chip->read_buf(mtd, oob, i);
61b03bd7 1381
f5bbdacc
TG		 1382 return 0;
1383}
1da177e4 1384
f5bbdacc 1385/**
8593fbc6
TG		 1386 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1387 * @chip: nand chip structure
844d3b42 1388 * @oob: oob destination address
8593fbc6 1389 * @ops: oob ops structure
7014568b 1390 * @len: size of oob to transfer
8593fbc6
TG		 1391 */
1392static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1393 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1394{
f8ac0414 1395 switch (ops->mode) {
8593fbc6
TG		 1396
1397 case MTD_OOB_PLACE:
1398 case MTD_OOB_RAW:
1399 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1400 return oob + len;
1401
1402 case MTD_OOB_AUTO: {
1403 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1404 uint32_t boffs = 0, roffs = ops->ooboffs;
1405 size_t bytes = 0;
8593fbc6 1406
f8ac0414 1407 for (; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 1408 /* Read request not from offset 0 ? */
1409 if (unlikely(roffs)) {
1410 if (roffs >= free->length) {
1411 roffs -= free->length;
1412 continue;
1413 }
1414 boffs = free->offset + roffs;
1415 bytes = min_t(size_t, len,
1416 (free->length - roffs));
1417 roffs = 0;
1418 } else {
1419 bytes = min_t(size_t, len, free->length);
1420 boffs = free->offset;
1421 }
1422 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1423 oob += bytes;
1424 }
1425 return oob;
1426 }
1427 default:
1428 BUG();
1429 }
1430 return NULL;
1431}
1432
1433/**
1434 * nand_do_read_ops - [Internal] Read data with ECC
f5bbdacc
TG		 1435 *
1436 * @mtd: MTD device structure
1437 * @from: offset to read from
844d3b42 1438 * @ops: oob ops structure
f5bbdacc
TG		 1439 *
1440 * Internal function. Called with chip held.
1441 */
8593fbc6
TG		 1442static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1443 struct mtd_oob_ops *ops)
f5bbdacc
TG		 1444{
1445 int chipnr, page, realpage, col, bytes, aligned;
1446 struct nand_chip *chip = mtd->priv;
1447 struct mtd_ecc_stats stats;
1448 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1449 int sndcmd = 1;
1450 int ret = 0;
8593fbc6 1451 uint32_t readlen = ops->len;
7014568b 1452 uint32_t oobreadlen = ops->ooblen;
9aca334e
ML		 1453 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1454 mtd->oobavail : mtd->oobsize;
1455
8593fbc6 1456 uint8_t *bufpoi, *oob, *buf;
1da177e4 1457
f5bbdacc 1458 stats = mtd->ecc_stats;
1da177e4 1459
f5bbdacc
TG		 1460 chipnr = (int)(from >> chip->chip_shift);
1461 chip->select_chip(mtd, chipnr);
61b03bd7 1462
f5bbdacc
TG		 1463 realpage = (int)(from >> chip->page_shift);
1464 page = realpage & chip->pagemask;
1da177e4 1465
f5bbdacc 1466 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1467
8593fbc6
TG		 1468 buf = ops->datbuf;
1469 oob = ops->oobbuf;
1470
f8ac0414 1471 while (1) {
f5bbdacc
TG		 1472 bytes = min(mtd->writesize - col, readlen);
1473 aligned = (bytes == mtd->writesize);
61b03bd7 1474
f5bbdacc 1475 /* Is the current page in the buffer ? */
8593fbc6 1476 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1477 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1478
f5bbdacc
TG		 1479 if (likely(sndcmd)) {
1480 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1481 sndcmd = 0;
1da177e4 1482 }
1da177e4 1483
f5bbdacc 1484 /* Now read the page into the buffer */
956e944c 1485 if (unlikely(ops->mode == MTD_OOB_RAW))
46a8cf2d
SN		 1486 ret = chip->ecc.read_page_raw(mtd, chip,
1487 bufpoi, page);
3d459559
AK		 1488 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1489 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
956e944c 1490 else
46a8cf2d
SN		 1491 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1492 page);
f5bbdacc 1493 if (ret < 0)
1da177e4 1494 break;
f5bbdacc
TG		 1495
1496 /* Transfer not aligned data */
1497 if (!aligned) {
3d459559
AK		 1498 if (!NAND_SUBPAGE_READ(chip) && !oob)
1499 chip->pagebuf = realpage;
4bf63fcb 1500 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1501 }
1502
8593fbc6
TG		 1503 buf += bytes;
1504
1505 if (unlikely(oob)) {
9aca334e 1506
b64d39d8
ML		 1507 int toread = min(oobreadlen, max_oobsize);
1508
1509 if (toread) {
1510 oob = nand_transfer_oob(chip,
1511 oob, ops, toread);
1512 oobreadlen -= toread;
1513 }
8593fbc6
TG		 1514 }
1515
f5bbdacc
TG		 1516 if (!(chip->options & NAND_NO_READRDY)) {
1517 /*
1518 * Apply delay or wait for ready/busy pin. Do
1519 * this before the AUTOINCR check, so no
1520 * problems arise if a chip which does auto
1521 * increment is marked as NOAUTOINCR by the
1522 * board driver.
1523 */
1524 if (!chip->dev_ready)
1525 udelay(chip->chip_delay);
1526 else
1527 nand_wait_ready(mtd);
1da177e4 1528 }
8593fbc6 1529 } else {
4bf63fcb 1530 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6
TG		 1531 buf += bytes;
1532 }
1da177e4 1533
f5bbdacc 1534 readlen -= bytes;
61b03bd7 1535
f5bbdacc 1536 if (!readlen)
61b03bd7 1537 break;
1da177e4
LT		 1538
1539 /* For subsequent reads align to page boundary. */
1540 col = 0;
1541 /* Increment page address */
1542 realpage++;
1543
ace4dfee 1544 page = realpage & chip->pagemask;
1da177e4
LT		 1545 /* Check, if we cross a chip boundary */
1546 if (!page) {
1547 chipnr++;
ace4dfee
TG		 1548 chip->select_chip(mtd, -1);
1549 chip->select_chip(mtd, chipnr);
1da177e4 1550 }
f5bbdacc 1551
61b03bd7
TG		 1552 /* Check, if the chip supports auto page increment
1553 * or if we have hit a block boundary.
e0c7d767 1554 */
f5bbdacc 1555 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
61b03bd7 1556 sndcmd = 1;
1da177e4
LT		 1557 }
1558
8593fbc6 1559 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1560 if (oob)
1561 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1562
f5bbdacc
TG		 1563 if (ret)
1564 return ret;
1565
9a1fcdfd
TG		 1566 if (mtd->ecc_stats.failed - stats.failed)
1567 return -EBADMSG;
1568
1569 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
f5bbdacc
TG		 1570}
1571
1572/**
1573 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1574 * @mtd: MTD device structure
1575 * @from: offset to read from
1576 * @len: number of bytes to read
1577 * @retlen: pointer to variable to store the number of read bytes
1578 * @buf: the databuffer to put data
1579 *
1580 * Get hold of the chip and call nand_do_read
1581 */
1582static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1583 size_t *retlen, uint8_t *buf)
1584{
8593fbc6 1585 struct nand_chip *chip = mtd->priv;
f5bbdacc
TG		 1586 int ret;
1587
f5bbdacc
TG		 1588 /* Do not allow reads past end of device */
1589 if ((from + len) > mtd->size)
1590 return -EINVAL;
1591 if (!len)
1592 return 0;
1593
8593fbc6 1594 nand_get_device(chip, mtd, FL_READING);
f5bbdacc 1595
8593fbc6
TG		 1596 chip->ops.len = len;
1597 chip->ops.datbuf = buf;
1598 chip->ops.oobbuf = NULL;
1599
1600 ret = nand_do_read_ops(mtd, from, &chip->ops);
f5bbdacc 1601
7fd5aecc
RP		 1602 *retlen = chip->ops.retlen;
1603
f5bbdacc
TG		 1604 nand_release_device(mtd);
1605
1606 return ret;
1da177e4
LT		 1607}
1608
7bc3312b
TG		 1609/**
1610 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1611 * @mtd: mtd info structure
1612 * @chip: nand chip info structure
1613 * @page: page number to read
1614 * @sndcmd: flag whether to issue read command or not
1615 */
1616static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1617 int page, int sndcmd)
1618{
1619 if (sndcmd) {
1620 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1621 sndcmd = 0;
1622 }
1623 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1624 return sndcmd;
1625}
1626
1627/**
1628 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1629 * with syndromes
1630 * @mtd: mtd info structure
1631 * @chip: nand chip info structure
1632 * @page: page number to read
1633 * @sndcmd: flag whether to issue read command or not
1634 */
1635static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1636 int page, int sndcmd)
1637{
1638 uint8_t *buf = chip->oob_poi;
1639 int length = mtd->oobsize;
1640 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1641 int eccsize = chip->ecc.size;
1642 uint8_t *bufpoi = buf;
1643 int i, toread, sndrnd = 0, pos;
1644
1645 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1646 for (i = 0; i < chip->ecc.steps; i++) {
1647 if (sndrnd) {
1648 pos = eccsize + i * (eccsize + chunk);
1649 if (mtd->writesize > 512)
1650 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1651 else
1652 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1653 } else
1654 sndrnd = 1;
1655 toread = min_t(int, length, chunk);
1656 chip->read_buf(mtd, bufpoi, toread);
1657 bufpoi += toread;
1658 length -= toread;
1659 }
1660 if (length > 0)
1661 chip->read_buf(mtd, bufpoi, length);
1662
1663 return 1;
1664}
1665
1666/**
1667 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1668 * @mtd: mtd info structure
1669 * @chip: nand chip info structure
1670 * @page: page number to write
1671 */
1672static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1673 int page)
1674{
1675 int status = 0;
1676 const uint8_t *buf = chip->oob_poi;
1677 int length = mtd->oobsize;
1678
1679 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1680 chip->write_buf(mtd, buf, length);
1681 /* Send command to program the OOB data */
1682 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1683
1684 status = chip->waitfunc(mtd, chip);
1685
0d420f9d 1686 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1687}
1688
1689/**
1690 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1691 * with syndrome - only for large page flash !
1692 * @mtd: mtd info structure
1693 * @chip: nand chip info structure
1694 * @page: page number to write
1695 */
1696static int nand_write_oob_syndrome(struct mtd_info *mtd,
1697 struct nand_chip *chip, int page)
1698{
1699 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1700 int eccsize = chip->ecc.size, length = mtd->oobsize;
1701 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1702 const uint8_t *bufpoi = chip->oob_poi;
1703
1704 /*
1705 * data-ecc-data-ecc ... ecc-oob
1706 * or
1707 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1708 */
1709 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1710 pos = steps * (eccsize + chunk);
1711 steps = 0;
1712 } else
8b0036ee 1713 pos = eccsize;
7bc3312b
TG		 1714
1715 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1716 for (i = 0; i < steps; i++) {
1717 if (sndcmd) {
1718 if (mtd->writesize <= 512) {
1719 uint32_t fill = 0xFFFFFFFF;
1720
1721 len = eccsize;
1722 while (len > 0) {
1723 int num = min_t(int, len, 4);
1724 chip->write_buf(mtd, (uint8_t *)&fill,
1725 num);
1726 len -= num;
1727 }
1728 } else {
1729 pos = eccsize + i * (eccsize + chunk);
1730 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1731 }
1732 } else
1733 sndcmd = 1;
1734 len = min_t(int, length, chunk);
1735 chip->write_buf(mtd, bufpoi, len);
1736 bufpoi += len;
1737 length -= len;
1738 }
1739 if (length > 0)
1740 chip->write_buf(mtd, bufpoi, length);
1741
1742 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1743 status = chip->waitfunc(mtd, chip);
1744
1745 return status & NAND_STATUS_FAIL ? -EIO : 0;
1746}
1747
1da177e4 1748/**
8593fbc6 1749 * nand_do_read_oob - [Intern] NAND read out-of-band
1da177e4
LT		 1750 * @mtd: MTD device structure
1751 * @from: offset to read from
8593fbc6 1752 * @ops: oob operations description structure
1da177e4
LT		 1753 *
1754 * NAND read out-of-band data from the spare area
1755 */
8593fbc6
TG		 1756static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1757 struct mtd_oob_ops *ops)
1da177e4 1758{
7bc3312b 1759 int page, realpage, chipnr, sndcmd = 1;
ace4dfee 1760 struct nand_chip *chip = mtd->priv;
7314e9e7 1761 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
7014568b
VW		 1762 int readlen = ops->ooblen;
1763 int len;
7bc3312b 1764 uint8_t *buf = ops->oobbuf;
61b03bd7 1765
20d8e248 1766 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1767 __func__, (unsigned long long)from, readlen);
1da177e4 1768
03736155 1769 if (ops->mode == MTD_OOB_AUTO)
7014568b 1770 len = chip->ecc.layout->oobavail;
03736155
AH		 1771 else
1772 len = mtd->oobsize;
1773
1774 if (unlikely(ops->ooboffs >= len)) {
20d8e248 1775 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1776 "outside oob\n", __func__);
03736155
AH		 1777 return -EINVAL;
1778 }
1779
1780 /* Do not allow reads past end of device */
1781 if (unlikely(from >= mtd->size ||
1782 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1783 (from >> chip->page_shift)) * len)) {
20d8e248 1784 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1785 "of device\n", __func__);
03736155
AH		 1786 return -EINVAL;
1787 }
7014568b 1788
7314e9e7 1789 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1790 chip->select_chip(mtd, chipnr);
1da177e4 1791
7314e9e7
TG		 1792 /* Shift to get page */
1793 realpage = (int)(from >> chip->page_shift);
1794 page = realpage & chip->pagemask;
1da177e4 1795
f8ac0414 1796 while (1) {
7bc3312b 1797 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
7014568b
VW		 1798
1799 len = min(len, readlen);
1800 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1801
7314e9e7
TG		 1802 if (!(chip->options & NAND_NO_READRDY)) {
1803 /*
1804 * Apply delay or wait for ready/busy pin. Do this
1805 * before the AUTOINCR check, so no problems arise if a
1806 * chip which does auto increment is marked as
1807 * NOAUTOINCR by the board driver.
19870da7 1808 */
ace4dfee
TG		 1809 if (!chip->dev_ready)
1810 udelay(chip->chip_delay);
19870da7
TG		 1811 else
1812 nand_wait_ready(mtd);
7314e9e7 1813 }
19870da7 1814
7014568b 1815 readlen -= len;
0d420f9d
SZ		 1816 if (!readlen)
1817 break;
1818
7314e9e7
TG		 1819 /* Increment page address */
1820 realpage++;
1821
1822 page = realpage & chip->pagemask;
1823 /* Check, if we cross a chip boundary */
1824 if (!page) {
1825 chipnr++;
1826 chip->select_chip(mtd, -1);
1827 chip->select_chip(mtd, chipnr);
1da177e4 1828 }
7314e9e7
TG		 1829
1830 /* Check, if the chip supports auto page increment
1831 * or if we have hit a block boundary.
1832 */
1833 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1834 sndcmd = 1;
1da177e4
LT		 1835 }
1836
7014568b 1837 ops->oobretlen = ops->ooblen;
1da177e4
LT		 1838 return 0;
1839}
1840
1841/**
8593fbc6 1842 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1da177e4 1843 * @mtd: MTD device structure
1da177e4 1844 * @from: offset to read from
8593fbc6 1845 * @ops: oob operation description structure
1da177e4 1846 *
8593fbc6 1847 * NAND read data and/or out-of-band data
1da177e4 1848 */
8593fbc6
TG		 1849static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1850 struct mtd_oob_ops *ops)
1da177e4 1851{
ace4dfee 1852 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1853 int ret = -ENOTSUPP;
1854
1855 ops->retlen = 0;
1da177e4
LT		 1856
1857 /* Do not allow reads past end of device */
7014568b 1858 if (ops->datbuf && (from + ops->len) > mtd->size) {
20d8e248 1859 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1860 "beyond end of device\n", __func__);
1da177e4
LT		 1861 return -EINVAL;
1862 }
1863
ace4dfee 1864 nand_get_device(chip, mtd, FL_READING);
1da177e4 1865
f8ac0414 1866 switch (ops->mode) {
8593fbc6
TG		 1867 case MTD_OOB_PLACE:
1868 case MTD_OOB_AUTO:
8593fbc6 1869 case MTD_OOB_RAW:
8593fbc6 1870 break;
1da177e4 1871
8593fbc6
TG		 1872 default:
1873 goto out;
1874 }
1da177e4 1875
8593fbc6
TG		 1876 if (!ops->datbuf)
1877 ret = nand_do_read_oob(mtd, from, ops);
1878 else
1879 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1880
8593fbc6
TG		 1881 out:
1882 nand_release_device(mtd);
1883 return ret;
1884}
61b03bd7 1885
1da177e4 1886
8593fbc6
TG		 1887/**
1888 * nand_write_page_raw - [Intern] raw page write function
1889 * @mtd: mtd info structure
1890 * @chip: nand chip info structure
1891 * @buf: data buffer
52ff49df
DB		 1892 *
1893 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1894 */
1895static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1896 const uint8_t *buf)
1897{
1898 chip->write_buf(mtd, buf, mtd->writesize);
1899 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1900}
1901
52ff49df
DB		 1902/**
1903 * nand_write_page_raw_syndrome - [Intern] raw page write function
1904 * @mtd: mtd info structure
1905 * @chip: nand chip info structure
1906 * @buf: data buffer
1907 *
1908 * We need a special oob layout and handling even when ECC isn't checked.
1909 */
1910static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1911 const uint8_t *buf)
1912{
1913 int eccsize = chip->ecc.size;
1914 int eccbytes = chip->ecc.bytes;
1915 uint8_t *oob = chip->oob_poi;
1916 int steps, size;
1917
1918 for (steps = chip->ecc.steps; steps > 0; steps--) {
1919 chip->write_buf(mtd, buf, eccsize);
1920 buf += eccsize;
1921
1922 if (chip->ecc.prepad) {
1923 chip->write_buf(mtd, oob, chip->ecc.prepad);
1924 oob += chip->ecc.prepad;
1925 }
1926
1927 chip->read_buf(mtd, oob, eccbytes);
1928 oob += eccbytes;
1929
1930 if (chip->ecc.postpad) {
1931 chip->write_buf(mtd, oob, chip->ecc.postpad);
1932 oob += chip->ecc.postpad;
1933 }
1934 }
1935
1936 size = mtd->oobsize - (oob - chip->oob_poi);
1937 if (size)
1938 chip->write_buf(mtd, oob, size);
1939}
9223a456 1940/**
d29ebdbe 1941 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
f75e5097
TG		 1942 * @mtd: mtd info structure
1943 * @chip: nand chip info structure
1944 * @buf: data buffer
9223a456 1945 */
f75e5097
TG		 1946static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1947 const uint8_t *buf)
9223a456 1948{
f75e5097
TG		 1949 int i, eccsize = chip->ecc.size;
1950 int eccbytes = chip->ecc.bytes;
1951 int eccsteps = chip->ecc.steps;
4bf63fcb 1952 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1953 const uint8_t *p = buf;
8b099a39 1954 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1955
8593fbc6
TG		 1956 /* Software ecc calculation */
1957 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1958 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1959
8593fbc6
TG		 1960 for (i = 0; i < chip->ecc.total; i++)
1961 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1962
90424de8 1963 chip->ecc.write_page_raw(mtd, chip, buf);
f75e5097 1964}
9223a456 1965
f75e5097 1966/**
d29ebdbe 1967 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
f75e5097
TG		 1968 * @mtd: mtd info structure
1969 * @chip: nand chip info structure
1970 * @buf: data buffer
1971 */
1972static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1973 const uint8_t *buf)
1974{
1975 int i, eccsize = chip->ecc.size;
1976 int eccbytes = chip->ecc.bytes;
1977 int eccsteps = chip->ecc.steps;
4bf63fcb 1978 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1979 const uint8_t *p = buf;
8b099a39 1980 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1981
f75e5097
TG		 1982 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1983 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1984 chip->write_buf(mtd, p, eccsize);
f75e5097 1985 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1986 }
1987
f75e5097
TG		 1988 for (i = 0; i < chip->ecc.total; i++)
1989 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1990
1991 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 1992}
1993
61b03bd7 1994/**
d29ebdbe 1995 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
f75e5097
TG		 1996 * @mtd: mtd info structure
1997 * @chip: nand chip info structure
1998 * @buf: data buffer
1da177e4 1999 *
f75e5097
TG		 2000 * The hw generator calculates the error syndrome automatically. Therefor
2001 * we need a special oob layout and handling.
2002 */
2003static void nand_write_page_syndrome(struct mtd_info *mtd,
2004 struct nand_chip *chip, const uint8_t *buf)
1da177e4 2005{
f75e5097
TG		 2006 int i, eccsize = chip->ecc.size;
2007 int eccbytes = chip->ecc.bytes;
2008 int eccsteps = chip->ecc.steps;
2009 const uint8_t *p = buf;
2010 uint8_t *oob = chip->oob_poi;
1da177e4 2011
f75e5097 2012 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2013
f75e5097
TG		 2014 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2015 chip->write_buf(mtd, p, eccsize);
61b03bd7 2016
f75e5097
TG		 2017 if (chip->ecc.prepad) {
2018 chip->write_buf(mtd, oob, chip->ecc.prepad);
2019 oob += chip->ecc.prepad;
2020 }
2021
2022 chip->ecc.calculate(mtd, p, oob);
2023 chip->write_buf(mtd, oob, eccbytes);
2024 oob += eccbytes;
2025
2026 if (chip->ecc.postpad) {
2027 chip->write_buf(mtd, oob, chip->ecc.postpad);
2028 oob += chip->ecc.postpad;
1da177e4 2029 }
1da177e4 2030 }
f75e5097
TG		 2031
2032 /* Calculate remaining oob bytes */
7e4178f9 2033 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2034 if (i)
2035 chip->write_buf(mtd, oob, i);
2036}
2037
2038/**
956e944c 2039 * nand_write_page - [REPLACEABLE] write one page
f75e5097
TG		 2040 * @mtd: MTD device structure
2041 * @chip: NAND chip descriptor
2042 * @buf: the data to write
2043 * @page: page number to write
2044 * @cached: cached programming
efbfe96c 2045 * @raw: use _raw version of write_page
f75e5097
TG		 2046 */
2047static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
956e944c 2048 const uint8_t *buf, int page, int cached, int raw)
f75e5097
TG		 2049{
2050 int status;
2051
2052 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2053
956e944c
DW		 2054 if (unlikely(raw))
2055 chip->ecc.write_page_raw(mtd, chip, buf);
2056 else
2057 chip->ecc.write_page(mtd, chip, buf);
f75e5097
TG		 2058
2059 /*
2060 * Cached progamming disabled for now, Not sure if its worth the
2061 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2062 */
2063 cached = 0;
2064
2065 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2066
2067 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2068 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2069 /*
2070 * See if operation failed and additional status checks are
2071 * available
2072 */
2073 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2074 status = chip->errstat(mtd, chip, FL_WRITING, status,
2075 page);
2076
2077 if (status & NAND_STATUS_FAIL)
2078 return -EIO;
2079 } else {
2080 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2081 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2082 }
2083
2084#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2085 /* Send command to read back the data */
2086 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2087
2088 if (chip->verify_buf(mtd, buf, mtd->writesize))
2089 return -EIO;
2090#endif
2091 return 0;
1da177e4
LT		 2092}
2093
8593fbc6
TG		 2094/**
2095 * nand_fill_oob - [Internal] Transfer client buffer to oob
2096 * @chip: nand chip structure
2097 * @oob: oob data buffer
b6d676db 2098 * @len: oob data write length
8593fbc6
TG		 2099 * @ops: oob ops structure
2100 */
782ce79a
ML		 2101static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
2102 struct mtd_oob_ops *ops)
8593fbc6 2103{
f8ac0414 2104 switch (ops->mode) {
8593fbc6
TG		 2105
2106 case MTD_OOB_PLACE:
2107 case MTD_OOB_RAW:
2108 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2109 return oob + len;
2110
2111 case MTD_OOB_AUTO: {
2112 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2113 uint32_t boffs = 0, woffs = ops->ooboffs;
2114 size_t bytes = 0;
8593fbc6 2115
f8ac0414 2116 for (; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 2117 /* Write request not from offset 0 ? */
2118 if (unlikely(woffs)) {
2119 if (woffs >= free->length) {
2120 woffs -= free->length;
2121 continue;
2122 }
2123 boffs = free->offset + woffs;
2124 bytes = min_t(size_t, len,
2125 (free->length - woffs));
2126 woffs = 0;
2127 } else {
2128 bytes = min_t(size_t, len, free->length);
2129 boffs = free->offset;
2130 }
8b0036ee 2131 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2132 oob += bytes;
2133 }
2134 return oob;
2135 }
2136 default:
2137 BUG();
2138 }
2139 return NULL;
2140}
2141
f8ac0414 2142#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2143
2144/**
8593fbc6 2145 * nand_do_write_ops - [Internal] NAND write with ECC
1da177e4
LT		 2146 * @mtd: MTD device structure
2147 * @to: offset to write to
8593fbc6 2148 * @ops: oob operations description structure
1da177e4
LT		 2149 *
2150 * NAND write with ECC
2151 */
8593fbc6
TG		 2152static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2153 struct mtd_oob_ops *ops)
1da177e4 2154{
29072b96 2155 int chipnr, realpage, page, blockmask, column;
ace4dfee 2156 struct nand_chip *chip = mtd->priv;
8593fbc6 2157 uint32_t writelen = ops->len;
782ce79a
ML		 2158
2159 uint32_t oobwritelen = ops->ooblen;
2160 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2161 mtd->oobavail : mtd->oobsize;
2162
8593fbc6
TG		 2163 uint8_t *oob = ops->oobbuf;
2164 uint8_t *buf = ops->datbuf;
29072b96 2165 int ret, subpage;
1da177e4 2166
8593fbc6 2167 ops->retlen = 0;
29072b96
TG		 2168 if (!writelen)
2169 return 0;
1da177e4 2170
61b03bd7 2171 /* reject writes, which are not page aligned */
8593fbc6 2172 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
20d8e248 2173 printk(KERN_NOTICE "%s: Attempt to write not "
2174 "page aligned data\n", __func__);
1da177e4
LT		 2175 return -EINVAL;
2176 }
2177
29072b96
TG		 2178 column = to & (mtd->writesize - 1);
2179 subpage = column || (writelen & (mtd->writesize - 1));
2180
2181 if (subpage && oob)
2182 return -EINVAL;
1da177e4 2183
6a930961
TG		 2184 chipnr = (int)(to >> chip->chip_shift);
2185 chip->select_chip(mtd, chipnr);
2186
1da177e4
LT		 2187 /* Check, if it is write protected */
2188 if (nand_check_wp(mtd))
8593fbc6 2189 return -EIO;
1da177e4 2190
f75e5097
TG		 2191 realpage = (int)(to >> chip->page_shift);
2192 page = realpage & chip->pagemask;
2193 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2194
2195 /* Invalidate the page cache, when we write to the cached page */
2196 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2197 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2198 chip->pagebuf = -1;
61b03bd7 2199
7dcdcbef
DW		 2200 /* If we're not given explicit OOB data, let it be 0xFF */
2201 if (likely(!oob))
2202 memset(chip->oob_poi, 0xff, mtd->oobsize);
61b03bd7 2203
782ce79a
ML		 2204 /* Don't allow multipage oob writes with offset */
2205 if (ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2206 return -EINVAL;
2207
f8ac0414 2208 while (1) {
29072b96 2209 int bytes = mtd->writesize;
f75e5097 2210 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2211 uint8_t *wbuf = buf;
2212
2213 /* Partial page write ? */
2214 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2215 cached = 0;
2216 bytes = min_t(int, bytes - column, (int) writelen);
2217 chip->pagebuf = -1;
2218 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2219 memcpy(&chip->buffers->databuf[column], buf, bytes);
2220 wbuf = chip->buffers->databuf;
2221 }
1da177e4 2222
782ce79a
ML		 2223 if (unlikely(oob)) {
2224 size_t len = min(oobwritelen, oobmaxlen);
2225 oob = nand_fill_oob(chip, oob, len, ops);
2226 oobwritelen -= len;
2227 }
8593fbc6 2228
29072b96 2229 ret = chip->write_page(mtd, chip, wbuf, page, cached,
956e944c 2230 (ops->mode == MTD_OOB_RAW));
f75e5097
TG		 2231 if (ret)
2232 break;
2233
2234 writelen -= bytes;
2235 if (!writelen)
2236 break;
2237
29072b96 2238 column = 0;
f75e5097
TG		 2239 buf += bytes;
2240 realpage++;
2241
2242 page = realpage & chip->pagemask;
2243 /* Check, if we cross a chip boundary */
2244 if (!page) {
2245 chipnr++;
2246 chip->select_chip(mtd, -1);
2247 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2248 }
2249 }
8593fbc6 2250
8593fbc6 2251 ops->retlen = ops->len - writelen;
7014568b
VW		 2252 if (unlikely(oob))
2253 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2254 return ret;
2255}
2256
2af7c653
SK		 2257/**
2258 * panic_nand_write - [MTD Interface] NAND write with ECC
2259 * @mtd: MTD device structure
2260 * @to: offset to write to
2261 * @len: number of bytes to write
2262 * @retlen: pointer to variable to store the number of written bytes
2263 * @buf: the data to write
2264 *
2265 * NAND write with ECC. Used when performing writes in interrupt context, this
2266 * may for example be called by mtdoops when writing an oops while in panic.
2267 */
2268static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2269 size_t *retlen, const uint8_t *buf)
2270{
2271 struct nand_chip *chip = mtd->priv;
2272 int ret;
2273
2274 /* Do not allow reads past end of device */
2275 if ((to + len) > mtd->size)
2276 return -EINVAL;
2277 if (!len)
2278 return 0;
2279
2280 /* Wait for the device to get ready. */
2281 panic_nand_wait(mtd, chip, 400);
2282
2283 /* Grab the device. */
2284 panic_nand_get_device(chip, mtd, FL_WRITING);
2285
2286 chip->ops.len = len;
2287 chip->ops.datbuf = (uint8_t *)buf;
2288 chip->ops.oobbuf = NULL;
2289
2290 ret = nand_do_write_ops(mtd, to, &chip->ops);
2291
2292 *retlen = chip->ops.retlen;
2293 return ret;
2294}
2295
f75e5097 2296/**
8593fbc6 2297 * nand_write - [MTD Interface] NAND write with ECC
f75e5097 2298 * @mtd: MTD device structure
f75e5097
TG		 2299 * @to: offset to write to
2300 * @len: number of bytes to write
8593fbc6
TG		 2301 * @retlen: pointer to variable to store the number of written bytes
2302 * @buf: the data to write
f75e5097 2303 *
8593fbc6 2304 * NAND write with ECC
f75e5097 2305 */
8593fbc6
TG		 2306static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2307 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2308{
2309 struct nand_chip *chip = mtd->priv;
f75e5097
TG		 2310 int ret;
2311
8593fbc6
TG		 2312 /* Do not allow reads past end of device */
2313 if ((to + len) > mtd->size)
f75e5097 2314 return -EINVAL;
8593fbc6
TG		 2315 if (!len)
2316 return 0;
f75e5097 2317
7bc3312b 2318 nand_get_device(chip, mtd, FL_WRITING);
f75e5097 2319
8593fbc6
TG		 2320 chip->ops.len = len;
2321 chip->ops.datbuf = (uint8_t *)buf;
2322 chip->ops.oobbuf = NULL;
f75e5097 2323
8593fbc6 2324 ret = nand_do_write_ops(mtd, to, &chip->ops);
f75e5097 2325
7fd5aecc
RP		 2326 *retlen = chip->ops.retlen;
2327
f75e5097 2328 nand_release_device(mtd);
8593fbc6 2329
8593fbc6 2330 return ret;
f75e5097 2331}
7314e9e7 2332
1da177e4 2333/**
8593fbc6 2334 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1da177e4
LT		 2335 * @mtd: MTD device structure
2336 * @to: offset to write to
8593fbc6 2337 * @ops: oob operation description structure
1da177e4
LT		 2338 *
2339 * NAND write out-of-band
2340 */
8593fbc6
TG		 2341static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2342 struct mtd_oob_ops *ops)
1da177e4 2343{
03736155 2344 int chipnr, page, status, len;
ace4dfee 2345 struct nand_chip *chip = mtd->priv;
1da177e4 2346
20d8e248 2347 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2348 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2349
03736155
AH		 2350 if (ops->mode == MTD_OOB_AUTO)
2351 len = chip->ecc.layout->oobavail;
2352 else
2353 len = mtd->oobsize;
2354
1da177e4 2355 /* Do not allow write past end of page */
03736155 2356 if ((ops->ooboffs + ops->ooblen) > len) {
20d8e248 2357 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2358 "past end of page\n", __func__);
1da177e4
LT		 2359 return -EINVAL;
2360 }
2361
03736155 2362 if (unlikely(ops->ooboffs >= len)) {
20d8e248 2363 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2364 "write outside oob\n", __func__);
03736155
AH		 2365 return -EINVAL;
2366 }
2367
2368 /* Do not allow reads past end of device */
2369 if (unlikely(to >= mtd->size ||
2370 ops->ooboffs + ops->ooblen >
2371 ((mtd->size >> chip->page_shift) -
2372 (to >> chip->page_shift)) * len)) {
20d8e248 2373 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2374 "end of device\n", __func__);
03736155
AH		 2375 return -EINVAL;
2376 }
2377
7314e9e7 2378 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2379 chip->select_chip(mtd, chipnr);
1da177e4 2380
7314e9e7
TG		 2381 /* Shift to get page */
2382 page = (int)(to >> chip->page_shift);
2383
2384 /*
2385 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2386 * of my DiskOnChip 2000 test units) will clear the whole data page too
2387 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2388 * it in the doc2000 driver in August 1999. dwmw2.
2389 */
ace4dfee 2390 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2391
2392 /* Check, if it is write protected */
2393 if (nand_check_wp(mtd))
8593fbc6 2394 return -EROFS;
61b03bd7 2395
1da177e4 2396 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2397 if (page == chip->pagebuf)
2398 chip->pagebuf = -1;
1da177e4 2399
7bc3312b 2400 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2401 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
7bc3312b
TG		 2402 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2403 memset(chip->oob_poi, 0xff, mtd->oobsize);
1da177e4 2404
7bc3312b
TG		 2405 if (status)
2406 return status;
1da177e4 2407
7014568b 2408 ops->oobretlen = ops->ooblen;
1da177e4 2409
7bc3312b 2410 return 0;
8593fbc6
TG		 2411}
2412
2413/**
2414 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2415 * @mtd: MTD device structure
844d3b42 2416 * @to: offset to write to
8593fbc6
TG		 2417 * @ops: oob operation description structure
2418 */
2419static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2420 struct mtd_oob_ops *ops)
2421{
8593fbc6
TG		 2422 struct nand_chip *chip = mtd->priv;
2423 int ret = -ENOTSUPP;
2424
2425 ops->retlen = 0;
2426
2427 /* Do not allow writes past end of device */
7014568b 2428 if (ops->datbuf && (to + ops->len) > mtd->size) {
20d8e248 2429 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2430 "end of device\n", __func__);
8593fbc6
TG		 2431 return -EINVAL;
2432 }
2433
7bc3312b 2434 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6 2435
f8ac0414 2436 switch (ops->mode) {
8593fbc6
TG		 2437 case MTD_OOB_PLACE:
2438 case MTD_OOB_AUTO:
8593fbc6 2439 case MTD_OOB_RAW:
8593fbc6
TG		 2440 break;
2441
2442 default:
2443 goto out;
2444 }
2445
2446 if (!ops->datbuf)
2447 ret = nand_do_write_oob(mtd, to, ops);
2448 else
2449 ret = nand_do_write_ops(mtd, to, ops);
2450
e0c7d767 2451 out:
1da177e4 2452 nand_release_device(mtd);
1da177e4
LT		 2453 return ret;
2454}
2455
1da177e4
LT		 2456/**
2457 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2458 * @mtd: MTD device structure
2459 * @page: the page address of the block which will be erased
2460 *
2461 * Standard erase command for NAND chips
2462 */
e0c7d767 2463static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2464{
ace4dfee 2465 struct nand_chip *chip = mtd->priv;
1da177e4 2466 /* Send commands to erase a block */
ace4dfee
TG		 2467 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2468 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2469}
2470
2471/**
2472 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2473 * @mtd: MTD device structure
2474 * @page: the page address of the block which will be erased
2475 *
2476 * AND multi block erase command function
2477 * Erase 4 consecutive blocks
2478 */
e0c7d767 2479static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2480{
ace4dfee 2481 struct nand_chip *chip = mtd->priv;
1da177e4 2482 /* Send commands to erase a block */
ace4dfee
TG		 2483 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2484 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2485 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2486 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2487 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2488}
2489
2490/**
2491 * nand_erase - [MTD Interface] erase block(s)
2492 * @mtd: MTD device structure
2493 * @instr: erase instruction
2494 *
2495 * Erase one ore more blocks
2496 */
e0c7d767 2497static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2498{
e0c7d767 2499 return nand_erase_nand(mtd, instr, 0);
1da177e4 2500}
61b03bd7 2501
30f464b7 2502#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2503/**
ace4dfee 2504 * nand_erase_nand - [Internal] erase block(s)
1da177e4
LT		 2505 * @mtd: MTD device structure
2506 * @instr: erase instruction
2507 * @allowbbt: allow erasing the bbt area
2508 *
2509 * Erase one ore more blocks
2510 */
ace4dfee
TG		 2511int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2512 int allowbbt)
1da177e4 2513{
69423d99 2514 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2515 struct nand_chip *chip = mtd->priv;
f8ac0414 2516 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
ace4dfee 2517 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2518 loff_t len;
1da177e4 2519
20d8e248 2520 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2521 __func__, (unsigned long long)instr->addr,
2522 (unsigned long long)instr->len);
1da177e4 2523
6fe5a6ac 2524 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2525 return -EINVAL;
1da177e4 2526
bb0eb217 2527 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
1da177e4
LT		 2528
2529 /* Grab the lock and see if the device is available */
ace4dfee 2530 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2531
2532 /* Shift to get first page */
ace4dfee
TG		 2533 page = (int)(instr->addr >> chip->page_shift);
2534 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2535
2536 /* Calculate pages in each block */
ace4dfee 2537 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2538
2539 /* Select the NAND device */
ace4dfee 2540 chip->select_chip(mtd, chipnr);
1da177e4 2541
1da177e4
LT		 2542 /* Check, if it is write protected */
2543 if (nand_check_wp(mtd)) {
20d8e248 2544 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2545 __func__);
1da177e4
LT		 2546 instr->state = MTD_ERASE_FAILED;
2547 goto erase_exit;
2548 }
2549
ace4dfee
TG		 2550 /*
2551 * If BBT requires refresh, set the BBT page mask to see if the BBT
2552 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2553 * can not be matched. This is also done when the bbt is actually
2554 * erased to avoid recusrsive updates
2555 */
2556 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2557 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2558
1da177e4
LT		 2559 /* Loop through the pages */
2560 len = instr->len;
2561
2562 instr->state = MTD_ERASING;
2563
2564 while (len) {
ace4dfee
TG		 2565 /*
2566 * heck if we have a bad block, we do not erase bad blocks !
2567 */
2568 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2569 chip->page_shift, 0, allowbbt)) {
20d8e248 2570 printk(KERN_WARNING "%s: attempt to erase a bad block "
2571 "at page 0x%08x\n", __func__, page);
1da177e4
LT		 2572 instr->state = MTD_ERASE_FAILED;
2573 goto erase_exit;
2574 }
61b03bd7 2575
ace4dfee
TG		 2576 /*
2577 * Invalidate the page cache, if we erase the block which
2578 * contains the current cached page
2579 */
2580 if (page <= chip->pagebuf && chip->pagebuf <
2581 (page + pages_per_block))
2582 chip->pagebuf = -1;
1da177e4 2583
ace4dfee 2584 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2585
7bc3312b 2586 status = chip->waitfunc(mtd, chip);
1da177e4 2587
ace4dfee
TG		 2588 /*
2589 * See if operation failed and additional status checks are
2590 * available
2591 */
2592 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2593 status = chip->errstat(mtd, chip, FL_ERASING,
2594 status, page);
068e3c0a 2595
1da177e4 2596 /* See if block erase succeeded */
a4ab4c5d 2597 if (status & NAND_STATUS_FAIL) {
20d8e248 2598 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2599 "page 0x%08x\n", __func__, page);
1da177e4 2600 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2601 instr->fail_addr =
2602 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2603 goto erase_exit;
2604 }
30f464b7 2605
ace4dfee
TG		 2606 /*
2607 * If BBT requires refresh, set the BBT rewrite flag to the
2608 * page being erased
2609 */
2610 if (bbt_masked_page != 0xffffffff &&
2611 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2612 rewrite_bbt[chipnr] =
2613 ((loff_t)page << chip->page_shift);
61b03bd7 2614
1da177e4 2615 /* Increment page address and decrement length */
ace4dfee 2616 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2617 page += pages_per_block;
2618
2619 /* Check, if we cross a chip boundary */
ace4dfee 2620 if (len && !(page & chip->pagemask)) {
1da177e4 2621 chipnr++;
ace4dfee
TG		 2622 chip->select_chip(mtd, -1);
2623 chip->select_chip(mtd, chipnr);
30f464b7 2624
ace4dfee
TG		 2625 /*
2626 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2627 * page mask to see if this BBT should be rewritten
2628 */
2629 if (bbt_masked_page != 0xffffffff &&
2630 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2631 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2632 BBT_PAGE_MASK;
1da177e4
LT		 2633 }
2634 }
2635 instr->state = MTD_ERASE_DONE;
2636
e0c7d767 2637 erase_exit:
1da177e4
LT		 2638
2639 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2640
2641 /* Deselect and wake up anyone waiting on the device */
2642 nand_release_device(mtd);
2643
49defc01
DW		 2644 /* Do call back function */
2645 if (!ret)
2646 mtd_erase_callback(instr);
2647
ace4dfee
TG		 2648 /*
2649 * If BBT requires refresh and erase was successful, rewrite any
2650 * selected bad block tables
2651 */
2652 if (bbt_masked_page == 0xffffffff || ret)
2653 return ret;
2654
2655 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2656 if (!rewrite_bbt[chipnr])
2657 continue;
2658 /* update the BBT for chip */
20d8e248 2659 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2660 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2661 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
ace4dfee 2662 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2663 }
2664
1da177e4
LT		 2665 /* Return more or less happy */
2666 return ret;
2667}
2668
2669/**
2670 * nand_sync - [MTD Interface] sync
2671 * @mtd: MTD device structure
2672 *
2673 * Sync is actually a wait for chip ready function
2674 */
e0c7d767 2675static void nand_sync(struct mtd_info *mtd)
1da177e4 2676{
ace4dfee 2677 struct nand_chip *chip = mtd->priv;
1da177e4 2678
20d8e248 2679 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
1da177e4
LT		 2680
2681 /* Grab the lock and see if the device is available */
ace4dfee 2682 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2683 /* Release it and go back */
e0c7d767 2684 nand_release_device(mtd);
1da177e4
LT		 2685}
2686
1da177e4 2687/**
ace4dfee 2688 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
1da177e4 2689 * @mtd: MTD device structure
844d3b42 2690 * @offs: offset relative to mtd start
1da177e4 2691 */
ace4dfee 2692static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4
LT		 2693{
2694 /* Check for invalid offset */
ace4dfee 2695 if (offs > mtd->size)
1da177e4 2696 return -EINVAL;
61b03bd7 2697
ace4dfee 2698 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2699}
2700
2701/**
ace4dfee 2702 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1da177e4
LT		 2703 * @mtd: MTD device structure
2704 * @ofs: offset relative to mtd start
2705 */
e0c7d767 2706static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2707{
ace4dfee 2708 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2709 int ret;
2710
f8ac0414
FF		 2711 ret = nand_block_isbad(mtd, ofs);
2712 if (ret) {
e0c7d767 2713 /* If it was bad already, return success and do nothing. */
1da177e4
LT		 2714 if (ret > 0)
2715 return 0;
e0c7d767
DW		 2716 return ret;
2717 }
1da177e4 2718
ace4dfee 2719 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2720}
2721
962034f4
VW		 2722/**
2723 * nand_suspend - [MTD Interface] Suspend the NAND flash
2724 * @mtd: MTD device structure
2725 */
2726static int nand_suspend(struct mtd_info *mtd)
2727{
ace4dfee 2728 struct nand_chip *chip = mtd->priv;
962034f4 2729
ace4dfee 2730 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2731}
2732
2733/**
2734 * nand_resume - [MTD Interface] Resume the NAND flash
2735 * @mtd: MTD device structure
2736 */
2737static void nand_resume(struct mtd_info *mtd)
2738{
ace4dfee 2739 struct nand_chip *chip = mtd->priv;
962034f4 2740
ace4dfee 2741 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2742 nand_release_device(mtd);
2743 else
20d8e248 2744 printk(KERN_ERR "%s called for a chip which is not "
2745 "in suspended state\n", __func__);
962034f4
VW		 2746}
2747
7aa65bfd
TG		 2748/*
2749 * Set default functions
2750 */
ace4dfee 2751static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2752{
1da177e4 2753 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2754 if (!chip->chip_delay)
2755 chip->chip_delay = 20;
1da177e4
LT		 2756
2757 /* check, if a user supplied command function given */
ace4dfee
TG		 2758 if (chip->cmdfunc == NULL)
2759 chip->cmdfunc = nand_command;
1da177e4
LT		 2760
2761 /* check, if a user supplied wait function given */
ace4dfee
TG		 2762 if (chip->waitfunc == NULL)
2763 chip->waitfunc = nand_wait;
2764
2765 if (!chip->select_chip)
2766 chip->select_chip = nand_select_chip;
2767 if (!chip->read_byte)
2768 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2769 if (!chip->read_word)
2770 chip->read_word = nand_read_word;
2771 if (!chip->block_bad)
2772 chip->block_bad = nand_block_bad;
2773 if (!chip->block_markbad)
2774 chip->block_markbad = nand_default_block_markbad;
2775 if (!chip->write_buf)
2776 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2777 if (!chip->read_buf)
2778 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2779 if (!chip->verify_buf)
2780 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2781 if (!chip->scan_bbt)
2782 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2783
2784 if (!chip->controller) {
2785 chip->controller = &chip->hwcontrol;
2786 spin_lock_init(&chip->controller->lock);
2787 init_waitqueue_head(&chip->controller->wq);
2788 }
2789
7aa65bfd
TG		 2790}
2791
d1e1f4e4
FF		 2792/*
2793 * sanitize ONFI strings so we can safely print them
2794 */
2795static void sanitize_string(uint8_t *s, size_t len)
2796{
2797 ssize_t i;
2798
2799 /* null terminate */
2800 s[len - 1] = 0;
2801
2802 /* remove non printable chars */
2803 for (i = 0; i < len - 1; i++) {
2804 if (s[i] < ' ' || s[i] > 127)
2805 s[i] = '?';
2806 }
2807
2808 /* remove trailing spaces */
2809 strim(s);
2810}
2811
2812static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2813{
2814 int i;
2815 while (len--) {
2816 crc ^= *p++ << 8;
2817 for (i = 0; i < 8; i++)
2818 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2819 }
2820
2821 return crc;
2822}
2823
6fb277ba
FF		 2824/*
2825 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2826 */
2827static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2828 int busw)
2829{
2830 struct nand_onfi_params *p = &chip->onfi_params;
2831 int i;
2832 int val;
2833
2834 /* try ONFI for unknow chip or LP */
2835 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2836 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2837 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2838 return 0;
2839
2840 printk(KERN_INFO "ONFI flash detected\n");
2841 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2842 for (i = 0; i < 3; i++) {
2843 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2844 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2845 le16_to_cpu(p->crc)) {
2846 printk(KERN_INFO "ONFI param page %d valid\n", i);
2847 break;
2848 }
2849 }
2850
2851 if (i == 3)
2852 return 0;
2853
2854 /* check version */
2855 val = le16_to_cpu(p->revision);
2856 if (val == 1 || val > (1 << 4)) {
2857 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2858 __func__, val);
2859 return 0;
2860 }
2861
2862 if (val & (1 << 4))
2863 chip->onfi_version = 22;
2864 else if (val & (1 << 3))
2865 chip->onfi_version = 21;
2866 else if (val & (1 << 2))
2867 chip->onfi_version = 20;
2868 else
2869 chip->onfi_version = 10;
2870
2871 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2872 sanitize_string(p->model, sizeof(p->model));
2873 if (!mtd->name)
2874 mtd->name = p->model;
2875 mtd->writesize = le32_to_cpu(p->byte_per_page);
2876 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2877 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2878 chip->chipsize = le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2879 busw = 0;
2880 if (le16_to_cpu(p->features) & 1)
2881 busw = NAND_BUSWIDTH_16;
2882
2883 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2884 chip->options |= (NAND_NO_READRDY |
2885 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2886
2887 return 1;
2888}
2889
7aa65bfd 2890/*
ace4dfee 2891 * Get the flash and manufacturer id and lookup if the type is supported
7aa65bfd
TG		 2892 */
2893static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2894 struct nand_chip *chip,
d1e1f4e4 2895 int busw, int *maf_id, int *dev_id,
5e81e88a 2896 struct nand_flash_dev *type)
7aa65bfd 2897{
d1e1f4e4 2898 int i, maf_idx;
426c457a 2899 u8 id_data[8];
6fb277ba 2900 int ret;
1da177e4
LT		 2901
2902 /* Select the device */
ace4dfee 2903 chip->select_chip(mtd, 0);
1da177e4 2904
ef89a880
KB		 2905 /*
2906 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2907 * after power-up
2908 */
2909 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2910
1da177e4 2911 /* Send the command for reading device ID */
ace4dfee 2912 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2913
2914 /* Read manufacturer and device IDs */
ace4dfee 2915 *maf_id = chip->read_byte(mtd);
d1e1f4e4 2916 *dev_id = chip->read_byte(mtd);
1da177e4 2917
ed8165c7
BD		 2918 /* Try again to make sure, as some systems the bus-hold or other
2919 * interface concerns can cause random data which looks like a
2920 * possibly credible NAND flash to appear. If the two results do
2921 * not match, ignore the device completely.
2922 */
2923
2924 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2925
d1e1f4e4 2926 for (i = 0; i < 2; i++)
426c457a 2927 id_data[i] = chip->read_byte(mtd);
ed8165c7 2928
d1e1f4e4 2929 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
ed8165c7
BD		 2930 printk(KERN_INFO "%s: second ID read did not match "
2931 "%02x,%02x against %02x,%02x\n", __func__,
d1e1f4e4 2932 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 2933 return ERR_PTR(-ENODEV);
2934 }
2935
7aa65bfd 2936 if (!type)
5e81e88a
DW		 2937 type = nand_flash_ids;
2938
2939 for (; type->name != NULL; type++)
d1e1f4e4 2940 if (*dev_id == type->id)
f8ac0414 2941 break;
5e81e88a 2942
d1e1f4e4
FF		 2943 chip->onfi_version = 0;
2944 if (!type->name || !type->pagesize) {
6fb277ba
FF		 2945 /* Check is chip is ONFI compliant */
2946 ret = nand_flash_detect_onfi(mtd, chip, busw);
2947 if (ret)
2948 goto ident_done;
d1e1f4e4
FF		 2949 }
2950
2951 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2952
2953 /* Read entire ID string */
2954
2955 for (i = 0; i < 8; i++)
2956 id_data[i] = chip->read_byte(mtd);
2957
5e81e88a 2958 if (!type->name)
7aa65bfd
TG		 2959 return ERR_PTR(-ENODEV);
2960
ba0251fe
TG		 2961 if (!mtd->name)
2962 mtd->name = type->name;
2963
69423d99 2964 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd
TG		 2965
2966 /* Newer devices have all the information in additional id bytes */
ba0251fe 2967 if (!type->pagesize) {
7aa65bfd 2968 int extid;
29072b96 2969 /* The 3rd id byte holds MLC / multichip data */
426c457a 2970 chip->cellinfo = id_data[2];
7aa65bfd 2971 /* The 4th id byte is the important one */
426c457a 2972 extid = id_data[3];
61b03bd7 2973
426c457a
KC		 2974 /*
2975 * Field definitions are in the following datasheets:
2976 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
34c5bf6c 2977 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
426c457a
KC		 2978 *
2979 * Check for wraparound + Samsung ID + nonzero 6th byte
2980 * to decide what to do.
2981 */
2982 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2983 id_data[0] == NAND_MFR_SAMSUNG &&
cfe3fdad 2984 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
426c457a
KC		 2985 id_data[5] != 0x00) {
2986 /* Calc pagesize */
2987 mtd->writesize = 2048 << (extid & 0x03);
2988 extid >>= 2;
2989 /* Calc oobsize */
34c5bf6c
BN		 2990 switch (extid & 0x03) {
2991 case 1:
2992 mtd->oobsize = 128;
2993 break;
2994 case 2:
2995 mtd->oobsize = 218;
2996 break;
2997 case 3:
2998 mtd->oobsize = 400;
2999 break;
3000 default:
3001 mtd->oobsize = 436;
3002 break;
3003 }
426c457a
KC		 3004 extid >>= 2;
3005 /* Calc blocksize */
3006 mtd->erasesize = (128 * 1024) <<
3007 (((extid >> 1) & 0x04) | (extid & 0x03));
3008 busw = 0;
3009 } else {
3010 /* Calc pagesize */
3011 mtd->writesize = 1024 << (extid & 0x03);
3012 extid >>= 2;
3013 /* Calc oobsize */
3014 mtd->oobsize = (8 << (extid & 0x01)) *
3015 (mtd->writesize >> 9);
3016 extid >>= 2;
3017 /* Calc blocksize. Blocksize is multiples of 64KiB */
3018 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3019 extid >>= 2;
3020 /* Get buswidth information */
3021 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3022 }
7aa65bfd
TG		 3023 } else {
3024 /*
ace4dfee 3025 * Old devices have chip data hardcoded in the device id table
7aa65bfd 3026 */
ba0251fe
TG		 3027 mtd->erasesize = type->erasesize;
3028 mtd->writesize = type->pagesize;
4cbb9b80 3029 mtd->oobsize = mtd->writesize / 32;
ba0251fe 3030 busw = type->options & NAND_BUSWIDTH_16;
2173bae8
BN		 3031
3032 /*
3033 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3034 * some Spansion chips have erasesize that conflicts with size
3035 * listed in nand_ids table
3036 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3037 */
3038 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3039 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3040 id_data[7] == 0x00 && mtd->writesize == 512) {
3041 mtd->erasesize = 128 * 1024;
3042 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3043 }
7aa65bfd 3044 }
d1e1f4e4
FF		 3045 /* Get chip options, preserve non chip based options */
3046 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3047 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3048
3049 /* Check if chip is a not a samsung device. Do not clear the
3050 * options for chips which are not having an extended id.
3051 */
3052 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3053 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3054ident_done:
3055
3056 /*
3057 * Set chip as a default. Board drivers can override it, if necessary
3058 */
3059 chip->options |= NAND_NO_AUTOINCR;
1da177e4 3060
7aa65bfd 3061 /* Try to identify manufacturer */
9a909867 3062 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3063 if (nand_manuf_ids[maf_idx].id == *maf_id)
3064 break;
3065 }
0ea4a755 3066
7aa65bfd
TG		 3067 /*
3068 * Check, if buswidth is correct. Hardware drivers should set
ace4dfee 3069 * chip correct !
7aa65bfd 3070 */
ace4dfee 3071 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
7aa65bfd
TG		 3072 printk(KERN_INFO "NAND device: Manufacturer ID:"
3073 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
d1e1f4e4 3074 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
7aa65bfd 3075 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
ace4dfee 3076 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
7aa65bfd
TG		 3077 busw ? 16 : 8);
3078 return ERR_PTR(-EINVAL);
3079 }
61b03bd7 3080
7aa65bfd 3081 /* Calculate the address shift from the page size */
ace4dfee 3082 chip->page_shift = ffs(mtd->writesize) - 1;
7aa65bfd 3083 /* Convert chipsize to number of pages per chip -1. */
ace4dfee 3084 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3085
ace4dfee 3086 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3087 ffs(mtd->erasesize) - 1;
69423d99
AH		 3088 if (chip->chipsize & 0xffffffff)
3089 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3090 else
3091 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
1da177e4 3092
7aa65bfd 3093 /* Set the bad block position */
065a1ed8 3094 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
c7b28e25 3095 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
065a1ed8
BN		 3096 else
3097 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
61b03bd7 3098
b60b08b0
KC		 3099 /*
3100 * Bad block marker is stored in the last page of each block
c7b28e25
BN		 3101 * on Samsung and Hynix MLC devices; stored in first two pages
3102 * of each block on Micron devices with 2KiB pages and on
13ed7aed
BN		 3103 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3104 * only the first page.
b60b08b0
KC		 3105 */
3106 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3107 (*maf_id == NAND_MFR_SAMSUNG ||
3108 *maf_id == NAND_MFR_HYNIX))
30fe8115 3109 chip->options |= NAND_BBT_SCANLASTPAGE;
c7b28e25
BN		 3110 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3111 (*maf_id == NAND_MFR_SAMSUNG ||
3112 *maf_id == NAND_MFR_HYNIX ||
13ed7aed 3113 *maf_id == NAND_MFR_TOSHIBA ||
c7b28e25
BN		 3114 *maf_id == NAND_MFR_AMD)) ||
3115 (mtd->writesize == 2048 &&
3116 *maf_id == NAND_MFR_MICRON))
3117 chip->options |= NAND_BBT_SCAN2NDPAGE;
3118
58373ff0
BN		 3119 /*
3120 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
3121 */
3122 if (!(busw & NAND_BUSWIDTH_16) &&
3123 *maf_id == NAND_MFR_STMICRO &&
3124 mtd->writesize == 2048) {
3125 chip->options |= NAND_BBT_SCANBYTE1AND6;
3126 chip->badblockpos = 0;
3127 }
b60b08b0 3128
7aa65bfd 3129 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 3130 if (chip->options & NAND_4PAGE_ARRAY)
3131 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 3132 else
ace4dfee 3133 chip->erase_cmd = single_erase_cmd;
7aa65bfd
TG		 3134
3135 /* Do not replace user supplied command function ! */
ace4dfee
TG		 3136 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3137 chip->cmdfunc = nand_command_lp;
7aa65bfd 3138
d1e1f4e4 3139 /* TODO onfi flash name */
7aa65bfd 3140 printk(KERN_INFO "NAND device: Manufacturer ID:"
d1e1f4e4
FF		 3141 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3142 nand_manuf_ids[maf_idx].name,
f8ac0414 3143 chip->onfi_version ? type->name : chip->onfi_params.model);
7aa65bfd
TG		 3144
3145 return type;
3146}
3147
7aa65bfd 3148/**
3b85c321
DW		 3149 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3150 * @mtd: MTD device structure
3151 * @maxchips: Number of chips to scan for
5e81e88a 3152 * @table: Alternative NAND ID table
7aa65bfd 3153 *
3b85c321
DW		 3154 * This is the first phase of the normal nand_scan() function. It
3155 * reads the flash ID and sets up MTD fields accordingly.
7aa65bfd 3156 *
3b85c321 3157 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3158 */
5e81e88a
DW		 3159int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3160 struct nand_flash_dev *table)
7aa65bfd 3161{
d1e1f4e4 3162 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3163 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3164 struct nand_flash_dev *type;
3165
7aa65bfd 3166 /* Get buswidth to select the correct functions */
ace4dfee 3167 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3168 /* Set the default functions */
ace4dfee 3169 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3170
3171 /* Read the flash type */
d1e1f4e4 3172 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3173
3174 if (IS_ERR(type)) {
b1c6e6db
BD		 3175 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3176 printk(KERN_WARNING "No NAND device found.\n");
ace4dfee 3177 chip->select_chip(mtd, -1);
7aa65bfd 3178 return PTR_ERR(type);
1da177e4
LT		 3179 }
3180
7aa65bfd 3181 /* Check for a chip array */
e0c7d767 3182 for (i = 1; i < maxchips; i++) {
ace4dfee 3183 chip->select_chip(mtd, i);
ef89a880
KB		 3184 /* See comment in nand_get_flash_type for reset */
3185 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3186 /* Send the command for reading device ID */
ace4dfee 3187 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3188 /* Read manufacturer and device IDs */
ace4dfee 3189 if (nand_maf_id != chip->read_byte(mtd) ||
d1e1f4e4 3190 nand_dev_id != chip->read_byte(mtd))
1da177e4
LT		 3191 break;
3192 }
3193 if (i > 1)
3194 printk(KERN_INFO "%d NAND chips detected\n", i);
61b03bd7 3195
1da177e4 3196 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3197 chip->numchips = i;
3198 mtd->size = i * chip->chipsize;
7aa65bfd 3199
3b85c321
DW		 3200 return 0;
3201}
3202
3203
3204/**
3205 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3206 * @mtd: MTD device structure
3b85c321
DW		 3207 *
3208 * This is the second phase of the normal nand_scan() function. It
3209 * fills out all the uninitialized function pointers with the defaults
3210 * and scans for a bad block table if appropriate.
3211 */
3212int nand_scan_tail(struct mtd_info *mtd)
3213{
3214 int i;
3215 struct nand_chip *chip = mtd->priv;
3216
4bf63fcb
DW		 3217 if (!(chip->options & NAND_OWN_BUFFERS))
3218 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3219 if (!chip->buffers)
3220 return -ENOMEM;
3221
7dcdcbef 3222 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3223 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3224
7aa65bfd
TG		 3225 /*
3226 * If no default placement scheme is given, select an appropriate one
3227 */
5bd34c09 3228 if (!chip->ecc.layout) {
61b03bd7 3229 switch (mtd->oobsize) {
1da177e4 3230 case 8:
5bd34c09 3231 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3232 break;
3233 case 16:
5bd34c09 3234 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3235 break;
3236 case 64:
5bd34c09 3237 chip->ecc.layout = &nand_oob_64;
1da177e4 3238 break;
81ec5364
TG		 3239 case 128:
3240 chip->ecc.layout = &nand_oob_128;
3241 break;
1da177e4 3242 default:
7aa65bfd
TG		 3243 printk(KERN_WARNING "No oob scheme defined for "
3244 "oobsize %d\n", mtd->oobsize);
1da177e4
LT		 3245 BUG();
3246 }
3247 }
61b03bd7 3248
956e944c
DW		 3249 if (!chip->write_page)
3250 chip->write_page = nand_write_page;
3251
61b03bd7 3252 /*
7aa65bfd
TG		 3253 * check ECC mode, default to software if 3byte/512byte hardware ECC is
3254 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3255 */
956e944c 3256
ace4dfee 3257 switch (chip->ecc.mode) {
6e0cb135
SN		 3258 case NAND_ECC_HW_OOB_FIRST:
3259 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3260 if (!chip->ecc.calculate || !chip->ecc.correct ||
3261 !chip->ecc.hwctl) {
3262 printk(KERN_WARNING "No ECC functions supplied; "
3263 "Hardware ECC not possible\n");
3264 BUG();
3265 }
3266 if (!chip->ecc.read_page)
3267 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3268
6dfc6d25 3269 case NAND_ECC_HW:
f5bbdacc
TG		 3270 /* Use standard hwecc read page function ? */
3271 if (!chip->ecc.read_page)
3272 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3273 if (!chip->ecc.write_page)
3274 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3275 if (!chip->ecc.read_page_raw)
3276 chip->ecc.read_page_raw = nand_read_page_raw;
3277 if (!chip->ecc.write_page_raw)
3278 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3279 if (!chip->ecc.read_oob)
3280 chip->ecc.read_oob = nand_read_oob_std;
3281 if (!chip->ecc.write_oob)
3282 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3283
6dfc6d25 3284 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3285 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3286 !chip->ecc.hwctl) &&
3287 (!chip->ecc.read_page ||
1c45f604 3288 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3289 !chip->ecc.write_page ||
1c45f604 3290 chip->ecc.write_page == nand_write_page_hwecc)) {
6e0cb135 3291 printk(KERN_WARNING "No ECC functions supplied; "
6dfc6d25
TG		 3292 "Hardware ECC not possible\n");
3293 BUG();
3294 }
f75e5097 3295 /* Use standard syndrome read/write page function ? */
f5bbdacc
TG		 3296 if (!chip->ecc.read_page)
3297 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3298 if (!chip->ecc.write_page)
3299 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3300 if (!chip->ecc.read_page_raw)
3301 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3302 if (!chip->ecc.write_page_raw)
3303 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3304 if (!chip->ecc.read_oob)
3305 chip->ecc.read_oob = nand_read_oob_syndrome;
3306 if (!chip->ecc.write_oob)
3307 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3308
ace4dfee 3309 if (mtd->writesize >= chip->ecc.size)
6dfc6d25
TG		 3310 break;
3311 printk(KERN_WARNING "%d byte HW ECC not possible on "
3312 "%d byte page size, fallback to SW ECC\n",
ace4dfee
TG		 3313 chip->ecc.size, mtd->writesize);
3314 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3315
6dfc6d25 3316 case NAND_ECC_SOFT:
ace4dfee
TG		 3317 chip->ecc.calculate = nand_calculate_ecc;
3318 chip->ecc.correct = nand_correct_data;
f5bbdacc 3319 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3320 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3321 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3322 chip->ecc.read_page_raw = nand_read_page_raw;
3323 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3324 chip->ecc.read_oob = nand_read_oob_std;
3325 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3326 if (!chip->ecc.size)
3327 chip->ecc.size = 256;
ace4dfee 3328 chip->ecc.bytes = 3;
1da177e4 3329 break;
61b03bd7
TG		 3330
3331 case NAND_ECC_NONE:
7aa65bfd
TG		 3332 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3333 "This is not recommended !!\n");
8593fbc6
TG		 3334 chip->ecc.read_page = nand_read_page_raw;
3335 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3336 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3337 chip->ecc.read_page_raw = nand_read_page_raw;
3338 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3339 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3340 chip->ecc.size = mtd->writesize;
3341 chip->ecc.bytes = 0;
1da177e4 3342 break;
956e944c 3343
1da177e4 3344 default:
7aa65bfd 3345 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
ace4dfee 3346 chip->ecc.mode);
61b03bd7 3347 BUG();
1da177e4 3348 }
61b03bd7 3349
5bd34c09
TG		 3350 /*
3351 * The number of bytes available for a client to place data into
3352 * the out of band area
3353 */
3354 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3355 for (i = 0; chip->ecc.layout->oobfree[i].length
3356 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3357 chip->ecc.layout->oobavail +=
3358 chip->ecc.layout->oobfree[i].length;
1f92267c 3359 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3360
7aa65bfd
TG		 3361 /*
3362 * Set the number of read / write steps for one page depending on ECC
3363 * mode
3364 */
ace4dfee 3365 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3366 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
6dfc6d25
TG		 3367 printk(KERN_WARNING "Invalid ecc parameters\n");
3368 BUG();
1da177e4 3369 }
f5bbdacc 3370 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3371
29072b96
TG		 3372 /*
3373 * Allow subpage writes up to ecc.steps. Not possible for MLC
3374 * FLASH.
3375 */
3376 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3377 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3378 switch (chip->ecc.steps) {
29072b96
TG		 3379 case 2:
3380 mtd->subpage_sft = 1;
3381 break;
3382 case 4:
3383 case 8:
81ec5364 3384 case 16:
29072b96
TG		 3385 mtd->subpage_sft = 2;
3386 break;
3387 }
3388 }
3389 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3390
04bbd0ea 3391 /* Initialize state */
ace4dfee 3392 chip->state = FL_READY;
1da177e4
LT		 3393
3394 /* De-select the device */
ace4dfee 3395 chip->select_chip(mtd, -1);
1da177e4
LT		 3396
3397 /* Invalidate the pagebuffer reference */
ace4dfee 3398 chip->pagebuf = -1;
1da177e4
LT		 3399
3400 /* Fill in remaining MTD driver data */
3401 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3402 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3403 MTD_CAP_NANDFLASH;
1da177e4
LT		 3404 mtd->erase = nand_erase;
3405 mtd->point = NULL;
3406 mtd->unpoint = NULL;
3407 mtd->read = nand_read;
3408 mtd->write = nand_write;
2af7c653 3409 mtd->panic_write = panic_nand_write;
1da177e4
LT		 3410 mtd->read_oob = nand_read_oob;
3411 mtd->write_oob = nand_write_oob;
1da177e4
LT		 3412 mtd->sync = nand_sync;
3413 mtd->lock = NULL;
3414 mtd->unlock = NULL;
962034f4
VW		 3415 mtd->suspend = nand_suspend;
3416 mtd->resume = nand_resume;
1da177e4
LT		 3417 mtd->block_isbad = nand_block_isbad;
3418 mtd->block_markbad = nand_block_markbad;
3419
5bd34c09
TG		 3420 /* propagate ecc.layout to mtd_info */
3421 mtd->ecclayout = chip->ecc.layout;
1da177e4 3422
0040bf38 3423 /* Check, if we should skip the bad block table scan */
ace4dfee 3424 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3425 return 0;
1da177e4
LT		 3426
3427 /* Build bad block table */
ace4dfee 3428 return chip->scan_bbt(mtd);
1da177e4
LT		 3429}
3430
a6e6abd5 3431/* is_module_text_address() isn't exported, and it's mostly a pointless
3b85c321
DW		 3432 test if this is a module _anyway_ -- they'd have to try _really_ hard
3433 to call us from in-kernel code if the core NAND support is modular. */
3434#ifdef MODULE
3435#define caller_is_module() (1)
3436#else
3437#define caller_is_module() \
a6e6abd5 3438 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3439#endif
3440
3441/**
3442 * nand_scan - [NAND Interface] Scan for the NAND device
3443 * @mtd: MTD device structure
3444 * @maxchips: Number of chips to scan for
3445 *
3446 * This fills out all the uninitialized function pointers
3447 * with the defaults.
3448 * The flash ID is read and the mtd/chip structures are
3449 * filled with the appropriate values.
3450 * The mtd->owner field must be set to the module of the caller
3451 *
3452 */
3453int nand_scan(struct mtd_info *mtd, int maxchips)
3454{
3455 int ret;
3456
3457 /* Many callers got this wrong, so check for it for a while... */
3458 if (!mtd->owner && caller_is_module()) {
20d8e248 3459 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3460 __func__);
3b85c321
DW		 3461 BUG();
3462 }
3463
5e81e88a 3464 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3465 if (!ret)
3466 ret = nand_scan_tail(mtd);
3467 return ret;
3468}
3469
1da177e4 3470/**
61b03bd7 3471 * nand_release - [NAND Interface] Free resources held by the NAND device
1da177e4
LT		 3472 * @mtd: MTD device structure
3473*/
e0c7d767 3474void nand_release(struct mtd_info *mtd)
1da177e4 3475{
ace4dfee 3476 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 3477
3478#ifdef CONFIG_MTD_PARTITIONS
3479 /* Deregister partitions */
e0c7d767 3480 del_mtd_partitions(mtd);
1da177e4
LT		 3481#endif
3482 /* Deregister the device */
e0c7d767 3483 del_mtd_device(mtd);
1da177e4 3484
fa671646 3485 /* Free bad block table memory */
ace4dfee 3486 kfree(chip->bbt);
4bf63fcb
DW		 3487 if (!(chip->options & NAND_OWN_BUFFERS))
3488 kfree(chip->buffers);
58373ff0
BN		 3489
3490 /* Free bad block descriptor memory */
3491 if (chip->badblock_pattern && chip->badblock_pattern->options
3492 & NAND_BBT_DYNAMICSTRUCT)
3493 kfree(chip->badblock_pattern);
1da177e4
LT		 3494}
3495
7d70f334
VS		 3496EXPORT_SYMBOL_GPL(nand_lock);
3497EXPORT_SYMBOL_GPL(nand_unlock);
e0c7d767 3498EXPORT_SYMBOL_GPL(nand_scan);
3b85c321
DW		 3499EXPORT_SYMBOL_GPL(nand_scan_ident);
3500EXPORT_SYMBOL_GPL(nand_scan_tail);
e0c7d767 3501EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3502
3503static int __init nand_base_init(void)
3504{
3505 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3506 return 0;
3507}
3508
3509static void __exit nand_base_exit(void)
3510{
3511 led_trigger_unregister_simple(nand_led_trigger);
3512}
3513
3514module_init(nand_base_init);
3515module_exit(nand_base_exit);
3516
e0c7d767
DW		 3517MODULE_LICENSE("GPL");
3518MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
3519MODULE_DESCRIPTION("Generic NAND flash driver code");
Clone of davem's net-next-2.6 tree