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Merge git://git.infradead.org/mtd-2.6
[net-next-2.6.git] / drivers / mtd / nand / nand_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
61b03bd7 8 *
1da177e4 9 * Additional technical information is available on
8b2b403c 10 * http://www.linux-mtd.infradead.org/doc/nand.html
61b03bd7 11 *
1da177e4 12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
ace4dfee 13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
1da177e4 14 *
ace4dfee 15 * Credits:
61b03bd7
TG		 16 * David Woodhouse for adding multichip support
17 *
1da177e4
LT		 18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
ace4dfee 21 * TODO:
1da177e4
LT		 22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
c0b8ba7b 27 * BBT table is not serialized, has to be fixed
1da177e4 28 *
1da177e4
LT		 29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
552d9205 35#include <linux/module.h>
1da177e4
LT		 36#include <linux/delay.h>
37#include <linux/errno.h>
7aa65bfd 38#include <linux/err.h>
1da177e4
LT		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
42#include <linux/mtd/mtd.h>
43#include <linux/mtd/nand.h>
44#include <linux/mtd/nand_ecc.h>
1da177e4
LT		 45#include <linux/interrupt.h>
46#include <linux/bitops.h>
8fe833c1 47#include <linux/leds.h>
7351d3a5 48#include <linux/io.h>
1da177e4
LT		 49
50#ifdef CONFIG_MTD_PARTITIONS
51#include <linux/mtd/partitions.h>
52#endif
53
54/* Define default oob placement schemes for large and small page devices */
5bd34c09 55static struct nand_ecclayout nand_oob_8 = {
1da177e4
LT		 56 .eccbytes = 3,
57 .eccpos = {0, 1, 2},
5bd34c09
TG		 58 .oobfree = {
59 {.offset = 3,
60 .length = 2},
61 {.offset = 6,
f8ac0414 62 .length = 2} }
1da177e4
LT		 63};
64
5bd34c09 65static struct nand_ecclayout nand_oob_16 = {
1da177e4
LT		 66 .eccbytes = 6,
67 .eccpos = {0, 1, 2, 3, 6, 7},
5bd34c09
TG		 68 .oobfree = {
69 {.offset = 8,
f8ac0414 70 . length = 8} }
1da177e4
LT		 71};
72
5bd34c09 73static struct nand_ecclayout nand_oob_64 = {
1da177e4
LT		 74 .eccbytes = 24,
75 .eccpos = {
e0c7d767
DW		 76 40, 41, 42, 43, 44, 45, 46, 47,
77 48, 49, 50, 51, 52, 53, 54, 55,
78 56, 57, 58, 59, 60, 61, 62, 63},
5bd34c09
TG		 79 .oobfree = {
80 {.offset = 2,
f8ac0414 81 .length = 38} }
1da177e4
LT		 82};
83
81ec5364
TG		 84static struct nand_ecclayout nand_oob_128 = {
85 .eccbytes = 48,
86 .eccpos = {
87 80, 81, 82, 83, 84, 85, 86, 87,
88 88, 89, 90, 91, 92, 93, 94, 95,
89 96, 97, 98, 99, 100, 101, 102, 103,
90 104, 105, 106, 107, 108, 109, 110, 111,
91 112, 113, 114, 115, 116, 117, 118, 119,
92 120, 121, 122, 123, 124, 125, 126, 127},
93 .oobfree = {
94 {.offset = 2,
f8ac0414 95 .length = 78} }
81ec5364
TG		 96};
97
ace4dfee 98static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
2c0a2bed 99 int new_state);
1da177e4 100
8593fbc6
TG		 101static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
102 struct mtd_oob_ops *ops);
103
d470a97c 104/*
8e87d782 105 * For devices which display every fart in the system on a separate LED. Is
d470a97c
TG		 106 * compiled away when LED support is disabled.
107 */
108DEFINE_LED_TRIGGER(nand_led_trigger);
109
6fe5a6ac
VS		 110static int check_offs_len(struct mtd_info *mtd,
111 loff_t ofs, uint64_t len)
112{
113 struct nand_chip *chip = mtd->priv;
114 int ret = 0;
115
116 /* Start address must align on block boundary */
117 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
118 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
119 ret = -EINVAL;
120 }
121
122 /* Length must align on block boundary */
123 if (len & ((1 << chip->phys_erase_shift) - 1)) {
124 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
125 __func__);
126 ret = -EINVAL;
127 }
128
129 /* Do not allow past end of device */
130 if (ofs + len > mtd->size) {
131 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
132 __func__);
133 ret = -EINVAL;
134 }
135
136 return ret;
137}
138
1da177e4
LT		 139/**
140 * nand_release_device - [GENERIC] release chip
141 * @mtd: MTD device structure
61b03bd7
TG		 142 *
143 * Deselect, release chip lock and wake up anyone waiting on the device
1da177e4 144 */
e0c7d767 145static void nand_release_device(struct mtd_info *mtd)
1da177e4 146{
ace4dfee 147 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 148
149 /* De-select the NAND device */
ace4dfee 150 chip->select_chip(mtd, -1);
0dfc6246 151
a36ed299 152 /* Release the controller and the chip */
ace4dfee
TG		 153 spin_lock(&chip->controller->lock);
154 chip->controller->active = NULL;
155 chip->state = FL_READY;
156 wake_up(&chip->controller->wq);
157 spin_unlock(&chip->controller->lock);
1da177e4
LT		 158}
159
160/**
161 * nand_read_byte - [DEFAULT] read one byte from the chip
162 * @mtd: MTD device structure
163 *
164 * Default read function for 8bit buswith
165 */
58dd8f2b 166static uint8_t nand_read_byte(struct mtd_info *mtd)
1da177e4 167{
ace4dfee
TG		 168 struct nand_chip *chip = mtd->priv;
169 return readb(chip->IO_ADDR_R);
1da177e4
LT		 170}
171
1da177e4
LT		 172/**
173 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
174 * @mtd: MTD device structure
175 *
61b03bd7 176 * Default read function for 16bit buswith with
1da177e4
LT		 177 * endianess conversion
178 */
58dd8f2b 179static uint8_t nand_read_byte16(struct mtd_info *mtd)
1da177e4 180{
ace4dfee
TG		 181 struct nand_chip *chip = mtd->priv;
182 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
1da177e4
LT		 183}
184
1da177e4
LT		 185/**
186 * nand_read_word - [DEFAULT] read one word from the chip
187 * @mtd: MTD device structure
188 *
61b03bd7 189 * Default read function for 16bit buswith without
1da177e4
LT		 190 * endianess conversion
191 */
192static u16 nand_read_word(struct mtd_info *mtd)
193{
ace4dfee
TG		 194 struct nand_chip *chip = mtd->priv;
195 return readw(chip->IO_ADDR_R);
1da177e4
LT		 196}
197
1da177e4
LT		 198/**
199 * nand_select_chip - [DEFAULT] control CE line
200 * @mtd: MTD device structure
844d3b42 201 * @chipnr: chipnumber to select, -1 for deselect
1da177e4
LT		 202 *
203 * Default select function for 1 chip devices.
204 */
ace4dfee 205static void nand_select_chip(struct mtd_info *mtd, int chipnr)
1da177e4 206{
ace4dfee
TG		 207 struct nand_chip *chip = mtd->priv;
208
209 switch (chipnr) {
1da177e4 210 case -1:
ace4dfee 211 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
1da177e4
LT		 212 break;
213 case 0:
1da177e4
LT		 214 break;
215
216 default:
217 BUG();
218 }
219}
220
221/**
222 * nand_write_buf - [DEFAULT] write buffer to chip
223 * @mtd: MTD device structure
224 * @buf: data buffer
225 * @len: number of bytes to write
226 *
227 * Default write function for 8bit buswith
228 */
58dd8f2b 229static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 230{
231 int i;
ace4dfee 232 struct nand_chip *chip = mtd->priv;
1da177e4 233
e0c7d767 234 for (i = 0; i < len; i++)
ace4dfee 235 writeb(buf[i], chip->IO_ADDR_W);
1da177e4
LT		 236}
237
238/**
61b03bd7 239 * nand_read_buf - [DEFAULT] read chip data into buffer
1da177e4
LT		 240 * @mtd: MTD device structure
241 * @buf: buffer to store date
242 * @len: number of bytes to read
243 *
244 * Default read function for 8bit buswith
245 */
58dd8f2b 246static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 247{
248 int i;
ace4dfee 249 struct nand_chip *chip = mtd->priv;
1da177e4 250
e0c7d767 251 for (i = 0; i < len; i++)
ace4dfee 252 buf[i] = readb(chip->IO_ADDR_R);
1da177e4
LT		 253}
254
255/**
61b03bd7 256 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 257 * @mtd: MTD device structure
258 * @buf: buffer containing the data to compare
259 * @len: number of bytes to compare
260 *
261 * Default verify function for 8bit buswith
262 */
58dd8f2b 263static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 264{
265 int i;
ace4dfee 266 struct nand_chip *chip = mtd->priv;
1da177e4 267
e0c7d767 268 for (i = 0; i < len; i++)
ace4dfee 269 if (buf[i] != readb(chip->IO_ADDR_R))
1da177e4 270 return -EFAULT;
1da177e4
LT		 271 return 0;
272}
273
274/**
275 * nand_write_buf16 - [DEFAULT] write buffer to chip
276 * @mtd: MTD device structure
277 * @buf: data buffer
278 * @len: number of bytes to write
279 *
280 * Default write function for 16bit buswith
281 */
58dd8f2b 282static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 283{
284 int i;
ace4dfee 285 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 286 u16 *p = (u16 *) buf;
287 len >>= 1;
61b03bd7 288
e0c7d767 289 for (i = 0; i < len; i++)
ace4dfee 290 writew(p[i], chip->IO_ADDR_W);
61b03bd7 291
1da177e4
LT		 292}
293
294/**
61b03bd7 295 * nand_read_buf16 - [DEFAULT] read chip data into buffer
1da177e4
LT		 296 * @mtd: MTD device structure
297 * @buf: buffer to store date
298 * @len: number of bytes to read
299 *
300 * Default read function for 16bit buswith
301 */
58dd8f2b 302static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
1da177e4
LT		 303{
304 int i;
ace4dfee 305 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 306 u16 *p = (u16 *) buf;
307 len >>= 1;
308
e0c7d767 309 for (i = 0; i < len; i++)
ace4dfee 310 p[i] = readw(chip->IO_ADDR_R);
1da177e4
LT		 311}
312
313/**
61b03bd7 314 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
1da177e4
LT		 315 * @mtd: MTD device structure
316 * @buf: buffer containing the data to compare
317 * @len: number of bytes to compare
318 *
319 * Default verify function for 16bit buswith
320 */
58dd8f2b 321static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
1da177e4
LT		 322{
323 int i;
ace4dfee 324 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 325 u16 *p = (u16 *) buf;
326 len >>= 1;
327
e0c7d767 328 for (i = 0; i < len; i++)
ace4dfee 329 if (p[i] != readw(chip->IO_ADDR_R))
1da177e4
LT		 330 return -EFAULT;
331
332 return 0;
333}
334
335/**
336 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
337 * @mtd: MTD device structure
338 * @ofs: offset from device start
339 * @getchip: 0, if the chip is already selected
340 *
61b03bd7 341 * Check, if the block is bad.
1da177e4
LT		 342 */
343static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
344{
345 int page, chipnr, res = 0;
ace4dfee 346 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 347 u16 bad;
348
30fe8115 349 if (chip->options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 350 ofs += mtd->erasesize - mtd->writesize;
351
1a12f46a
TK		 352 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
353
1da177e4 354 if (getchip) {
ace4dfee 355 chipnr = (int)(ofs >> chip->chip_shift);
1da177e4 356
ace4dfee 357 nand_get_device(chip, mtd, FL_READING);
1da177e4
LT		 358
359 /* Select the NAND device */
ace4dfee 360 chip->select_chip(mtd, chipnr);
1a12f46a 361 }
1da177e4 362
ace4dfee
TG		 363 if (chip->options & NAND_BUSWIDTH_16) {
364 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
1a12f46a 365 page);
ace4dfee
TG		 366 bad = cpu_to_le16(chip->read_word(mtd));
367 if (chip->badblockpos & 0x1)
49196f33 368 bad >>= 8;
e0b58d0a
ML		 369 else
370 bad &= 0xFF;
1da177e4 371 } else {
1a12f46a 372 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
e0b58d0a 373 bad = chip->read_byte(mtd);
1da177e4 374 }
61b03bd7 375
e0b58d0a
ML		 376 if (likely(chip->badblockbits == 8))
377 res = bad != 0xFF;
378 else
379 res = hweight8(bad) < chip->badblockbits;
380
ace4dfee 381 if (getchip)
1da177e4 382 nand_release_device(mtd);
61b03bd7 383
1da177e4
LT		 384 return res;
385}
386
387/**
388 * nand_default_block_markbad - [DEFAULT] mark a block bad
389 * @mtd: MTD device structure
390 * @ofs: offset from device start
391 *
392 * This is the default implementation, which can be overridden by
393 * a hardware specific driver.
394*/
395static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
396{
ace4dfee 397 struct nand_chip *chip = mtd->priv;
58dd8f2b 398 uint8_t buf[2] = { 0, 0 };
02ed70bb 399 int block, ret, i = 0;
61b03bd7 400
30fe8115 401 if (chip->options & NAND_BBT_SCANLASTPAGE)
b60b08b0
KC		 402 ofs += mtd->erasesize - mtd->writesize;
403
1da177e4 404 /* Get block number */
4226b510 405 block = (int)(ofs >> chip->bbt_erase_shift);
ace4dfee
TG		 406 if (chip->bbt)
407 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
1da177e4
LT		 408
409 /* Do we have a flash based bad block table ? */
ace4dfee 410 if (chip->options & NAND_USE_FLASH_BBT)
f1a28c02
TG		 411 ret = nand_update_bbt(mtd, ofs);
412 else {
c0b8ba7b 413 nand_get_device(chip, mtd, FL_WRITING);
f1a28c02 414
02ed70bb
BN		 415 /* Write to first two pages and to byte 1 and 6 if necessary.
416 * If we write to more than one location, the first error
417 * encountered quits the procedure. We write two bytes per
418 * location, so we dont have to mess with 16 bit access.
419 */
420 do {
421 chip->ops.len = chip->ops.ooblen = 2;
422 chip->ops.datbuf = NULL;
423 chip->ops.oobbuf = buf;
424 chip->ops.ooboffs = chip->badblockpos & ~0x01;
425
426 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
427
428 if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) {
429 chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS
430 & ~0x01;
431 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
432 }
433 i++;
434 ofs += mtd->writesize;
435 } while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) &&
436 i < 2);
437
c0b8ba7b 438 nand_release_device(mtd);
f1a28c02
TG		 439 }
440 if (!ret)
441 mtd->ecc_stats.badblocks++;
c0b8ba7b 442
f1a28c02 443 return ret;
1da177e4
LT		 444}
445
61b03bd7 446/**
1da177e4
LT		 447 * nand_check_wp - [GENERIC] check if the chip is write protected
448 * @mtd: MTD device structure
61b03bd7 449 * Check, if the device is write protected
1da177e4 450 *
61b03bd7 451 * The function expects, that the device is already selected
1da177e4 452 */
e0c7d767 453static int nand_check_wp(struct mtd_info *mtd)
1da177e4 454{
ace4dfee 455 struct nand_chip *chip = mtd->priv;
93edbad6
ML		 456
457 /* broken xD cards report WP despite being writable */
458 if (chip->options & NAND_BROKEN_XD)
459 return 0;
460
1da177e4 461 /* Check the WP bit */
ace4dfee
TG		 462 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
463 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
1da177e4
LT		 464}
465
466/**
467 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
468 * @mtd: MTD device structure
469 * @ofs: offset from device start
470 * @getchip: 0, if the chip is already selected
471 * @allowbbt: 1, if its allowed to access the bbt area
472 *
473 * Check, if the block is bad. Either by reading the bad block table or
474 * calling of the scan function.
475 */
2c0a2bed
TG		 476static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
477 int allowbbt)
1da177e4 478{
ace4dfee 479 struct nand_chip *chip = mtd->priv;
61b03bd7 480
ace4dfee
TG		 481 if (!chip->bbt)
482 return chip->block_bad(mtd, ofs, getchip);
61b03bd7 483
1da177e4 484 /* Return info from the table */
e0c7d767 485 return nand_isbad_bbt(mtd, ofs, allowbbt);
1da177e4
LT		 486}
487
2af7c653
SK		 488/**
489 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
490 * @mtd: MTD device structure
491 * @timeo: Timeout
492 *
493 * Helper function for nand_wait_ready used when needing to wait in interrupt
494 * context.
495 */
496static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
497{
498 struct nand_chip *chip = mtd->priv;
499 int i;
500
501 /* Wait for the device to get ready */
502 for (i = 0; i < timeo; i++) {
503 if (chip->dev_ready(mtd))
504 break;
505 touch_softlockup_watchdog();
506 mdelay(1);
507 }
508}
509
61b03bd7 510/*
3b88775c
TG		 511 * Wait for the ready pin, after a command
512 * The timeout is catched later.
513 */
4b648b02 514void nand_wait_ready(struct mtd_info *mtd)
3b88775c 515{
ace4dfee 516 struct nand_chip *chip = mtd->priv;
e0c7d767 517 unsigned long timeo = jiffies + 2;
3b88775c 518
2af7c653
SK		 519 /* 400ms timeout */
520 if (in_interrupt() || oops_in_progress)
521 return panic_nand_wait_ready(mtd, 400);
522
8fe833c1 523 led_trigger_event(nand_led_trigger, LED_FULL);
3b88775c
TG		 524 /* wait until command is processed or timeout occures */
525 do {
ace4dfee 526 if (chip->dev_ready(mtd))
8fe833c1 527 break;
8446f1d3 528 touch_softlockup_watchdog();
61b03bd7 529 } while (time_before(jiffies, timeo));
8fe833c1 530 led_trigger_event(nand_led_trigger, LED_OFF);
3b88775c 531}
4b648b02 532EXPORT_SYMBOL_GPL(nand_wait_ready);
3b88775c 533
1da177e4
LT		 534/**
535 * nand_command - [DEFAULT] Send command to NAND device
536 * @mtd: MTD device structure
537 * @command: the command to be sent
538 * @column: the column address for this command, -1 if none
539 * @page_addr: the page address for this command, -1 if none
540 *
541 * Send command to NAND device. This function is used for small page
542 * devices (256/512 Bytes per page)
543 */
7abd3ef9
TG		 544static void nand_command(struct mtd_info *mtd, unsigned int command,
545 int column, int page_addr)
1da177e4 546{
ace4dfee 547 register struct nand_chip *chip = mtd->priv;
7abd3ef9 548 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
1da177e4 549
1da177e4
LT		 550 /*
551 * Write out the command to the device.
552 */
553 if (command == NAND_CMD_SEQIN) {
554 int readcmd;
555
28318776 556 if (column >= mtd->writesize) {
1da177e4 557 /* OOB area */
28318776 558 column -= mtd->writesize;
1da177e4
LT		 559 readcmd = NAND_CMD_READOOB;
560 } else if (column < 256) {
561 /* First 256 bytes --> READ0 */
562 readcmd = NAND_CMD_READ0;
563 } else {
564 column -= 256;
565 readcmd = NAND_CMD_READ1;
566 }
ace4dfee 567 chip->cmd_ctrl(mtd, readcmd, ctrl);
7abd3ef9 568 ctrl &= ~NAND_CTRL_CHANGE;
1da177e4 569 }
ace4dfee 570 chip->cmd_ctrl(mtd, command, ctrl);
1da177e4 571
7abd3ef9
TG		 572 /*
573 * Address cycle, when necessary
574 */
575 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
576 /* Serially input address */
577 if (column != -1) {
578 /* Adjust columns for 16 bit buswidth */
ace4dfee 579 if (chip->options & NAND_BUSWIDTH_16)
7abd3ef9 580 column >>= 1;
ace4dfee 581 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9
TG		 582 ctrl &= ~NAND_CTRL_CHANGE;
583 }
584 if (page_addr != -1) {
ace4dfee 585 chip->cmd_ctrl(mtd, page_addr, ctrl);
7abd3ef9 586 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 587 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
7abd3ef9 588 /* One more address cycle for devices > 32MiB */
ace4dfee
TG		 589 if (chip->chipsize > (32 << 20))
590 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
1da177e4 591 }
ace4dfee 592 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 593
594 /*
595 * program and erase have their own busy handlers
1da177e4 596 * status and sequential in needs no delay
e0c7d767 597 */
1da177e4 598 switch (command) {
61b03bd7 599
1da177e4
LT		 600 case NAND_CMD_PAGEPROG:
601 case NAND_CMD_ERASE1:
602 case NAND_CMD_ERASE2:
603 case NAND_CMD_SEQIN:
604 case NAND_CMD_STATUS:
605 return;
606
607 case NAND_CMD_RESET:
ace4dfee 608 if (chip->dev_ready)
1da177e4 609 break;
ace4dfee
TG		 610 udelay(chip->chip_delay);
611 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
7abd3ef9 612 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
12efdde3
TG		 613 chip->cmd_ctrl(mtd,
614 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 615 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
616 ;
1da177e4
LT		 617 return;
618
e0c7d767 619 /* This applies to read commands */
1da177e4 620 default:
61b03bd7 621 /*
1da177e4
LT		 622 * If we don't have access to the busy pin, we apply the given
623 * command delay
e0c7d767 624 */
ace4dfee
TG		 625 if (!chip->dev_ready) {
626 udelay(chip->chip_delay);
1da177e4 627 return;
61b03bd7 628 }
1da177e4 629 }
1da177e4
LT		 630 /* Apply this short delay always to ensure that we do wait tWB in
631 * any case on any machine. */
e0c7d767 632 ndelay(100);
3b88775c
TG		 633
634 nand_wait_ready(mtd);
1da177e4
LT		 635}
636
637/**
638 * nand_command_lp - [DEFAULT] Send command to NAND large page device
639 * @mtd: MTD device structure
640 * @command: the command to be sent
641 * @column: the column address for this command, -1 if none
642 * @page_addr: the page address for this command, -1 if none
643 *
7abd3ef9
TG		 644 * Send command to NAND device. This is the version for the new large page
645 * devices We dont have the separate regions as we have in the small page
646 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
1da177e4 647 */
7abd3ef9
TG		 648static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
649 int column, int page_addr)
1da177e4 650{
ace4dfee 651 register struct nand_chip *chip = mtd->priv;
1da177e4
LT		 652
653 /* Emulate NAND_CMD_READOOB */
654 if (command == NAND_CMD_READOOB) {
28318776 655 column += mtd->writesize;
1da177e4
LT		 656 command = NAND_CMD_READ0;
657 }
61b03bd7 658
7abd3ef9 659 /* Command latch cycle */
ace4dfee 660 chip->cmd_ctrl(mtd, command & 0xff,
7abd3ef9 661 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
1da177e4
LT		 662
663 if (column != -1 || page_addr != -1) {
7abd3ef9 664 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
1da177e4
LT		 665
666 /* Serially input address */
667 if (column != -1) {
668 /* Adjust columns for 16 bit buswidth */
ace4dfee 669 if (chip->options & NAND_BUSWIDTH_16)
1da177e4 670 column >>= 1;
ace4dfee 671 chip->cmd_ctrl(mtd, column, ctrl);
7abd3ef9 672 ctrl &= ~NAND_CTRL_CHANGE;
ace4dfee 673 chip->cmd_ctrl(mtd, column >> 8, ctrl);
61b03bd7 674 }
1da177e4 675 if (page_addr != -1) {
ace4dfee
TG		 676 chip->cmd_ctrl(mtd, page_addr, ctrl);
677 chip->cmd_ctrl(mtd, page_addr >> 8,
7abd3ef9 678 NAND_NCE | NAND_ALE);
1da177e4 679 /* One more address cycle for devices > 128MiB */
ace4dfee
TG		 680 if (chip->chipsize > (128 << 20))
681 chip->cmd_ctrl(mtd, page_addr >> 16,
7abd3ef9 682 NAND_NCE | NAND_ALE);
1da177e4 683 }
1da177e4 684 }
ace4dfee 685 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7
TG		 686
687 /*
688 * program and erase have their own busy handlers
30f464b7
DM		 689 * status, sequential in, and deplete1 need no delay
690 */
1da177e4 691 switch (command) {
61b03bd7 692
1da177e4
LT		 693 case NAND_CMD_CACHEDPROG:
694 case NAND_CMD_PAGEPROG:
695 case NAND_CMD_ERASE1:
696 case NAND_CMD_ERASE2:
697 case NAND_CMD_SEQIN:
7bc3312b 698 case NAND_CMD_RNDIN:
1da177e4 699 case NAND_CMD_STATUS:
30f464b7 700 case NAND_CMD_DEPLETE1:
1da177e4
LT		 701 return;
702
e0c7d767
DW		 703 /*
704 * read error status commands require only a short delay
705 */
30f464b7
DM		 706 case NAND_CMD_STATUS_ERROR:
707 case NAND_CMD_STATUS_ERROR0:
708 case NAND_CMD_STATUS_ERROR1:
709 case NAND_CMD_STATUS_ERROR2:
710 case NAND_CMD_STATUS_ERROR3:
ace4dfee 711 udelay(chip->chip_delay);
30f464b7 712 return;
1da177e4
LT		 713
714 case NAND_CMD_RESET:
ace4dfee 715 if (chip->dev_ready)
1da177e4 716 break;
ace4dfee 717 udelay(chip->chip_delay);
12efdde3
TG		 718 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
719 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
720 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
721 NAND_NCE | NAND_CTRL_CHANGE);
f8ac0414
FF		 722 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
723 ;
1da177e4
LT		 724 return;
725
7bc3312b
TG		 726 case NAND_CMD_RNDOUT:
727 /* No ready / busy check necessary */
728 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
729 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
730 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
731 NAND_NCE | NAND_CTRL_CHANGE);
732 return;
733
1da177e4 734 case NAND_CMD_READ0:
12efdde3
TG		 735 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
736 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
737 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
738 NAND_NCE | NAND_CTRL_CHANGE);
61b03bd7 739
e0c7d767 740 /* This applies to read commands */
1da177e4 741 default:
61b03bd7 742 /*
1da177e4
LT		 743 * If we don't have access to the busy pin, we apply the given
744 * command delay
e0c7d767 745 */
ace4dfee
TG		 746 if (!chip->dev_ready) {
747 udelay(chip->chip_delay);
1da177e4 748 return;
61b03bd7 749 }
1da177e4 750 }
3b88775c 751
1da177e4
LT		 752 /* Apply this short delay always to ensure that we do wait tWB in
753 * any case on any machine. */
e0c7d767 754 ndelay(100);
3b88775c
TG		 755
756 nand_wait_ready(mtd);
1da177e4
LT		 757}
758
2af7c653
SK		 759/**
760 * panic_nand_get_device - [GENERIC] Get chip for selected access
761 * @chip: the nand chip descriptor
762 * @mtd: MTD device structure
763 * @new_state: the state which is requested
764 *
765 * Used when in panic, no locks are taken.
766 */
767static void panic_nand_get_device(struct nand_chip *chip,
768 struct mtd_info *mtd, int new_state)
769{
770 /* Hardware controller shared among independend devices */
771 chip->controller->active = chip;
772 chip->state = new_state;
773}
774
1da177e4
LT		 775/**
776 * nand_get_device - [GENERIC] Get chip for selected access
844d3b42 777 * @chip: the nand chip descriptor
1da177e4 778 * @mtd: MTD device structure
61b03bd7 779 * @new_state: the state which is requested
1da177e4
LT		 780 *
781 * Get the device and lock it for exclusive access
782 */
2c0a2bed 783static int
ace4dfee 784nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
1da177e4 785{
ace4dfee
TG		 786 spinlock_t *lock = &chip->controller->lock;
787 wait_queue_head_t *wq = &chip->controller->wq;
e0c7d767 788 DECLARE_WAITQUEUE(wait, current);
7351d3a5 789retry:
0dfc6246
TG		 790 spin_lock(lock);
791
b8b3ee9a 792 /* Hardware controller shared among independent devices */
ace4dfee
TG		 793 if (!chip->controller->active)
794 chip->controller->active = chip;
a36ed299 795
ace4dfee
TG		 796 if (chip->controller->active == chip && chip->state == FL_READY) {
797 chip->state = new_state;
0dfc6246 798 spin_unlock(lock);
962034f4
VW		 799 return 0;
800 }
801 if (new_state == FL_PM_SUSPENDED) {
6b0d9a84
LY		 802 if (chip->controller->active->state == FL_PM_SUSPENDED) {
803 chip->state = FL_PM_SUSPENDED;
804 spin_unlock(lock);
805 return 0;
6b0d9a84 806 }
0dfc6246
TG		 807 }
808 set_current_state(TASK_UNINTERRUPTIBLE);
809 add_wait_queue(wq, &wait);
810 spin_unlock(lock);
811 schedule();
812 remove_wait_queue(wq, &wait);
1da177e4
LT		 813 goto retry;
814}
815
2af7c653
SK		 816/**
817 * panic_nand_wait - [GENERIC] wait until the command is done
818 * @mtd: MTD device structure
819 * @chip: NAND chip structure
820 * @timeo: Timeout
821 *
822 * Wait for command done. This is a helper function for nand_wait used when
823 * we are in interrupt context. May happen when in panic and trying to write
824 * an oops trough mtdoops.
825 */
826static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
827 unsigned long timeo)
828{
829 int i;
830 for (i = 0; i < timeo; i++) {
831 if (chip->dev_ready) {
832 if (chip->dev_ready(mtd))
833 break;
834 } else {
835 if (chip->read_byte(mtd) & NAND_STATUS_READY)
836 break;
837 }
838 mdelay(1);
f8ac0414 839 }
2af7c653
SK		 840}
841
1da177e4
LT		 842/**
843 * nand_wait - [DEFAULT] wait until the command is done
844 * @mtd: MTD device structure
844d3b42 845 * @chip: NAND chip structure
1da177e4
LT		 846 *
847 * Wait for command done. This applies to erase and program only
61b03bd7 848 * Erase can take up to 400ms and program up to 20ms according to
1da177e4 849 * general NAND and SmartMedia specs
844d3b42 850 */
7bc3312b 851static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
1da177e4
LT		 852{
853
e0c7d767 854 unsigned long timeo = jiffies;
7bc3312b 855 int status, state = chip->state;
61b03bd7 856
1da177e4 857 if (state == FL_ERASING)
e0c7d767 858 timeo += (HZ * 400) / 1000;
1da177e4 859 else
e0c7d767 860 timeo += (HZ * 20) / 1000;
1da177e4 861
8fe833c1
RP		 862 led_trigger_event(nand_led_trigger, LED_FULL);
863
1da177e4
LT		 864 /* Apply this short delay always to ensure that we do wait tWB in
865 * any case on any machine. */
e0c7d767 866 ndelay(100);
1da177e4 867
ace4dfee
TG		 868 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
869 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
61b03bd7 870 else
ace4dfee 871 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
1da177e4 872
2af7c653
SK		 873 if (in_interrupt() || oops_in_progress)
874 panic_nand_wait(mtd, chip, timeo);
875 else {
876 while (time_before(jiffies, timeo)) {
877 if (chip->dev_ready) {
878 if (chip->dev_ready(mtd))
879 break;
880 } else {
881 if (chip->read_byte(mtd) & NAND_STATUS_READY)
882 break;
883 }
884 cond_resched();
1da177e4 885 }
1da177e4 886 }
8fe833c1
RP		 887 led_trigger_event(nand_led_trigger, LED_OFF);
888
ace4dfee 889 status = (int)chip->read_byte(mtd);
1da177e4
LT		 890 return status;
891}
892
7d70f334 893/**
b6d676db 894 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
7d70f334 895 *
b6d676db
RD		 896 * @mtd: mtd info
897 * @ofs: offset to start unlock from
898 * @len: length to unlock
899 * @invert: when = 0, unlock the range of blocks within the lower and
7d70f334 900 * upper boundary address
b6d676db 901 * when = 1, unlock the range of blocks outside the boundaries
7d70f334
VS		 902 * of the lower and upper boundary address
903 *
b6d676db 904 * return - unlock status
7d70f334
VS		 905 */
906static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
907 uint64_t len, int invert)
908{
909 int ret = 0;
910 int status, page;
911 struct nand_chip *chip = mtd->priv;
912
913 /* Submit address of first page to unlock */
914 page = ofs >> chip->page_shift;
915 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
916
917 /* Submit address of last page to unlock */
918 page = (ofs + len) >> chip->page_shift;
919 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
920 (page | invert) & chip->pagemask);
921
922 /* Call wait ready function */
923 status = chip->waitfunc(mtd, chip);
924 udelay(1000);
925 /* See if device thinks it succeeded */
926 if (status & 0x01) {
927 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
928 __func__, status);
929 ret = -EIO;
930 }
931
932 return ret;
933}
934
935/**
b6d676db 936 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
7d70f334 937 *
b6d676db
RD		 938 * @mtd: mtd info
939 * @ofs: offset to start unlock from
940 * @len: length to unlock
7d70f334 941 *
b6d676db 942 * return - unlock status
7d70f334
VS		 943 */
944int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
945{
946 int ret = 0;
947 int chipnr;
948 struct nand_chip *chip = mtd->priv;
949
950 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
951 __func__, (unsigned long long)ofs, len);
952
953 if (check_offs_len(mtd, ofs, len))
954 ret = -EINVAL;
955
956 /* Align to last block address if size addresses end of the device */
957 if (ofs + len == mtd->size)
958 len -= mtd->erasesize;
959
960 nand_get_device(chip, mtd, FL_UNLOCKING);
961
962 /* Shift to get chip number */
963 chipnr = ofs >> chip->chip_shift;
964
965 chip->select_chip(mtd, chipnr);
966
967 /* Check, if it is write protected */
968 if (nand_check_wp(mtd)) {
969 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
970 __func__);
971 ret = -EIO;
972 goto out;
973 }
974
975 ret = __nand_unlock(mtd, ofs, len, 0);
976
977out:
978 /* de-select the NAND device */
979 chip->select_chip(mtd, -1);
980
981 nand_release_device(mtd);
982
983 return ret;
984}
7351d3a5 985EXPORT_SYMBOL(nand_unlock);
7d70f334
VS		 986
987/**
b6d676db 988 * nand_lock - [REPLACEABLE] locks all blocks present in the device
7d70f334 989 *
b6d676db
RD		 990 * @mtd: mtd info
991 * @ofs: offset to start unlock from
992 * @len: length to unlock
7d70f334 993 *
b6d676db 994 * return - lock status
7d70f334 995 *
b6d676db
RD		 996 * This feature is not supported in many NAND parts. 'Micron' NAND parts
997 * do have this feature, but it allows only to lock all blocks, not for
7d70f334
VS		 998 * specified range for block.
999 *
1000 * Implementing 'lock' feature by making use of 'unlock', for now.
1001 */
1002int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1003{
1004 int ret = 0;
1005 int chipnr, status, page;
1006 struct nand_chip *chip = mtd->priv;
1007
1008 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
1009 __func__, (unsigned long long)ofs, len);
1010
1011 if (check_offs_len(mtd, ofs, len))
1012 ret = -EINVAL;
1013
1014 nand_get_device(chip, mtd, FL_LOCKING);
1015
1016 /* Shift to get chip number */
1017 chipnr = ofs >> chip->chip_shift;
1018
1019 chip->select_chip(mtd, chipnr);
1020
1021 /* Check, if it is write protected */
1022 if (nand_check_wp(mtd)) {
1023 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
1024 __func__);
1025 status = MTD_ERASE_FAILED;
1026 ret = -EIO;
1027 goto out;
1028 }
1029
1030 /* Submit address of first page to lock */
1031 page = ofs >> chip->page_shift;
1032 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1033
1034 /* Call wait ready function */
1035 status = chip->waitfunc(mtd, chip);
1036 udelay(1000);
1037 /* See if device thinks it succeeded */
1038 if (status & 0x01) {
1039 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1040 __func__, status);
1041 ret = -EIO;
1042 goto out;
1043 }
1044
1045 ret = __nand_unlock(mtd, ofs, len, 0x1);
1046
1047out:
1048 /* de-select the NAND device */
1049 chip->select_chip(mtd, -1);
1050
1051 nand_release_device(mtd);
1052
1053 return ret;
1054}
7351d3a5 1055EXPORT_SYMBOL(nand_lock);
7d70f334 1056
8593fbc6
TG		 1057/**
1058 * nand_read_page_raw - [Intern] read raw page data without ecc
1059 * @mtd: mtd info structure
1060 * @chip: nand chip info structure
1061 * @buf: buffer to store read data
58475fb9 1062 * @page: page number to read
52ff49df
DB		 1063 *
1064 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1065 */
1066static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1067 uint8_t *buf, int page)
8593fbc6
TG		 1068{
1069 chip->read_buf(mtd, buf, mtd->writesize);
1070 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1071 return 0;
1072}
1073
52ff49df
DB		 1074/**
1075 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1076 * @mtd: mtd info structure
1077 * @chip: nand chip info structure
1078 * @buf: buffer to store read data
58475fb9 1079 * @page: page number to read
52ff49df
DB		 1080 *
1081 * We need a special oob layout and handling even when OOB isn't used.
1082 */
7351d3a5
FF		 1083static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1084 struct nand_chip *chip,
1085 uint8_t *buf, int page)
52ff49df
DB		 1086{
1087 int eccsize = chip->ecc.size;
1088 int eccbytes = chip->ecc.bytes;
1089 uint8_t *oob = chip->oob_poi;
1090 int steps, size;
1091
1092 for (steps = chip->ecc.steps; steps > 0; steps--) {
1093 chip->read_buf(mtd, buf, eccsize);
1094 buf += eccsize;
1095
1096 if (chip->ecc.prepad) {
1097 chip->read_buf(mtd, oob, chip->ecc.prepad);
1098 oob += chip->ecc.prepad;
1099 }
1100
1101 chip->read_buf(mtd, oob, eccbytes);
1102 oob += eccbytes;
1103
1104 if (chip->ecc.postpad) {
1105 chip->read_buf(mtd, oob, chip->ecc.postpad);
1106 oob += chip->ecc.postpad;
1107 }
1108 }
1109
1110 size = mtd->oobsize - (oob - chip->oob_poi);
1111 if (size)
1112 chip->read_buf(mtd, oob, size);
1113
1114 return 0;
1115}
1116
1da177e4 1117/**
d29ebdbe 1118 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
f5bbdacc
TG		 1119 * @mtd: mtd info structure
1120 * @chip: nand chip info structure
1121 * @buf: buffer to store read data
58475fb9 1122 * @page: page number to read
068e3c0a 1123 */
f5bbdacc 1124static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1125 uint8_t *buf, int page)
1da177e4 1126{
f5bbdacc
TG		 1127 int i, eccsize = chip->ecc.size;
1128 int eccbytes = chip->ecc.bytes;
1129 int eccsteps = chip->ecc.steps;
1130 uint8_t *p = buf;
4bf63fcb
DW		 1131 uint8_t *ecc_calc = chip->buffers->ecccalc;
1132 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1133 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc 1134
46a8cf2d 1135 chip->ecc.read_page_raw(mtd, chip, buf, page);
f5bbdacc
TG		 1136
1137 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1138 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1139
1140 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1141 ecc_code[i] = chip->oob_poi[eccpos[i]];
f5bbdacc
TG		 1142
1143 eccsteps = chip->ecc.steps;
1144 p = buf;
1145
1146 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1147 int stat;
1148
1149 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1150 if (stat < 0)
f5bbdacc
TG		 1151 mtd->ecc_stats.failed++;
1152 else
1153 mtd->ecc_stats.corrected += stat;
1154 }
1155 return 0;
22c60f5f 1156}
1da177e4 1157
3d459559
AK		 1158/**
1159 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1160 * @mtd: mtd info structure
1161 * @chip: nand chip info structure
17c1d2be
AK		 1162 * @data_offs: offset of requested data within the page
1163 * @readlen: data length
1164 * @bufpoi: buffer to store read data
3d459559 1165 */
7351d3a5
FF		 1166static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1167 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
3d459559
AK		 1168{
1169 int start_step, end_step, num_steps;
1170 uint32_t *eccpos = chip->ecc.layout->eccpos;
1171 uint8_t *p;
1172 int data_col_addr, i, gaps = 0;
1173 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1174 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
7351d3a5 1175 int index = 0;
3d459559
AK		 1176
1177 /* Column address wihin the page aligned to ECC size (256bytes). */
1178 start_step = data_offs / chip->ecc.size;
1179 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1180 num_steps = end_step - start_step + 1;
1181
1182 /* Data size aligned to ECC ecc.size*/
1183 datafrag_len = num_steps * chip->ecc.size;
1184 eccfrag_len = num_steps * chip->ecc.bytes;
1185
1186 data_col_addr = start_step * chip->ecc.size;
1187 /* If we read not a page aligned data */
1188 if (data_col_addr != 0)
1189 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1190
1191 p = bufpoi + data_col_addr;
1192 chip->read_buf(mtd, p, datafrag_len);
1193
1194 /* Calculate ECC */
1195 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1196 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1197
1198 /* The performance is faster if to position offsets
1199 according to ecc.pos. Let make sure here that
1200 there are no gaps in ecc positions */
1201 for (i = 0; i < eccfrag_len - 1; i++) {
1202 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1203 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1204 gaps = 1;
1205 break;
1206 }
1207 }
1208 if (gaps) {
1209 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1210 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1211 } else {
1212 /* send the command to read the particular ecc bytes */
1213 /* take care about buswidth alignment in read_buf */
7351d3a5
FF		 1214 index = start_step * chip->ecc.bytes;
1215
1216 aligned_pos = eccpos[index] & ~(busw - 1);
3d459559 1217 aligned_len = eccfrag_len;
7351d3a5 1218 if (eccpos[index] & (busw - 1))
3d459559 1219 aligned_len++;
7351d3a5 1220 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
3d459559
AK		 1221 aligned_len++;
1222
7351d3a5
FF		 1223 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1224 mtd->writesize + aligned_pos, -1);
3d459559
AK		 1225 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1226 }
1227
1228 for (i = 0; i < eccfrag_len; i++)
7351d3a5 1229 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
3d459559
AK		 1230
1231 p = bufpoi + data_col_addr;
1232 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1233 int stat;
1234
7351d3a5
FF		 1235 stat = chip->ecc.correct(mtd, p,
1236 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
12c8eb98 1237 if (stat < 0)
3d459559
AK		 1238 mtd->ecc_stats.failed++;
1239 else
1240 mtd->ecc_stats.corrected += stat;
1241 }
1242 return 0;
1243}
1244
068e3c0a 1245/**
d29ebdbe 1246 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
f5bbdacc
TG		 1247 * @mtd: mtd info structure
1248 * @chip: nand chip info structure
1249 * @buf: buffer to store read data
58475fb9 1250 * @page: page number to read
068e3c0a 1251 *
f5bbdacc 1252 * Not for syndrome calculating ecc controllers which need a special oob layout
068e3c0a 1253 */
f5bbdacc 1254static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1255 uint8_t *buf, int page)
1da177e4 1256{
f5bbdacc
TG		 1257 int i, eccsize = chip->ecc.size;
1258 int eccbytes = chip->ecc.bytes;
1259 int eccsteps = chip->ecc.steps;
1260 uint8_t *p = buf;
4bf63fcb
DW		 1261 uint8_t *ecc_calc = chip->buffers->ecccalc;
1262 uint8_t *ecc_code = chip->buffers->ecccode;
8b099a39 1263 uint32_t *eccpos = chip->ecc.layout->eccpos;
f5bbdacc
TG		 1264
1265 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1266 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1267 chip->read_buf(mtd, p, eccsize);
1268 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1da177e4 1269 }
f75e5097 1270 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4 1271
f5bbdacc 1272 for (i = 0; i < chip->ecc.total; i++)
f75e5097 1273 ecc_code[i] = chip->oob_poi[eccpos[i]];
1da177e4 1274
f5bbdacc
TG		 1275 eccsteps = chip->ecc.steps;
1276 p = buf;
61b03bd7 1277
f5bbdacc
TG		 1278 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1279 int stat;
1da177e4 1280
f5bbdacc 1281 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
c32b8dcc 1282 if (stat < 0)
f5bbdacc
TG		 1283 mtd->ecc_stats.failed++;
1284 else
1285 mtd->ecc_stats.corrected += stat;
1286 }
1287 return 0;
1288}
1da177e4 1289
6e0cb135
SN		 1290/**
1291 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1292 * @mtd: mtd info structure
1293 * @chip: nand chip info structure
1294 * @buf: buffer to store read data
58475fb9 1295 * @page: page number to read
6e0cb135
SN		 1296 *
1297 * Hardware ECC for large page chips, require OOB to be read first.
1298 * For this ECC mode, the write_page method is re-used from ECC_HW.
1299 * These methods read/write ECC from the OOB area, unlike the
1300 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1301 * "infix ECC" scheme and reads/writes ECC from the data area, by
1302 * overwriting the NAND manufacturer bad block markings.
1303 */
1304static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1305 struct nand_chip *chip, uint8_t *buf, int page)
1306{
1307 int i, eccsize = chip->ecc.size;
1308 int eccbytes = chip->ecc.bytes;
1309 int eccsteps = chip->ecc.steps;
1310 uint8_t *p = buf;
1311 uint8_t *ecc_code = chip->buffers->ecccode;
1312 uint32_t *eccpos = chip->ecc.layout->eccpos;
1313 uint8_t *ecc_calc = chip->buffers->ecccalc;
1314
1315 /* Read the OOB area first */
1316 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1317 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1318 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1319
1320 for (i = 0; i < chip->ecc.total; i++)
1321 ecc_code[i] = chip->oob_poi[eccpos[i]];
1322
1323 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1324 int stat;
1325
1326 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1327 chip->read_buf(mtd, p, eccsize);
1328 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1329
1330 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1331 if (stat < 0)
1332 mtd->ecc_stats.failed++;
1333 else
1334 mtd->ecc_stats.corrected += stat;
1335 }
1336 return 0;
1337}
1338
f5bbdacc 1339/**
d29ebdbe 1340 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
f5bbdacc
TG		 1341 * @mtd: mtd info structure
1342 * @chip: nand chip info structure
1343 * @buf: buffer to store read data
58475fb9 1344 * @page: page number to read
f5bbdacc
TG		 1345 *
1346 * The hw generator calculates the error syndrome automatically. Therefor
f75e5097 1347 * we need a special oob layout and handling.
f5bbdacc
TG		 1348 */
1349static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
46a8cf2d 1350 uint8_t *buf, int page)
f5bbdacc
TG		 1351{
1352 int i, eccsize = chip->ecc.size;
1353 int eccbytes = chip->ecc.bytes;
1354 int eccsteps = chip->ecc.steps;
1355 uint8_t *p = buf;
f75e5097 1356 uint8_t *oob = chip->oob_poi;
1da177e4 1357
f5bbdacc
TG		 1358 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1359 int stat;
61b03bd7 1360
f5bbdacc
TG		 1361 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1362 chip->read_buf(mtd, p, eccsize);
1da177e4 1363
f5bbdacc
TG		 1364 if (chip->ecc.prepad) {
1365 chip->read_buf(mtd, oob, chip->ecc.prepad);
1366 oob += chip->ecc.prepad;
1367 }
1da177e4 1368
f5bbdacc
TG		 1369 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1370 chip->read_buf(mtd, oob, eccbytes);
1371 stat = chip->ecc.correct(mtd, p, oob, NULL);
61b03bd7 1372
c32b8dcc 1373 if (stat < 0)
f5bbdacc 1374 mtd->ecc_stats.failed++;
61b03bd7 1375 else
f5bbdacc 1376 mtd->ecc_stats.corrected += stat;
61b03bd7 1377
f5bbdacc 1378 oob += eccbytes;
1da177e4 1379
f5bbdacc
TG		 1380 if (chip->ecc.postpad) {
1381 chip->read_buf(mtd, oob, chip->ecc.postpad);
1382 oob += chip->ecc.postpad;
61b03bd7 1383 }
f5bbdacc 1384 }
1da177e4 1385
f5bbdacc 1386 /* Calculate remaining oob bytes */
7e4178f9 1387 i = mtd->oobsize - (oob - chip->oob_poi);
f5bbdacc
TG		 1388 if (i)
1389 chip->read_buf(mtd, oob, i);
61b03bd7 1390
f5bbdacc
TG		 1391 return 0;
1392}
1da177e4 1393
f5bbdacc 1394/**
8593fbc6
TG		 1395 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1396 * @chip: nand chip structure
844d3b42 1397 * @oob: oob destination address
8593fbc6 1398 * @ops: oob ops structure
7014568b 1399 * @len: size of oob to transfer
8593fbc6
TG		 1400 */
1401static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
7014568b 1402 struct mtd_oob_ops *ops, size_t len)
8593fbc6 1403{
f8ac0414 1404 switch (ops->mode) {
8593fbc6
TG		 1405
1406 case MTD_OOB_PLACE:
1407 case MTD_OOB_RAW:
1408 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1409 return oob + len;
1410
1411 case MTD_OOB_AUTO: {
1412 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 1413 uint32_t boffs = 0, roffs = ops->ooboffs;
1414 size_t bytes = 0;
8593fbc6 1415
f8ac0414 1416 for (; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 1417 /* Read request not from offset 0 ? */
1418 if (unlikely(roffs)) {
1419 if (roffs >= free->length) {
1420 roffs -= free->length;
1421 continue;
1422 }
1423 boffs = free->offset + roffs;
1424 bytes = min_t(size_t, len,
1425 (free->length - roffs));
1426 roffs = 0;
1427 } else {
1428 bytes = min_t(size_t, len, free->length);
1429 boffs = free->offset;
1430 }
1431 memcpy(oob, chip->oob_poi + boffs, bytes);
8593fbc6
TG		 1432 oob += bytes;
1433 }
1434 return oob;
1435 }
1436 default:
1437 BUG();
1438 }
1439 return NULL;
1440}
1441
1442/**
1443 * nand_do_read_ops - [Internal] Read data with ECC
f5bbdacc
TG		 1444 *
1445 * @mtd: MTD device structure
1446 * @from: offset to read from
844d3b42 1447 * @ops: oob ops structure
f5bbdacc
TG		 1448 *
1449 * Internal function. Called with chip held.
1450 */
8593fbc6
TG		 1451static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1452 struct mtd_oob_ops *ops)
f5bbdacc
TG		 1453{
1454 int chipnr, page, realpage, col, bytes, aligned;
1455 struct nand_chip *chip = mtd->priv;
1456 struct mtd_ecc_stats stats;
1457 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1458 int sndcmd = 1;
1459 int ret = 0;
8593fbc6 1460 uint32_t readlen = ops->len;
7014568b 1461 uint32_t oobreadlen = ops->ooblen;
9aca334e
ML		 1462 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1463 mtd->oobavail : mtd->oobsize;
1464
8593fbc6 1465 uint8_t *bufpoi, *oob, *buf;
1da177e4 1466
f5bbdacc 1467 stats = mtd->ecc_stats;
1da177e4 1468
f5bbdacc
TG		 1469 chipnr = (int)(from >> chip->chip_shift);
1470 chip->select_chip(mtd, chipnr);
61b03bd7 1471
f5bbdacc
TG		 1472 realpage = (int)(from >> chip->page_shift);
1473 page = realpage & chip->pagemask;
1da177e4 1474
f5bbdacc 1475 col = (int)(from & (mtd->writesize - 1));
61b03bd7 1476
8593fbc6
TG		 1477 buf = ops->datbuf;
1478 oob = ops->oobbuf;
1479
f8ac0414 1480 while (1) {
f5bbdacc
TG		 1481 bytes = min(mtd->writesize - col, readlen);
1482 aligned = (bytes == mtd->writesize);
61b03bd7 1483
f5bbdacc 1484 /* Is the current page in the buffer ? */
8593fbc6 1485 if (realpage != chip->pagebuf || oob) {
4bf63fcb 1486 bufpoi = aligned ? buf : chip->buffers->databuf;
61b03bd7 1487
f5bbdacc
TG		 1488 if (likely(sndcmd)) {
1489 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1490 sndcmd = 0;
1da177e4 1491 }
1da177e4 1492
f5bbdacc 1493 /* Now read the page into the buffer */
956e944c 1494 if (unlikely(ops->mode == MTD_OOB_RAW))
46a8cf2d
SN		 1495 ret = chip->ecc.read_page_raw(mtd, chip,
1496 bufpoi, page);
3d459559 1497 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
7351d3a5
FF		 1498 ret = chip->ecc.read_subpage(mtd, chip,
1499 col, bytes, bufpoi);
956e944c 1500 else
46a8cf2d
SN		 1501 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1502 page);
f5bbdacc 1503 if (ret < 0)
1da177e4 1504 break;
f5bbdacc
TG		 1505
1506 /* Transfer not aligned data */
1507 if (!aligned) {
c1194c79
AB		 1508 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1509 !(mtd->ecc_stats.failed - stats.failed))
3d459559 1510 chip->pagebuf = realpage;
4bf63fcb 1511 memcpy(buf, chip->buffers->databuf + col, bytes);
f5bbdacc
TG		 1512 }
1513
8593fbc6
TG		 1514 buf += bytes;
1515
1516 if (unlikely(oob)) {
9aca334e 1517
b64d39d8
ML		 1518 int toread = min(oobreadlen, max_oobsize);
1519
1520 if (toread) {
1521 oob = nand_transfer_oob(chip,
1522 oob, ops, toread);
1523 oobreadlen -= toread;
1524 }
8593fbc6
TG		 1525 }
1526
f5bbdacc
TG		 1527 if (!(chip->options & NAND_NO_READRDY)) {
1528 /*
1529 * Apply delay or wait for ready/busy pin. Do
1530 * this before the AUTOINCR check, so no
1531 * problems arise if a chip which does auto
1532 * increment is marked as NOAUTOINCR by the
1533 * board driver.
1534 */
1535 if (!chip->dev_ready)
1536 udelay(chip->chip_delay);
1537 else
1538 nand_wait_ready(mtd);
1da177e4 1539 }
8593fbc6 1540 } else {
4bf63fcb 1541 memcpy(buf, chip->buffers->databuf + col, bytes);
8593fbc6
TG		 1542 buf += bytes;
1543 }
1da177e4 1544
f5bbdacc 1545 readlen -= bytes;
61b03bd7 1546
f5bbdacc 1547 if (!readlen)
61b03bd7 1548 break;
1da177e4
LT		 1549
1550 /* For subsequent reads align to page boundary. */
1551 col = 0;
1552 /* Increment page address */
1553 realpage++;
1554
ace4dfee 1555 page = realpage & chip->pagemask;
1da177e4
LT		 1556 /* Check, if we cross a chip boundary */
1557 if (!page) {
1558 chipnr++;
ace4dfee
TG		 1559 chip->select_chip(mtd, -1);
1560 chip->select_chip(mtd, chipnr);
1da177e4 1561 }
f5bbdacc 1562
61b03bd7
TG		 1563 /* Check, if the chip supports auto page increment
1564 * or if we have hit a block boundary.
e0c7d767 1565 */
f5bbdacc 1566 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
61b03bd7 1567 sndcmd = 1;
1da177e4
LT		 1568 }
1569
8593fbc6 1570 ops->retlen = ops->len - (size_t) readlen;
7014568b
VW		 1571 if (oob)
1572 ops->oobretlen = ops->ooblen - oobreadlen;
1da177e4 1573
f5bbdacc
TG		 1574 if (ret)
1575 return ret;
1576
9a1fcdfd
TG		 1577 if (mtd->ecc_stats.failed - stats.failed)
1578 return -EBADMSG;
1579
1580 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
f5bbdacc
TG		 1581}
1582
1583/**
1584 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1585 * @mtd: MTD device structure
1586 * @from: offset to read from
1587 * @len: number of bytes to read
1588 * @retlen: pointer to variable to store the number of read bytes
1589 * @buf: the databuffer to put data
1590 *
1591 * Get hold of the chip and call nand_do_read
1592 */
1593static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1594 size_t *retlen, uint8_t *buf)
1595{
8593fbc6 1596 struct nand_chip *chip = mtd->priv;
f5bbdacc
TG		 1597 int ret;
1598
f5bbdacc
TG		 1599 /* Do not allow reads past end of device */
1600 if ((from + len) > mtd->size)
1601 return -EINVAL;
1602 if (!len)
1603 return 0;
1604
8593fbc6 1605 nand_get_device(chip, mtd, FL_READING);
f5bbdacc 1606
8593fbc6
TG		 1607 chip->ops.len = len;
1608 chip->ops.datbuf = buf;
1609 chip->ops.oobbuf = NULL;
1610
1611 ret = nand_do_read_ops(mtd, from, &chip->ops);
f5bbdacc 1612
7fd5aecc
RP		 1613 *retlen = chip->ops.retlen;
1614
f5bbdacc
TG		 1615 nand_release_device(mtd);
1616
1617 return ret;
1da177e4
LT		 1618}
1619
7bc3312b
TG		 1620/**
1621 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1622 * @mtd: mtd info structure
1623 * @chip: nand chip info structure
1624 * @page: page number to read
1625 * @sndcmd: flag whether to issue read command or not
1626 */
1627static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1628 int page, int sndcmd)
1629{
1630 if (sndcmd) {
1631 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1632 sndcmd = 0;
1633 }
1634 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1635 return sndcmd;
1636}
1637
1638/**
1639 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1640 * with syndromes
1641 * @mtd: mtd info structure
1642 * @chip: nand chip info structure
1643 * @page: page number to read
1644 * @sndcmd: flag whether to issue read command or not
1645 */
1646static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1647 int page, int sndcmd)
1648{
1649 uint8_t *buf = chip->oob_poi;
1650 int length = mtd->oobsize;
1651 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1652 int eccsize = chip->ecc.size;
1653 uint8_t *bufpoi = buf;
1654 int i, toread, sndrnd = 0, pos;
1655
1656 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1657 for (i = 0; i < chip->ecc.steps; i++) {
1658 if (sndrnd) {
1659 pos = eccsize + i * (eccsize + chunk);
1660 if (mtd->writesize > 512)
1661 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1662 else
1663 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1664 } else
1665 sndrnd = 1;
1666 toread = min_t(int, length, chunk);
1667 chip->read_buf(mtd, bufpoi, toread);
1668 bufpoi += toread;
1669 length -= toread;
1670 }
1671 if (length > 0)
1672 chip->read_buf(mtd, bufpoi, length);
1673
1674 return 1;
1675}
1676
1677/**
1678 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1679 * @mtd: mtd info structure
1680 * @chip: nand chip info structure
1681 * @page: page number to write
1682 */
1683static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1684 int page)
1685{
1686 int status = 0;
1687 const uint8_t *buf = chip->oob_poi;
1688 int length = mtd->oobsize;
1689
1690 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1691 chip->write_buf(mtd, buf, length);
1692 /* Send command to program the OOB data */
1693 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1694
1695 status = chip->waitfunc(mtd, chip);
1696
0d420f9d 1697 return status & NAND_STATUS_FAIL ? -EIO : 0;
7bc3312b
TG		 1698}
1699
1700/**
1701 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1702 * with syndrome - only for large page flash !
1703 * @mtd: mtd info structure
1704 * @chip: nand chip info structure
1705 * @page: page number to write
1706 */
1707static int nand_write_oob_syndrome(struct mtd_info *mtd,
1708 struct nand_chip *chip, int page)
1709{
1710 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1711 int eccsize = chip->ecc.size, length = mtd->oobsize;
1712 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1713 const uint8_t *bufpoi = chip->oob_poi;
1714
1715 /*
1716 * data-ecc-data-ecc ... ecc-oob
1717 * or
1718 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1719 */
1720 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1721 pos = steps * (eccsize + chunk);
1722 steps = 0;
1723 } else
8b0036ee 1724 pos = eccsize;
7bc3312b
TG		 1725
1726 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1727 for (i = 0; i < steps; i++) {
1728 if (sndcmd) {
1729 if (mtd->writesize <= 512) {
1730 uint32_t fill = 0xFFFFFFFF;
1731
1732 len = eccsize;
1733 while (len > 0) {
1734 int num = min_t(int, len, 4);
1735 chip->write_buf(mtd, (uint8_t *)&fill,
1736 num);
1737 len -= num;
1738 }
1739 } else {
1740 pos = eccsize + i * (eccsize + chunk);
1741 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1742 }
1743 } else
1744 sndcmd = 1;
1745 len = min_t(int, length, chunk);
1746 chip->write_buf(mtd, bufpoi, len);
1747 bufpoi += len;
1748 length -= len;
1749 }
1750 if (length > 0)
1751 chip->write_buf(mtd, bufpoi, length);
1752
1753 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1754 status = chip->waitfunc(mtd, chip);
1755
1756 return status & NAND_STATUS_FAIL ? -EIO : 0;
1757}
1758
1da177e4 1759/**
8593fbc6 1760 * nand_do_read_oob - [Intern] NAND read out-of-band
1da177e4
LT		 1761 * @mtd: MTD device structure
1762 * @from: offset to read from
8593fbc6 1763 * @ops: oob operations description structure
1da177e4
LT		 1764 *
1765 * NAND read out-of-band data from the spare area
1766 */
8593fbc6
TG		 1767static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1768 struct mtd_oob_ops *ops)
1da177e4 1769{
7bc3312b 1770 int page, realpage, chipnr, sndcmd = 1;
ace4dfee 1771 struct nand_chip *chip = mtd->priv;
7314e9e7 1772 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
7014568b
VW		 1773 int readlen = ops->ooblen;
1774 int len;
7bc3312b 1775 uint8_t *buf = ops->oobbuf;
61b03bd7 1776
20d8e248 1777 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1778 __func__, (unsigned long long)from, readlen);
1da177e4 1779
03736155 1780 if (ops->mode == MTD_OOB_AUTO)
7014568b 1781 len = chip->ecc.layout->oobavail;
03736155
AH		 1782 else
1783 len = mtd->oobsize;
1784
1785 if (unlikely(ops->ooboffs >= len)) {
20d8e248 1786 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1787 "outside oob\n", __func__);
03736155
AH		 1788 return -EINVAL;
1789 }
1790
1791 /* Do not allow reads past end of device */
1792 if (unlikely(from >= mtd->size ||
1793 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1794 (from >> chip->page_shift)) * len)) {
20d8e248 1795 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1796 "of device\n", __func__);
03736155
AH		 1797 return -EINVAL;
1798 }
7014568b 1799
7314e9e7 1800 chipnr = (int)(from >> chip->chip_shift);
ace4dfee 1801 chip->select_chip(mtd, chipnr);
1da177e4 1802
7314e9e7
TG		 1803 /* Shift to get page */
1804 realpage = (int)(from >> chip->page_shift);
1805 page = realpage & chip->pagemask;
1da177e4 1806
f8ac0414 1807 while (1) {
7bc3312b 1808 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
7014568b
VW		 1809
1810 len = min(len, readlen);
1811 buf = nand_transfer_oob(chip, buf, ops, len);
8593fbc6 1812
7314e9e7
TG		 1813 if (!(chip->options & NAND_NO_READRDY)) {
1814 /*
1815 * Apply delay or wait for ready/busy pin. Do this
1816 * before the AUTOINCR check, so no problems arise if a
1817 * chip which does auto increment is marked as
1818 * NOAUTOINCR by the board driver.
19870da7 1819 */
ace4dfee
TG		 1820 if (!chip->dev_ready)
1821 udelay(chip->chip_delay);
19870da7
TG		 1822 else
1823 nand_wait_ready(mtd);
7314e9e7 1824 }
19870da7 1825
7014568b 1826 readlen -= len;
0d420f9d
SZ		 1827 if (!readlen)
1828 break;
1829
7314e9e7
TG		 1830 /* Increment page address */
1831 realpage++;
1832
1833 page = realpage & chip->pagemask;
1834 /* Check, if we cross a chip boundary */
1835 if (!page) {
1836 chipnr++;
1837 chip->select_chip(mtd, -1);
1838 chip->select_chip(mtd, chipnr);
1da177e4 1839 }
7314e9e7
TG		 1840
1841 /* Check, if the chip supports auto page increment
1842 * or if we have hit a block boundary.
1843 */
1844 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1845 sndcmd = 1;
1da177e4
LT		 1846 }
1847
7014568b 1848 ops->oobretlen = ops->ooblen;
1da177e4
LT		 1849 return 0;
1850}
1851
1852/**
8593fbc6 1853 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1da177e4 1854 * @mtd: MTD device structure
1da177e4 1855 * @from: offset to read from
8593fbc6 1856 * @ops: oob operation description structure
1da177e4 1857 *
8593fbc6 1858 * NAND read data and/or out-of-band data
1da177e4 1859 */
8593fbc6
TG		 1860static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1861 struct mtd_oob_ops *ops)
1da177e4 1862{
ace4dfee 1863 struct nand_chip *chip = mtd->priv;
8593fbc6
TG		 1864 int ret = -ENOTSUPP;
1865
1866 ops->retlen = 0;
1da177e4
LT		 1867
1868 /* Do not allow reads past end of device */
7014568b 1869 if (ops->datbuf && (from + ops->len) > mtd->size) {
20d8e248 1870 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1871 "beyond end of device\n", __func__);
1da177e4
LT		 1872 return -EINVAL;
1873 }
1874
ace4dfee 1875 nand_get_device(chip, mtd, FL_READING);
1da177e4 1876
f8ac0414 1877 switch (ops->mode) {
8593fbc6
TG		 1878 case MTD_OOB_PLACE:
1879 case MTD_OOB_AUTO:
8593fbc6 1880 case MTD_OOB_RAW:
8593fbc6 1881 break;
1da177e4 1882
8593fbc6
TG		 1883 default:
1884 goto out;
1885 }
1da177e4 1886
8593fbc6
TG		 1887 if (!ops->datbuf)
1888 ret = nand_do_read_oob(mtd, from, ops);
1889 else
1890 ret = nand_do_read_ops(mtd, from, ops);
61b03bd7 1891
7351d3a5 1892out:
8593fbc6
TG		 1893 nand_release_device(mtd);
1894 return ret;
1895}
61b03bd7 1896
1da177e4 1897
8593fbc6
TG		 1898/**
1899 * nand_write_page_raw - [Intern] raw page write function
1900 * @mtd: mtd info structure
1901 * @chip: nand chip info structure
1902 * @buf: data buffer
52ff49df
DB		 1903 *
1904 * Not for syndrome calculating ecc controllers, which use a special oob layout
8593fbc6
TG		 1905 */
1906static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1907 const uint8_t *buf)
1908{
1909 chip->write_buf(mtd, buf, mtd->writesize);
1910 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1da177e4
LT		 1911}
1912
52ff49df
DB		 1913/**
1914 * nand_write_page_raw_syndrome - [Intern] raw page write function
1915 * @mtd: mtd info structure
1916 * @chip: nand chip info structure
1917 * @buf: data buffer
1918 *
1919 * We need a special oob layout and handling even when ECC isn't checked.
1920 */
7351d3a5
FF		 1921static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1922 struct nand_chip *chip,
1923 const uint8_t *buf)
52ff49df
DB		 1924{
1925 int eccsize = chip->ecc.size;
1926 int eccbytes = chip->ecc.bytes;
1927 uint8_t *oob = chip->oob_poi;
1928 int steps, size;
1929
1930 for (steps = chip->ecc.steps; steps > 0; steps--) {
1931 chip->write_buf(mtd, buf, eccsize);
1932 buf += eccsize;
1933
1934 if (chip->ecc.prepad) {
1935 chip->write_buf(mtd, oob, chip->ecc.prepad);
1936 oob += chip->ecc.prepad;
1937 }
1938
1939 chip->read_buf(mtd, oob, eccbytes);
1940 oob += eccbytes;
1941
1942 if (chip->ecc.postpad) {
1943 chip->write_buf(mtd, oob, chip->ecc.postpad);
1944 oob += chip->ecc.postpad;
1945 }
1946 }
1947
1948 size = mtd->oobsize - (oob - chip->oob_poi);
1949 if (size)
1950 chip->write_buf(mtd, oob, size);
1951}
9223a456 1952/**
d29ebdbe 1953 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
f75e5097
TG		 1954 * @mtd: mtd info structure
1955 * @chip: nand chip info structure
1956 * @buf: data buffer
9223a456 1957 */
f75e5097
TG		 1958static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1959 const uint8_t *buf)
9223a456 1960{
f75e5097
TG		 1961 int i, eccsize = chip->ecc.size;
1962 int eccbytes = chip->ecc.bytes;
1963 int eccsteps = chip->ecc.steps;
4bf63fcb 1964 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1965 const uint8_t *p = buf;
8b099a39 1966 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1967
8593fbc6
TG		 1968 /* Software ecc calculation */
1969 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1970 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456 1971
8593fbc6
TG		 1972 for (i = 0; i < chip->ecc.total; i++)
1973 chip->oob_poi[eccpos[i]] = ecc_calc[i];
9223a456 1974
90424de8 1975 chip->ecc.write_page_raw(mtd, chip, buf);
f75e5097 1976}
9223a456 1977
f75e5097 1978/**
d29ebdbe 1979 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
f75e5097
TG		 1980 * @mtd: mtd info structure
1981 * @chip: nand chip info structure
1982 * @buf: data buffer
1983 */
1984static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1985 const uint8_t *buf)
1986{
1987 int i, eccsize = chip->ecc.size;
1988 int eccbytes = chip->ecc.bytes;
1989 int eccsteps = chip->ecc.steps;
4bf63fcb 1990 uint8_t *ecc_calc = chip->buffers->ecccalc;
f75e5097 1991 const uint8_t *p = buf;
8b099a39 1992 uint32_t *eccpos = chip->ecc.layout->eccpos;
9223a456 1993
f75e5097
TG		 1994 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1995 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
29da9cea 1996 chip->write_buf(mtd, p, eccsize);
f75e5097 1997 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
9223a456
TG		 1998 }
1999
f75e5097
TG		 2000 for (i = 0; i < chip->ecc.total; i++)
2001 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2002
2003 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
9223a456
TG		 2004}
2005
61b03bd7 2006/**
d29ebdbe 2007 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
f75e5097
TG		 2008 * @mtd: mtd info structure
2009 * @chip: nand chip info structure
2010 * @buf: data buffer
1da177e4 2011 *
f75e5097
TG		 2012 * The hw generator calculates the error syndrome automatically. Therefor
2013 * we need a special oob layout and handling.
2014 */
2015static void nand_write_page_syndrome(struct mtd_info *mtd,
2016 struct nand_chip *chip, const uint8_t *buf)
1da177e4 2017{
f75e5097
TG		 2018 int i, eccsize = chip->ecc.size;
2019 int eccbytes = chip->ecc.bytes;
2020 int eccsteps = chip->ecc.steps;
2021 const uint8_t *p = buf;
2022 uint8_t *oob = chip->oob_poi;
1da177e4 2023
f75e5097 2024 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1da177e4 2025
f75e5097
TG		 2026 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2027 chip->write_buf(mtd, p, eccsize);
61b03bd7 2028
f75e5097
TG		 2029 if (chip->ecc.prepad) {
2030 chip->write_buf(mtd, oob, chip->ecc.prepad);
2031 oob += chip->ecc.prepad;
2032 }
2033
2034 chip->ecc.calculate(mtd, p, oob);
2035 chip->write_buf(mtd, oob, eccbytes);
2036 oob += eccbytes;
2037
2038 if (chip->ecc.postpad) {
2039 chip->write_buf(mtd, oob, chip->ecc.postpad);
2040 oob += chip->ecc.postpad;
1da177e4 2041 }
1da177e4 2042 }
f75e5097
TG		 2043
2044 /* Calculate remaining oob bytes */
7e4178f9 2045 i = mtd->oobsize - (oob - chip->oob_poi);
f75e5097
TG		 2046 if (i)
2047 chip->write_buf(mtd, oob, i);
2048}
2049
2050/**
956e944c 2051 * nand_write_page - [REPLACEABLE] write one page
f75e5097
TG		 2052 * @mtd: MTD device structure
2053 * @chip: NAND chip descriptor
2054 * @buf: the data to write
2055 * @page: page number to write
2056 * @cached: cached programming
efbfe96c 2057 * @raw: use _raw version of write_page
f75e5097
TG		 2058 */
2059static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
956e944c 2060 const uint8_t *buf, int page, int cached, int raw)
f75e5097
TG		 2061{
2062 int status;
2063
2064 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2065
956e944c
DW		 2066 if (unlikely(raw))
2067 chip->ecc.write_page_raw(mtd, chip, buf);
2068 else
2069 chip->ecc.write_page(mtd, chip, buf);
f75e5097
TG		 2070
2071 /*
2072 * Cached progamming disabled for now, Not sure if its worth the
2073 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2074 */
2075 cached = 0;
2076
2077 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2078
2079 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
7bc3312b 2080 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2081 /*
2082 * See if operation failed and additional status checks are
2083 * available
2084 */
2085 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2086 status = chip->errstat(mtd, chip, FL_WRITING, status,
2087 page);
2088
2089 if (status & NAND_STATUS_FAIL)
2090 return -EIO;
2091 } else {
2092 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
7bc3312b 2093 status = chip->waitfunc(mtd, chip);
f75e5097
TG		 2094 }
2095
2096#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2097 /* Send command to read back the data */
2098 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2099
2100 if (chip->verify_buf(mtd, buf, mtd->writesize))
2101 return -EIO;
2102#endif
2103 return 0;
1da177e4
LT		 2104}
2105
8593fbc6
TG		 2106/**
2107 * nand_fill_oob - [Internal] Transfer client buffer to oob
2108 * @chip: nand chip structure
2109 * @oob: oob data buffer
b6d676db 2110 * @len: oob data write length
8593fbc6
TG		 2111 * @ops: oob ops structure
2112 */
782ce79a
ML		 2113static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
2114 struct mtd_oob_ops *ops)
8593fbc6 2115{
f8ac0414 2116 switch (ops->mode) {
8593fbc6
TG		 2117
2118 case MTD_OOB_PLACE:
2119 case MTD_OOB_RAW:
2120 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2121 return oob + len;
2122
2123 case MTD_OOB_AUTO: {
2124 struct nand_oobfree *free = chip->ecc.layout->oobfree;
7bc3312b
TG		 2125 uint32_t boffs = 0, woffs = ops->ooboffs;
2126 size_t bytes = 0;
8593fbc6 2127
f8ac0414 2128 for (; free->length && len; free++, len -= bytes) {
7bc3312b
TG		 2129 /* Write request not from offset 0 ? */
2130 if (unlikely(woffs)) {
2131 if (woffs >= free->length) {
2132 woffs -= free->length;
2133 continue;
2134 }
2135 boffs = free->offset + woffs;
2136 bytes = min_t(size_t, len,
2137 (free->length - woffs));
2138 woffs = 0;
2139 } else {
2140 bytes = min_t(size_t, len, free->length);
2141 boffs = free->offset;
2142 }
8b0036ee 2143 memcpy(chip->oob_poi + boffs, oob, bytes);
8593fbc6
TG		 2144 oob += bytes;
2145 }
2146 return oob;
2147 }
2148 default:
2149 BUG();
2150 }
2151 return NULL;
2152}
2153
f8ac0414 2154#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
1da177e4
LT		 2155
2156/**
8593fbc6 2157 * nand_do_write_ops - [Internal] NAND write with ECC
1da177e4
LT		 2158 * @mtd: MTD device structure
2159 * @to: offset to write to
8593fbc6 2160 * @ops: oob operations description structure
1da177e4
LT		 2161 *
2162 * NAND write with ECC
2163 */
8593fbc6
TG		 2164static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2165 struct mtd_oob_ops *ops)
1da177e4 2166{
29072b96 2167 int chipnr, realpage, page, blockmask, column;
ace4dfee 2168 struct nand_chip *chip = mtd->priv;
8593fbc6 2169 uint32_t writelen = ops->len;
782ce79a
ML		 2170
2171 uint32_t oobwritelen = ops->ooblen;
2172 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2173 mtd->oobavail : mtd->oobsize;
2174
8593fbc6
TG		 2175 uint8_t *oob = ops->oobbuf;
2176 uint8_t *buf = ops->datbuf;
29072b96 2177 int ret, subpage;
1da177e4 2178
8593fbc6 2179 ops->retlen = 0;
29072b96
TG		 2180 if (!writelen)
2181 return 0;
1da177e4 2182
61b03bd7 2183 /* reject writes, which are not page aligned */
8593fbc6 2184 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
20d8e248 2185 printk(KERN_NOTICE "%s: Attempt to write not "
2186 "page aligned data\n", __func__);
1da177e4
LT		 2187 return -EINVAL;
2188 }
2189
29072b96
TG		 2190 column = to & (mtd->writesize - 1);
2191 subpage = column || (writelen & (mtd->writesize - 1));
2192
2193 if (subpage && oob)
2194 return -EINVAL;
1da177e4 2195
6a930961
TG		 2196 chipnr = (int)(to >> chip->chip_shift);
2197 chip->select_chip(mtd, chipnr);
2198
1da177e4
LT		 2199 /* Check, if it is write protected */
2200 if (nand_check_wp(mtd))
8593fbc6 2201 return -EIO;
1da177e4 2202
f75e5097
TG		 2203 realpage = (int)(to >> chip->page_shift);
2204 page = realpage & chip->pagemask;
2205 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2206
2207 /* Invalidate the page cache, when we write to the cached page */
2208 if (to <= (chip->pagebuf << chip->page_shift) &&
8593fbc6 2209 (chip->pagebuf << chip->page_shift) < (to + ops->len))
ace4dfee 2210 chip->pagebuf = -1;
61b03bd7 2211
7dcdcbef
DW		 2212 /* If we're not given explicit OOB data, let it be 0xFF */
2213 if (likely(!oob))
2214 memset(chip->oob_poi, 0xff, mtd->oobsize);
61b03bd7 2215
782ce79a 2216 /* Don't allow multipage oob writes with offset */
cdcf12b2 2217 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
782ce79a
ML		 2218 return -EINVAL;
2219
f8ac0414 2220 while (1) {
29072b96 2221 int bytes = mtd->writesize;
f75e5097 2222 int cached = writelen > bytes && page != blockmask;
29072b96
TG		 2223 uint8_t *wbuf = buf;
2224
2225 /* Partial page write ? */
2226 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2227 cached = 0;
2228 bytes = min_t(int, bytes - column, (int) writelen);
2229 chip->pagebuf = -1;
2230 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2231 memcpy(&chip->buffers->databuf[column], buf, bytes);
2232 wbuf = chip->buffers->databuf;
2233 }
1da177e4 2234
782ce79a
ML		 2235 if (unlikely(oob)) {
2236 size_t len = min(oobwritelen, oobmaxlen);
2237 oob = nand_fill_oob(chip, oob, len, ops);
2238 oobwritelen -= len;
2239 }
8593fbc6 2240
29072b96 2241 ret = chip->write_page(mtd, chip, wbuf, page, cached,
956e944c 2242 (ops->mode == MTD_OOB_RAW));
f75e5097
TG		 2243 if (ret)
2244 break;
2245
2246 writelen -= bytes;
2247 if (!writelen)
2248 break;
2249
29072b96 2250 column = 0;
f75e5097
TG		 2251 buf += bytes;
2252 realpage++;
2253
2254 page = realpage & chip->pagemask;
2255 /* Check, if we cross a chip boundary */
2256 if (!page) {
2257 chipnr++;
2258 chip->select_chip(mtd, -1);
2259 chip->select_chip(mtd, chipnr);
1da177e4
LT		 2260 }
2261 }
8593fbc6 2262
8593fbc6 2263 ops->retlen = ops->len - writelen;
7014568b
VW		 2264 if (unlikely(oob))
2265 ops->oobretlen = ops->ooblen;
1da177e4
LT		 2266 return ret;
2267}
2268
2af7c653
SK		 2269/**
2270 * panic_nand_write - [MTD Interface] NAND write with ECC
2271 * @mtd: MTD device structure
2272 * @to: offset to write to
2273 * @len: number of bytes to write
2274 * @retlen: pointer to variable to store the number of written bytes
2275 * @buf: the data to write
2276 *
2277 * NAND write with ECC. Used when performing writes in interrupt context, this
2278 * may for example be called by mtdoops when writing an oops while in panic.
2279 */
2280static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2281 size_t *retlen, const uint8_t *buf)
2282{
2283 struct nand_chip *chip = mtd->priv;
2284 int ret;
2285
2286 /* Do not allow reads past end of device */
2287 if ((to + len) > mtd->size)
2288 return -EINVAL;
2289 if (!len)
2290 return 0;
2291
2292 /* Wait for the device to get ready. */
2293 panic_nand_wait(mtd, chip, 400);
2294
2295 /* Grab the device. */
2296 panic_nand_get_device(chip, mtd, FL_WRITING);
2297
2298 chip->ops.len = len;
2299 chip->ops.datbuf = (uint8_t *)buf;
2300 chip->ops.oobbuf = NULL;
2301
2302 ret = nand_do_write_ops(mtd, to, &chip->ops);
2303
2304 *retlen = chip->ops.retlen;
2305 return ret;
2306}
2307
f75e5097 2308/**
8593fbc6 2309 * nand_write - [MTD Interface] NAND write with ECC
f75e5097 2310 * @mtd: MTD device structure
f75e5097
TG		 2311 * @to: offset to write to
2312 * @len: number of bytes to write
8593fbc6
TG		 2313 * @retlen: pointer to variable to store the number of written bytes
2314 * @buf: the data to write
f75e5097 2315 *
8593fbc6 2316 * NAND write with ECC
f75e5097 2317 */
8593fbc6
TG		 2318static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2319 size_t *retlen, const uint8_t *buf)
f75e5097
TG		 2320{
2321 struct nand_chip *chip = mtd->priv;
f75e5097
TG		 2322 int ret;
2323
8593fbc6
TG		 2324 /* Do not allow reads past end of device */
2325 if ((to + len) > mtd->size)
f75e5097 2326 return -EINVAL;
8593fbc6
TG		 2327 if (!len)
2328 return 0;
f75e5097 2329
7bc3312b 2330 nand_get_device(chip, mtd, FL_WRITING);
f75e5097 2331
8593fbc6
TG		 2332 chip->ops.len = len;
2333 chip->ops.datbuf = (uint8_t *)buf;
2334 chip->ops.oobbuf = NULL;
f75e5097 2335
8593fbc6 2336 ret = nand_do_write_ops(mtd, to, &chip->ops);
f75e5097 2337
7fd5aecc
RP		 2338 *retlen = chip->ops.retlen;
2339
f75e5097 2340 nand_release_device(mtd);
8593fbc6 2341
8593fbc6 2342 return ret;
f75e5097 2343}
7314e9e7 2344
1da177e4 2345/**
8593fbc6 2346 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1da177e4
LT		 2347 * @mtd: MTD device structure
2348 * @to: offset to write to
8593fbc6 2349 * @ops: oob operation description structure
1da177e4
LT		 2350 *
2351 * NAND write out-of-band
2352 */
8593fbc6
TG		 2353static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2354 struct mtd_oob_ops *ops)
1da177e4 2355{
03736155 2356 int chipnr, page, status, len;
ace4dfee 2357 struct nand_chip *chip = mtd->priv;
1da177e4 2358
20d8e248 2359 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2360 __func__, (unsigned int)to, (int)ops->ooblen);
1da177e4 2361
03736155
AH		 2362 if (ops->mode == MTD_OOB_AUTO)
2363 len = chip->ecc.layout->oobavail;
2364 else
2365 len = mtd->oobsize;
2366
1da177e4 2367 /* Do not allow write past end of page */
03736155 2368 if ((ops->ooboffs + ops->ooblen) > len) {
20d8e248 2369 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2370 "past end of page\n", __func__);
1da177e4
LT		 2371 return -EINVAL;
2372 }
2373
03736155 2374 if (unlikely(ops->ooboffs >= len)) {
20d8e248 2375 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2376 "write outside oob\n", __func__);
03736155
AH		 2377 return -EINVAL;
2378 }
2379
2380 /* Do not allow reads past end of device */
2381 if (unlikely(to >= mtd->size ||
2382 ops->ooboffs + ops->ooblen >
2383 ((mtd->size >> chip->page_shift) -
2384 (to >> chip->page_shift)) * len)) {
20d8e248 2385 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2386 "end of device\n", __func__);
03736155
AH		 2387 return -EINVAL;
2388 }
2389
7314e9e7 2390 chipnr = (int)(to >> chip->chip_shift);
ace4dfee 2391 chip->select_chip(mtd, chipnr);
1da177e4 2392
7314e9e7
TG		 2393 /* Shift to get page */
2394 page = (int)(to >> chip->page_shift);
2395
2396 /*
2397 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2398 * of my DiskOnChip 2000 test units) will clear the whole data page too
2399 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2400 * it in the doc2000 driver in August 1999. dwmw2.
2401 */
ace4dfee 2402 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4
LT		 2403
2404 /* Check, if it is write protected */
2405 if (nand_check_wp(mtd))
8593fbc6 2406 return -EROFS;
61b03bd7 2407
1da177e4 2408 /* Invalidate the page cache, if we write to the cached page */
ace4dfee
TG		 2409 if (page == chip->pagebuf)
2410 chip->pagebuf = -1;
1da177e4 2411
7bc3312b 2412 memset(chip->oob_poi, 0xff, mtd->oobsize);
782ce79a 2413 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
7bc3312b
TG		 2414 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2415 memset(chip->oob_poi, 0xff, mtd->oobsize);
1da177e4 2416
7bc3312b
TG		 2417 if (status)
2418 return status;
1da177e4 2419
7014568b 2420 ops->oobretlen = ops->ooblen;
1da177e4 2421
7bc3312b 2422 return 0;
8593fbc6
TG		 2423}
2424
2425/**
2426 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2427 * @mtd: MTD device structure
844d3b42 2428 * @to: offset to write to
8593fbc6
TG		 2429 * @ops: oob operation description structure
2430 */
2431static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2432 struct mtd_oob_ops *ops)
2433{
8593fbc6
TG		 2434 struct nand_chip *chip = mtd->priv;
2435 int ret = -ENOTSUPP;
2436
2437 ops->retlen = 0;
2438
2439 /* Do not allow writes past end of device */
7014568b 2440 if (ops->datbuf && (to + ops->len) > mtd->size) {
20d8e248 2441 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2442 "end of device\n", __func__);
8593fbc6
TG		 2443 return -EINVAL;
2444 }
2445
7bc3312b 2446 nand_get_device(chip, mtd, FL_WRITING);
8593fbc6 2447
f8ac0414 2448 switch (ops->mode) {
8593fbc6
TG		 2449 case MTD_OOB_PLACE:
2450 case MTD_OOB_AUTO:
8593fbc6 2451 case MTD_OOB_RAW:
8593fbc6
TG		 2452 break;
2453
2454 default:
2455 goto out;
2456 }
2457
2458 if (!ops->datbuf)
2459 ret = nand_do_write_oob(mtd, to, ops);
2460 else
2461 ret = nand_do_write_ops(mtd, to, ops);
2462
7351d3a5 2463out:
1da177e4 2464 nand_release_device(mtd);
1da177e4
LT		 2465 return ret;
2466}
2467
1da177e4
LT		 2468/**
2469 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2470 * @mtd: MTD device structure
2471 * @page: the page address of the block which will be erased
2472 *
2473 * Standard erase command for NAND chips
2474 */
e0c7d767 2475static void single_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2476{
ace4dfee 2477 struct nand_chip *chip = mtd->priv;
1da177e4 2478 /* Send commands to erase a block */
ace4dfee
TG		 2479 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2480 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2481}
2482
2483/**
2484 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2485 * @mtd: MTD device structure
2486 * @page: the page address of the block which will be erased
2487 *
2488 * AND multi block erase command function
2489 * Erase 4 consecutive blocks
2490 */
e0c7d767 2491static void multi_erase_cmd(struct mtd_info *mtd, int page)
1da177e4 2492{
ace4dfee 2493 struct nand_chip *chip = mtd->priv;
1da177e4 2494 /* Send commands to erase a block */
ace4dfee
TG		 2495 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2496 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2497 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2498 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2499 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1da177e4
LT		 2500}
2501
2502/**
2503 * nand_erase - [MTD Interface] erase block(s)
2504 * @mtd: MTD device structure
2505 * @instr: erase instruction
2506 *
2507 * Erase one ore more blocks
2508 */
e0c7d767 2509static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1da177e4 2510{
e0c7d767 2511 return nand_erase_nand(mtd, instr, 0);
1da177e4 2512}
61b03bd7 2513
30f464b7 2514#define BBT_PAGE_MASK 0xffffff3f
1da177e4 2515/**
ace4dfee 2516 * nand_erase_nand - [Internal] erase block(s)
1da177e4
LT		 2517 * @mtd: MTD device structure
2518 * @instr: erase instruction
2519 * @allowbbt: allow erasing the bbt area
2520 *
2521 * Erase one ore more blocks
2522 */
ace4dfee
TG		 2523int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2524 int allowbbt)
1da177e4 2525{
69423d99 2526 int page, status, pages_per_block, ret, chipnr;
ace4dfee 2527 struct nand_chip *chip = mtd->priv;
f8ac0414 2528 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
ace4dfee 2529 unsigned int bbt_masked_page = 0xffffffff;
69423d99 2530 loff_t len;
1da177e4 2531
20d8e248 2532 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2533 __func__, (unsigned long long)instr->addr,
2534 (unsigned long long)instr->len);
1da177e4 2535
6fe5a6ac 2536 if (check_offs_len(mtd, instr->addr, instr->len))
1da177e4 2537 return -EINVAL;
1da177e4 2538
bb0eb217 2539 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
1da177e4
LT		 2540
2541 /* Grab the lock and see if the device is available */
ace4dfee 2542 nand_get_device(chip, mtd, FL_ERASING);
1da177e4
LT		 2543
2544 /* Shift to get first page */
ace4dfee
TG		 2545 page = (int)(instr->addr >> chip->page_shift);
2546 chipnr = (int)(instr->addr >> chip->chip_shift);
1da177e4
LT		 2547
2548 /* Calculate pages in each block */
ace4dfee 2549 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1da177e4
LT		 2550
2551 /* Select the NAND device */
ace4dfee 2552 chip->select_chip(mtd, chipnr);
1da177e4 2553
1da177e4
LT		 2554 /* Check, if it is write protected */
2555 if (nand_check_wp(mtd)) {
20d8e248 2556 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2557 __func__);
1da177e4
LT		 2558 instr->state = MTD_ERASE_FAILED;
2559 goto erase_exit;
2560 }
2561
ace4dfee
TG		 2562 /*
2563 * If BBT requires refresh, set the BBT page mask to see if the BBT
2564 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2565 * can not be matched. This is also done when the bbt is actually
2566 * erased to avoid recusrsive updates
2567 */
2568 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2569 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
30f464b7 2570
1da177e4
LT		 2571 /* Loop through the pages */
2572 len = instr->len;
2573
2574 instr->state = MTD_ERASING;
2575
2576 while (len) {
ace4dfee
TG		 2577 /*
2578 * heck if we have a bad block, we do not erase bad blocks !
2579 */
2580 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2581 chip->page_shift, 0, allowbbt)) {
20d8e248 2582 printk(KERN_WARNING "%s: attempt to erase a bad block "
2583 "at page 0x%08x\n", __func__, page);
1da177e4
LT		 2584 instr->state = MTD_ERASE_FAILED;
2585 goto erase_exit;
2586 }
61b03bd7 2587
ace4dfee
TG		 2588 /*
2589 * Invalidate the page cache, if we erase the block which
2590 * contains the current cached page
2591 */
2592 if (page <= chip->pagebuf && chip->pagebuf <
2593 (page + pages_per_block))
2594 chip->pagebuf = -1;
1da177e4 2595
ace4dfee 2596 chip->erase_cmd(mtd, page & chip->pagemask);
61b03bd7 2597
7bc3312b 2598 status = chip->waitfunc(mtd, chip);
1da177e4 2599
ace4dfee
TG		 2600 /*
2601 * See if operation failed and additional status checks are
2602 * available
2603 */
2604 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2605 status = chip->errstat(mtd, chip, FL_ERASING,
2606 status, page);
068e3c0a 2607
1da177e4 2608 /* See if block erase succeeded */
a4ab4c5d 2609 if (status & NAND_STATUS_FAIL) {
20d8e248 2610 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2611 "page 0x%08x\n", __func__, page);
1da177e4 2612 instr->state = MTD_ERASE_FAILED;
69423d99
AH		 2613 instr->fail_addr =
2614 ((loff_t)page << chip->page_shift);
1da177e4
LT		 2615 goto erase_exit;
2616 }
30f464b7 2617
ace4dfee
TG		 2618 /*
2619 * If BBT requires refresh, set the BBT rewrite flag to the
2620 * page being erased
2621 */
2622 if (bbt_masked_page != 0xffffffff &&
2623 (page & BBT_PAGE_MASK) == bbt_masked_page)
69423d99
AH		 2624 rewrite_bbt[chipnr] =
2625 ((loff_t)page << chip->page_shift);
61b03bd7 2626
1da177e4 2627 /* Increment page address and decrement length */
ace4dfee 2628 len -= (1 << chip->phys_erase_shift);
1da177e4
LT		 2629 page += pages_per_block;
2630
2631 /* Check, if we cross a chip boundary */
ace4dfee 2632 if (len && !(page & chip->pagemask)) {
1da177e4 2633 chipnr++;
ace4dfee
TG		 2634 chip->select_chip(mtd, -1);
2635 chip->select_chip(mtd, chipnr);
30f464b7 2636
ace4dfee
TG		 2637 /*
2638 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2639 * page mask to see if this BBT should be rewritten
2640 */
2641 if (bbt_masked_page != 0xffffffff &&
2642 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2643 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2644 BBT_PAGE_MASK;
1da177e4
LT		 2645 }
2646 }
2647 instr->state = MTD_ERASE_DONE;
2648
7351d3a5 2649erase_exit:
1da177e4
LT		 2650
2651 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1da177e4
LT		 2652
2653 /* Deselect and wake up anyone waiting on the device */
2654 nand_release_device(mtd);
2655
49defc01
DW		 2656 /* Do call back function */
2657 if (!ret)
2658 mtd_erase_callback(instr);
2659
ace4dfee
TG		 2660 /*
2661 * If BBT requires refresh and erase was successful, rewrite any
2662 * selected bad block tables
2663 */
2664 if (bbt_masked_page == 0xffffffff || ret)
2665 return ret;
2666
2667 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2668 if (!rewrite_bbt[chipnr])
2669 continue;
2670 /* update the BBT for chip */
20d8e248 2671 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2672 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2673 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
ace4dfee 2674 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
30f464b7
DM		 2675 }
2676
1da177e4
LT		 2677 /* Return more or less happy */
2678 return ret;
2679}
2680
2681/**
2682 * nand_sync - [MTD Interface] sync
2683 * @mtd: MTD device structure
2684 *
2685 * Sync is actually a wait for chip ready function
2686 */
e0c7d767 2687static void nand_sync(struct mtd_info *mtd)
1da177e4 2688{
ace4dfee 2689 struct nand_chip *chip = mtd->priv;
1da177e4 2690
20d8e248 2691 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
1da177e4
LT		 2692
2693 /* Grab the lock and see if the device is available */
ace4dfee 2694 nand_get_device(chip, mtd, FL_SYNCING);
1da177e4 2695 /* Release it and go back */
e0c7d767 2696 nand_release_device(mtd);
1da177e4
LT		 2697}
2698
1da177e4 2699/**
ace4dfee 2700 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
1da177e4 2701 * @mtd: MTD device structure
844d3b42 2702 * @offs: offset relative to mtd start
1da177e4 2703 */
ace4dfee 2704static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1da177e4
LT		 2705{
2706 /* Check for invalid offset */
ace4dfee 2707 if (offs > mtd->size)
1da177e4 2708 return -EINVAL;
61b03bd7 2709
ace4dfee 2710 return nand_block_checkbad(mtd, offs, 1, 0);
1da177e4
LT		 2711}
2712
2713/**
ace4dfee 2714 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1da177e4
LT		 2715 * @mtd: MTD device structure
2716 * @ofs: offset relative to mtd start
2717 */
e0c7d767 2718static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1da177e4 2719{
ace4dfee 2720 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 2721 int ret;
2722
f8ac0414
FF		 2723 ret = nand_block_isbad(mtd, ofs);
2724 if (ret) {
e0c7d767 2725 /* If it was bad already, return success and do nothing. */
1da177e4
LT		 2726 if (ret > 0)
2727 return 0;
e0c7d767
DW		 2728 return ret;
2729 }
1da177e4 2730
ace4dfee 2731 return chip->block_markbad(mtd, ofs);
1da177e4
LT		 2732}
2733
962034f4
VW		 2734/**
2735 * nand_suspend - [MTD Interface] Suspend the NAND flash
2736 * @mtd: MTD device structure
2737 */
2738static int nand_suspend(struct mtd_info *mtd)
2739{
ace4dfee 2740 struct nand_chip *chip = mtd->priv;
962034f4 2741
ace4dfee 2742 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
962034f4
VW		 2743}
2744
2745/**
2746 * nand_resume - [MTD Interface] Resume the NAND flash
2747 * @mtd: MTD device structure
2748 */
2749static void nand_resume(struct mtd_info *mtd)
2750{
ace4dfee 2751 struct nand_chip *chip = mtd->priv;
962034f4 2752
ace4dfee 2753 if (chip->state == FL_PM_SUSPENDED)
962034f4
VW		 2754 nand_release_device(mtd);
2755 else
20d8e248 2756 printk(KERN_ERR "%s called for a chip which is not "
2757 "in suspended state\n", __func__);
962034f4
VW		 2758}
2759
7aa65bfd
TG		 2760/*
2761 * Set default functions
2762 */
ace4dfee 2763static void nand_set_defaults(struct nand_chip *chip, int busw)
7aa65bfd 2764{
1da177e4 2765 /* check for proper chip_delay setup, set 20us if not */
ace4dfee
TG		 2766 if (!chip->chip_delay)
2767 chip->chip_delay = 20;
1da177e4
LT		 2768
2769 /* check, if a user supplied command function given */
ace4dfee
TG		 2770 if (chip->cmdfunc == NULL)
2771 chip->cmdfunc = nand_command;
1da177e4
LT		 2772
2773 /* check, if a user supplied wait function given */
ace4dfee
TG		 2774 if (chip->waitfunc == NULL)
2775 chip->waitfunc = nand_wait;
2776
2777 if (!chip->select_chip)
2778 chip->select_chip = nand_select_chip;
2779 if (!chip->read_byte)
2780 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2781 if (!chip->read_word)
2782 chip->read_word = nand_read_word;
2783 if (!chip->block_bad)
2784 chip->block_bad = nand_block_bad;
2785 if (!chip->block_markbad)
2786 chip->block_markbad = nand_default_block_markbad;
2787 if (!chip->write_buf)
2788 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2789 if (!chip->read_buf)
2790 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2791 if (!chip->verify_buf)
2792 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2793 if (!chip->scan_bbt)
2794 chip->scan_bbt = nand_default_bbt;
f75e5097
TG		 2795
2796 if (!chip->controller) {
2797 chip->controller = &chip->hwcontrol;
2798 spin_lock_init(&chip->controller->lock);
2799 init_waitqueue_head(&chip->controller->wq);
2800 }
2801
7aa65bfd
TG		 2802}
2803
d1e1f4e4
FF		 2804/*
2805 * sanitize ONFI strings so we can safely print them
2806 */
2807static void sanitize_string(uint8_t *s, size_t len)
2808{
2809 ssize_t i;
2810
2811 /* null terminate */
2812 s[len - 1] = 0;
2813
2814 /* remove non printable chars */
2815 for (i = 0; i < len - 1; i++) {
2816 if (s[i] < ' ' || s[i] > 127)
2817 s[i] = '?';
2818 }
2819
2820 /* remove trailing spaces */
2821 strim(s);
2822}
2823
2824static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2825{
2826 int i;
2827 while (len--) {
2828 crc ^= *p++ << 8;
2829 for (i = 0; i < 8; i++)
2830 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2831 }
2832
2833 return crc;
2834}
2835
6fb277ba
FF		 2836/*
2837 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2838 */
2839static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2840 int busw)
2841{
2842 struct nand_onfi_params *p = &chip->onfi_params;
2843 int i;
2844 int val;
2845
2846 /* try ONFI for unknow chip or LP */
2847 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2848 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2849 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2850 return 0;
2851
2852 printk(KERN_INFO "ONFI flash detected\n");
2853 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2854 for (i = 0; i < 3; i++) {
2855 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2856 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2857 le16_to_cpu(p->crc)) {
2858 printk(KERN_INFO "ONFI param page %d valid\n", i);
2859 break;
2860 }
2861 }
2862
2863 if (i == 3)
2864 return 0;
2865
2866 /* check version */
2867 val = le16_to_cpu(p->revision);
2868 if (val == 1 || val > (1 << 4)) {
2869 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2870 __func__, val);
2871 return 0;
2872 }
2873
2874 if (val & (1 << 4))
2875 chip->onfi_version = 22;
2876 else if (val & (1 << 3))
2877 chip->onfi_version = 21;
2878 else if (val & (1 << 2))
2879 chip->onfi_version = 20;
2880 else
2881 chip->onfi_version = 10;
2882
2883 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2884 sanitize_string(p->model, sizeof(p->model));
2885 if (!mtd->name)
2886 mtd->name = p->model;
2887 mtd->writesize = le32_to_cpu(p->byte_per_page);
2888 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2889 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2890 chip->chipsize = le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2891 busw = 0;
2892 if (le16_to_cpu(p->features) & 1)
2893 busw = NAND_BUSWIDTH_16;
2894
2895 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2896 chip->options |= (NAND_NO_READRDY |
2897 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2898
2899 return 1;
2900}
2901
7aa65bfd 2902/*
ace4dfee 2903 * Get the flash and manufacturer id and lookup if the type is supported
7aa65bfd
TG		 2904 */
2905static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
ace4dfee 2906 struct nand_chip *chip,
7351d3a5
FF		 2907 int busw,
2908 int *maf_id, int *dev_id,
5e81e88a 2909 struct nand_flash_dev *type)
7aa65bfd 2910{
d1e1f4e4 2911 int i, maf_idx;
426c457a 2912 u8 id_data[8];
6fb277ba 2913 int ret;
1da177e4
LT		 2914
2915 /* Select the device */
ace4dfee 2916 chip->select_chip(mtd, 0);
1da177e4 2917
ef89a880
KB		 2918 /*
2919 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2920 * after power-up
2921 */
2922 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2923
1da177e4 2924 /* Send the command for reading device ID */
ace4dfee 2925 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4
LT		 2926
2927 /* Read manufacturer and device IDs */
ace4dfee 2928 *maf_id = chip->read_byte(mtd);
d1e1f4e4 2929 *dev_id = chip->read_byte(mtd);
1da177e4 2930
ed8165c7
BD		 2931 /* Try again to make sure, as some systems the bus-hold or other
2932 * interface concerns can cause random data which looks like a
2933 * possibly credible NAND flash to appear. If the two results do
2934 * not match, ignore the device completely.
2935 */
2936
2937 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2938
d1e1f4e4 2939 for (i = 0; i < 2; i++)
426c457a 2940 id_data[i] = chip->read_byte(mtd);
ed8165c7 2941
d1e1f4e4 2942 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
ed8165c7
BD		 2943 printk(KERN_INFO "%s: second ID read did not match "
2944 "%02x,%02x against %02x,%02x\n", __func__,
d1e1f4e4 2945 *maf_id, *dev_id, id_data[0], id_data[1]);
ed8165c7
BD		 2946 return ERR_PTR(-ENODEV);
2947 }
2948
7aa65bfd 2949 if (!type)
5e81e88a
DW		 2950 type = nand_flash_ids;
2951
2952 for (; type->name != NULL; type++)
d1e1f4e4 2953 if (*dev_id == type->id)
f8ac0414 2954 break;
5e81e88a 2955
d1e1f4e4
FF		 2956 chip->onfi_version = 0;
2957 if (!type->name || !type->pagesize) {
6fb277ba
FF		 2958 /* Check is chip is ONFI compliant */
2959 ret = nand_flash_detect_onfi(mtd, chip, busw);
2960 if (ret)
2961 goto ident_done;
d1e1f4e4
FF		 2962 }
2963
2964 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2965
2966 /* Read entire ID string */
2967
2968 for (i = 0; i < 8; i++)
2969 id_data[i] = chip->read_byte(mtd);
2970
5e81e88a 2971 if (!type->name)
7aa65bfd
TG		 2972 return ERR_PTR(-ENODEV);
2973
ba0251fe
TG		 2974 if (!mtd->name)
2975 mtd->name = type->name;
2976
69423d99 2977 chip->chipsize = (uint64_t)type->chipsize << 20;
7aa65bfd 2978
12a40a57
HS		 2979 if (!type->pagesize && chip->init_size) {
2980 /* set the pagesize, oobsize, erasesize by the driver*/
2981 busw = chip->init_size(mtd, chip, id_data);
2982 } else if (!type->pagesize) {
7aa65bfd 2983 int extid;
29072b96 2984 /* The 3rd id byte holds MLC / multichip data */
426c457a 2985 chip->cellinfo = id_data[2];
7aa65bfd 2986 /* The 4th id byte is the important one */
426c457a 2987 extid = id_data[3];
61b03bd7 2988
426c457a
KC		 2989 /*
2990 * Field definitions are in the following datasheets:
2991 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
34c5bf6c 2992 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
426c457a
KC		 2993 *
2994 * Check for wraparound + Samsung ID + nonzero 6th byte
2995 * to decide what to do.
2996 */
2997 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2998 id_data[0] == NAND_MFR_SAMSUNG &&
cfe3fdad 2999 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
426c457a
KC		 3000 id_data[5] != 0x00) {
3001 /* Calc pagesize */
3002 mtd->writesize = 2048 << (extid & 0x03);
3003 extid >>= 2;
3004 /* Calc oobsize */
34c5bf6c
BN		 3005 switch (extid & 0x03) {
3006 case 1:
3007 mtd->oobsize = 128;
3008 break;
3009 case 2:
3010 mtd->oobsize = 218;
3011 break;
3012 case 3:
3013 mtd->oobsize = 400;
3014 break;
3015 default:
3016 mtd->oobsize = 436;
3017 break;
3018 }
426c457a
KC		 3019 extid >>= 2;
3020 /* Calc blocksize */
3021 mtd->erasesize = (128 * 1024) <<
3022 (((extid >> 1) & 0x04) | (extid & 0x03));
3023 busw = 0;
3024 } else {
3025 /* Calc pagesize */
3026 mtd->writesize = 1024 << (extid & 0x03);
3027 extid >>= 2;
3028 /* Calc oobsize */
3029 mtd->oobsize = (8 << (extid & 0x01)) *
3030 (mtd->writesize >> 9);
3031 extid >>= 2;
3032 /* Calc blocksize. Blocksize is multiples of 64KiB */
3033 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3034 extid >>= 2;
3035 /* Get buswidth information */
3036 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3037 }
7aa65bfd
TG		 3038 } else {
3039 /*
ace4dfee 3040 * Old devices have chip data hardcoded in the device id table
7aa65bfd 3041 */
ba0251fe
TG		 3042 mtd->erasesize = type->erasesize;
3043 mtd->writesize = type->pagesize;
4cbb9b80 3044 mtd->oobsize = mtd->writesize / 32;
ba0251fe 3045 busw = type->options & NAND_BUSWIDTH_16;
2173bae8
BN		 3046
3047 /*
3048 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3049 * some Spansion chips have erasesize that conflicts with size
3050 * listed in nand_ids table
3051 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3052 */
3053 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3054 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3055 id_data[7] == 0x00 && mtd->writesize == 512) {
3056 mtd->erasesize = 128 * 1024;
3057 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3058 }
7aa65bfd 3059 }
d1e1f4e4
FF		 3060 /* Get chip options, preserve non chip based options */
3061 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3062 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3063
3064 /* Check if chip is a not a samsung device. Do not clear the
3065 * options for chips which are not having an extended id.
3066 */
3067 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3068 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3069ident_done:
3070
3071 /*
3072 * Set chip as a default. Board drivers can override it, if necessary
3073 */
3074 chip->options |= NAND_NO_AUTOINCR;
1da177e4 3075
7aa65bfd 3076 /* Try to identify manufacturer */
9a909867 3077 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
7aa65bfd
TG		 3078 if (nand_manuf_ids[maf_idx].id == *maf_id)
3079 break;
3080 }
0ea4a755 3081
7aa65bfd
TG		 3082 /*
3083 * Check, if buswidth is correct. Hardware drivers should set
ace4dfee 3084 * chip correct !
7aa65bfd 3085 */
ace4dfee 3086 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
7aa65bfd
TG		 3087 printk(KERN_INFO "NAND device: Manufacturer ID:"
3088 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
d1e1f4e4 3089 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
7aa65bfd 3090 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
ace4dfee 3091 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
7aa65bfd
TG		 3092 busw ? 16 : 8);
3093 return ERR_PTR(-EINVAL);
3094 }
61b03bd7 3095
7aa65bfd 3096 /* Calculate the address shift from the page size */
ace4dfee 3097 chip->page_shift = ffs(mtd->writesize) - 1;
7aa65bfd 3098 /* Convert chipsize to number of pages per chip -1. */
ace4dfee 3099 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
61b03bd7 3100
ace4dfee 3101 chip->bbt_erase_shift = chip->phys_erase_shift =
7aa65bfd 3102 ffs(mtd->erasesize) - 1;
69423d99
AH		 3103 if (chip->chipsize & 0xffffffff)
3104 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
7351d3a5
FF		 3105 else {
3106 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3107 chip->chip_shift += 32 - 1;
3108 }
1da177e4 3109
7aa65bfd 3110 /* Set the bad block position */
065a1ed8 3111 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
c7b28e25 3112 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
065a1ed8
BN		 3113 else
3114 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
61b03bd7 3115
b60b08b0
KC		 3116 /*
3117 * Bad block marker is stored in the last page of each block
c7b28e25
BN		 3118 * on Samsung and Hynix MLC devices; stored in first two pages
3119 * of each block on Micron devices with 2KiB pages and on
13ed7aed
BN		 3120 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3121 * only the first page.
b60b08b0
KC		 3122 */
3123 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3124 (*maf_id == NAND_MFR_SAMSUNG ||
3125 *maf_id == NAND_MFR_HYNIX))
30fe8115 3126 chip->options |= NAND_BBT_SCANLASTPAGE;
c7b28e25
BN		 3127 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3128 (*maf_id == NAND_MFR_SAMSUNG ||
3129 *maf_id == NAND_MFR_HYNIX ||
13ed7aed 3130 *maf_id == NAND_MFR_TOSHIBA ||
c7b28e25
BN		 3131 *maf_id == NAND_MFR_AMD)) ||
3132 (mtd->writesize == 2048 &&
3133 *maf_id == NAND_MFR_MICRON))
3134 chip->options |= NAND_BBT_SCAN2NDPAGE;
3135
58373ff0
BN		 3136 /*
3137 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
3138 */
3139 if (!(busw & NAND_BUSWIDTH_16) &&
3140 *maf_id == NAND_MFR_STMICRO &&
3141 mtd->writesize == 2048) {
3142 chip->options |= NAND_BBT_SCANBYTE1AND6;
3143 chip->badblockpos = 0;
3144 }
b60b08b0 3145
7aa65bfd 3146 /* Check for AND chips with 4 page planes */
ace4dfee
TG		 3147 if (chip->options & NAND_4PAGE_ARRAY)
3148 chip->erase_cmd = multi_erase_cmd;
7aa65bfd 3149 else
ace4dfee 3150 chip->erase_cmd = single_erase_cmd;
7aa65bfd
TG		 3151
3152 /* Do not replace user supplied command function ! */
ace4dfee
TG		 3153 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3154 chip->cmdfunc = nand_command_lp;
7aa65bfd 3155
d1e1f4e4 3156 /* TODO onfi flash name */
7aa65bfd 3157 printk(KERN_INFO "NAND device: Manufacturer ID:"
d1e1f4e4
FF		 3158 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3159 nand_manuf_ids[maf_idx].name,
f8ac0414 3160 chip->onfi_version ? type->name : chip->onfi_params.model);
7aa65bfd
TG		 3161
3162 return type;
3163}
3164
7aa65bfd 3165/**
3b85c321
DW		 3166 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3167 * @mtd: MTD device structure
3168 * @maxchips: Number of chips to scan for
5e81e88a 3169 * @table: Alternative NAND ID table
7aa65bfd 3170 *
3b85c321
DW		 3171 * This is the first phase of the normal nand_scan() function. It
3172 * reads the flash ID and sets up MTD fields accordingly.
7aa65bfd 3173 *
3b85c321 3174 * The mtd->owner field must be set to the module of the caller.
7aa65bfd 3175 */
5e81e88a
DW		 3176int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3177 struct nand_flash_dev *table)
7aa65bfd 3178{
d1e1f4e4 3179 int i, busw, nand_maf_id, nand_dev_id;
ace4dfee 3180 struct nand_chip *chip = mtd->priv;
7aa65bfd
TG		 3181 struct nand_flash_dev *type;
3182
7aa65bfd 3183 /* Get buswidth to select the correct functions */
ace4dfee 3184 busw = chip->options & NAND_BUSWIDTH_16;
7aa65bfd 3185 /* Set the default functions */
ace4dfee 3186 nand_set_defaults(chip, busw);
7aa65bfd
TG		 3187
3188 /* Read the flash type */
7351d3a5
FF		 3189 type = nand_get_flash_type(mtd, chip, busw,
3190 &nand_maf_id, &nand_dev_id, table);
7aa65bfd
TG		 3191
3192 if (IS_ERR(type)) {
b1c6e6db
BD		 3193 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3194 printk(KERN_WARNING "No NAND device found.\n");
ace4dfee 3195 chip->select_chip(mtd, -1);
7aa65bfd 3196 return PTR_ERR(type);
1da177e4
LT		 3197 }
3198
7aa65bfd 3199 /* Check for a chip array */
e0c7d767 3200 for (i = 1; i < maxchips; i++) {
ace4dfee 3201 chip->select_chip(mtd, i);
ef89a880
KB		 3202 /* See comment in nand_get_flash_type for reset */
3203 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1da177e4 3204 /* Send the command for reading device ID */
ace4dfee 3205 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1da177e4 3206 /* Read manufacturer and device IDs */
ace4dfee 3207 if (nand_maf_id != chip->read_byte(mtd) ||
d1e1f4e4 3208 nand_dev_id != chip->read_byte(mtd))
1da177e4
LT		 3209 break;
3210 }
3211 if (i > 1)
3212 printk(KERN_INFO "%d NAND chips detected\n", i);
61b03bd7 3213
1da177e4 3214 /* Store the number of chips and calc total size for mtd */
ace4dfee
TG		 3215 chip->numchips = i;
3216 mtd->size = i * chip->chipsize;
7aa65bfd 3217
3b85c321
DW		 3218 return 0;
3219}
7351d3a5 3220EXPORT_SYMBOL(nand_scan_ident);
3b85c321
DW		 3221
3222
3223/**
3224 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3225 * @mtd: MTD device structure
3b85c321
DW		 3226 *
3227 * This is the second phase of the normal nand_scan() function. It
3228 * fills out all the uninitialized function pointers with the defaults
3229 * and scans for a bad block table if appropriate.
3230 */
3231int nand_scan_tail(struct mtd_info *mtd)
3232{
3233 int i;
3234 struct nand_chip *chip = mtd->priv;
3235
4bf63fcb
DW		 3236 if (!(chip->options & NAND_OWN_BUFFERS))
3237 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3238 if (!chip->buffers)
3239 return -ENOMEM;
3240
7dcdcbef 3241 /* Set the internal oob buffer location, just after the page data */
784f4d5e 3242 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
1da177e4 3243
7aa65bfd
TG		 3244 /*
3245 * If no default placement scheme is given, select an appropriate one
3246 */
5bd34c09 3247 if (!chip->ecc.layout) {
61b03bd7 3248 switch (mtd->oobsize) {
1da177e4 3249 case 8:
5bd34c09 3250 chip->ecc.layout = &nand_oob_8;
1da177e4
LT		 3251 break;
3252 case 16:
5bd34c09 3253 chip->ecc.layout = &nand_oob_16;
1da177e4
LT		 3254 break;
3255 case 64:
5bd34c09 3256 chip->ecc.layout = &nand_oob_64;
1da177e4 3257 break;
81ec5364
TG		 3258 case 128:
3259 chip->ecc.layout = &nand_oob_128;
3260 break;
1da177e4 3261 default:
7aa65bfd
TG		 3262 printk(KERN_WARNING "No oob scheme defined for "
3263 "oobsize %d\n", mtd->oobsize);
1da177e4
LT		 3264 BUG();
3265 }
3266 }
61b03bd7 3267
956e944c
DW		 3268 if (!chip->write_page)
3269 chip->write_page = nand_write_page;
3270
61b03bd7 3271 /*
7aa65bfd
TG		 3272 * check ECC mode, default to software if 3byte/512byte hardware ECC is
3273 * selected and we have 256 byte pagesize fallback to software ECC
e0c7d767 3274 */
956e944c 3275
ace4dfee 3276 switch (chip->ecc.mode) {
6e0cb135
SN		 3277 case NAND_ECC_HW_OOB_FIRST:
3278 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3279 if (!chip->ecc.calculate || !chip->ecc.correct ||
3280 !chip->ecc.hwctl) {
3281 printk(KERN_WARNING "No ECC functions supplied; "
3282 "Hardware ECC not possible\n");
3283 BUG();
3284 }
3285 if (!chip->ecc.read_page)
3286 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3287
6dfc6d25 3288 case NAND_ECC_HW:
f5bbdacc
TG		 3289 /* Use standard hwecc read page function ? */
3290 if (!chip->ecc.read_page)
3291 chip->ecc.read_page = nand_read_page_hwecc;
f75e5097
TG		 3292 if (!chip->ecc.write_page)
3293 chip->ecc.write_page = nand_write_page_hwecc;
52ff49df
DB		 3294 if (!chip->ecc.read_page_raw)
3295 chip->ecc.read_page_raw = nand_read_page_raw;
3296 if (!chip->ecc.write_page_raw)
3297 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3298 if (!chip->ecc.read_oob)
3299 chip->ecc.read_oob = nand_read_oob_std;
3300 if (!chip->ecc.write_oob)
3301 chip->ecc.write_oob = nand_write_oob_std;
f5bbdacc 3302
6dfc6d25 3303 case NAND_ECC_HW_SYNDROME:
78b65179
SW		 3304 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3305 !chip->ecc.hwctl) &&
3306 (!chip->ecc.read_page ||
1c45f604 3307 chip->ecc.read_page == nand_read_page_hwecc ||
78b65179 3308 !chip->ecc.write_page ||
1c45f604 3309 chip->ecc.write_page == nand_write_page_hwecc)) {
6e0cb135 3310 printk(KERN_WARNING "No ECC functions supplied; "
6dfc6d25
TG		 3311 "Hardware ECC not possible\n");
3312 BUG();
3313 }
f75e5097 3314 /* Use standard syndrome read/write page function ? */
f5bbdacc
TG		 3315 if (!chip->ecc.read_page)
3316 chip->ecc.read_page = nand_read_page_syndrome;
f75e5097
TG		 3317 if (!chip->ecc.write_page)
3318 chip->ecc.write_page = nand_write_page_syndrome;
52ff49df
DB		 3319 if (!chip->ecc.read_page_raw)
3320 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3321 if (!chip->ecc.write_page_raw)
3322 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
7bc3312b
TG		 3323 if (!chip->ecc.read_oob)
3324 chip->ecc.read_oob = nand_read_oob_syndrome;
3325 if (!chip->ecc.write_oob)
3326 chip->ecc.write_oob = nand_write_oob_syndrome;
f5bbdacc 3327
ace4dfee 3328 if (mtd->writesize >= chip->ecc.size)
6dfc6d25
TG		 3329 break;
3330 printk(KERN_WARNING "%d byte HW ECC not possible on "
3331 "%d byte page size, fallback to SW ECC\n",
ace4dfee
TG		 3332 chip->ecc.size, mtd->writesize);
3333 chip->ecc.mode = NAND_ECC_SOFT;
61b03bd7 3334
6dfc6d25 3335 case NAND_ECC_SOFT:
ace4dfee
TG		 3336 chip->ecc.calculate = nand_calculate_ecc;
3337 chip->ecc.correct = nand_correct_data;
f5bbdacc 3338 chip->ecc.read_page = nand_read_page_swecc;
3d459559 3339 chip->ecc.read_subpage = nand_read_subpage;
f75e5097 3340 chip->ecc.write_page = nand_write_page_swecc;
52ff49df
DB		 3341 chip->ecc.read_page_raw = nand_read_page_raw;
3342 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b
TG		 3343 chip->ecc.read_oob = nand_read_oob_std;
3344 chip->ecc.write_oob = nand_write_oob_std;
9a73290d
SV		 3345 if (!chip->ecc.size)
3346 chip->ecc.size = 256;
ace4dfee 3347 chip->ecc.bytes = 3;
1da177e4 3348 break;
61b03bd7
TG		 3349
3350 case NAND_ECC_NONE:
7aa65bfd
TG		 3351 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3352 "This is not recommended !!\n");
8593fbc6
TG		 3353 chip->ecc.read_page = nand_read_page_raw;
3354 chip->ecc.write_page = nand_write_page_raw;
7bc3312b 3355 chip->ecc.read_oob = nand_read_oob_std;
52ff49df
DB		 3356 chip->ecc.read_page_raw = nand_read_page_raw;
3357 chip->ecc.write_page_raw = nand_write_page_raw;
7bc3312b 3358 chip->ecc.write_oob = nand_write_oob_std;
ace4dfee
TG		 3359 chip->ecc.size = mtd->writesize;
3360 chip->ecc.bytes = 0;
1da177e4 3361 break;
956e944c 3362
1da177e4 3363 default:
7aa65bfd 3364 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
ace4dfee 3365 chip->ecc.mode);
61b03bd7 3366 BUG();
1da177e4 3367 }
61b03bd7 3368
5bd34c09
TG		 3369 /*
3370 * The number of bytes available for a client to place data into
3371 * the out of band area
3372 */
3373 chip->ecc.layout->oobavail = 0;
81d19b04
DB		 3374 for (i = 0; chip->ecc.layout->oobfree[i].length
3375 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
5bd34c09
TG		 3376 chip->ecc.layout->oobavail +=
3377 chip->ecc.layout->oobfree[i].length;
1f92267c 3378 mtd->oobavail = chip->ecc.layout->oobavail;
5bd34c09 3379
7aa65bfd
TG		 3380 /*
3381 * Set the number of read / write steps for one page depending on ECC
3382 * mode
3383 */
ace4dfee 3384 chip->ecc.steps = mtd->writesize / chip->ecc.size;
f8ac0414 3385 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
6dfc6d25
TG		 3386 printk(KERN_WARNING "Invalid ecc parameters\n");
3387 BUG();
1da177e4 3388 }
f5bbdacc 3389 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
61b03bd7 3390
29072b96
TG		 3391 /*
3392 * Allow subpage writes up to ecc.steps. Not possible for MLC
3393 * FLASH.
3394 */
3395 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3396 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
f8ac0414 3397 switch (chip->ecc.steps) {
29072b96
TG		 3398 case 2:
3399 mtd->subpage_sft = 1;
3400 break;
3401 case 4:
3402 case 8:
81ec5364 3403 case 16:
29072b96
TG		 3404 mtd->subpage_sft = 2;
3405 break;
3406 }
3407 }
3408 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3409
04bbd0ea 3410 /* Initialize state */
ace4dfee 3411 chip->state = FL_READY;
1da177e4
LT		 3412
3413 /* De-select the device */
ace4dfee 3414 chip->select_chip(mtd, -1);
1da177e4
LT		 3415
3416 /* Invalidate the pagebuffer reference */
ace4dfee 3417 chip->pagebuf = -1;
1da177e4
LT		 3418
3419 /* Fill in remaining MTD driver data */
3420 mtd->type = MTD_NANDFLASH;
93edbad6
ML		 3421 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3422 MTD_CAP_NANDFLASH;
1da177e4
LT		 3423 mtd->erase = nand_erase;
3424 mtd->point = NULL;
3425 mtd->unpoint = NULL;
3426 mtd->read = nand_read;
3427 mtd->write = nand_write;
2af7c653 3428 mtd->panic_write = panic_nand_write;
1da177e4
LT		 3429 mtd->read_oob = nand_read_oob;
3430 mtd->write_oob = nand_write_oob;
1da177e4
LT		 3431 mtd->sync = nand_sync;
3432 mtd->lock = NULL;
3433 mtd->unlock = NULL;
962034f4
VW		 3434 mtd->suspend = nand_suspend;
3435 mtd->resume = nand_resume;
1da177e4
LT		 3436 mtd->block_isbad = nand_block_isbad;
3437 mtd->block_markbad = nand_block_markbad;
3438
5bd34c09
TG		 3439 /* propagate ecc.layout to mtd_info */
3440 mtd->ecclayout = chip->ecc.layout;
1da177e4 3441
0040bf38 3442 /* Check, if we should skip the bad block table scan */
ace4dfee 3443 if (chip->options & NAND_SKIP_BBTSCAN)
0040bf38 3444 return 0;
1da177e4
LT		 3445
3446 /* Build bad block table */
ace4dfee 3447 return chip->scan_bbt(mtd);
1da177e4 3448}
7351d3a5 3449EXPORT_SYMBOL(nand_scan_tail);
1da177e4 3450
a6e6abd5 3451/* is_module_text_address() isn't exported, and it's mostly a pointless
7351d3a5
FF		 3452 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3453 * to call us from in-kernel code if the core NAND support is modular. */
3b85c321
DW		 3454#ifdef MODULE
3455#define caller_is_module() (1)
3456#else
3457#define caller_is_module() \
a6e6abd5 3458 is_module_text_address((unsigned long)__builtin_return_address(0))
3b85c321
DW		 3459#endif
3460
3461/**
3462 * nand_scan - [NAND Interface] Scan for the NAND device
3463 * @mtd: MTD device structure
3464 * @maxchips: Number of chips to scan for
3465 *
3466 * This fills out all the uninitialized function pointers
3467 * with the defaults.
3468 * The flash ID is read and the mtd/chip structures are
3469 * filled with the appropriate values.
3470 * The mtd->owner field must be set to the module of the caller
3471 *
3472 */
3473int nand_scan(struct mtd_info *mtd, int maxchips)
3474{
3475 int ret;
3476
3477 /* Many callers got this wrong, so check for it for a while... */
3478 if (!mtd->owner && caller_is_module()) {
20d8e248 3479 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3480 __func__);
3b85c321
DW		 3481 BUG();
3482 }
3483
5e81e88a 3484 ret = nand_scan_ident(mtd, maxchips, NULL);
3b85c321
DW		 3485 if (!ret)
3486 ret = nand_scan_tail(mtd);
3487 return ret;
3488}
7351d3a5 3489EXPORT_SYMBOL(nand_scan);
3b85c321 3490
1da177e4 3491/**
61b03bd7 3492 * nand_release - [NAND Interface] Free resources held by the NAND device
1da177e4
LT		 3493 * @mtd: MTD device structure
3494*/
e0c7d767 3495void nand_release(struct mtd_info *mtd)
1da177e4 3496{
ace4dfee 3497 struct nand_chip *chip = mtd->priv;
1da177e4
LT		 3498
3499#ifdef CONFIG_MTD_PARTITIONS
3500 /* Deregister partitions */
e0c7d767 3501 del_mtd_partitions(mtd);
1da177e4
LT		 3502#endif
3503 /* Deregister the device */
e0c7d767 3504 del_mtd_device(mtd);
1da177e4 3505
fa671646 3506 /* Free bad block table memory */
ace4dfee 3507 kfree(chip->bbt);
4bf63fcb
DW		 3508 if (!(chip->options & NAND_OWN_BUFFERS))
3509 kfree(chip->buffers);
58373ff0
BN		 3510
3511 /* Free bad block descriptor memory */
3512 if (chip->badblock_pattern && chip->badblock_pattern->options
3513 & NAND_BBT_DYNAMICSTRUCT)
3514 kfree(chip->badblock_pattern);
1da177e4 3515}
e0c7d767 3516EXPORT_SYMBOL_GPL(nand_release);
8fe833c1
RP		 3517
3518static int __init nand_base_init(void)
3519{
3520 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3521 return 0;
3522}
3523
3524static void __exit nand_base_exit(void)
3525{
3526 led_trigger_unregister_simple(nand_led_trigger);
3527}
3528
3529module_init(nand_base_init);
3530module_exit(nand_base_exit);
3531
e0c7d767 3532MODULE_LICENSE("GPL");
7351d3a5
FF		 3533MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3534MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
e0c7d767 3535MODULE_DESCRIPTION("Generic NAND flash driver code");
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