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b37bde14 BW |
1 | /* linux/drivers/mtd/nand/bf5xx_nand.c |
2 | * | |
afc4bca6 | 3 | * Copyright 2006-2008 Analog Devices Inc. |
b37bde14 BW |
4 | * http://blackfin.uclinux.org/ |
5 | * Bryan Wu <bryan.wu@analog.com> | |
6 | * | |
8e87d782 | 7 | * Blackfin BF5xx on-chip NAND flash controller driver |
b37bde14 BW |
8 | * |
9 | * Derived from drivers/mtd/nand/s3c2410.c | |
10 | * Copyright (c) 2007 Ben Dooks <ben@simtec.co.uk> | |
11 | * | |
12 | * Derived from drivers/mtd/nand/cafe.c | |
13 | * Copyright © 2006 Red Hat, Inc. | |
14 | * Copyright © 2006 David Woodhouse <dwmw2@infradead.org> | |
15 | * | |
16 | * Changelog: | |
17 | * 12-Jun-2007 Bryan Wu: Initial version | |
18 | * 18-Jul-2007 Bryan Wu: | |
19 | * - ECC_HW and ECC_SW supported | |
20 | * - DMA supported in ECC_HW | |
21 | * - YAFFS tested as rootfs in both ECC_HW and ECC_SW | |
22 | * | |
b37bde14 BW |
23 | * This program is free software; you can redistribute it and/or modify |
24 | * it under the terms of the GNU General Public License as published by | |
25 | * the Free Software Foundation; either version 2 of the License, or | |
26 | * (at your option) any later version. | |
27 | * | |
28 | * This program is distributed in the hope that it will be useful, | |
29 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
30 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
31 | * GNU General Public License for more details. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License | |
34 | * along with this program; if not, write to the Free Software | |
35 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
36 | */ | |
37 | ||
38 | #include <linux/module.h> | |
39 | #include <linux/types.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/kernel.h> | |
42 | #include <linux/string.h> | |
43 | #include <linux/ioport.h> | |
44 | #include <linux/platform_device.h> | |
45 | #include <linux/delay.h> | |
46 | #include <linux/dma-mapping.h> | |
47 | #include <linux/err.h> | |
48 | #include <linux/slab.h> | |
49 | #include <linux/io.h> | |
50 | #include <linux/bitops.h> | |
51 | ||
52 | #include <linux/mtd/mtd.h> | |
53 | #include <linux/mtd/nand.h> | |
54 | #include <linux/mtd/nand_ecc.h> | |
55 | #include <linux/mtd/partitions.h> | |
56 | ||
57 | #include <asm/blackfin.h> | |
58 | #include <asm/dma.h> | |
59 | #include <asm/cacheflush.h> | |
60 | #include <asm/nand.h> | |
61 | #include <asm/portmux.h> | |
62 | ||
63 | #define DRV_NAME "bf5xx-nand" | |
64 | #define DRV_VERSION "1.2" | |
65 | #define DRV_AUTHOR "Bryan Wu <bryan.wu@analog.com>" | |
66 | #define DRV_DESC "BF5xx on-chip NAND FLash Controller Driver" | |
67 | ||
ac39ee30 MF |
68 | /* NFC_STAT Masks */ |
69 | #define NBUSY 0x01 /* Not Busy */ | |
70 | #define WB_FULL 0x02 /* Write Buffer Full */ | |
71 | #define PG_WR_STAT 0x04 /* Page Write Pending */ | |
72 | #define PG_RD_STAT 0x08 /* Page Read Pending */ | |
73 | #define WB_EMPTY 0x10 /* Write Buffer Empty */ | |
74 | ||
75 | /* NFC_IRQSTAT Masks */ | |
76 | #define NBUSYIRQ 0x01 /* Not Busy IRQ */ | |
77 | #define WB_OVF 0x02 /* Write Buffer Overflow */ | |
78 | #define WB_EDGE 0x04 /* Write Buffer Edge Detect */ | |
79 | #define RD_RDY 0x08 /* Read Data Ready */ | |
80 | #define WR_DONE 0x10 /* Page Write Done */ | |
81 | ||
82 | /* NFC_RST Masks */ | |
83 | #define ECC_RST 0x01 /* ECC (and NFC counters) Reset */ | |
84 | ||
85 | /* NFC_PGCTL Masks */ | |
86 | #define PG_RD_START 0x01 /* Page Read Start */ | |
87 | #define PG_WR_START 0x02 /* Page Write Start */ | |
88 | ||
b37bde14 BW |
89 | #ifdef CONFIG_MTD_NAND_BF5XX_HWECC |
90 | static int hardware_ecc = 1; | |
91 | #else | |
92 | static int hardware_ecc; | |
93 | #endif | |
94 | ||
afc4bca6 | 95 | static const unsigned short bfin_nfc_pin_req[] = |
a25b7fee MH |
96 | {P_NAND_CE, |
97 | P_NAND_RB, | |
98 | P_NAND_D0, | |
99 | P_NAND_D1, | |
100 | P_NAND_D2, | |
101 | P_NAND_D3, | |
102 | P_NAND_D4, | |
103 | P_NAND_D5, | |
104 | P_NAND_D6, | |
105 | P_NAND_D7, | |
106 | P_NAND_WE, | |
107 | P_NAND_RE, | |
108 | P_NAND_CLE, | |
109 | P_NAND_ALE, | |
110 | 0}; | |
b37bde14 | 111 | |
fcb90ba7 MF |
112 | #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC |
113 | static uint8_t bbt_pattern[] = { 0xff }; | |
114 | ||
115 | static struct nand_bbt_descr bootrom_bbt = { | |
116 | .options = 0, | |
117 | .offs = 63, | |
118 | .len = 1, | |
119 | .pattern = bbt_pattern, | |
120 | }; | |
121 | ||
122 | static struct nand_ecclayout bootrom_ecclayout = { | |
123 | .eccbytes = 24, | |
124 | .eccpos = { | |
125 | 0x8 * 0, 0x8 * 0 + 1, 0x8 * 0 + 2, | |
126 | 0x8 * 1, 0x8 * 1 + 1, 0x8 * 1 + 2, | |
127 | 0x8 * 2, 0x8 * 2 + 1, 0x8 * 2 + 2, | |
128 | 0x8 * 3, 0x8 * 3 + 1, 0x8 * 3 + 2, | |
129 | 0x8 * 4, 0x8 * 4 + 1, 0x8 * 4 + 2, | |
130 | 0x8 * 5, 0x8 * 5 + 1, 0x8 * 5 + 2, | |
131 | 0x8 * 6, 0x8 * 6 + 1, 0x8 * 6 + 2, | |
132 | 0x8 * 7, 0x8 * 7 + 1, 0x8 * 7 + 2 | |
133 | }, | |
134 | .oobfree = { | |
135 | { 0x8 * 0 + 3, 5 }, | |
136 | { 0x8 * 1 + 3, 5 }, | |
137 | { 0x8 * 2 + 3, 5 }, | |
138 | { 0x8 * 3 + 3, 5 }, | |
139 | { 0x8 * 4 + 3, 5 }, | |
140 | { 0x8 * 5 + 3, 5 }, | |
141 | { 0x8 * 6 + 3, 5 }, | |
142 | { 0x8 * 7 + 3, 5 }, | |
143 | } | |
144 | }; | |
145 | #endif | |
146 | ||
b37bde14 BW |
147 | /* |
148 | * Data structures for bf5xx nand flash controller driver | |
149 | */ | |
150 | ||
151 | /* bf5xx nand info */ | |
152 | struct bf5xx_nand_info { | |
153 | /* mtd info */ | |
154 | struct nand_hw_control controller; | |
155 | struct mtd_info mtd; | |
156 | struct nand_chip chip; | |
157 | ||
158 | /* platform info */ | |
159 | struct bf5xx_nand_platform *platform; | |
160 | ||
161 | /* device info */ | |
162 | struct device *device; | |
163 | ||
164 | /* DMA stuff */ | |
165 | struct completion dma_completion; | |
166 | }; | |
167 | ||
168 | /* | |
169 | * Conversion functions | |
170 | */ | |
171 | static struct bf5xx_nand_info *mtd_to_nand_info(struct mtd_info *mtd) | |
172 | { | |
173 | return container_of(mtd, struct bf5xx_nand_info, mtd); | |
174 | } | |
175 | ||
176 | static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev) | |
177 | { | |
178 | return platform_get_drvdata(pdev); | |
179 | } | |
180 | ||
181 | static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev) | |
182 | { | |
183 | return pdev->dev.platform_data; | |
184 | } | |
185 | ||
186 | /* | |
187 | * struct nand_chip interface function pointers | |
188 | */ | |
189 | ||
190 | /* | |
191 | * bf5xx_nand_hwcontrol | |
192 | * | |
193 | * Issue command and address cycles to the chip | |
194 | */ | |
195 | static void bf5xx_nand_hwcontrol(struct mtd_info *mtd, int cmd, | |
196 | unsigned int ctrl) | |
197 | { | |
198 | if (cmd == NAND_CMD_NONE) | |
199 | return; | |
200 | ||
201 | while (bfin_read_NFC_STAT() & WB_FULL) | |
202 | cpu_relax(); | |
203 | ||
204 | if (ctrl & NAND_CLE) | |
205 | bfin_write_NFC_CMD(cmd); | |
fd508da2 | 206 | else if (ctrl & NAND_ALE) |
b37bde14 BW |
207 | bfin_write_NFC_ADDR(cmd); |
208 | SSYNC(); | |
209 | } | |
210 | ||
211 | /* | |
212 | * bf5xx_nand_devready() | |
213 | * | |
214 | * returns 0 if the nand is busy, 1 if it is ready | |
215 | */ | |
216 | static int bf5xx_nand_devready(struct mtd_info *mtd) | |
217 | { | |
d2350c2a | 218 | unsigned short val = bfin_read_NFC_STAT(); |
b37bde14 | 219 | |
d2350c2a | 220 | if ((val & NBUSY) == NBUSY) |
b37bde14 BW |
221 | return 1; |
222 | else | |
223 | return 0; | |
224 | } | |
225 | ||
226 | /* | |
227 | * ECC functions | |
228 | * These allow the bf5xx to use the controller's ECC | |
229 | * generator block to ECC the data as it passes through | |
230 | */ | |
231 | ||
232 | /* | |
233 | * ECC error correction function | |
234 | */ | |
235 | static int bf5xx_nand_correct_data_256(struct mtd_info *mtd, u_char *dat, | |
236 | u_char *read_ecc, u_char *calc_ecc) | |
237 | { | |
238 | struct bf5xx_nand_info *info = mtd_to_nand_info(mtd); | |
239 | u32 syndrome[5]; | |
240 | u32 calced, stored; | |
241 | int i; | |
242 | unsigned short failing_bit, failing_byte; | |
243 | u_char data; | |
244 | ||
245 | calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16); | |
246 | stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16); | |
247 | ||
248 | syndrome[0] = (calced ^ stored); | |
249 | ||
250 | /* | |
251 | * syndrome 0: all zero | |
252 | * No error in data | |
253 | * No action | |
254 | */ | |
255 | if (!syndrome[0] || !calced || !stored) | |
256 | return 0; | |
257 | ||
258 | /* | |
259 | * sysdrome 0: only one bit is one | |
260 | * ECC data was incorrect | |
261 | * No action | |
262 | */ | |
263 | if (hweight32(syndrome[0]) == 1) { | |
264 | dev_err(info->device, "ECC data was incorrect!\n"); | |
265 | return 1; | |
266 | } | |
267 | ||
268 | syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF); | |
269 | syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF); | |
270 | syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF); | |
271 | syndrome[4] = syndrome[2] ^ syndrome[3]; | |
272 | ||
273 | for (i = 0; i < 5; i++) | |
274 | dev_info(info->device, "syndrome[%d] 0x%08x\n", i, syndrome[i]); | |
275 | ||
276 | dev_info(info->device, | |
277 | "calced[0x%08x], stored[0x%08x]\n", | |
278 | calced, stored); | |
279 | ||
280 | /* | |
281 | * sysdrome 0: exactly 11 bits are one, each parity | |
282 | * and parity' pair is 1 & 0 or 0 & 1. | |
283 | * 1-bit correctable error | |
284 | * Correct the error | |
285 | */ | |
286 | if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) { | |
287 | dev_info(info->device, | |
288 | "1-bit correctable error, correct it.\n"); | |
289 | dev_info(info->device, | |
290 | "syndrome[1] 0x%08x\n", syndrome[1]); | |
291 | ||
292 | failing_bit = syndrome[1] & 0x7; | |
293 | failing_byte = syndrome[1] >> 0x3; | |
294 | data = *(dat + failing_byte); | |
295 | data = data ^ (0x1 << failing_bit); | |
296 | *(dat + failing_byte) = data; | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
301 | /* | |
302 | * sysdrome 0: random data | |
303 | * More than 1-bit error, non-correctable error | |
304 | * Discard data, mark bad block | |
305 | */ | |
306 | dev_err(info->device, | |
307 | "More than 1-bit error, non-correctable error.\n"); | |
308 | dev_err(info->device, | |
309 | "Please discard data, mark bad block\n"); | |
310 | ||
311 | return 1; | |
312 | } | |
313 | ||
314 | static int bf5xx_nand_correct_data(struct mtd_info *mtd, u_char *dat, | |
315 | u_char *read_ecc, u_char *calc_ecc) | |
316 | { | |
44299179 | 317 | struct nand_chip *chip = mtd->priv; |
b37bde14 BW |
318 | int ret; |
319 | ||
320 | ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc); | |
321 | ||
44299179 BS |
322 | /* If ecc size is 512, correct second 256 bytes */ |
323 | if (chip->ecc.size == 512) { | |
b37bde14 | 324 | dat += 256; |
44299179 BS |
325 | read_ecc += 3; |
326 | calc_ecc += 3; | |
e274f025 | 327 | ret |= bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc); |
b37bde14 BW |
328 | } |
329 | ||
330 | return ret; | |
331 | } | |
332 | ||
333 | static void bf5xx_nand_enable_hwecc(struct mtd_info *mtd, int mode) | |
334 | { | |
335 | return; | |
336 | } | |
337 | ||
338 | static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd, | |
339 | const u_char *dat, u_char *ecc_code) | |
340 | { | |
341 | struct bf5xx_nand_info *info = mtd_to_nand_info(mtd); | |
44299179 | 342 | struct nand_chip *chip = mtd->priv; |
b37bde14 BW |
343 | u16 ecc0, ecc1; |
344 | u32 code[2]; | |
345 | u8 *p; | |
b37bde14 | 346 | |
44299179 | 347 | /* first 3 bytes ECC code for 256 page size */ |
b37bde14 BW |
348 | ecc0 = bfin_read_NFC_ECC0(); |
349 | ecc1 = bfin_read_NFC_ECC1(); | |
350 | ||
cf840392 | 351 | code[0] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11); |
b37bde14 BW |
352 | |
353 | dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]); | |
354 | ||
5eb91034 BW |
355 | p = (u8 *) code; |
356 | memcpy(ecc_code, p, 3); | |
357 | ||
44299179 BS |
358 | /* second 3 bytes ECC code for 512 ecc size */ |
359 | if (chip->ecc.size == 512) { | |
b37bde14 BW |
360 | ecc0 = bfin_read_NFC_ECC2(); |
361 | ecc1 = bfin_read_NFC_ECC3(); | |
cf840392 | 362 | code[1] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11); |
5eb91034 BW |
363 | |
364 | /* second 3 bytes in ecc_code for second 256 | |
365 | * bytes of 512 page size | |
366 | */ | |
367 | p = (u8 *) (code + 1); | |
368 | memcpy((ecc_code + 3), p, 3); | |
b37bde14 BW |
369 | dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]); |
370 | } | |
371 | ||
b37bde14 BW |
372 | return 0; |
373 | } | |
374 | ||
375 | /* | |
376 | * PIO mode for buffer writing and reading | |
377 | */ | |
378 | static void bf5xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) | |
379 | { | |
380 | int i; | |
381 | unsigned short val; | |
382 | ||
383 | /* | |
384 | * Data reads are requested by first writing to NFC_DATA_RD | |
385 | * and then reading back from NFC_READ. | |
386 | */ | |
387 | for (i = 0; i < len; i++) { | |
388 | while (bfin_read_NFC_STAT() & WB_FULL) | |
389 | cpu_relax(); | |
390 | ||
391 | /* Contents do not matter */ | |
392 | bfin_write_NFC_DATA_RD(0x0000); | |
393 | SSYNC(); | |
394 | ||
395 | while ((bfin_read_NFC_IRQSTAT() & RD_RDY) != RD_RDY) | |
396 | cpu_relax(); | |
397 | ||
398 | buf[i] = bfin_read_NFC_READ(); | |
399 | ||
400 | val = bfin_read_NFC_IRQSTAT(); | |
401 | val |= RD_RDY; | |
402 | bfin_write_NFC_IRQSTAT(val); | |
403 | SSYNC(); | |
404 | } | |
405 | } | |
406 | ||
407 | static uint8_t bf5xx_nand_read_byte(struct mtd_info *mtd) | |
408 | { | |
409 | uint8_t val; | |
410 | ||
411 | bf5xx_nand_read_buf(mtd, &val, 1); | |
412 | ||
413 | return val; | |
414 | } | |
415 | ||
416 | static void bf5xx_nand_write_buf(struct mtd_info *mtd, | |
417 | const uint8_t *buf, int len) | |
418 | { | |
419 | int i; | |
420 | ||
421 | for (i = 0; i < len; i++) { | |
422 | while (bfin_read_NFC_STAT() & WB_FULL) | |
423 | cpu_relax(); | |
424 | ||
425 | bfin_write_NFC_DATA_WR(buf[i]); | |
426 | SSYNC(); | |
427 | } | |
428 | } | |
429 | ||
430 | static void bf5xx_nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len) | |
431 | { | |
432 | int i; | |
433 | u16 *p = (u16 *) buf; | |
434 | len >>= 1; | |
435 | ||
436 | /* | |
437 | * Data reads are requested by first writing to NFC_DATA_RD | |
438 | * and then reading back from NFC_READ. | |
439 | */ | |
440 | bfin_write_NFC_DATA_RD(0x5555); | |
441 | ||
442 | SSYNC(); | |
443 | ||
444 | for (i = 0; i < len; i++) | |
445 | p[i] = bfin_read_NFC_READ(); | |
446 | } | |
447 | ||
448 | static void bf5xx_nand_write_buf16(struct mtd_info *mtd, | |
449 | const uint8_t *buf, int len) | |
450 | { | |
451 | int i; | |
452 | u16 *p = (u16 *) buf; | |
453 | len >>= 1; | |
454 | ||
455 | for (i = 0; i < len; i++) | |
456 | bfin_write_NFC_DATA_WR(p[i]); | |
457 | ||
458 | SSYNC(); | |
459 | } | |
460 | ||
461 | /* | |
462 | * DMA functions for buffer writing and reading | |
463 | */ | |
464 | static irqreturn_t bf5xx_nand_dma_irq(int irq, void *dev_id) | |
465 | { | |
466 | struct bf5xx_nand_info *info = dev_id; | |
467 | ||
468 | clear_dma_irqstat(CH_NFC); | |
469 | disable_dma(CH_NFC); | |
470 | complete(&info->dma_completion); | |
471 | ||
472 | return IRQ_HANDLED; | |
473 | } | |
474 | ||
530c3b60 | 475 | static void bf5xx_nand_dma_rw(struct mtd_info *mtd, |
b37bde14 BW |
476 | uint8_t *buf, int is_read) |
477 | { | |
478 | struct bf5xx_nand_info *info = mtd_to_nand_info(mtd); | |
44299179 | 479 | struct nand_chip *chip = mtd->priv; |
b37bde14 BW |
480 | unsigned short val; |
481 | ||
482 | dev_dbg(info->device, " mtd->%p, buf->%p, is_read %d\n", | |
483 | mtd, buf, is_read); | |
484 | ||
485 | /* | |
486 | * Before starting a dma transfer, be sure to invalidate/flush | |
487 | * the cache over the address range of your DMA buffer to | |
488 | * prevent cache coherency problems. Otherwise very subtle bugs | |
489 | * can be introduced to your driver. | |
490 | */ | |
491 | if (is_read) | |
492 | invalidate_dcache_range((unsigned int)buf, | |
44299179 | 493 | (unsigned int)(buf + chip->ecc.size)); |
b37bde14 BW |
494 | else |
495 | flush_dcache_range((unsigned int)buf, | |
44299179 | 496 | (unsigned int)(buf + chip->ecc.size)); |
b37bde14 BW |
497 | |
498 | /* | |
499 | * This register must be written before each page is | |
500 | * transferred to generate the correct ECC register | |
501 | * values. | |
502 | */ | |
ac39ee30 | 503 | bfin_write_NFC_RST(ECC_RST); |
b37bde14 | 504 | SSYNC(); |
752b957a BS |
505 | while (bfin_read_NFC_RST() & ECC_RST) |
506 | cpu_relax(); | |
b37bde14 BW |
507 | |
508 | disable_dma(CH_NFC); | |
509 | clear_dma_irqstat(CH_NFC); | |
510 | ||
511 | /* setup DMA register with Blackfin DMA API */ | |
512 | set_dma_config(CH_NFC, 0x0); | |
513 | set_dma_start_addr(CH_NFC, (unsigned long) buf); | |
c3a9f356 | 514 | |
ac39ee30 | 515 | /* The DMAs have different size on BF52x and BF54x */ |
c3a9f356 | 516 | #ifdef CONFIG_BF52x |
44299179 | 517 | set_dma_x_count(CH_NFC, (chip->ecc.size >> 1)); |
c3a9f356 CC |
518 | set_dma_x_modify(CH_NFC, 2); |
519 | val = DI_EN | WDSIZE_16; | |
520 | #endif | |
521 | ||
522 | #ifdef CONFIG_BF54x | |
44299179 | 523 | set_dma_x_count(CH_NFC, (chip->ecc.size >> 2)); |
b37bde14 | 524 | set_dma_x_modify(CH_NFC, 4); |
b37bde14 | 525 | val = DI_EN | WDSIZE_32; |
c3a9f356 CC |
526 | #endif |
527 | /* setup write or read operation */ | |
b37bde14 BW |
528 | if (is_read) |
529 | val |= WNR; | |
530 | set_dma_config(CH_NFC, val); | |
531 | enable_dma(CH_NFC); | |
532 | ||
533 | /* Start PAGE read/write operation */ | |
534 | if (is_read) | |
ac39ee30 | 535 | bfin_write_NFC_PGCTL(PG_RD_START); |
b37bde14 | 536 | else |
ac39ee30 | 537 | bfin_write_NFC_PGCTL(PG_WR_START); |
b37bde14 | 538 | wait_for_completion(&info->dma_completion); |
b37bde14 BW |
539 | } |
540 | ||
541 | static void bf5xx_nand_dma_read_buf(struct mtd_info *mtd, | |
542 | uint8_t *buf, int len) | |
543 | { | |
544 | struct bf5xx_nand_info *info = mtd_to_nand_info(mtd); | |
44299179 | 545 | struct nand_chip *chip = mtd->priv; |
b37bde14 BW |
546 | |
547 | dev_dbg(info->device, "mtd->%p, buf->%p, int %d\n", mtd, buf, len); | |
548 | ||
44299179 | 549 | if (len == chip->ecc.size) |
b37bde14 BW |
550 | bf5xx_nand_dma_rw(mtd, buf, 1); |
551 | else | |
552 | bf5xx_nand_read_buf(mtd, buf, len); | |
553 | } | |
554 | ||
555 | static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd, | |
556 | const uint8_t *buf, int len) | |
557 | { | |
558 | struct bf5xx_nand_info *info = mtd_to_nand_info(mtd); | |
44299179 | 559 | struct nand_chip *chip = mtd->priv; |
b37bde14 BW |
560 | |
561 | dev_dbg(info->device, "mtd->%p, buf->%p, len %d\n", mtd, buf, len); | |
562 | ||
44299179 | 563 | if (len == chip->ecc.size) |
b37bde14 BW |
564 | bf5xx_nand_dma_rw(mtd, (uint8_t *)buf, 0); |
565 | else | |
566 | bf5xx_nand_write_buf(mtd, buf, len); | |
567 | } | |
568 | ||
085d45fb BS |
569 | static int bf5xx_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, |
570 | uint8_t *buf, int page) | |
571 | { | |
572 | bf5xx_nand_read_buf(mtd, buf, mtd->writesize); | |
573 | bf5xx_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize); | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | static void bf5xx_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip, | |
579 | const uint8_t *buf) | |
580 | { | |
581 | bf5xx_nand_write_buf(mtd, buf, mtd->writesize); | |
582 | bf5xx_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize); | |
583 | } | |
584 | ||
b37bde14 BW |
585 | /* |
586 | * System initialization functions | |
587 | */ | |
b37bde14 BW |
588 | static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info) |
589 | { | |
590 | int ret; | |
b37bde14 BW |
591 | |
592 | /* Do not use dma */ | |
593 | if (!hardware_ecc) | |
594 | return 0; | |
595 | ||
596 | init_completion(&info->dma_completion); | |
597 | ||
b37bde14 BW |
598 | /* Request NFC DMA channel */ |
599 | ret = request_dma(CH_NFC, "BF5XX NFC driver"); | |
600 | if (ret < 0) { | |
601 | dev_err(info->device, " unable to get DMA channel\n"); | |
602 | return ret; | |
603 | } | |
604 | ||
08d2503e MF |
605 | #ifdef CONFIG_BF54x |
606 | /* Setup DMAC1 channel mux for NFC which shared with SDH */ | |
607 | bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() & ~1); | |
608 | SSYNC(); | |
609 | #endif | |
610 | ||
bfc49257 | 611 | set_dma_callback(CH_NFC, bf5xx_nand_dma_irq, info); |
b37bde14 BW |
612 | |
613 | /* Turn off the DMA channel first */ | |
614 | disable_dma(CH_NFC); | |
615 | return 0; | |
616 | } | |
617 | ||
4f0ca70e BW |
618 | static void bf5xx_nand_dma_remove(struct bf5xx_nand_info *info) |
619 | { | |
620 | /* Free NFC DMA channel */ | |
621 | if (hardware_ecc) | |
622 | free_dma(CH_NFC); | |
623 | } | |
624 | ||
b37bde14 BW |
625 | /* |
626 | * BF5XX NFC hardware initialization | |
627 | * - pin mux setup | |
628 | * - clear interrupt status | |
629 | */ | |
630 | static int bf5xx_nand_hw_init(struct bf5xx_nand_info *info) | |
631 | { | |
632 | int err = 0; | |
633 | unsigned short val; | |
634 | struct bf5xx_nand_platform *plat = info->platform; | |
635 | ||
636 | /* setup NFC_CTL register */ | |
637 | dev_info(info->device, | |
44299179 | 638 | "data_width=%d, wr_dly=%d, rd_dly=%d\n", |
b37bde14 BW |
639 | (plat->data_width ? 16 : 8), |
640 | plat->wr_dly, plat->rd_dly); | |
641 | ||
44299179 | 642 | val = (1 << NFC_PG_SIZE_OFFSET) | |
b37bde14 BW |
643 | (plat->data_width << NFC_NWIDTH_OFFSET) | |
644 | (plat->rd_dly << NFC_RDDLY_OFFSET) | | |
00355b0b | 645 | (plat->wr_dly << NFC_WRDLY_OFFSET); |
b37bde14 BW |
646 | dev_dbg(info->device, "NFC_CTL is 0x%04x\n", val); |
647 | ||
648 | bfin_write_NFC_CTL(val); | |
649 | SSYNC(); | |
650 | ||
651 | /* clear interrupt status */ | |
652 | bfin_write_NFC_IRQMASK(0x0); | |
653 | SSYNC(); | |
654 | val = bfin_read_NFC_IRQSTAT(); | |
655 | bfin_write_NFC_IRQSTAT(val); | |
656 | SSYNC(); | |
657 | ||
b37bde14 BW |
658 | /* DMA initialization */ |
659 | if (bf5xx_nand_dma_init(info)) | |
660 | err = -ENXIO; | |
661 | ||
662 | return err; | |
663 | } | |
664 | ||
665 | /* | |
666 | * Device management interface | |
667 | */ | |
8d30cab0 | 668 | static int __devinit bf5xx_nand_add_partition(struct bf5xx_nand_info *info) |
b37bde14 BW |
669 | { |
670 | struct mtd_info *mtd = &info->mtd; | |
671 | ||
672 | #ifdef CONFIG_MTD_PARTITIONS | |
673 | struct mtd_partition *parts = info->platform->partitions; | |
674 | int nr = info->platform->nr_partitions; | |
675 | ||
676 | return add_mtd_partitions(mtd, parts, nr); | |
677 | #else | |
678 | return add_mtd_device(mtd); | |
679 | #endif | |
680 | } | |
681 | ||
2445af38 | 682 | static int __devexit bf5xx_nand_remove(struct platform_device *pdev) |
b37bde14 BW |
683 | { |
684 | struct bf5xx_nand_info *info = to_nand_info(pdev); | |
b37bde14 BW |
685 | |
686 | platform_set_drvdata(pdev, NULL); | |
687 | ||
688 | /* first thing we need to do is release all our mtds | |
689 | * and their partitions, then go through freeing the | |
690 | * resources used | |
691 | */ | |
8b865d5e | 692 | nand_release(&info->mtd); |
b37bde14 BW |
693 | |
694 | peripheral_free_list(bfin_nfc_pin_req); | |
4f0ca70e | 695 | bf5xx_nand_dma_remove(info); |
b37bde14 BW |
696 | |
697 | /* free the common resources */ | |
698 | kfree(info); | |
699 | ||
700 | return 0; | |
701 | } | |
702 | ||
44299179 BS |
703 | static int bf5xx_nand_scan(struct mtd_info *mtd) |
704 | { | |
705 | struct nand_chip *chip = mtd->priv; | |
706 | int ret; | |
707 | ||
eac15a42 | 708 | ret = nand_scan_ident(mtd, 1, NULL); |
44299179 BS |
709 | if (ret) |
710 | return ret; | |
711 | ||
712 | if (hardware_ecc) { | |
713 | /* | |
714 | * for nand with page size > 512B, think it as several sections with 512B | |
715 | */ | |
716 | if (likely(mtd->writesize >= 512)) { | |
717 | chip->ecc.size = 512; | |
718 | chip->ecc.bytes = 6; | |
719 | } else { | |
720 | chip->ecc.size = 256; | |
721 | chip->ecc.bytes = 3; | |
722 | bfin_write_NFC_CTL(bfin_read_NFC_CTL() & ~(1 << NFC_PG_SIZE_OFFSET)); | |
723 | SSYNC(); | |
724 | } | |
725 | } | |
726 | ||
727 | return nand_scan_tail(mtd); | |
728 | } | |
729 | ||
b37bde14 BW |
730 | /* |
731 | * bf5xx_nand_probe | |
732 | * | |
733 | * called by device layer when it finds a device matching | |
734 | * one our driver can handled. This code checks to see if | |
735 | * it can allocate all necessary resources then calls the | |
736 | * nand layer to look for devices | |
737 | */ | |
2445af38 | 738 | static int __devinit bf5xx_nand_probe(struct platform_device *pdev) |
b37bde14 BW |
739 | { |
740 | struct bf5xx_nand_platform *plat = to_nand_plat(pdev); | |
741 | struct bf5xx_nand_info *info = NULL; | |
742 | struct nand_chip *chip = NULL; | |
743 | struct mtd_info *mtd = NULL; | |
744 | int err = 0; | |
745 | ||
746 | dev_dbg(&pdev->dev, "(%p)\n", pdev); | |
747 | ||
4f0ca70e BW |
748 | if (!plat) { |
749 | dev_err(&pdev->dev, "no platform specific information\n"); | |
750 | return -EINVAL; | |
751 | } | |
752 | ||
afc4bca6 | 753 | if (peripheral_request_list(bfin_nfc_pin_req, DRV_NAME)) { |
0ee002b0 | 754 | dev_err(&pdev->dev, "requesting Peripherals failed\n"); |
afc4bca6 MH |
755 | return -EFAULT; |
756 | } | |
757 | ||
b37bde14 BW |
758 | info = kzalloc(sizeof(*info), GFP_KERNEL); |
759 | if (info == NULL) { | |
760 | dev_err(&pdev->dev, "no memory for flash info\n"); | |
761 | err = -ENOMEM; | |
4f0ca70e | 762 | goto out_err_kzalloc; |
b37bde14 BW |
763 | } |
764 | ||
765 | platform_set_drvdata(pdev, info); | |
766 | ||
767 | spin_lock_init(&info->controller.lock); | |
768 | init_waitqueue_head(&info->controller.wq); | |
769 | ||
770 | info->device = &pdev->dev; | |
771 | info->platform = plat; | |
772 | ||
773 | /* initialise chip data struct */ | |
774 | chip = &info->chip; | |
775 | ||
776 | if (plat->data_width) | |
777 | chip->options |= NAND_BUSWIDTH_16; | |
778 | ||
779 | chip->options |= NAND_CACHEPRG | NAND_SKIP_BBTSCAN; | |
780 | ||
781 | chip->read_buf = (plat->data_width) ? | |
782 | bf5xx_nand_read_buf16 : bf5xx_nand_read_buf; | |
783 | chip->write_buf = (plat->data_width) ? | |
784 | bf5xx_nand_write_buf16 : bf5xx_nand_write_buf; | |
785 | ||
786 | chip->read_byte = bf5xx_nand_read_byte; | |
787 | ||
788 | chip->cmd_ctrl = bf5xx_nand_hwcontrol; | |
789 | chip->dev_ready = bf5xx_nand_devready; | |
790 | ||
791 | chip->priv = &info->mtd; | |
792 | chip->controller = &info->controller; | |
793 | ||
794 | chip->IO_ADDR_R = (void __iomem *) NFC_READ; | |
795 | chip->IO_ADDR_W = (void __iomem *) NFC_DATA_WR; | |
796 | ||
797 | chip->chip_delay = 0; | |
798 | ||
799 | /* initialise mtd info data struct */ | |
800 | mtd = &info->mtd; | |
801 | mtd->priv = chip; | |
802 | mtd->owner = THIS_MODULE; | |
803 | ||
804 | /* initialise the hardware */ | |
805 | err = bf5xx_nand_hw_init(info); | |
4f0ca70e BW |
806 | if (err) |
807 | goto out_err_hw_init; | |
b37bde14 BW |
808 | |
809 | /* setup hardware ECC data struct */ | |
810 | if (hardware_ecc) { | |
fcb90ba7 MF |
811 | #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC |
812 | chip->badblock_pattern = &bootrom_bbt; | |
813 | chip->ecc.layout = &bootrom_ecclayout; | |
814 | #endif | |
b37bde14 BW |
815 | chip->read_buf = bf5xx_nand_dma_read_buf; |
816 | chip->write_buf = bf5xx_nand_dma_write_buf; | |
817 | chip->ecc.calculate = bf5xx_nand_calculate_ecc; | |
818 | chip->ecc.correct = bf5xx_nand_correct_data; | |
819 | chip->ecc.mode = NAND_ECC_HW; | |
820 | chip->ecc.hwctl = bf5xx_nand_enable_hwecc; | |
085d45fb BS |
821 | chip->ecc.read_page_raw = bf5xx_nand_read_page_raw; |
822 | chip->ecc.write_page_raw = bf5xx_nand_write_page_raw; | |
b37bde14 BW |
823 | } else { |
824 | chip->ecc.mode = NAND_ECC_SOFT; | |
825 | } | |
826 | ||
827 | /* scan hardware nand chip and setup mtd info data struct */ | |
44299179 | 828 | if (bf5xx_nand_scan(mtd)) { |
b37bde14 | 829 | err = -ENXIO; |
4f0ca70e | 830 | goto out_err_nand_scan; |
b37bde14 BW |
831 | } |
832 | ||
833 | /* add NAND partition */ | |
834 | bf5xx_nand_add_partition(info); | |
835 | ||
836 | dev_dbg(&pdev->dev, "initialised ok\n"); | |
837 | return 0; | |
838 | ||
4f0ca70e BW |
839 | out_err_nand_scan: |
840 | bf5xx_nand_dma_remove(info); | |
841 | out_err_hw_init: | |
842 | platform_set_drvdata(pdev, NULL); | |
843 | kfree(info); | |
844 | out_err_kzalloc: | |
845 | peripheral_free_list(bfin_nfc_pin_req); | |
b37bde14 | 846 | |
b37bde14 BW |
847 | return err; |
848 | } | |
849 | ||
850 | /* PM Support */ | |
851 | #ifdef CONFIG_PM | |
852 | ||
853 | static int bf5xx_nand_suspend(struct platform_device *dev, pm_message_t pm) | |
854 | { | |
855 | struct bf5xx_nand_info *info = platform_get_drvdata(dev); | |
856 | ||
857 | return 0; | |
858 | } | |
859 | ||
860 | static int bf5xx_nand_resume(struct platform_device *dev) | |
861 | { | |
862 | struct bf5xx_nand_info *info = platform_get_drvdata(dev); | |
863 | ||
b37bde14 BW |
864 | return 0; |
865 | } | |
866 | ||
867 | #else | |
868 | #define bf5xx_nand_suspend NULL | |
869 | #define bf5xx_nand_resume NULL | |
870 | #endif | |
871 | ||
872 | /* driver device registration */ | |
873 | static struct platform_driver bf5xx_nand_driver = { | |
874 | .probe = bf5xx_nand_probe, | |
2445af38 | 875 | .remove = __devexit_p(bf5xx_nand_remove), |
b37bde14 BW |
876 | .suspend = bf5xx_nand_suspend, |
877 | .resume = bf5xx_nand_resume, | |
878 | .driver = { | |
879 | .name = DRV_NAME, | |
880 | .owner = THIS_MODULE, | |
881 | }, | |
882 | }; | |
883 | ||
884 | static int __init bf5xx_nand_init(void) | |
885 | { | |
886 | printk(KERN_INFO "%s, Version %s (c) 2007 Analog Devices, Inc.\n", | |
887 | DRV_DESC, DRV_VERSION); | |
888 | ||
889 | return platform_driver_register(&bf5xx_nand_driver); | |
890 | } | |
891 | ||
892 | static void __exit bf5xx_nand_exit(void) | |
893 | { | |
894 | platform_driver_unregister(&bf5xx_nand_driver); | |
895 | } | |
896 | ||
897 | module_init(bf5xx_nand_init); | |
898 | module_exit(bf5xx_nand_exit); | |
899 | ||
900 | MODULE_LICENSE("GPL"); | |
901 | MODULE_AUTHOR(DRV_AUTHOR); | |
902 | MODULE_DESCRIPTION(DRV_DESC); | |
1ff18422 | 903 | MODULE_ALIAS("platform:" DRV_NAME); |