]>
Commit | Line | Data |
---|---|---|
2f9f7628 | 1 | /* |
fa0a8c71 | 2 | * MTD SPI driver for ST M25Pxx (and similar) serial flash chips |
2f9f7628 ML |
3 | * |
4 | * Author: Mike Lavender, mike@steroidmicros.com | |
5 | * | |
6 | * Copyright (c) 2005, Intec Automation Inc. | |
7 | * | |
8 | * Some parts are based on lart.c by Abraham Van Der Merwe | |
9 | * | |
10 | * Cleaned up and generalized based on mtd_dataflash.c | |
11 | * | |
12 | * This code is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/init.h> | |
9d2c4f3f AV |
19 | #include <linux/err.h> |
20 | #include <linux/errno.h> | |
2f9f7628 ML |
21 | #include <linux/module.h> |
22 | #include <linux/device.h> | |
23 | #include <linux/interrupt.h> | |
7d5230ea | 24 | #include <linux/mutex.h> |
d85316ac | 25 | #include <linux/math64.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
d43c36dc | 27 | #include <linux/sched.h> |
b34bc037 | 28 | #include <linux/mod_devicetable.h> |
7d5230ea | 29 | |
2f9f7628 ML |
30 | #include <linux/mtd/mtd.h> |
31 | #include <linux/mtd/partitions.h> | |
7d5230ea | 32 | |
2f9f7628 ML |
33 | #include <linux/spi/spi.h> |
34 | #include <linux/spi/flash.h> | |
35 | ||
2f9f7628 | 36 | /* Flash opcodes. */ |
fa0a8c71 DB |
37 | #define OPCODE_WREN 0x06 /* Write enable */ |
38 | #define OPCODE_RDSR 0x05 /* Read status register */ | |
72289824 | 39 | #define OPCODE_WRSR 0x01 /* Write status register 1 byte */ |
2230b76b | 40 | #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ |
fa0a8c71 DB |
41 | #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ |
42 | #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ | |
7854643a | 43 | #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ |
02d087db | 44 | #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ |
7854643a | 45 | #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ |
02d087db | 46 | #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ |
2f9f7628 ML |
47 | #define OPCODE_RDID 0x9f /* Read JEDEC ID */ |
48 | ||
49aac4ae GY |
49 | /* Used for SST flashes only. */ |
50 | #define OPCODE_BP 0x02 /* Byte program */ | |
51 | #define OPCODE_WRDI 0x04 /* Write disable */ | |
52 | #define OPCODE_AAI_WP 0xad /* Auto address increment word program */ | |
53 | ||
2f9f7628 ML |
54 | /* Status Register bits. */ |
55 | #define SR_WIP 1 /* Write in progress */ | |
56 | #define SR_WEL 2 /* Write enable latch */ | |
fa0a8c71 | 57 | /* meaning of other SR_* bits may differ between vendors */ |
2f9f7628 ML |
58 | #define SR_BP0 4 /* Block protect 0 */ |
59 | #define SR_BP1 8 /* Block protect 1 */ | |
60 | #define SR_BP2 0x10 /* Block protect 2 */ | |
61 | #define SR_SRWD 0x80 /* SR write protect */ | |
62 | ||
63 | /* Define max times to check status register before we give up. */ | |
89bb871e | 64 | #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */ |
837479d2 | 65 | #define MAX_CMD_SIZE 4 |
2f9f7628 | 66 | |
2230b76b BW |
67 | #ifdef CONFIG_M25PXX_USE_FAST_READ |
68 | #define OPCODE_READ OPCODE_FAST_READ | |
69 | #define FAST_READ_DUMMY_BYTE 1 | |
70 | #else | |
71 | #define OPCODE_READ OPCODE_NORM_READ | |
72 | #define FAST_READ_DUMMY_BYTE 0 | |
73 | #endif | |
2f9f7628 | 74 | |
2f9f7628 ML |
75 | /****************************************************************************/ |
76 | ||
77 | struct m25p { | |
78 | struct spi_device *spi; | |
7d5230ea | 79 | struct mutex lock; |
2f9f7628 | 80 | struct mtd_info mtd; |
fa0a8c71 | 81 | unsigned partitioned:1; |
837479d2 AV |
82 | u16 page_size; |
83 | u16 addr_width; | |
fa0a8c71 | 84 | u8 erase_opcode; |
61c3506c | 85 | u8 *command; |
2f9f7628 ML |
86 | }; |
87 | ||
88 | static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) | |
89 | { | |
90 | return container_of(mtd, struct m25p, mtd); | |
91 | } | |
92 | ||
93 | /****************************************************************************/ | |
94 | ||
95 | /* | |
96 | * Internal helper functions | |
97 | */ | |
98 | ||
99 | /* | |
100 | * Read the status register, returning its value in the location | |
101 | * Return the status register value. | |
102 | * Returns negative if error occurred. | |
103 | */ | |
104 | static int read_sr(struct m25p *flash) | |
105 | { | |
106 | ssize_t retval; | |
107 | u8 code = OPCODE_RDSR; | |
108 | u8 val; | |
109 | ||
110 | retval = spi_write_then_read(flash->spi, &code, 1, &val, 1); | |
111 | ||
112 | if (retval < 0) { | |
113 | dev_err(&flash->spi->dev, "error %d reading SR\n", | |
114 | (int) retval); | |
115 | return retval; | |
116 | } | |
117 | ||
118 | return val; | |
119 | } | |
120 | ||
72289824 MH |
121 | /* |
122 | * Write status register 1 byte | |
123 | * Returns negative if error occurred. | |
124 | */ | |
125 | static int write_sr(struct m25p *flash, u8 val) | |
126 | { | |
127 | flash->command[0] = OPCODE_WRSR; | |
128 | flash->command[1] = val; | |
129 | ||
130 | return spi_write(flash->spi, flash->command, 2); | |
131 | } | |
2f9f7628 ML |
132 | |
133 | /* | |
134 | * Set write enable latch with Write Enable command. | |
135 | * Returns negative if error occurred. | |
136 | */ | |
137 | static inline int write_enable(struct m25p *flash) | |
138 | { | |
139 | u8 code = OPCODE_WREN; | |
140 | ||
8a1a6272 | 141 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); |
2f9f7628 ML |
142 | } |
143 | ||
49aac4ae GY |
144 | /* |
145 | * Send write disble instruction to the chip. | |
146 | */ | |
147 | static inline int write_disable(struct m25p *flash) | |
148 | { | |
149 | u8 code = OPCODE_WRDI; | |
150 | ||
151 | return spi_write_then_read(flash->spi, &code, 1, NULL, 0); | |
152 | } | |
2f9f7628 ML |
153 | |
154 | /* | |
155 | * Service routine to read status register until ready, or timeout occurs. | |
156 | * Returns non-zero if error. | |
157 | */ | |
158 | static int wait_till_ready(struct m25p *flash) | |
159 | { | |
cd1a6de7 | 160 | unsigned long deadline; |
2f9f7628 ML |
161 | int sr; |
162 | ||
cd1a6de7 PH |
163 | deadline = jiffies + MAX_READY_WAIT_JIFFIES; |
164 | ||
165 | do { | |
2f9f7628 ML |
166 | if ((sr = read_sr(flash)) < 0) |
167 | break; | |
168 | else if (!(sr & SR_WIP)) | |
169 | return 0; | |
170 | ||
cd1a6de7 PH |
171 | cond_resched(); |
172 | ||
173 | } while (!time_after_eq(jiffies, deadline)); | |
2f9f7628 ML |
174 | |
175 | return 1; | |
176 | } | |
177 | ||
faff3750 CG |
178 | /* |
179 | * Erase the whole flash memory | |
180 | * | |
181 | * Returns 0 if successful, non-zero otherwise. | |
182 | */ | |
7854643a | 183 | static int erase_chip(struct m25p *flash) |
faff3750 | 184 | { |
d85316ac | 185 | DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %lldKiB\n", |
160bbab3 KS |
186 | dev_name(&flash->spi->dev), __func__, |
187 | (long long)(flash->mtd.size >> 10)); | |
faff3750 CG |
188 | |
189 | /* Wait until finished previous write command. */ | |
190 | if (wait_till_ready(flash)) | |
191 | return 1; | |
192 | ||
193 | /* Send write enable, then erase commands. */ | |
194 | write_enable(flash); | |
195 | ||
196 | /* Set up command buffer. */ | |
7854643a | 197 | flash->command[0] = OPCODE_CHIP_ERASE; |
faff3750 CG |
198 | |
199 | spi_write(flash->spi, flash->command, 1); | |
200 | ||
201 | return 0; | |
202 | } | |
2f9f7628 | 203 | |
837479d2 AV |
204 | static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd) |
205 | { | |
206 | /* opcode is in cmd[0] */ | |
207 | cmd[1] = addr >> (flash->addr_width * 8 - 8); | |
208 | cmd[2] = addr >> (flash->addr_width * 8 - 16); | |
209 | cmd[3] = addr >> (flash->addr_width * 8 - 24); | |
210 | } | |
211 | ||
212 | static int m25p_cmdsz(struct m25p *flash) | |
213 | { | |
214 | return 1 + flash->addr_width; | |
215 | } | |
216 | ||
2f9f7628 ML |
217 | /* |
218 | * Erase one sector of flash memory at offset ``offset'' which is any | |
219 | * address within the sector which should be erased. | |
220 | * | |
221 | * Returns 0 if successful, non-zero otherwise. | |
222 | */ | |
223 | static int erase_sector(struct m25p *flash, u32 offset) | |
224 | { | |
02d087db | 225 | DEBUG(MTD_DEBUG_LEVEL3, "%s: %s %dKiB at 0x%08x\n", |
160bbab3 | 226 | dev_name(&flash->spi->dev), __func__, |
fa0a8c71 | 227 | flash->mtd.erasesize / 1024, offset); |
2f9f7628 ML |
228 | |
229 | /* Wait until finished previous write command. */ | |
230 | if (wait_till_ready(flash)) | |
231 | return 1; | |
232 | ||
233 | /* Send write enable, then erase commands. */ | |
234 | write_enable(flash); | |
235 | ||
236 | /* Set up command buffer. */ | |
fa0a8c71 | 237 | flash->command[0] = flash->erase_opcode; |
837479d2 | 238 | m25p_addr2cmd(flash, offset, flash->command); |
2f9f7628 | 239 | |
837479d2 | 240 | spi_write(flash->spi, flash->command, m25p_cmdsz(flash)); |
2f9f7628 ML |
241 | |
242 | return 0; | |
243 | } | |
244 | ||
245 | /****************************************************************************/ | |
246 | ||
247 | /* | |
248 | * MTD implementation | |
249 | */ | |
250 | ||
251 | /* | |
252 | * Erase an address range on the flash chip. The address range may extend | |
253 | * one or more erase sectors. Return an error is there is a problem erasing. | |
254 | */ | |
255 | static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) | |
256 | { | |
257 | struct m25p *flash = mtd_to_m25p(mtd); | |
258 | u32 addr,len; | |
d85316ac | 259 | uint32_t rem; |
2f9f7628 | 260 | |
d85316ac | 261 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%llx, len %lld\n", |
160bbab3 KS |
262 | dev_name(&flash->spi->dev), __func__, "at", |
263 | (long long)instr->addr, (long long)instr->len); | |
2f9f7628 ML |
264 | |
265 | /* sanity checks */ | |
266 | if (instr->addr + instr->len > flash->mtd.size) | |
267 | return -EINVAL; | |
d85316ac AB |
268 | div_u64_rem(instr->len, mtd->erasesize, &rem); |
269 | if (rem) | |
2f9f7628 | 270 | return -EINVAL; |
2f9f7628 ML |
271 | |
272 | addr = instr->addr; | |
273 | len = instr->len; | |
274 | ||
7d5230ea | 275 | mutex_lock(&flash->lock); |
2f9f7628 | 276 | |
7854643a | 277 | /* whole-chip erase? */ |
3f33b0aa SF |
278 | if (len == flash->mtd.size) { |
279 | if (erase_chip(flash)) { | |
280 | instr->state = MTD_ERASE_FAILED; | |
281 | mutex_unlock(&flash->lock); | |
282 | return -EIO; | |
283 | } | |
7854643a CG |
284 | |
285 | /* REVISIT in some cases we could speed up erasing large regions | |
286 | * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up | |
287 | * to use "small sector erase", but that's not always optimal. | |
288 | */ | |
289 | ||
290 | /* "sector"-at-a-time erase */ | |
faff3750 CG |
291 | } else { |
292 | while (len) { | |
293 | if (erase_sector(flash, addr)) { | |
294 | instr->state = MTD_ERASE_FAILED; | |
295 | mutex_unlock(&flash->lock); | |
296 | return -EIO; | |
297 | } | |
298 | ||
299 | addr += mtd->erasesize; | |
300 | len -= mtd->erasesize; | |
2f9f7628 | 301 | } |
2f9f7628 ML |
302 | } |
303 | ||
7d5230ea | 304 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
305 | |
306 | instr->state = MTD_ERASE_DONE; | |
307 | mtd_erase_callback(instr); | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | /* | |
313 | * Read an address range from the flash chip. The address range | |
314 | * may be any size provided it is within the physical boundaries. | |
315 | */ | |
316 | static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, | |
317 | size_t *retlen, u_char *buf) | |
318 | { | |
319 | struct m25p *flash = mtd_to_m25p(mtd); | |
320 | struct spi_transfer t[2]; | |
321 | struct spi_message m; | |
322 | ||
323 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n", | |
160bbab3 | 324 | dev_name(&flash->spi->dev), __func__, "from", |
2f9f7628 ML |
325 | (u32)from, len); |
326 | ||
327 | /* sanity checks */ | |
328 | if (!len) | |
329 | return 0; | |
330 | ||
331 | if (from + len > flash->mtd.size) | |
332 | return -EINVAL; | |
333 | ||
8275c642 VW |
334 | spi_message_init(&m); |
335 | memset(t, 0, (sizeof t)); | |
336 | ||
2230b76b BW |
337 | /* NOTE: |
338 | * OPCODE_FAST_READ (if available) is faster. | |
339 | * Should add 1 byte DUMMY_BYTE. | |
340 | */ | |
8275c642 | 341 | t[0].tx_buf = flash->command; |
837479d2 | 342 | t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE; |
8275c642 VW |
343 | spi_message_add_tail(&t[0], &m); |
344 | ||
345 | t[1].rx_buf = buf; | |
346 | t[1].len = len; | |
347 | spi_message_add_tail(&t[1], &m); | |
348 | ||
349 | /* Byte count starts at zero. */ | |
350 | if (retlen) | |
351 | *retlen = 0; | |
352 | ||
7d5230ea | 353 | mutex_lock(&flash->lock); |
2f9f7628 ML |
354 | |
355 | /* Wait till previous write/erase is done. */ | |
356 | if (wait_till_ready(flash)) { | |
357 | /* REVISIT status return?? */ | |
7d5230ea | 358 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
359 | return 1; |
360 | } | |
361 | ||
fa0a8c71 DB |
362 | /* FIXME switch to OPCODE_FAST_READ. It's required for higher |
363 | * clocks; and at this writing, every chip this driver handles | |
364 | * supports that opcode. | |
365 | */ | |
2f9f7628 ML |
366 | |
367 | /* Set up the write data buffer. */ | |
368 | flash->command[0] = OPCODE_READ; | |
837479d2 | 369 | m25p_addr2cmd(flash, from, flash->command); |
2f9f7628 | 370 | |
2f9f7628 ML |
371 | spi_sync(flash->spi, &m); |
372 | ||
837479d2 | 373 | *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE; |
2f9f7628 | 374 | |
7d5230ea | 375 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
376 | |
377 | return 0; | |
378 | } | |
379 | ||
380 | /* | |
381 | * Write an address range to the flash chip. Data must be written in | |
382 | * FLASH_PAGESIZE chunks. The address range may be any size provided | |
383 | * it is within the physical boundaries. | |
384 | */ | |
385 | static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, | |
386 | size_t *retlen, const u_char *buf) | |
387 | { | |
388 | struct m25p *flash = mtd_to_m25p(mtd); | |
389 | u32 page_offset, page_size; | |
390 | struct spi_transfer t[2]; | |
391 | struct spi_message m; | |
392 | ||
393 | DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n", | |
160bbab3 | 394 | dev_name(&flash->spi->dev), __func__, "to", |
2f9f7628 ML |
395 | (u32)to, len); |
396 | ||
397 | if (retlen) | |
398 | *retlen = 0; | |
399 | ||
400 | /* sanity checks */ | |
401 | if (!len) | |
402 | return(0); | |
403 | ||
404 | if (to + len > flash->mtd.size) | |
405 | return -EINVAL; | |
406 | ||
8275c642 VW |
407 | spi_message_init(&m); |
408 | memset(t, 0, (sizeof t)); | |
409 | ||
410 | t[0].tx_buf = flash->command; | |
837479d2 | 411 | t[0].len = m25p_cmdsz(flash); |
8275c642 VW |
412 | spi_message_add_tail(&t[0], &m); |
413 | ||
414 | t[1].tx_buf = buf; | |
415 | spi_message_add_tail(&t[1], &m); | |
416 | ||
7d5230ea | 417 | mutex_lock(&flash->lock); |
2f9f7628 ML |
418 | |
419 | /* Wait until finished previous write command. */ | |
bc018863 CG |
420 | if (wait_till_ready(flash)) { |
421 | mutex_unlock(&flash->lock); | |
2f9f7628 | 422 | return 1; |
bc018863 | 423 | } |
2f9f7628 ML |
424 | |
425 | write_enable(flash); | |
426 | ||
2f9f7628 ML |
427 | /* Set up the opcode in the write buffer. */ |
428 | flash->command[0] = OPCODE_PP; | |
837479d2 | 429 | m25p_addr2cmd(flash, to, flash->command); |
2f9f7628 | 430 | |
837479d2 | 431 | page_offset = to & (flash->page_size - 1); |
2f9f7628 ML |
432 | |
433 | /* do all the bytes fit onto one page? */ | |
837479d2 | 434 | if (page_offset + len <= flash->page_size) { |
2f9f7628 ML |
435 | t[1].len = len; |
436 | ||
437 | spi_sync(flash->spi, &m); | |
438 | ||
837479d2 | 439 | *retlen = m.actual_length - m25p_cmdsz(flash); |
2f9f7628 ML |
440 | } else { |
441 | u32 i; | |
442 | ||
443 | /* the size of data remaining on the first page */ | |
837479d2 | 444 | page_size = flash->page_size - page_offset; |
2f9f7628 | 445 | |
2f9f7628 ML |
446 | t[1].len = page_size; |
447 | spi_sync(flash->spi, &m); | |
448 | ||
837479d2 | 449 | *retlen = m.actual_length - m25p_cmdsz(flash); |
2f9f7628 | 450 | |
837479d2 | 451 | /* write everything in flash->page_size chunks */ |
2f9f7628 ML |
452 | for (i = page_size; i < len; i += page_size) { |
453 | page_size = len - i; | |
837479d2 AV |
454 | if (page_size > flash->page_size) |
455 | page_size = flash->page_size; | |
2f9f7628 ML |
456 | |
457 | /* write the next page to flash */ | |
837479d2 | 458 | m25p_addr2cmd(flash, to + i, flash->command); |
2f9f7628 ML |
459 | |
460 | t[1].tx_buf = buf + i; | |
461 | t[1].len = page_size; | |
462 | ||
463 | wait_till_ready(flash); | |
464 | ||
465 | write_enable(flash); | |
466 | ||
467 | spi_sync(flash->spi, &m); | |
468 | ||
7111763d | 469 | if (retlen) |
837479d2 | 470 | *retlen += m.actual_length - m25p_cmdsz(flash); |
7d5230ea DB |
471 | } |
472 | } | |
2f9f7628 | 473 | |
7d5230ea | 474 | mutex_unlock(&flash->lock); |
2f9f7628 ML |
475 | |
476 | return 0; | |
477 | } | |
478 | ||
49aac4ae GY |
479 | static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, |
480 | size_t *retlen, const u_char *buf) | |
481 | { | |
482 | struct m25p *flash = mtd_to_m25p(mtd); | |
483 | struct spi_transfer t[2]; | |
484 | struct spi_message m; | |
485 | size_t actual; | |
486 | int cmd_sz, ret; | |
487 | ||
488 | if (retlen) | |
489 | *retlen = 0; | |
490 | ||
491 | /* sanity checks */ | |
492 | if (!len) | |
493 | return 0; | |
494 | ||
495 | if (to + len > flash->mtd.size) | |
496 | return -EINVAL; | |
497 | ||
498 | spi_message_init(&m); | |
499 | memset(t, 0, (sizeof t)); | |
500 | ||
501 | t[0].tx_buf = flash->command; | |
837479d2 | 502 | t[0].len = m25p_cmdsz(flash); |
49aac4ae GY |
503 | spi_message_add_tail(&t[0], &m); |
504 | ||
505 | t[1].tx_buf = buf; | |
506 | spi_message_add_tail(&t[1], &m); | |
507 | ||
508 | mutex_lock(&flash->lock); | |
509 | ||
510 | /* Wait until finished previous write command. */ | |
511 | ret = wait_till_ready(flash); | |
512 | if (ret) | |
513 | goto time_out; | |
514 | ||
515 | write_enable(flash); | |
516 | ||
517 | actual = to % 2; | |
518 | /* Start write from odd address. */ | |
519 | if (actual) { | |
520 | flash->command[0] = OPCODE_BP; | |
837479d2 | 521 | m25p_addr2cmd(flash, to, flash->command); |
49aac4ae GY |
522 | |
523 | /* write one byte. */ | |
524 | t[1].len = 1; | |
525 | spi_sync(flash->spi, &m); | |
526 | ret = wait_till_ready(flash); | |
527 | if (ret) | |
528 | goto time_out; | |
837479d2 | 529 | *retlen += m.actual_length - m25p_cmdsz(flash); |
49aac4ae GY |
530 | } |
531 | to += actual; | |
532 | ||
533 | flash->command[0] = OPCODE_AAI_WP; | |
837479d2 | 534 | m25p_addr2cmd(flash, to, flash->command); |
49aac4ae GY |
535 | |
536 | /* Write out most of the data here. */ | |
837479d2 | 537 | cmd_sz = m25p_cmdsz(flash); |
49aac4ae GY |
538 | for (; actual < len - 1; actual += 2) { |
539 | t[0].len = cmd_sz; | |
540 | /* write two bytes. */ | |
541 | t[1].len = 2; | |
542 | t[1].tx_buf = buf + actual; | |
543 | ||
544 | spi_sync(flash->spi, &m); | |
545 | ret = wait_till_ready(flash); | |
546 | if (ret) | |
547 | goto time_out; | |
548 | *retlen += m.actual_length - cmd_sz; | |
549 | cmd_sz = 1; | |
550 | to += 2; | |
551 | } | |
552 | write_disable(flash); | |
553 | ret = wait_till_ready(flash); | |
554 | if (ret) | |
555 | goto time_out; | |
556 | ||
557 | /* Write out trailing byte if it exists. */ | |
558 | if (actual != len) { | |
559 | write_enable(flash); | |
560 | flash->command[0] = OPCODE_BP; | |
837479d2 AV |
561 | m25p_addr2cmd(flash, to, flash->command); |
562 | t[0].len = m25p_cmdsz(flash); | |
49aac4ae GY |
563 | t[1].len = 1; |
564 | t[1].tx_buf = buf + actual; | |
565 | ||
566 | spi_sync(flash->spi, &m); | |
567 | ret = wait_till_ready(flash); | |
568 | if (ret) | |
569 | goto time_out; | |
837479d2 | 570 | *retlen += m.actual_length - m25p_cmdsz(flash); |
49aac4ae GY |
571 | write_disable(flash); |
572 | } | |
573 | ||
574 | time_out: | |
575 | mutex_unlock(&flash->lock); | |
576 | return ret; | |
577 | } | |
2f9f7628 ML |
578 | |
579 | /****************************************************************************/ | |
580 | ||
581 | /* | |
582 | * SPI device driver setup and teardown | |
583 | */ | |
584 | ||
585 | struct flash_info { | |
fa0a8c71 DB |
586 | /* JEDEC id zero means "no ID" (most older chips); otherwise it has |
587 | * a high byte of zero plus three data bytes: the manufacturer id, | |
588 | * then a two byte device id. | |
589 | */ | |
590 | u32 jedec_id; | |
d0e8c47c | 591 | u16 ext_id; |
fa0a8c71 DB |
592 | |
593 | /* The size listed here is what works with OPCODE_SE, which isn't | |
594 | * necessarily called a "sector" by the vendor. | |
595 | */ | |
2f9f7628 | 596 | unsigned sector_size; |
fa0a8c71 DB |
597 | u16 n_sectors; |
598 | ||
837479d2 AV |
599 | u16 page_size; |
600 | u16 addr_width; | |
601 | ||
fa0a8c71 DB |
602 | u16 flags; |
603 | #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ | |
837479d2 | 604 | #define M25P_NO_ERASE 0x02 /* No erase command needed */ |
2f9f7628 ML |
605 | }; |
606 | ||
b34bc037 AV |
607 | #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ |
608 | ((kernel_ulong_t)&(struct flash_info) { \ | |
609 | .jedec_id = (_jedec_id), \ | |
610 | .ext_id = (_ext_id), \ | |
611 | .sector_size = (_sector_size), \ | |
612 | .n_sectors = (_n_sectors), \ | |
837479d2 AV |
613 | .page_size = 256, \ |
614 | .addr_width = 3, \ | |
b34bc037 AV |
615 | .flags = (_flags), \ |
616 | }) | |
fa0a8c71 | 617 | |
837479d2 AV |
618 | #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \ |
619 | ((kernel_ulong_t)&(struct flash_info) { \ | |
620 | .sector_size = (_sector_size), \ | |
621 | .n_sectors = (_n_sectors), \ | |
622 | .page_size = (_page_size), \ | |
623 | .addr_width = (_addr_width), \ | |
624 | .flags = M25P_NO_ERASE, \ | |
625 | }) | |
fa0a8c71 DB |
626 | |
627 | /* NOTE: double check command sets and memory organization when you add | |
628 | * more flash chips. This current list focusses on newer chips, which | |
629 | * have been converging on command sets which including JEDEC ID. | |
630 | */ | |
b34bc037 | 631 | static const struct spi_device_id m25p_ids[] = { |
fa0a8c71 | 632 | /* Atmel -- some are (confusingly) marketed as "DataFlash" */ |
b34bc037 AV |
633 | { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, |
634 | { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, | |
fa0a8c71 | 635 | |
b34bc037 AV |
636 | { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, |
637 | { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, | |
fa0a8c71 | 638 | |
b34bc037 AV |
639 | { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, |
640 | { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, | |
641 | { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, | |
642 | { "at26df321", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, | |
fa0a8c71 | 643 | |
60845e72 GJ |
644 | /* EON -- en25pxx */ |
645 | { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, | |
646 | { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, | |
647 | ||
f80e521c GJ |
648 | /* Intel/Numonyx -- xxxs33b */ |
649 | { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, | |
650 | { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, | |
651 | { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, | |
652 | ||
ab1ff210 | 653 | /* Macronix */ |
df0094d7 | 654 | { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, |
6175f4a1 | 655 | { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, |
b34bc037 AV |
656 | { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) }, |
657 | { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) }, | |
658 | { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, | |
659 | { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, | |
ab1ff210 | 660 | |
fa0a8c71 DB |
661 | /* Spansion -- single (large) sector size only, at least |
662 | * for the chips listed here (without boot sectors). | |
663 | */ | |
b34bc037 AV |
664 | { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, |
665 | { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, | |
666 | { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, | |
667 | { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, | |
668 | { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, | |
669 | { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, | |
670 | { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, | |
671 | { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) }, | |
672 | { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) }, | |
fa0a8c71 DB |
673 | |
674 | /* SST -- large erase sizes are "overlays", "sectors" are 4K */ | |
b34bc037 AV |
675 | { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) }, |
676 | { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K) }, | |
677 | { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K) }, | |
678 | { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K) }, | |
679 | { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K) }, | |
680 | { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) }, | |
681 | { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) }, | |
682 | { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) }, | |
fa0a8c71 DB |
683 | |
684 | /* ST Microelectronics -- newer production may have feature updates */ | |
b34bc037 AV |
685 | { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, |
686 | { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, | |
687 | { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, | |
688 | { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, | |
689 | { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, | |
690 | { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, | |
691 | { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, | |
692 | { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, | |
693 | { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, | |
694 | ||
f7b00090 AV |
695 | { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, |
696 | { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, | |
697 | { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, | |
698 | { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, | |
699 | { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, | |
700 | { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, | |
701 | { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, | |
702 | { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, | |
703 | { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, | |
704 | ||
b34bc037 AV |
705 | { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, |
706 | { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, | |
707 | { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, | |
708 | ||
709 | { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, | |
710 | { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, | |
fa0a8c71 | 711 | |
02d087db | 712 | /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ |
b34bc037 AV |
713 | { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, |
714 | { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, | |
715 | { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, | |
716 | { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, | |
717 | { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, | |
718 | { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, | |
0af18d27 | 719 | { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, |
b34bc037 | 720 | { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, |
837479d2 AV |
721 | |
722 | /* Catalyst / On Semiconductor -- non-JEDEC */ | |
723 | { "cat25c11", CAT25_INFO( 16, 8, 16, 1) }, | |
724 | { "cat25c03", CAT25_INFO( 32, 8, 16, 2) }, | |
725 | { "cat25c09", CAT25_INFO( 128, 8, 32, 2) }, | |
726 | { "cat25c17", CAT25_INFO( 256, 8, 32, 2) }, | |
727 | { "cat25128", CAT25_INFO(2048, 8, 64, 2) }, | |
b34bc037 | 728 | { }, |
2f9f7628 | 729 | }; |
b34bc037 | 730 | MODULE_DEVICE_TABLE(spi, m25p_ids); |
2f9f7628 | 731 | |
b34bc037 | 732 | static const struct spi_device_id *__devinit jedec_probe(struct spi_device *spi) |
fa0a8c71 DB |
733 | { |
734 | int tmp; | |
735 | u8 code = OPCODE_RDID; | |
daa84735 | 736 | u8 id[5]; |
fa0a8c71 | 737 | u32 jedec; |
d0e8c47c | 738 | u16 ext_jedec; |
fa0a8c71 DB |
739 | struct flash_info *info; |
740 | ||
741 | /* JEDEC also defines an optional "extended device information" | |
742 | * string for after vendor-specific data, after the three bytes | |
743 | * we use here. Supporting some chips might require using it. | |
744 | */ | |
daa84735 | 745 | tmp = spi_write_then_read(spi, &code, 1, id, 5); |
fa0a8c71 DB |
746 | if (tmp < 0) { |
747 | DEBUG(MTD_DEBUG_LEVEL0, "%s: error %d reading JEDEC ID\n", | |
160bbab3 | 748 | dev_name(&spi->dev), tmp); |
9d2c4f3f | 749 | return ERR_PTR(tmp); |
fa0a8c71 DB |
750 | } |
751 | jedec = id[0]; | |
752 | jedec = jedec << 8; | |
753 | jedec |= id[1]; | |
754 | jedec = jedec << 8; | |
755 | jedec |= id[2]; | |
756 | ||
d0e8c47c CG |
757 | ext_jedec = id[3] << 8 | id[4]; |
758 | ||
b34bc037 AV |
759 | for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) { |
760 | info = (void *)m25p_ids[tmp].driver_data; | |
a3d3f73c | 761 | if (info->jedec_id == jedec) { |
9168ab86 | 762 | if (info->ext_id != 0 && info->ext_id != ext_jedec) |
d0e8c47c | 763 | continue; |
b34bc037 | 764 | return &m25p_ids[tmp]; |
a3d3f73c | 765 | } |
fa0a8c71 | 766 | } |
9d2c4f3f | 767 | return ERR_PTR(-ENODEV); |
fa0a8c71 DB |
768 | } |
769 | ||
770 | ||
2f9f7628 ML |
771 | /* |
772 | * board specific setup should have ensured the SPI clock used here | |
773 | * matches what the READ command supports, at least until this driver | |
774 | * understands FAST_READ (for clocks over 25 MHz). | |
775 | */ | |
776 | static int __devinit m25p_probe(struct spi_device *spi) | |
777 | { | |
18c6182b | 778 | const struct spi_device_id *id = spi_get_device_id(spi); |
2f9f7628 ML |
779 | struct flash_platform_data *data; |
780 | struct m25p *flash; | |
781 | struct flash_info *info; | |
782 | unsigned i; | |
783 | ||
784 | /* Platform data helps sort out which chip type we have, as | |
fa0a8c71 DB |
785 | * well as how this board partitions it. If we don't have |
786 | * a chip ID, try the JEDEC id commands; they'll work for most | |
787 | * newer chips, even if we don't recognize the particular chip. | |
2f9f7628 ML |
788 | */ |
789 | data = spi->dev.platform_data; | |
fa0a8c71 | 790 | if (data && data->type) { |
18c6182b | 791 | const struct spi_device_id *plat_id; |
2f9f7628 | 792 | |
b34bc037 | 793 | for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) { |
18c6182b AV |
794 | plat_id = &m25p_ids[i]; |
795 | if (strcmp(data->type, plat_id->name)) | |
b34bc037 AV |
796 | continue; |
797 | break; | |
fa0a8c71 | 798 | } |
fa0a8c71 | 799 | |
18c6182b AV |
800 | if (plat_id) |
801 | id = plat_id; | |
802 | else | |
803 | dev_warn(&spi->dev, "unrecognized id %s\n", data->type); | |
b34bc037 | 804 | } |
fa0a8c71 | 805 | |
18c6182b AV |
806 | info = (void *)id->driver_data; |
807 | ||
808 | if (info->jedec_id) { | |
809 | const struct spi_device_id *jid; | |
810 | ||
811 | jid = jedec_probe(spi); | |
9d2c4f3f AV |
812 | if (IS_ERR(jid)) { |
813 | return PTR_ERR(jid); | |
18c6182b AV |
814 | } else if (jid != id) { |
815 | /* | |
816 | * JEDEC knows better, so overwrite platform ID. We | |
817 | * can't trust partitions any longer, but we'll let | |
818 | * mtd apply them anyway, since some partitions may be | |
819 | * marked read-only, and we don't want to lose that | |
820 | * information, even if it's not 100% accurate. | |
821 | */ | |
822 | dev_warn(&spi->dev, "found %s, expected %s\n", | |
823 | jid->name, id->name); | |
824 | id = jid; | |
825 | info = (void *)jid->driver_data; | |
826 | } | |
827 | } | |
2f9f7628 | 828 | |
e94b1766 | 829 | flash = kzalloc(sizeof *flash, GFP_KERNEL); |
2f9f7628 ML |
830 | if (!flash) |
831 | return -ENOMEM; | |
837479d2 | 832 | flash->command = kmalloc(MAX_CMD_SIZE + FAST_READ_DUMMY_BYTE, GFP_KERNEL); |
61c3506c JS |
833 | if (!flash->command) { |
834 | kfree(flash); | |
835 | return -ENOMEM; | |
836 | } | |
2f9f7628 ML |
837 | |
838 | flash->spi = spi; | |
7d5230ea | 839 | mutex_init(&flash->lock); |
2f9f7628 ML |
840 | dev_set_drvdata(&spi->dev, flash); |
841 | ||
72289824 | 842 | /* |
f80e521c | 843 | * Atmel, SST and Intel/Numonyx serial flash tend to power |
ea60658a | 844 | * up with the software protection bits set |
72289824 MH |
845 | */ |
846 | ||
ea60658a | 847 | if (info->jedec_id >> 16 == 0x1f || |
f80e521c | 848 | info->jedec_id >> 16 == 0x89 || |
ea60658a | 849 | info->jedec_id >> 16 == 0xbf) { |
72289824 MH |
850 | write_enable(flash); |
851 | write_sr(flash, 0); | |
852 | } | |
853 | ||
fa0a8c71 | 854 | if (data && data->name) |
2f9f7628 ML |
855 | flash->mtd.name = data->name; |
856 | else | |
160bbab3 | 857 | flash->mtd.name = dev_name(&spi->dev); |
2f9f7628 ML |
858 | |
859 | flash->mtd.type = MTD_NORFLASH; | |
783ed81f | 860 | flash->mtd.writesize = 1; |
2f9f7628 ML |
861 | flash->mtd.flags = MTD_CAP_NORFLASH; |
862 | flash->mtd.size = info->sector_size * info->n_sectors; | |
2f9f7628 ML |
863 | flash->mtd.erase = m25p80_erase; |
864 | flash->mtd.read = m25p80_read; | |
49aac4ae GY |
865 | |
866 | /* sst flash chips use AAI word program */ | |
867 | if (info->jedec_id >> 16 == 0xbf) | |
868 | flash->mtd.write = sst_write; | |
869 | else | |
870 | flash->mtd.write = m25p80_write; | |
2f9f7628 | 871 | |
fa0a8c71 DB |
872 | /* prefer "small sector" erase if possible */ |
873 | if (info->flags & SECT_4K) { | |
874 | flash->erase_opcode = OPCODE_BE_4K; | |
875 | flash->mtd.erasesize = 4096; | |
876 | } else { | |
877 | flash->erase_opcode = OPCODE_SE; | |
878 | flash->mtd.erasesize = info->sector_size; | |
879 | } | |
880 | ||
837479d2 AV |
881 | if (info->flags & M25P_NO_ERASE) |
882 | flash->mtd.flags |= MTD_NO_ERASE; | |
883 | ||
87f39f04 | 884 | flash->mtd.dev.parent = &spi->dev; |
837479d2 AV |
885 | flash->page_size = info->page_size; |
886 | flash->addr_width = info->addr_width; | |
87f39f04 | 887 | |
b34bc037 | 888 | dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name, |
d85316ac | 889 | (long long)flash->mtd.size >> 10); |
2f9f7628 ML |
890 | |
891 | DEBUG(MTD_DEBUG_LEVEL2, | |
d85316ac | 892 | "mtd .name = %s, .size = 0x%llx (%lldMiB) " |
02d087db | 893 | ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", |
2f9f7628 | 894 | flash->mtd.name, |
d85316ac | 895 | (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20), |
2f9f7628 ML |
896 | flash->mtd.erasesize, flash->mtd.erasesize / 1024, |
897 | flash->mtd.numeraseregions); | |
898 | ||
899 | if (flash->mtd.numeraseregions) | |
900 | for (i = 0; i < flash->mtd.numeraseregions; i++) | |
901 | DEBUG(MTD_DEBUG_LEVEL2, | |
d85316ac | 902 | "mtd.eraseregions[%d] = { .offset = 0x%llx, " |
02d087db | 903 | ".erasesize = 0x%.8x (%uKiB), " |
2f9f7628 | 904 | ".numblocks = %d }\n", |
d85316ac | 905 | i, (long long)flash->mtd.eraseregions[i].offset, |
2f9f7628 ML |
906 | flash->mtd.eraseregions[i].erasesize, |
907 | flash->mtd.eraseregions[i].erasesize / 1024, | |
908 | flash->mtd.eraseregions[i].numblocks); | |
909 | ||
910 | ||
911 | /* partitions should match sector boundaries; and it may be good to | |
912 | * use readonly partitions for writeprotected sectors (BP2..BP0). | |
913 | */ | |
914 | if (mtd_has_partitions()) { | |
915 | struct mtd_partition *parts = NULL; | |
916 | int nr_parts = 0; | |
917 | ||
a4b6d516 DB |
918 | if (mtd_has_cmdlinepart()) { |
919 | static const char *part_probes[] | |
920 | = { "cmdlinepart", NULL, }; | |
2f9f7628 | 921 | |
a4b6d516 DB |
922 | nr_parts = parse_mtd_partitions(&flash->mtd, |
923 | part_probes, &parts, 0); | |
924 | } | |
2f9f7628 ML |
925 | |
926 | if (nr_parts <= 0 && data && data->parts) { | |
927 | parts = data->parts; | |
928 | nr_parts = data->nr_parts; | |
929 | } | |
930 | ||
931 | if (nr_parts > 0) { | |
fa0a8c71 | 932 | for (i = 0; i < nr_parts; i++) { |
2f9f7628 | 933 | DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = " |
d85316ac AB |
934 | "{.name = %s, .offset = 0x%llx, " |
935 | ".size = 0x%llx (%lldKiB) }\n", | |
fa0a8c71 | 936 | i, parts[i].name, |
d85316ac AB |
937 | (long long)parts[i].offset, |
938 | (long long)parts[i].size, | |
939 | (long long)(parts[i].size >> 10)); | |
2f9f7628 ML |
940 | } |
941 | flash->partitioned = 1; | |
942 | return add_mtd_partitions(&flash->mtd, parts, nr_parts); | |
943 | } | |
edcb3b14 | 944 | } else if (data && data->nr_parts) |
2f9f7628 ML |
945 | dev_warn(&spi->dev, "ignoring %d default partitions on %s\n", |
946 | data->nr_parts, data->name); | |
947 | ||
948 | return add_mtd_device(&flash->mtd) == 1 ? -ENODEV : 0; | |
949 | } | |
950 | ||
951 | ||
952 | static int __devexit m25p_remove(struct spi_device *spi) | |
953 | { | |
954 | struct m25p *flash = dev_get_drvdata(&spi->dev); | |
955 | int status; | |
956 | ||
957 | /* Clean up MTD stuff. */ | |
958 | if (mtd_has_partitions() && flash->partitioned) | |
959 | status = del_mtd_partitions(&flash->mtd); | |
960 | else | |
961 | status = del_mtd_device(&flash->mtd); | |
61c3506c JS |
962 | if (status == 0) { |
963 | kfree(flash->command); | |
2f9f7628 | 964 | kfree(flash); |
61c3506c | 965 | } |
2f9f7628 ML |
966 | return 0; |
967 | } | |
968 | ||
969 | ||
970 | static struct spi_driver m25p80_driver = { | |
971 | .driver = { | |
972 | .name = "m25p80", | |
973 | .bus = &spi_bus_type, | |
974 | .owner = THIS_MODULE, | |
975 | }, | |
b34bc037 | 976 | .id_table = m25p_ids, |
2f9f7628 ML |
977 | .probe = m25p_probe, |
978 | .remove = __devexit_p(m25p_remove), | |
fa0a8c71 DB |
979 | |
980 | /* REVISIT: many of these chips have deep power-down modes, which | |
981 | * should clearly be entered on suspend() to minimize power use. | |
982 | * And also when they're otherwise idle... | |
983 | */ | |
2f9f7628 ML |
984 | }; |
985 | ||
986 | ||
627df23c | 987 | static int __init m25p80_init(void) |
2f9f7628 ML |
988 | { |
989 | return spi_register_driver(&m25p80_driver); | |
990 | } | |
991 | ||
992 | ||
627df23c | 993 | static void __exit m25p80_exit(void) |
2f9f7628 ML |
994 | { |
995 | spi_unregister_driver(&m25p80_driver); | |
996 | } | |
997 | ||
998 | ||
999 | module_init(m25p80_init); | |
1000 | module_exit(m25p80_exit); | |
1001 | ||
1002 | MODULE_LICENSE("GPL"); | |
1003 | MODULE_AUTHOR("Mike Lavender"); | |
1004 | MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips"); |