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tifm: use bus methods to handle probe/remove instead of driver ones.
[net-next-2.6.git] / drivers / mmc / tifm_sd.c
CommitLineData
4020f2d7
AD		 1/*
2 * tifm_sd.c - TI FlashMedia driver
3 *
4 * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12
13#include <linux/tifm.h>
14#include <linux/mmc/protocol.h>
15#include <linux/mmc/host.h>
16#include <linux/highmem.h>
2099c99e 17#include <asm/io.h>
4020f2d7
AD		 18
19#define DRIVER_NAME "tifm_sd"
4552f0cb 20#define DRIVER_VERSION "0.8"
4020f2d7
AD		 21
22static int no_dma = 0;
23static int fixed_timeout = 0;
24module_param(no_dma, bool, 0644);
25module_param(fixed_timeout, bool, 0644);
26
27/* Constants here are mostly from OMAP5912 datasheet */
28#define TIFM_MMCSD_RESET 0x0002
29#define TIFM_MMCSD_CLKMASK 0x03ff
30#define TIFM_MMCSD_POWER 0x0800
31#define TIFM_MMCSD_4BBUS 0x8000
32#define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
33#define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
34#define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
35#define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
36#define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
37#define TIFM_MMCSD_READ 0x8000
38
12c83452
AD		 39#define TIFM_MMCSD_DATAMASK 0x401d /* set bits: CERR, EOFB, BRS, CB, EOC */
40#define TIFM_MMCSD_ERRMASK 0x01e0 /* set bits: CCRC, CTO, DCRC, DTO */
4020f2d7
AD		 41#define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
42#define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
43#define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
44#define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
45#define TIFM_MMCSD_DTO 0x0020 /* data time-out */
46#define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
47#define TIFM_MMCSD_CTO 0x0080 /* command time-out */
48#define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
49#define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
50#define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
51#define TIFM_MMCSD_CERR 0x4000 /* card status error */
52
53#define TIFM_MMCSD_FIFO_SIZE 0x0020
54
55#define TIFM_MMCSD_RSP_R0 0x0000
56#define TIFM_MMCSD_RSP_R1 0x0100
57#define TIFM_MMCSD_RSP_R2 0x0200
58#define TIFM_MMCSD_RSP_R3 0x0300
59#define TIFM_MMCSD_RSP_R4 0x0400
60#define TIFM_MMCSD_RSP_R5 0x0500
61#define TIFM_MMCSD_RSP_R6 0x0600
62
63#define TIFM_MMCSD_RSP_BUSY 0x0800
64
65#define TIFM_MMCSD_CMD_BC 0x0000
66#define TIFM_MMCSD_CMD_BCR 0x1000
67#define TIFM_MMCSD_CMD_AC 0x2000
68#define TIFM_MMCSD_CMD_ADTC 0x3000
69
70typedef enum {
71 IDLE = 0,
72 CMD, /* main command ended */
73 BRS, /* block transfer finished */
74 SCMD, /* stop command ended */
75 CARD, /* card left busy state */
76 FIFO, /* FIFO operation completed (uncertain) */
77 READY
78} card_state_t;
79
80enum {
81 FIFO_RDY = 0x0001, /* hardware dependent value */
4020f2d7
AD		 82 EJECT = 0x0004,
83 EJECT_DONE = 0x0008,
84 CARD_BUSY = 0x0010,
85 OPENDRAIN = 0x0040, /* hardware dependent value */
86 CARD_EVENT = 0x0100, /* hardware dependent value */
87 CARD_RO = 0x0200, /* hardware dependent value */
88 FIFO_EVENT = 0x10000 }; /* hardware dependent value */
89
90struct tifm_sd {
91 struct tifm_dev *dev;
92
93 unsigned int flags;
94 card_state_t state;
95 unsigned int clk_freq;
96 unsigned int clk_div;
0803dd0c 97 unsigned long timeout_jiffies;
4020f2d7 98
8e02f858 99 struct tasklet_struct finish_tasklet;
0803dd0c 100 struct timer_list timer;
4020f2d7 101 struct mmc_request *req;
8e02f858 102 wait_queue_head_t notify;
4020f2d7
AD		 103
104 size_t written_blocks;
4020f2d7
AD		 105 size_t buffer_size;
106 size_t buffer_pos;
107
108};
109
f9d429a2 110static char* tifm_sd_data_buffer(struct mmc_data *data)
255ef22e 111{
f9d429a2 112 return page_address(data->sg->page) + data->sg->offset;
255ef22e
AD		 113}
114
4020f2d7 115static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
2e8ce5e7 116 unsigned int host_status)
4020f2d7
AD		 117{
118 struct mmc_command *cmd = host->req->cmd;
119 unsigned int t_val = 0, cnt = 0;
255ef22e 120 char *buffer;
4020f2d7
AD		 121
122 if (host_status & TIFM_MMCSD_BRS) {
123 /* in non-dma rx mode BRS fires when fifo is still not empty */
255ef22e 124 if (no_dma && (cmd->data->flags & MMC_DATA_READ)) {
f9d429a2 125 buffer = tifm_sd_data_buffer(host->req->data);
4020f2d7
AD		 126 while (host->buffer_size > host->buffer_pos) {
127 t_val = readl(sock->addr + SOCK_MMCSD_DATA);
255ef22e
AD		 128 buffer[host->buffer_pos++] = t_val & 0xff;
129 buffer[host->buffer_pos++] =
4020f2d7
AD		 130 (t_val >> 8) & 0xff;
131 }
132 }
133 return 1;
255ef22e 134 } else if (no_dma) {
f9d429a2 135 buffer = tifm_sd_data_buffer(host->req->data);
4020f2d7
AD		 136 if ((cmd->data->flags & MMC_DATA_READ) &&
137 (host_status & TIFM_MMCSD_AF)) {
138 for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
139 t_val = readl(sock->addr + SOCK_MMCSD_DATA);
140 if (host->buffer_size > host->buffer_pos) {
255ef22e 141 buffer[host->buffer_pos++] =
4020f2d7 142 t_val & 0xff;
255ef22e 143 buffer[host->buffer_pos++] =
4020f2d7
AD		 144 (t_val >> 8) & 0xff;
145 }
146 }
147 } else if ((cmd->data->flags & MMC_DATA_WRITE)
148 && (host_status & TIFM_MMCSD_AE)) {
149 for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
150 if (host->buffer_size > host->buffer_pos) {
255ef22e
AD		 151 t_val = buffer[host->buffer_pos++]
152 & 0x00ff;
153 t_val |= ((buffer[host->buffer_pos++])
154 << 8) & 0xff00;
4020f2d7 155 writel(t_val,
2e8ce5e7 156 sock->addr + SOCK_MMCSD_DATA);
4020f2d7
AD		 157 }
158 }
159 }
160 }
161 return 0;
162}
163
164static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
165{
166 unsigned int rc = 0;
167
168 switch (mmc_resp_type(cmd)) {
169 case MMC_RSP_NONE:
170 rc |= TIFM_MMCSD_RSP_R0;
171 break;
172 case MMC_RSP_R1B:
173 rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
174 case MMC_RSP_R1:
175 rc |= TIFM_MMCSD_RSP_R1;
176 break;
177 case MMC_RSP_R2:
178 rc |= TIFM_MMCSD_RSP_R2;
179 break;
180 case MMC_RSP_R3:
181 rc |= TIFM_MMCSD_RSP_R3;
182 break;
4020f2d7
AD		 183 default:
184 BUG();
185 }
186
187 switch (mmc_cmd_type(cmd)) {
188 case MMC_CMD_BC:
189 rc |= TIFM_MMCSD_CMD_BC;
190 break;
191 case MMC_CMD_BCR:
192 rc |= TIFM_MMCSD_CMD_BCR;
193 break;
194 case MMC_CMD_AC:
195 rc |= TIFM_MMCSD_CMD_AC;
196 break;
197 case MMC_CMD_ADTC:
198 rc |= TIFM_MMCSD_CMD_ADTC;
199 break;
200 default:
201 BUG();
202 }
203 return rc;
204}
205
206static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
207{
208 struct tifm_dev *sock = host->dev;
209 unsigned int cmd_mask = tifm_sd_op_flags(cmd) |
210 (host->flags & OPENDRAIN);
211
212 if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
213 cmd_mask |= TIFM_MMCSD_READ;
214
215 dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
2e8ce5e7 216 cmd->opcode, cmd->arg, cmd_mask);
4020f2d7
AD		 217
218 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
219 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
220 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
221}
222
223static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
224{
225 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
226 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
227 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
228 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
229 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
230 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
231 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
232 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
233}
234
235static void tifm_sd_process_cmd(struct tifm_dev *sock, struct tifm_sd *host,
236 unsigned int host_status)
237{
238 struct mmc_command *cmd = host->req->cmd;
239
240change_state:
241 switch (host->state) {
242 case IDLE:
243 return;
244 case CMD:
12c83452 245 if (host_status & (TIFM_MMCSD_EOC | TIFM_MMCSD_CERR)) {
4020f2d7
AD		 246 tifm_sd_fetch_resp(cmd, sock);
247 if (cmd->data) {
248 host->state = BRS;
1289335a 249 } else {
4020f2d7 250 host->state = READY;
1289335a 251 }
4020f2d7
AD		 252 goto change_state;
253 }
254 break;
255 case BRS:
256 if (tifm_sd_transfer_data(sock, host, host_status)) {
1289335a
AD		 257 if (cmd->data->flags & MMC_DATA_WRITE) {
258 host->state = CARD;
259 } else {
260 if (no_dma) {
261 if (host->req->stop) {
262 tifm_sd_exec(host, host->req->stop);
263 host->state = SCMD;
264 } else {
265 host->state = READY;
266 }
4020f2d7 267 } else {
1289335a 268 host->state = FIFO;
4020f2d7 269 }
4020f2d7 270 }
1289335a 271 goto change_state;
4020f2d7
AD		 272 }
273 break;
274 case SCMD:
275 if (host_status & TIFM_MMCSD_EOC) {
276 tifm_sd_fetch_resp(host->req->stop, sock);
1289335a 277 host->state = READY;
4020f2d7
AD		 278 goto change_state;
279 }
280 break;
281 case CARD:
1289335a
AD		 282 dev_dbg(&sock->dev, "waiting for CARD, have %zd blocks\n",
283 host->written_blocks);
4020f2d7
AD		 284 if (!(host->flags & CARD_BUSY)
285 && (host->written_blocks == cmd->data->blocks)) {
1289335a
AD		 286 if (no_dma) {
287 if (host->req->stop) {
288 tifm_sd_exec(host, host->req->stop);
289 host->state = SCMD;
290 } else {
291 host->state = READY;
292 }
293 } else {
294 host->state = FIFO;
295 }
4020f2d7
AD		 296 goto change_state;
297 }
298 break;
299 case FIFO:
300 if (host->flags & FIFO_RDY) {
4020f2d7 301 host->flags &= ~FIFO_RDY;
1289335a
AD		 302 if (host->req->stop) {
303 tifm_sd_exec(host, host->req->stop);
304 host->state = SCMD;
305 } else {
306 host->state = READY;
307 }
4020f2d7
AD		 308 goto change_state;
309 }
310 break;
311 case READY:
8e02f858 312 tasklet_schedule(&host->finish_tasklet);
4020f2d7
AD		 313 return;
314 }
315
4020f2d7
AD		 316}
317
318/* Called from interrupt handler */
4552f0cb 319static void tifm_sd_data_event(struct tifm_dev *sock)
4020f2d7
AD		 320{
321 struct tifm_sd *host;
4552f0cb 322 unsigned int fifo_status = 0;
4020f2d7
AD		 323
324 spin_lock(&sock->lock);
325 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
4020f2d7 326
4552f0cb
AD		 327 fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
328 writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
329
330 host->flags |= fifo_status & FIFO_RDY;
331
332 if (host->req)
333 tifm_sd_process_cmd(sock, host, 0);
334
335 dev_dbg(&sock->dev, "fifo_status %x\n", fifo_status);
336 spin_unlock(&sock->lock);
337
338}
339
340/* Called from interrupt handler */
341static void tifm_sd_card_event(struct tifm_dev *sock)
342{
343 struct tifm_sd *host;
344 unsigned int host_status = 0;
345 int error_code = 0;
346
347 spin_lock(&sock->lock);
348 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
4020f2d7 349
4020f2d7 350
4020f2d7
AD		 351 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
352 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
353
4020f2d7
AD		 354 if (!host->req)
355 goto done;
356
357 if (host_status & TIFM_MMCSD_ERRMASK) {
12c83452 358 if (host_status & (TIFM_MMCSD_CTO | TIFM_MMCSD_DTO))
4020f2d7 359 error_code = MMC_ERR_TIMEOUT;
2e8ce5e7
AD		 360 else if (host_status
361 & (TIFM_MMCSD_CCRC | TIFM_MMCSD_DCRC))
4020f2d7
AD		 362 error_code = MMC_ERR_BADCRC;
363
364 writel(TIFM_FIFO_INT_SETALL,
365 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
366 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
367
368 if (host->req->stop) {
369 if (host->state == SCMD) {
370 host->req->stop->error = error_code;
1289335a
AD		 371 } else if (host->state == BRS
372 || host->state == CARD
373 || host->state == FIFO) {
4020f2d7
AD		 374 host->req->cmd->error = error_code;
375 tifm_sd_exec(host, host->req->stop);
4020f2d7
AD		 376 host->state = SCMD;
377 goto done;
378 } else {
379 host->req->cmd->error = error_code;
380 }
381 } else {
382 host->req->cmd->error = error_code;
383 }
384 host->state = READY;
385 }
386
387 if (host_status & TIFM_MMCSD_CB)
388 host->flags |= CARD_BUSY;
2e8ce5e7
AD		 389 if ((host_status & TIFM_MMCSD_EOFB)
390 && (host->flags & CARD_BUSY)) {
4020f2d7
AD		 391 host->written_blocks++;
392 host->flags &= ~CARD_BUSY;
393 }
4020f2d7
AD		 394
395 if (host->req)
396 tifm_sd_process_cmd(sock, host, host_status);
397done:
4552f0cb 398 dev_dbg(&sock->dev, "host_status %x\n", host_status);
4020f2d7 399 spin_unlock(&sock->lock);
4020f2d7
AD		 400}
401
2e8ce5e7 402static void tifm_sd_prepare_data(struct tifm_sd *host, struct mmc_command *cmd)
4020f2d7 403{
2e8ce5e7 404 struct tifm_dev *sock = host->dev;
4020f2d7
AD		 405 unsigned int dest_cnt;
406
407 /* DMA style IO */
2e8ce5e7
AD		 408 dev_dbg(&sock->dev, "setting dma for %d blocks\n",
409 cmd->data->blocks);
4020f2d7 410 writel(TIFM_FIFO_INT_SETALL,
2e8ce5e7 411 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
f0d1b0b3 412 writel(ilog2(cmd->data->blksz) - 2,
2e8ce5e7 413 sock->addr + SOCK_FIFO_PAGE_SIZE);
4020f2d7
AD		 414 writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
415 writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
416
417 dest_cnt = (cmd->data->blocks) << 8;
418
419 writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
420
421 writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
422 writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
423
424 if (cmd->data->flags & MMC_DATA_WRITE) {
425 writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
426 writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
2e8ce5e7 427 sock->addr + SOCK_DMA_CONTROL);
4020f2d7
AD		 428 } else {
429 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
430 writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
431 }
432}
433
434static void tifm_sd_set_data_timeout(struct tifm_sd *host,
2e8ce5e7 435 struct mmc_data *data)
4020f2d7
AD		 436{
437 struct tifm_dev *sock = host->dev;
438 unsigned int data_timeout = data->timeout_clks;
439
440 if (fixed_timeout)
441 return;
442
443 data_timeout += data->timeout_ns /
83d420ba 444 ((1000000000UL / host->clk_freq) * host->clk_div);
4020f2d7
AD		 445
446 if (data_timeout < 0xffff) {
4020f2d7 447 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
83d420ba
AD		 448 writel((~TIFM_MMCSD_DPE)
449 & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
450 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
4020f2d7 451 } else {
4020f2d7 452 data_timeout = (data_timeout >> 10) + 1;
2e8ce5e7 453 if (data_timeout > 0xffff)
4020f2d7
AD		 454 data_timeout = 0; /* set to unlimited */
455 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
83d420ba
AD		 456 writel(TIFM_MMCSD_DPE
457 | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
458 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
4020f2d7
AD		 459 }
460}
461
462static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
463{
464 struct tifm_sd *host = mmc_priv(mmc);
465 struct tifm_dev *sock = host->dev;
466 unsigned long flags;
467 int sg_count = 0;
468 struct mmc_data *r_data = mrq->cmd->data;
469
470 spin_lock_irqsave(&sock->lock, flags);
471 if (host->flags & EJECT) {
472 spin_unlock_irqrestore(&sock->lock, flags);
473 goto err_out;
474 }
475
476 if (host->req) {
477 printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
478 spin_unlock_irqrestore(&sock->lock, flags);
479 goto err_out;
480 }
481
482 if (r_data) {
483 tifm_sd_set_data_timeout(host, r_data);
484
485 sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
486 mrq->cmd->flags & MMC_DATA_WRITE
487 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
488 if (sg_count != 1) {
489 printk(KERN_ERR DRIVER_NAME
490 ": scatterlist map failed\n");
491 spin_unlock_irqrestore(&sock->lock, flags);
492 goto err_out;
493 }
494
495 host->written_blocks = 0;
496 host->flags &= ~CARD_BUSY;
497 tifm_sd_prepare_data(host, mrq->cmd);
498 }
499
500 host->req = mrq;
0803dd0c 501 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
4020f2d7 502 host->state = CMD;
4020f2d7 503 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 504 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 505 tifm_sd_exec(host, mrq->cmd);
506 spin_unlock_irqrestore(&sock->lock, flags);
507 return;
508
509err_out:
510 if (sg_count > 0)
511 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
512 (r_data->flags & MMC_DATA_WRITE)
513 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
514
515 mrq->cmd->error = MMC_ERR_TIMEOUT;
516 mmc_request_done(mmc, mrq);
517}
518
8e02f858 519static void tifm_sd_end_cmd(unsigned long data)
4020f2d7 520{
8e02f858 521 struct tifm_sd *host = (struct tifm_sd*)data;
4020f2d7
AD		 522 struct tifm_dev *sock = host->dev;
523 struct mmc_host *mmc = tifm_get_drvdata(sock);
524 struct mmc_request *mrq;
e069d79d 525 struct mmc_data *r_data = NULL;
4020f2d7
AD		 526 unsigned long flags;
527
528 spin_lock_irqsave(&sock->lock, flags);
529
0803dd0c 530 del_timer(&host->timer);
4020f2d7 531 mrq = host->req;
e069d79d 532 host->req = NULL;
4020f2d7
AD		 533 host->state = IDLE;
534
535 if (!mrq) {
536 printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
537 spin_unlock_irqrestore(&sock->lock, flags);
538 return;
539 }
540
541 r_data = mrq->cmd->data;
542 if (r_data) {
543 if (r_data->flags & MMC_DATA_WRITE) {
2e8ce5e7
AD		 544 r_data->bytes_xfered = host->written_blocks
545 * r_data->blksz;
4020f2d7
AD		 546 } else {
547 r_data->bytes_xfered = r_data->blocks -
548 readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
549 r_data->bytes_xfered *= r_data->blksz;
550 r_data->bytes_xfered += r_data->blksz -
551 readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
552 }
553 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
554 (r_data->flags & MMC_DATA_WRITE)
555 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
556 }
557
558 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 559 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 560
561 spin_unlock_irqrestore(&sock->lock, flags);
562 mmc_request_done(mmc, mrq);
563}
564
565static void tifm_sd_request_nodma(struct mmc_host *mmc, struct mmc_request *mrq)
566{
567 struct tifm_sd *host = mmc_priv(mmc);
568 struct tifm_dev *sock = host->dev;
569 unsigned long flags;
570 struct mmc_data *r_data = mrq->cmd->data;
4020f2d7
AD		 571
572 spin_lock_irqsave(&sock->lock, flags);
573 if (host->flags & EJECT) {
574 spin_unlock_irqrestore(&sock->lock, flags);
575 goto err_out;
576 }
577
578 if (host->req) {
579 printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
580 spin_unlock_irqrestore(&sock->lock, flags);
581 goto err_out;
582 }
583
584 if (r_data) {
585 tifm_sd_set_data_timeout(host, r_data);
586
2e8ce5e7
AD		 587 host->buffer_size = mrq->cmd->data->blocks
588 * mrq->cmd->data->blksz;
4020f2d7 589
2e8ce5e7
AD		 590 writel(TIFM_MMCSD_BUFINT
591 | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
4020f2d7 592 sock->addr + SOCK_MMCSD_INT_ENABLE);
2e8ce5e7
AD		 593 writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
594 | (TIFM_MMCSD_FIFO_SIZE - 1),
4020f2d7
AD		 595 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
596
597 host->written_blocks = 0;
598 host->flags &= ~CARD_BUSY;
599 host->buffer_pos = 0;
600 writel(r_data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
601 writel(r_data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
602 }
603
604 host->req = mrq;
0803dd0c 605 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
4020f2d7 606 host->state = CMD;
4020f2d7 607 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 608 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 609 tifm_sd_exec(host, mrq->cmd);
610 spin_unlock_irqrestore(&sock->lock, flags);
611 return;
612
613err_out:
4020f2d7
AD		 614 mrq->cmd->error = MMC_ERR_TIMEOUT;
615 mmc_request_done(mmc, mrq);
616}
617
8e02f858 618static void tifm_sd_end_cmd_nodma(unsigned long data)
4020f2d7 619{
8e02f858 620 struct tifm_sd *host = (struct tifm_sd*)data;
4020f2d7
AD		 621 struct tifm_dev *sock = host->dev;
622 struct mmc_host *mmc = tifm_get_drvdata(sock);
623 struct mmc_request *mrq;
e069d79d 624 struct mmc_data *r_data = NULL;
4020f2d7
AD		 625 unsigned long flags;
626
627 spin_lock_irqsave(&sock->lock, flags);
628
0803dd0c 629 del_timer(&host->timer);
4020f2d7 630 mrq = host->req;
e069d79d 631 host->req = NULL;
4020f2d7
AD		 632 host->state = IDLE;
633
634 if (!mrq) {
635 printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
636 spin_unlock_irqrestore(&sock->lock, flags);
637 return;
638 }
639
640 r_data = mrq->cmd->data;
641 if (r_data) {
642 writel((~TIFM_MMCSD_BUFINT) &
643 readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
644 sock->addr + SOCK_MMCSD_INT_ENABLE);
645
646 if (r_data->flags & MMC_DATA_WRITE) {
2e8ce5e7
AD		 647 r_data->bytes_xfered = host->written_blocks
648 * r_data->blksz;
4020f2d7
AD		 649 } else {
650 r_data->bytes_xfered = r_data->blocks -
651 readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
652 r_data->bytes_xfered *= r_data->blksz;
653 r_data->bytes_xfered += r_data->blksz -
654 readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
655 }
4020f2d7
AD		 656 host->buffer_pos = 0;
657 host->buffer_size = 0;
658 }
659
660 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 661 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 662
663 spin_unlock_irqrestore(&sock->lock, flags);
664
4020f2d7
AD		 665 mmc_request_done(mmc, mrq);
666}
667
8e02f858
AD		 668static void tifm_sd_terminate(struct tifm_sd *host)
669{
670 struct tifm_dev *sock = host->dev;
671 unsigned long flags;
672
673 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
674 mmiowb();
675 spin_lock_irqsave(&sock->lock, flags);
676 host->flags |= EJECT;
677 if (host->req) {
678 writel(TIFM_FIFO_INT_SETALL,
679 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
680 writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
681 tasklet_schedule(&host->finish_tasklet);
682 }
683 spin_unlock_irqrestore(&sock->lock, flags);
684}
685
0803dd0c 686static void tifm_sd_abort(unsigned long data)
4020f2d7 687{
8e02f858
AD		 688 struct tifm_sd *host = (struct tifm_sd*)data;
689
4020f2d7 690 printk(KERN_ERR DRIVER_NAME
0803dd0c 691 ": card failed to respond for a long period of time");
8e02f858
AD		 692
693 tifm_sd_terminate(host);
694 tifm_eject(host->dev);
4020f2d7
AD		 695}
696
697static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
698{
699 struct tifm_sd *host = mmc_priv(mmc);
700 struct tifm_dev *sock = host->dev;
701 unsigned int clk_div1, clk_div2;
702 unsigned long flags;
703
704 spin_lock_irqsave(&sock->lock, flags);
705
706 dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
707 ios->power_mode);
708 if (ios->bus_width == MMC_BUS_WIDTH_4) {
709 writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
710 sock->addr + SOCK_MMCSD_CONFIG);
711 } else {
2e8ce5e7
AD		 712 writel((~TIFM_MMCSD_4BBUS)
713 & readl(sock->addr + SOCK_MMCSD_CONFIG),
714 sock->addr + SOCK_MMCSD_CONFIG);
4020f2d7
AD		 715 }
716
717 if (ios->clock) {
718 clk_div1 = 20000000 / ios->clock;
719 if (!clk_div1)
720 clk_div1 = 1;
721
722 clk_div2 = 24000000 / ios->clock;
723 if (!clk_div2)
724 clk_div2 = 1;
725
726 if ((20000000 / clk_div1) > ios->clock)
727 clk_div1++;
728 if ((24000000 / clk_div2) > ios->clock)
729 clk_div2++;
730 if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
731 host->clk_freq = 20000000;
732 host->clk_div = clk_div1;
2e8ce5e7
AD		 733 writel((~TIFM_CTRL_FAST_CLK)
734 & readl(sock->addr + SOCK_CONTROL),
735 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 736 } else {
737 host->clk_freq = 24000000;
738 host->clk_div = clk_div2;
2e8ce5e7
AD		 739 writel(TIFM_CTRL_FAST_CLK
740 | readl(sock->addr + SOCK_CONTROL),
741 sock->addr + SOCK_CONTROL);
4020f2d7
AD		 742 }
743 } else {
744 host->clk_div = 0;
745 }
746 host->clk_div &= TIFM_MMCSD_CLKMASK;
2e8ce5e7
AD		 747 writel(host->clk_div
748 | ((~TIFM_MMCSD_CLKMASK)
749 & readl(sock->addr + SOCK_MMCSD_CONFIG)),
750 sock->addr + SOCK_MMCSD_CONFIG);
4020f2d7
AD		 751
752 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
753 host->flags |= OPENDRAIN;
754 else
755 host->flags &= ~OPENDRAIN;
756
757 /* chip_select : maybe later */
758 //vdd
759 //power is set before probe / after remove
760 //I believe, power_off when already marked for eject is sufficient to
761 // allow removal.
762 if ((host->flags & EJECT) && ios->power_mode == MMC_POWER_OFF) {
763 host->flags |= EJECT_DONE;
8e02f858 764 wake_up_all(&host->notify);
4020f2d7
AD		 765 }
766
767 spin_unlock_irqrestore(&sock->lock, flags);
768}
769
770static int tifm_sd_ro(struct mmc_host *mmc)
771{
772 int rc;
773 struct tifm_sd *host = mmc_priv(mmc);
774 struct tifm_dev *sock = host->dev;
775 unsigned long flags;
776
777 spin_lock_irqsave(&sock->lock, flags);
778
779 host->flags |= (CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE));
780 rc = (host->flags & CARD_RO) ? 1 : 0;
781
782 spin_unlock_irqrestore(&sock->lock, flags);
783 return rc;
784}
785
786static struct mmc_host_ops tifm_sd_ops = {
787 .request = tifm_sd_request,
788 .set_ios = tifm_sd_ios,
789 .get_ro = tifm_sd_ro
790};
791
8e02f858 792static int tifm_sd_initialize_host(struct tifm_sd *host)
4020f2d7 793{
8e02f858
AD		 794 int rc;
795 unsigned int host_status = 0;
4020f2d7 796 struct tifm_dev *sock = host->dev;
4020f2d7 797
8e02f858
AD		 798 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
799 mmiowb();
800 host->clk_div = 61;
801 host->clk_freq = 20000000;
802 writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
803 writel(host->clk_div | TIFM_MMCSD_POWER,
804 sock->addr + SOCK_MMCSD_CONFIG);
805
806 /* wait up to 0.51 sec for reset */
807 for (rc = 2; rc <= 256; rc <<= 1) {
808 if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
809 rc = 0;
810 break;
811 }
812 msleep(rc);
813 }
814
815 if (rc) {
816 printk(KERN_ERR DRIVER_NAME
817 ": controller failed to reset\n");
818 return -ENODEV;
819 }
820
821 writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
822 writel(host->clk_div | TIFM_MMCSD_POWER,
823 sock->addr + SOCK_MMCSD_CONFIG);
824 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
825
826 // command timeout fixed to 64 clocks for now
827 writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
828 writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
829
830 /* INAB should take much less than reset */
831 for (rc = 1; rc <= 16; rc <<= 1) {
832 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
833 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
834 if (!(host_status & TIFM_MMCSD_ERRMASK)
835 && (host_status & TIFM_MMCSD_EOC)) {
836 rc = 0;
837 break;
838 }
839 msleep(rc);
840 }
841
842 if (rc) {
843 printk(KERN_ERR DRIVER_NAME
844 ": card not ready - probe failed on initialization\n");
845 return -ENODEV;
846 }
847
848 writel(TIFM_MMCSD_DATAMASK | TIFM_MMCSD_ERRMASK,
849 sock->addr + SOCK_MMCSD_INT_ENABLE);
850 mmiowb();
851
852 return 0;
4020f2d7
AD		 853}
854
855static int tifm_sd_probe(struct tifm_dev *sock)
856{
857 struct mmc_host *mmc;
858 struct tifm_sd *host;
859 int rc = -EIO;
860
2e8ce5e7
AD		 861 if (!(TIFM_SOCK_STATE_OCCUPIED
862 & readl(sock->addr + SOCK_PRESENT_STATE))) {
4020f2d7
AD		 863 printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
864 return rc;
865 }
866
867 mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
868 if (!mmc)
869 return -ENOMEM;
870
871 host = mmc_priv(mmc);
4020f2d7 872 tifm_set_drvdata(sock, mmc);
8e02f858 873 host->dev = sock;
4020f2d7
AD		 874 host->timeout_jiffies = msecs_to_jiffies(1000);
875
8e02f858
AD		 876 init_waitqueue_head(&host->notify);
877 tasklet_init(&host->finish_tasklet,
878 no_dma ? tifm_sd_end_cmd_nodma : tifm_sd_end_cmd,
879 (unsigned long)host);
880 setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
881
4020f2d7
AD		 882 tifm_sd_ops.request = no_dma ? tifm_sd_request_nodma : tifm_sd_request;
883 mmc->ops = &tifm_sd_ops;
884 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
8e02f858 885 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE;
4020f2d7
AD		 886 mmc->f_min = 20000000 / 60;
887 mmc->f_max = 24000000;
888 mmc->max_hw_segs = 1;
889 mmc->max_phys_segs = 1;
55db890a
PO		 890 // limited by DMA counter - it's safer to stick with
891 // block counter has 11 bits though
892 mmc->max_blk_count = 256;
893 // 2k maximum hw block length
fe4a3c7a 894 mmc->max_blk_size = 2048;
55db890a
PO		 895 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
896 mmc->max_seg_size = mmc->max_req_size;
4552f0cb
AD		 897 sock->card_event = tifm_sd_card_event;
898 sock->data_event = tifm_sd_data_event;
8e02f858 899 rc = tifm_sd_initialize_host(host);
4020f2d7 900
8e02f858
AD		 901 if (!rc)
902 rc = mmc_add_host(mmc);
903 if (rc)
904 goto out_free_mmc;
4020f2d7
AD		 905
906 return 0;
8e02f858
AD		 907out_free_mmc:
908 mmc_free_host(mmc);
4020f2d7
AD		 909 return rc;
910}
911
912static void tifm_sd_remove(struct tifm_dev *sock)
913{
914 struct mmc_host *mmc = tifm_get_drvdata(sock);
915 struct tifm_sd *host = mmc_priv(mmc);
4020f2d7 916
0803dd0c 917 del_timer_sync(&host->timer);
8e02f858
AD		 918 tifm_sd_terminate(host);
919 wait_event_timeout(host->notify, host->flags & EJECT_DONE,
920 host->timeout_jiffies);
921 tasklet_kill(&host->finish_tasklet);
922 mmc_remove_host(mmc);
4020f2d7
AD		 923
924 /* The meaning of the bit majority in this constant is unknown. */
925 writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
2e8ce5e7 926 sock->addr + SOCK_CONTROL);
4020f2d7 927
e069d79d 928 tifm_set_drvdata(sock, NULL);
4020f2d7
AD		 929 mmc_free_host(mmc);
930}
931
dba4acca
AD		 932#ifdef CONFIG_PM
933
934static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
935{
936 struct mmc_host *mmc = tifm_get_drvdata(sock);
937 int rc;
938
939 rc = mmc_suspend_host(mmc, state);
940 /* The meaning of the bit majority in this constant is unknown. */
941 writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
942 sock->addr + SOCK_CONTROL);
943 return rc;
944}
945
946static int tifm_sd_resume(struct tifm_dev *sock)
947{
948 struct mmc_host *mmc = tifm_get_drvdata(sock);
949 struct tifm_sd *host = mmc_priv(mmc);
950
951 if (sock->media_id != FM_SD
952 || tifm_sd_initialize_host(host)) {
953 tifm_eject(sock);
954 return 0;
955 } else {
956 return mmc_resume_host(mmc);
957 }
958}
959
960#else
961
962#define tifm_sd_suspend NULL
963#define tifm_sd_resume NULL
964
965#endif /* CONFIG_PM */
966
4020f2d7
AD		 967static tifm_media_id tifm_sd_id_tbl[] = {
968 FM_SD, 0
969};
970
971static struct tifm_driver tifm_sd_driver = {
972 .driver = {
973 .name = DRIVER_NAME,
974 .owner = THIS_MODULE
975 },
976 .id_table = tifm_sd_id_tbl,
977 .probe = tifm_sd_probe,
dba4acca
AD		 978 .remove = tifm_sd_remove,
979 .suspend = tifm_sd_suspend,
980 .resume = tifm_sd_resume
4020f2d7
AD		 981};
982
983static int __init tifm_sd_init(void)
984{
985 return tifm_register_driver(&tifm_sd_driver);
986}
987
988static void __exit tifm_sd_exit(void)
989{
990 tifm_unregister_driver(&tifm_sd_driver);
991}
992
993MODULE_AUTHOR("Alex Dubov");
994MODULE_DESCRIPTION("TI FlashMedia SD driver");
995MODULE_LICENSE("GPL");
996MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
997MODULE_VERSION(DRIVER_VERSION);
998
999module_init(tifm_sd_init);
1000module_exit(tifm_sd_exit);
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