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tifm_sd: fix hardware timeout setup
[net-next-2.6.git] / drivers / mmc / tifm_sd.c
CommitLineData
4020f2d7
AD		 1/*
2 * tifm_sd.c - TI FlashMedia driver
3 *
4 * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12
13#include <linux/tifm.h>
14#include <linux/mmc/protocol.h>
15#include <linux/mmc/host.h>
16#include <linux/highmem.h>
2099c99e 17#include <asm/io.h>
4020f2d7
AD		 18
19#define DRIVER_NAME "tifm_sd"
1289335a 20#define DRIVER_VERSION "0.7"
4020f2d7
AD		 21
22static int no_dma = 0;
23static int fixed_timeout = 0;
24module_param(no_dma, bool, 0644);
25module_param(fixed_timeout, bool, 0644);
26
27/* Constants here are mostly from OMAP5912 datasheet */
28#define TIFM_MMCSD_RESET 0x0002
29#define TIFM_MMCSD_CLKMASK 0x03ff
30#define TIFM_MMCSD_POWER 0x0800
31#define TIFM_MMCSD_4BBUS 0x8000
32#define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
33#define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
34#define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
35#define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
36#define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
37#define TIFM_MMCSD_READ 0x8000
38
39#define TIFM_MMCSD_DATAMASK 0x001d /* set bits: EOFB, BRS, CB, EOC */
40#define TIFM_MMCSD_ERRMASK 0x41e0 /* set bits: CERR, CCRC, CTO, DCRC, DTO */
41#define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
42#define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
43#define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
44#define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
45#define TIFM_MMCSD_DTO 0x0020 /* data time-out */
46#define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
47#define TIFM_MMCSD_CTO 0x0080 /* command time-out */
48#define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
49#define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
50#define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
51#define TIFM_MMCSD_CERR 0x4000 /* card status error */
52
53#define TIFM_MMCSD_FIFO_SIZE 0x0020
54
55#define TIFM_MMCSD_RSP_R0 0x0000
56#define TIFM_MMCSD_RSP_R1 0x0100
57#define TIFM_MMCSD_RSP_R2 0x0200
58#define TIFM_MMCSD_RSP_R3 0x0300
59#define TIFM_MMCSD_RSP_R4 0x0400
60#define TIFM_MMCSD_RSP_R5 0x0500
61#define TIFM_MMCSD_RSP_R6 0x0600
62
63#define TIFM_MMCSD_RSP_BUSY 0x0800
64
65#define TIFM_MMCSD_CMD_BC 0x0000
66#define TIFM_MMCSD_CMD_BCR 0x1000
67#define TIFM_MMCSD_CMD_AC 0x2000
68#define TIFM_MMCSD_CMD_ADTC 0x3000
69
70typedef enum {
71 IDLE = 0,
72 CMD, /* main command ended */
73 BRS, /* block transfer finished */
74 SCMD, /* stop command ended */
75 CARD, /* card left busy state */
76 FIFO, /* FIFO operation completed (uncertain) */
77 READY
78} card_state_t;
79
80enum {
81 FIFO_RDY = 0x0001, /* hardware dependent value */
82 HOST_REG = 0x0002,
83 EJECT = 0x0004,
84 EJECT_DONE = 0x0008,
85 CARD_BUSY = 0x0010,
86 OPENDRAIN = 0x0040, /* hardware dependent value */
87 CARD_EVENT = 0x0100, /* hardware dependent value */
88 CARD_RO = 0x0200, /* hardware dependent value */
89 FIFO_EVENT = 0x10000 }; /* hardware dependent value */
90
91struct tifm_sd {
92 struct tifm_dev *dev;
93
94 unsigned int flags;
95 card_state_t state;
96 unsigned int clk_freq;
97 unsigned int clk_div;
0803dd0c 98 unsigned long timeout_jiffies;
4020f2d7 99
0803dd0c 100 struct timer_list timer;
4020f2d7
AD		 101 struct mmc_request *req;
102 struct work_struct cmd_handler;
4020f2d7
AD		 103 wait_queue_head_t can_eject;
104
105 size_t written_blocks;
4020f2d7
AD		 106 size_t buffer_size;
107 size_t buffer_pos;
108
109};
110
255ef22e
AD		 111static char* tifm_sd_kmap_atomic(struct mmc_data *data)
112{
113 return kmap_atomic(data->sg->page, KM_BIO_SRC_IRQ) + data->sg->offset;
114}
115
116static void tifm_sd_kunmap_atomic(char *buffer, struct mmc_data *data)
117{
118 kunmap_atomic(buffer - data->sg->offset, KM_BIO_SRC_IRQ);
119}
120
4020f2d7
AD		 121static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
122 unsigned int host_status)
123{
124 struct mmc_command *cmd = host->req->cmd;
125 unsigned int t_val = 0, cnt = 0;
255ef22e 126 char *buffer;
4020f2d7
AD		 127
128 if (host_status & TIFM_MMCSD_BRS) {
129 /* in non-dma rx mode BRS fires when fifo is still not empty */
255ef22e
AD		 130 if (no_dma && (cmd->data->flags & MMC_DATA_READ)) {
131 buffer = tifm_sd_kmap_atomic(host->req->data);
4020f2d7
AD		 132 while (host->buffer_size > host->buffer_pos) {
133 t_val = readl(sock->addr + SOCK_MMCSD_DATA);
255ef22e
AD		 134 buffer[host->buffer_pos++] = t_val & 0xff;
135 buffer[host->buffer_pos++] =
4020f2d7
AD		 136 (t_val >> 8) & 0xff;
137 }
255ef22e 138 tifm_sd_kunmap_atomic(buffer, host->req->data);
4020f2d7
AD		 139 }
140 return 1;
255ef22e
AD		 141 } else if (no_dma) {
142 buffer = tifm_sd_kmap_atomic(host->req->data);
4020f2d7
AD		 143 if ((cmd->data->flags & MMC_DATA_READ) &&
144 (host_status & TIFM_MMCSD_AF)) {
145 for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
146 t_val = readl(sock->addr + SOCK_MMCSD_DATA);
147 if (host->buffer_size > host->buffer_pos) {
255ef22e 148 buffer[host->buffer_pos++] =
4020f2d7 149 t_val & 0xff;
255ef22e 150 buffer[host->buffer_pos++] =
4020f2d7
AD		 151 (t_val >> 8) & 0xff;
152 }
153 }
154 } else if ((cmd->data->flags & MMC_DATA_WRITE)
155 && (host_status & TIFM_MMCSD_AE)) {
156 for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
157 if (host->buffer_size > host->buffer_pos) {
255ef22e
AD		 158 t_val = buffer[host->buffer_pos++]
159 & 0x00ff;
160 t_val |= ((buffer[host->buffer_pos++])
161 << 8) & 0xff00;
4020f2d7
AD		 162 writel(t_val,
163 sock->addr + SOCK_MMCSD_DATA);
164 }
165 }
166 }
255ef22e 167 tifm_sd_kunmap_atomic(buffer, host->req->data);
4020f2d7
AD		 168 }
169 return 0;
170}
171
172static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
173{
174 unsigned int rc = 0;
175
176 switch (mmc_resp_type(cmd)) {
177 case MMC_RSP_NONE:
178 rc |= TIFM_MMCSD_RSP_R0;
179 break;
180 case MMC_RSP_R1B:
181 rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
182 case MMC_RSP_R1:
183 rc |= TIFM_MMCSD_RSP_R1;
184 break;
185 case MMC_RSP_R2:
186 rc |= TIFM_MMCSD_RSP_R2;
187 break;
188 case MMC_RSP_R3:
189 rc |= TIFM_MMCSD_RSP_R3;
190 break;
4020f2d7
AD		 191 default:
192 BUG();
193 }
194
195 switch (mmc_cmd_type(cmd)) {
196 case MMC_CMD_BC:
197 rc |= TIFM_MMCSD_CMD_BC;
198 break;
199 case MMC_CMD_BCR:
200 rc |= TIFM_MMCSD_CMD_BCR;
201 break;
202 case MMC_CMD_AC:
203 rc |= TIFM_MMCSD_CMD_AC;
204 break;
205 case MMC_CMD_ADTC:
206 rc |= TIFM_MMCSD_CMD_ADTC;
207 break;
208 default:
209 BUG();
210 }
211 return rc;
212}
213
214static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
215{
216 struct tifm_dev *sock = host->dev;
217 unsigned int cmd_mask = tifm_sd_op_flags(cmd) |
218 (host->flags & OPENDRAIN);
219
220 if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
221 cmd_mask |= TIFM_MMCSD_READ;
222
223 dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
224 cmd->opcode, cmd->arg, cmd_mask);
225
226 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
227 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
228 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
229}
230
231static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
232{
233 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
234 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
235 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
236 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
237 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
238 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
239 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
240 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
241}
242
243static void tifm_sd_process_cmd(struct tifm_dev *sock, struct tifm_sd *host,
244 unsigned int host_status)
245{
246 struct mmc_command *cmd = host->req->cmd;
247
248change_state:
249 switch (host->state) {
250 case IDLE:
251 return;
252 case CMD:
253 if (host_status & TIFM_MMCSD_EOC) {
254 tifm_sd_fetch_resp(cmd, sock);
255 if (cmd->data) {
256 host->state = BRS;
1289335a 257 } else {
4020f2d7 258 host->state = READY;
1289335a 259 }
4020f2d7
AD		 260 goto change_state;
261 }
262 break;
263 case BRS:
264 if (tifm_sd_transfer_data(sock, host, host_status)) {
1289335a
AD		 265 if (cmd->data->flags & MMC_DATA_WRITE) {
266 host->state = CARD;
267 } else {
268 if (no_dma) {
269 if (host->req->stop) {
270 tifm_sd_exec(host, host->req->stop);
271 host->state = SCMD;
272 } else {
273 host->state = READY;
274 }
4020f2d7 275 } else {
1289335a 276 host->state = FIFO;
4020f2d7 277 }
4020f2d7 278 }
1289335a 279 goto change_state;
4020f2d7
AD		 280 }
281 break;
282 case SCMD:
283 if (host_status & TIFM_MMCSD_EOC) {
284 tifm_sd_fetch_resp(host->req->stop, sock);
1289335a 285 host->state = READY;
4020f2d7
AD		 286 goto change_state;
287 }
288 break;
289 case CARD:
1289335a
AD		 290 dev_dbg(&sock->dev, "waiting for CARD, have %zd blocks\n",
291 host->written_blocks);
4020f2d7
AD		 292 if (!(host->flags & CARD_BUSY)
293 && (host->written_blocks == cmd->data->blocks)) {
1289335a
AD		 294 if (no_dma) {
295 if (host->req->stop) {
296 tifm_sd_exec(host, host->req->stop);
297 host->state = SCMD;
298 } else {
299 host->state = READY;
300 }
301 } else {
302 host->state = FIFO;
303 }
4020f2d7
AD		 304 goto change_state;
305 }
306 break;
307 case FIFO:
308 if (host->flags & FIFO_RDY) {
4020f2d7 309 host->flags &= ~FIFO_RDY;
1289335a
AD		 310 if (host->req->stop) {
311 tifm_sd_exec(host, host->req->stop);
312 host->state = SCMD;
313 } else {
314 host->state = READY;
315 }
4020f2d7
AD		 316 goto change_state;
317 }
318 break;
319 case READY:
320 queue_work(sock->wq, &host->cmd_handler);
321 return;
322 }
323
4020f2d7
AD		 324}
325
326/* Called from interrupt handler */
327static unsigned int tifm_sd_signal_irq(struct tifm_dev *sock,
328 unsigned int sock_irq_status)
329{
330 struct tifm_sd *host;
331 unsigned int host_status = 0, fifo_status = 0;
332 int error_code = 0;
333
334 spin_lock(&sock->lock);
335 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
4020f2d7
AD		 336
337 if (sock_irq_status & FIFO_EVENT) {
338 fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
339 writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
340
341 host->flags |= fifo_status & FIFO_RDY;
342 }
343
344 if (sock_irq_status & CARD_EVENT) {
345 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
346 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
347
348 if (!(host->flags & HOST_REG))
349 queue_work(sock->wq, &host->cmd_handler);
350 if (!host->req)
351 goto done;
352
353 if (host_status & TIFM_MMCSD_ERRMASK) {
354 if (host_status & TIFM_MMCSD_CERR)
355 error_code = MMC_ERR_FAILED;
356 else if (host_status &
357 (TIFM_MMCSD_CTO | TIFM_MMCSD_DTO))
358 error_code = MMC_ERR_TIMEOUT;
359 else if (host_status &
360 (TIFM_MMCSD_CCRC | TIFM_MMCSD_DCRC))
361 error_code = MMC_ERR_BADCRC;
362
363 writel(TIFM_FIFO_INT_SETALL,
364 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
365 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
366
367 if (host->req->stop) {
368 if (host->state == SCMD) {
369 host->req->stop->error = error_code;
1289335a
AD		 370 } else if (host->state == BRS
371 || host->state == CARD
372 || host->state == FIFO) {
4020f2d7
AD		 373 host->req->cmd->error = error_code;
374 tifm_sd_exec(host, host->req->stop);
4020f2d7
AD		 375 host->state = SCMD;
376 goto done;
377 } else {
378 host->req->cmd->error = error_code;
379 }
380 } else {
381 host->req->cmd->error = error_code;
382 }
383 host->state = READY;
384 }
385
386 if (host_status & TIFM_MMCSD_CB)
387 host->flags |= CARD_BUSY;
388 if ((host_status & TIFM_MMCSD_EOFB) &&
389 (host->flags & CARD_BUSY)) {
390 host->written_blocks++;
391 host->flags &= ~CARD_BUSY;
392 }
393 }
394
395 if (host->req)
396 tifm_sd_process_cmd(sock, host, host_status);
397done:
398 dev_dbg(&sock->dev, "host_status %x, fifo_status %x\n",
399 host_status, fifo_status);
400 spin_unlock(&sock->lock);
401 return sock_irq_status;
402}
403
404static void tifm_sd_prepare_data(struct tifm_sd *card, struct mmc_command *cmd)
405{
406 struct tifm_dev *sock = card->dev;
407 unsigned int dest_cnt;
408
409 /* DMA style IO */
410
411 writel(TIFM_FIFO_INT_SETALL,
412 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
f0d1b0b3 413 writel(ilog2(cmd->data->blksz) - 2,
4020f2d7
AD		 414 sock->addr + SOCK_FIFO_PAGE_SIZE);
415 writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
416 writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
417
418 dest_cnt = (cmd->data->blocks) << 8;
419
420 writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
421
422 writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
423 writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
424
425 if (cmd->data->flags & MMC_DATA_WRITE) {
426 writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
427 writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
428 sock->addr + SOCK_DMA_CONTROL);
429 } else {
430 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
431 writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
432 }
433}
434
435static void tifm_sd_set_data_timeout(struct tifm_sd *host,
436 struct mmc_data *data)
437{
438 struct tifm_dev *sock = host->dev;
439 unsigned int data_timeout = data->timeout_clks;
440
441 if (fixed_timeout)
442 return;
443
444 data_timeout += data->timeout_ns /
83d420ba 445 ((1000000000UL / host->clk_freq) * host->clk_div);
4020f2d7
AD		 446
447 if (data_timeout < 0xffff) {
4020f2d7 448 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
83d420ba
AD		 449 writel((~TIFM_MMCSD_DPE)
450 & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
451 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
4020f2d7 452 } else {
4020f2d7
AD		 453 data_timeout = (data_timeout >> 10) + 1;
454 if(data_timeout > 0xffff)
455 data_timeout = 0; /* set to unlimited */
456 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
83d420ba
AD		 457 writel(TIFM_MMCSD_DPE
458 | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
459 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
4020f2d7
AD		 460 }
461}
462
463static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
464{
465 struct tifm_sd *host = mmc_priv(mmc);
466 struct tifm_dev *sock = host->dev;
467 unsigned long flags;
468 int sg_count = 0;
469 struct mmc_data *r_data = mrq->cmd->data;
470
471 spin_lock_irqsave(&sock->lock, flags);
472 if (host->flags & EJECT) {
473 spin_unlock_irqrestore(&sock->lock, flags);
474 goto err_out;
475 }
476
477 if (host->req) {
478 printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
479 spin_unlock_irqrestore(&sock->lock, flags);
480 goto err_out;
481 }
482
483 if (r_data) {
484 tifm_sd_set_data_timeout(host, r_data);
485
486 sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
487 mrq->cmd->flags & MMC_DATA_WRITE
488 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
489 if (sg_count != 1) {
490 printk(KERN_ERR DRIVER_NAME
491 ": scatterlist map failed\n");
492 spin_unlock_irqrestore(&sock->lock, flags);
493 goto err_out;
494 }
495
496 host->written_blocks = 0;
497 host->flags &= ~CARD_BUSY;
498 tifm_sd_prepare_data(host, mrq->cmd);
499 }
500
501 host->req = mrq;
0803dd0c 502 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
4020f2d7 503 host->state = CMD;
4020f2d7
AD		 504 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
505 sock->addr + SOCK_CONTROL);
506 tifm_sd_exec(host, mrq->cmd);
507 spin_unlock_irqrestore(&sock->lock, flags);
508 return;
509
510err_out:
511 if (sg_count > 0)
512 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
513 (r_data->flags & MMC_DATA_WRITE)
514 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
515
516 mrq->cmd->error = MMC_ERR_TIMEOUT;
517 mmc_request_done(mmc, mrq);
518}
519
c4028958 520static void tifm_sd_end_cmd(struct work_struct *work)
4020f2d7 521{
c4028958 522 struct tifm_sd *host = container_of(work, struct tifm_sd, cmd_handler);
4020f2d7
AD		 523 struct tifm_dev *sock = host->dev;
524 struct mmc_host *mmc = tifm_get_drvdata(sock);
525 struct mmc_request *mrq;
e069d79d 526 struct mmc_data *r_data = NULL;
4020f2d7
AD		 527 unsigned long flags;
528
529 spin_lock_irqsave(&sock->lock, flags);
530
0803dd0c 531 del_timer(&host->timer);
4020f2d7 532 mrq = host->req;
e069d79d 533 host->req = NULL;
4020f2d7
AD		 534 host->state = IDLE;
535
536 if (!mrq) {
537 printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
538 spin_unlock_irqrestore(&sock->lock, flags);
539 return;
540 }
541
542 r_data = mrq->cmd->data;
543 if (r_data) {
544 if (r_data->flags & MMC_DATA_WRITE) {
545 r_data->bytes_xfered = host->written_blocks *
546 r_data->blksz;
547 } else {
548 r_data->bytes_xfered = r_data->blocks -
549 readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
550 r_data->bytes_xfered *= r_data->blksz;
551 r_data->bytes_xfered += r_data->blksz -
552 readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
553 }
554 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
555 (r_data->flags & MMC_DATA_WRITE)
556 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
557 }
558
559 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
560 sock->addr + SOCK_CONTROL);
561
562 spin_unlock_irqrestore(&sock->lock, flags);
563 mmc_request_done(mmc, mrq);
564}
565
566static void tifm_sd_request_nodma(struct mmc_host *mmc, struct mmc_request *mrq)
567{
568 struct tifm_sd *host = mmc_priv(mmc);
569 struct tifm_dev *sock = host->dev;
570 unsigned long flags;
571 struct mmc_data *r_data = mrq->cmd->data;
4020f2d7
AD		 572
573 spin_lock_irqsave(&sock->lock, flags);
574 if (host->flags & EJECT) {
575 spin_unlock_irqrestore(&sock->lock, flags);
576 goto err_out;
577 }
578
579 if (host->req) {
580 printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
581 spin_unlock_irqrestore(&sock->lock, flags);
582 goto err_out;
583 }
584
585 if (r_data) {
586 tifm_sd_set_data_timeout(host, r_data);
587
4020f2d7
AD		 588 host->buffer_size = mrq->cmd->data->blocks *
589 mrq->cmd->data->blksz;
590
591 writel(TIFM_MMCSD_BUFINT |
592 readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
593 sock->addr + SOCK_MMCSD_INT_ENABLE);
594 writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8) |
595 (TIFM_MMCSD_FIFO_SIZE - 1),
596 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
597
598 host->written_blocks = 0;
599 host->flags &= ~CARD_BUSY;
600 host->buffer_pos = 0;
601 writel(r_data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
602 writel(r_data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
603 }
604
605 host->req = mrq;
0803dd0c 606 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
4020f2d7 607 host->state = CMD;
4020f2d7
AD		 608 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
609 sock->addr + SOCK_CONTROL);
610 tifm_sd_exec(host, mrq->cmd);
611 spin_unlock_irqrestore(&sock->lock, flags);
612 return;
613
614err_out:
4020f2d7
AD		 615 mrq->cmd->error = MMC_ERR_TIMEOUT;
616 mmc_request_done(mmc, mrq);
617}
618
c4028958 619static void tifm_sd_end_cmd_nodma(struct work_struct *work)
4020f2d7 620{
c4028958 621 struct tifm_sd *host = container_of(work, struct tifm_sd, cmd_handler);
4020f2d7
AD		 622 struct tifm_dev *sock = host->dev;
623 struct mmc_host *mmc = tifm_get_drvdata(sock);
624 struct mmc_request *mrq;
e069d79d 625 struct mmc_data *r_data = NULL;
4020f2d7
AD		 626 unsigned long flags;
627
628 spin_lock_irqsave(&sock->lock, flags);
629
0803dd0c 630 del_timer(&host->timer);
4020f2d7 631 mrq = host->req;
e069d79d 632 host->req = NULL;
4020f2d7
AD		 633 host->state = IDLE;
634
635 if (!mrq) {
636 printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
637 spin_unlock_irqrestore(&sock->lock, flags);
638 return;
639 }
640
641 r_data = mrq->cmd->data;
642 if (r_data) {
643 writel((~TIFM_MMCSD_BUFINT) &
644 readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
645 sock->addr + SOCK_MMCSD_INT_ENABLE);
646
647 if (r_data->flags & MMC_DATA_WRITE) {
648 r_data->bytes_xfered = host->written_blocks *
649 r_data->blksz;
650 } else {
651 r_data->bytes_xfered = r_data->blocks -
652 readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
653 r_data->bytes_xfered *= r_data->blksz;
654 r_data->bytes_xfered += r_data->blksz -
655 readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
656 }
4020f2d7
AD		 657 host->buffer_pos = 0;
658 host->buffer_size = 0;
659 }
660
661 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
662 sock->addr + SOCK_CONTROL);
663
664 spin_unlock_irqrestore(&sock->lock, flags);
665
4020f2d7
AD		 666 mmc_request_done(mmc, mrq);
667}
668
0803dd0c 669static void tifm_sd_abort(unsigned long data)
4020f2d7
AD		 670{
671 printk(KERN_ERR DRIVER_NAME
0803dd0c
AD		 672 ": card failed to respond for a long period of time");
673 tifm_eject(((struct tifm_sd*)data)->dev);
4020f2d7
AD		 674}
675
676static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
677{
678 struct tifm_sd *host = mmc_priv(mmc);
679 struct tifm_dev *sock = host->dev;
680 unsigned int clk_div1, clk_div2;
681 unsigned long flags;
682
683 spin_lock_irqsave(&sock->lock, flags);
684
685 dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
686 ios->power_mode);
687 if (ios->bus_width == MMC_BUS_WIDTH_4) {
688 writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
689 sock->addr + SOCK_MMCSD_CONFIG);
690 } else {
691 writel((~TIFM_MMCSD_4BBUS) &
692 readl(sock->addr + SOCK_MMCSD_CONFIG),
693 sock->addr + SOCK_MMCSD_CONFIG);
694 }
695
696 if (ios->clock) {
697 clk_div1 = 20000000 / ios->clock;
698 if (!clk_div1)
699 clk_div1 = 1;
700
701 clk_div2 = 24000000 / ios->clock;
702 if (!clk_div2)
703 clk_div2 = 1;
704
705 if ((20000000 / clk_div1) > ios->clock)
706 clk_div1++;
707 if ((24000000 / clk_div2) > ios->clock)
708 clk_div2++;
709 if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
710 host->clk_freq = 20000000;
711 host->clk_div = clk_div1;
712 writel((~TIFM_CTRL_FAST_CLK) &
713 readl(sock->addr + SOCK_CONTROL),
714 sock->addr + SOCK_CONTROL);
715 } else {
716 host->clk_freq = 24000000;
717 host->clk_div = clk_div2;
718 writel(TIFM_CTRL_FAST_CLK |
719 readl(sock->addr + SOCK_CONTROL),
720 sock->addr + SOCK_CONTROL);
721 }
722 } else {
723 host->clk_div = 0;
724 }
725 host->clk_div &= TIFM_MMCSD_CLKMASK;
726 writel(host->clk_div | ((~TIFM_MMCSD_CLKMASK) &
727 readl(sock->addr + SOCK_MMCSD_CONFIG)),
728 sock->addr + SOCK_MMCSD_CONFIG);
729
730 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
731 host->flags |= OPENDRAIN;
732 else
733 host->flags &= ~OPENDRAIN;
734
735 /* chip_select : maybe later */
736 //vdd
737 //power is set before probe / after remove
738 //I believe, power_off when already marked for eject is sufficient to
739 // allow removal.
740 if ((host->flags & EJECT) && ios->power_mode == MMC_POWER_OFF) {
741 host->flags |= EJECT_DONE;
742 wake_up_all(&host->can_eject);
743 }
744
745 spin_unlock_irqrestore(&sock->lock, flags);
746}
747
748static int tifm_sd_ro(struct mmc_host *mmc)
749{
750 int rc;
751 struct tifm_sd *host = mmc_priv(mmc);
752 struct tifm_dev *sock = host->dev;
753 unsigned long flags;
754
755 spin_lock_irqsave(&sock->lock, flags);
756
757 host->flags |= (CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE));
758 rc = (host->flags & CARD_RO) ? 1 : 0;
759
760 spin_unlock_irqrestore(&sock->lock, flags);
761 return rc;
762}
763
764static struct mmc_host_ops tifm_sd_ops = {
765 .request = tifm_sd_request,
766 .set_ios = tifm_sd_ios,
767 .get_ro = tifm_sd_ro
768};
769
c4028958 770static void tifm_sd_register_host(struct work_struct *work)
4020f2d7 771{
c4028958 772 struct tifm_sd *host = container_of(work, struct tifm_sd, cmd_handler);
4020f2d7
AD		 773 struct tifm_dev *sock = host->dev;
774 struct mmc_host *mmc = tifm_get_drvdata(sock);
775 unsigned long flags;
776
777 spin_lock_irqsave(&sock->lock, flags);
0803dd0c 778 del_timer(&host->timer);
4020f2d7
AD		 779 host->flags |= HOST_REG;
780 PREPARE_WORK(&host->cmd_handler,
c4028958 781 no_dma ? tifm_sd_end_cmd_nodma : tifm_sd_end_cmd);
4020f2d7
AD		 782 spin_unlock_irqrestore(&sock->lock, flags);
783 dev_dbg(&sock->dev, "adding host\n");
784 mmc_add_host(mmc);
785}
786
787static int tifm_sd_probe(struct tifm_dev *sock)
788{
789 struct mmc_host *mmc;
790 struct tifm_sd *host;
791 int rc = -EIO;
792
793 if (!(TIFM_SOCK_STATE_OCCUPIED &
794 readl(sock->addr + SOCK_PRESENT_STATE))) {
795 printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
796 return rc;
797 }
798
799 mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
800 if (!mmc)
801 return -ENOMEM;
802
803 host = mmc_priv(mmc);
804 host->dev = sock;
805 host->clk_div = 61;
806 init_waitqueue_head(&host->can_eject);
c4028958 807 INIT_WORK(&host->cmd_handler, tifm_sd_register_host);
0803dd0c 808 setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
4020f2d7
AD		 809
810 tifm_set_drvdata(sock, mmc);
811 sock->signal_irq = tifm_sd_signal_irq;
812
813 host->clk_freq = 20000000;
814 host->timeout_jiffies = msecs_to_jiffies(1000);
815
816 tifm_sd_ops.request = no_dma ? tifm_sd_request_nodma : tifm_sd_request;
817 mmc->ops = &tifm_sd_ops;
818 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
819 mmc->caps = MMC_CAP_4_BIT_DATA;
820 mmc->f_min = 20000000 / 60;
821 mmc->f_max = 24000000;
822 mmc->max_hw_segs = 1;
823 mmc->max_phys_segs = 1;
824 mmc->max_sectors = 127;
825 mmc->max_seg_size = mmc->max_sectors << 11; //2k maximum hw block length
826
827 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
828 writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
829 writel(host->clk_div | TIFM_MMCSD_POWER,
830 sock->addr + SOCK_MMCSD_CONFIG);
831
832 for (rc = 0; rc < 50; rc++) {
833 /* Wait for reset ack */
834 if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
835 rc = 0;
836 break;
837 }
838 msleep(10);
839 }
840
841 if (rc) {
842 printk(KERN_ERR DRIVER_NAME
843 ": card not ready - probe failed\n");
844 mmc_free_host(mmc);
845 return -ENODEV;
846 }
847
848 writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
849 writel(host->clk_div | TIFM_MMCSD_POWER,
850 sock->addr + SOCK_MMCSD_CONFIG);
851 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
852 writel(TIFM_MMCSD_DATAMASK | TIFM_MMCSD_ERRMASK,
853 sock->addr + SOCK_MMCSD_INT_ENABLE);
854
855 writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO); // command timeout 64 clocks for now
856 writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
857 writel(host->clk_div | TIFM_MMCSD_POWER,
858 sock->addr + SOCK_MMCSD_CONFIG);
859
0803dd0c 860 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
4020f2d7
AD		 861
862 return 0;
863}
864
865static int tifm_sd_host_is_down(struct tifm_dev *sock)
866{
867 struct mmc_host *mmc = tifm_get_drvdata(sock);
868 struct tifm_sd *host = mmc_priv(mmc);
869 unsigned long flags;
870 int rc = 0;
871
872 spin_lock_irqsave(&sock->lock, flags);
873 rc = (host->flags & EJECT_DONE);
874 spin_unlock_irqrestore(&sock->lock, flags);
875 return rc;
876}
877
878static void tifm_sd_remove(struct tifm_dev *sock)
879{
880 struct mmc_host *mmc = tifm_get_drvdata(sock);
881 struct tifm_sd *host = mmc_priv(mmc);
882 unsigned long flags;
883
0803dd0c 884 del_timer_sync(&host->timer);
4020f2d7
AD		 885 spin_lock_irqsave(&sock->lock, flags);
886 host->flags |= EJECT;
887 if (host->req)
888 queue_work(sock->wq, &host->cmd_handler);
889 spin_unlock_irqrestore(&sock->lock, flags);
890 wait_event_timeout(host->can_eject, tifm_sd_host_is_down(sock),
891 host->timeout_jiffies);
892
893 if (host->flags & HOST_REG)
894 mmc_remove_host(mmc);
895
896 /* The meaning of the bit majority in this constant is unknown. */
897 writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
898 sock->addr + SOCK_CONTROL);
899 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
900 writel(TIFM_FIFO_INT_SETALL,
901 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
902 writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
903
e069d79d 904 tifm_set_drvdata(sock, NULL);
4020f2d7
AD		 905 mmc_free_host(mmc);
906}
907
908static tifm_media_id tifm_sd_id_tbl[] = {
909 FM_SD, 0
910};
911
912static struct tifm_driver tifm_sd_driver = {
913 .driver = {
914 .name = DRIVER_NAME,
915 .owner = THIS_MODULE
916 },
917 .id_table = tifm_sd_id_tbl,
918 .probe = tifm_sd_probe,
919 .remove = tifm_sd_remove
920};
921
922static int __init tifm_sd_init(void)
923{
924 return tifm_register_driver(&tifm_sd_driver);
925}
926
927static void __exit tifm_sd_exit(void)
928{
929 tifm_unregister_driver(&tifm_sd_driver);
930}
931
932MODULE_AUTHOR("Alex Dubov");
933MODULE_DESCRIPTION("TI FlashMedia SD driver");
934MODULE_LICENSE("GPL");
935MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
936MODULE_VERSION(DRIVER_VERSION);
937
938module_init(tifm_sd_init);
939module_exit(tifm_sd_exit);
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