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tifm_sd: Switch software timeout handler from work_struct to timer
[net-next-2.6.git] / drivers / mmc / tifm_sd.c
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1/*
2 * tifm_sd.c - TI FlashMedia driver
3 *
4 * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12
13#include <linux/tifm.h>
14#include <linux/mmc/protocol.h>
15#include <linux/mmc/host.h>
16#include <linux/highmem.h>
2099c99e 17#include <asm/io.h>
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18
19#define DRIVER_NAME "tifm_sd"
1289335a 20#define DRIVER_VERSION "0.7"
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21
22static int no_dma = 0;
23static int fixed_timeout = 0;
24module_param(no_dma, bool, 0644);
25module_param(fixed_timeout, bool, 0644);
26
27/* Constants here are mostly from OMAP5912 datasheet */
28#define TIFM_MMCSD_RESET 0x0002
29#define TIFM_MMCSD_CLKMASK 0x03ff
30#define TIFM_MMCSD_POWER 0x0800
31#define TIFM_MMCSD_4BBUS 0x8000
32#define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
33#define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
34#define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
35#define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
36#define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
37#define TIFM_MMCSD_READ 0x8000
38
39#define TIFM_MMCSD_DATAMASK 0x001d /* set bits: EOFB, BRS, CB, EOC */
40#define TIFM_MMCSD_ERRMASK 0x41e0 /* set bits: CERR, CCRC, CTO, DCRC, DTO */
41#define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
42#define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
43#define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
44#define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
45#define TIFM_MMCSD_DTO 0x0020 /* data time-out */
46#define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
47#define TIFM_MMCSD_CTO 0x0080 /* command time-out */
48#define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
49#define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
50#define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
51#define TIFM_MMCSD_CERR 0x4000 /* card status error */
52
53#define TIFM_MMCSD_FIFO_SIZE 0x0020
54
55#define TIFM_MMCSD_RSP_R0 0x0000
56#define TIFM_MMCSD_RSP_R1 0x0100
57#define TIFM_MMCSD_RSP_R2 0x0200
58#define TIFM_MMCSD_RSP_R3 0x0300
59#define TIFM_MMCSD_RSP_R4 0x0400
60#define TIFM_MMCSD_RSP_R5 0x0500
61#define TIFM_MMCSD_RSP_R6 0x0600
62
63#define TIFM_MMCSD_RSP_BUSY 0x0800
64
65#define TIFM_MMCSD_CMD_BC 0x0000
66#define TIFM_MMCSD_CMD_BCR 0x1000
67#define TIFM_MMCSD_CMD_AC 0x2000
68#define TIFM_MMCSD_CMD_ADTC 0x3000
69
70typedef enum {
71 IDLE = 0,
72 CMD, /* main command ended */
73 BRS, /* block transfer finished */
74 SCMD, /* stop command ended */
75 CARD, /* card left busy state */
76 FIFO, /* FIFO operation completed (uncertain) */
77 READY
78} card_state_t;
79
80enum {
81 FIFO_RDY = 0x0001, /* hardware dependent value */
82 HOST_REG = 0x0002,
83 EJECT = 0x0004,
84 EJECT_DONE = 0x0008,
85 CARD_BUSY = 0x0010,
86 OPENDRAIN = 0x0040, /* hardware dependent value */
87 CARD_EVENT = 0x0100, /* hardware dependent value */
88 CARD_RO = 0x0200, /* hardware dependent value */
89 FIFO_EVENT = 0x10000 }; /* hardware dependent value */
90
91struct tifm_sd {
92 struct tifm_dev *dev;
93
94 unsigned int flags;
95 card_state_t state;
96 unsigned int clk_freq;
97 unsigned int clk_div;
0803dd0c 98 unsigned long timeout_jiffies;
4020f2d7 99
0803dd0c 100 struct timer_list timer;
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101 struct mmc_request *req;
102 struct work_struct cmd_handler;
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103 wait_queue_head_t can_eject;
104
105 size_t written_blocks;
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106 size_t buffer_size;
107 size_t buffer_pos;
108
109};
110
255ef22e
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111static char* tifm_sd_kmap_atomic(struct mmc_data *data)
112{
113 return kmap_atomic(data->sg->page, KM_BIO_SRC_IRQ) + data->sg->offset;
114}
115
116static void tifm_sd_kunmap_atomic(char *buffer, struct mmc_data *data)
117{
118 kunmap_atomic(buffer - data->sg->offset, KM_BIO_SRC_IRQ);
119}
120
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121static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
122 unsigned int host_status)
123{
124 struct mmc_command *cmd = host->req->cmd;
125 unsigned int t_val = 0, cnt = 0;
255ef22e 126 char *buffer;
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127
128 if (host_status & TIFM_MMCSD_BRS) {
129 /* in non-dma rx mode BRS fires when fifo is still not empty */
255ef22e
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130 if (no_dma && (cmd->data->flags & MMC_DATA_READ)) {
131 buffer = tifm_sd_kmap_atomic(host->req->data);
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132 while (host->buffer_size > host->buffer_pos) {
133 t_val = readl(sock->addr + SOCK_MMCSD_DATA);
255ef22e
AD
134 buffer[host->buffer_pos++] = t_val & 0xff;
135 buffer[host->buffer_pos++] =
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136 (t_val >> 8) & 0xff;
137 }
255ef22e 138 tifm_sd_kunmap_atomic(buffer, host->req->data);
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139 }
140 return 1;
255ef22e
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141 } else if (no_dma) {
142 buffer = tifm_sd_kmap_atomic(host->req->data);
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143 if ((cmd->data->flags & MMC_DATA_READ) &&
144 (host_status & TIFM_MMCSD_AF)) {
145 for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
146 t_val = readl(sock->addr + SOCK_MMCSD_DATA);
147 if (host->buffer_size > host->buffer_pos) {
255ef22e 148 buffer[host->buffer_pos++] =
4020f2d7 149 t_val & 0xff;
255ef22e 150 buffer[host->buffer_pos++] =
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151 (t_val >> 8) & 0xff;
152 }
153 }
154 } else if ((cmd->data->flags & MMC_DATA_WRITE)
155 && (host_status & TIFM_MMCSD_AE)) {
156 for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
157 if (host->buffer_size > host->buffer_pos) {
255ef22e
AD
158 t_val = buffer[host->buffer_pos++]
159 & 0x00ff;
160 t_val |= ((buffer[host->buffer_pos++])
161 << 8) & 0xff00;
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162 writel(t_val,
163 sock->addr + SOCK_MMCSD_DATA);
164 }
165 }
166 }
255ef22e 167 tifm_sd_kunmap_atomic(buffer, host->req->data);
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168 }
169 return 0;
170}
171
172static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
173{
174 unsigned int rc = 0;
175
176 switch (mmc_resp_type(cmd)) {
177 case MMC_RSP_NONE:
178 rc |= TIFM_MMCSD_RSP_R0;
179 break;
180 case MMC_RSP_R1B:
181 rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
182 case MMC_RSP_R1:
183 rc |= TIFM_MMCSD_RSP_R1;
184 break;
185 case MMC_RSP_R2:
186 rc |= TIFM_MMCSD_RSP_R2;
187 break;
188 case MMC_RSP_R3:
189 rc |= TIFM_MMCSD_RSP_R3;
190 break;
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191 default:
192 BUG();
193 }
194
195 switch (mmc_cmd_type(cmd)) {
196 case MMC_CMD_BC:
197 rc |= TIFM_MMCSD_CMD_BC;
198 break;
199 case MMC_CMD_BCR:
200 rc |= TIFM_MMCSD_CMD_BCR;
201 break;
202 case MMC_CMD_AC:
203 rc |= TIFM_MMCSD_CMD_AC;
204 break;
205 case MMC_CMD_ADTC:
206 rc |= TIFM_MMCSD_CMD_ADTC;
207 break;
208 default:
209 BUG();
210 }
211 return rc;
212}
213
214static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
215{
216 struct tifm_dev *sock = host->dev;
217 unsigned int cmd_mask = tifm_sd_op_flags(cmd) |
218 (host->flags & OPENDRAIN);
219
220 if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
221 cmd_mask |= TIFM_MMCSD_READ;
222
223 dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
224 cmd->opcode, cmd->arg, cmd_mask);
225
226 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
227 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
228 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
229}
230
231static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
232{
233 cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
234 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
235 cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
236 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
237 cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
238 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
239 cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
240 | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
241}
242
243static void tifm_sd_process_cmd(struct tifm_dev *sock, struct tifm_sd *host,
244 unsigned int host_status)
245{
246 struct mmc_command *cmd = host->req->cmd;
247
248change_state:
249 switch (host->state) {
250 case IDLE:
251 return;
252 case CMD:
253 if (host_status & TIFM_MMCSD_EOC) {
254 tifm_sd_fetch_resp(cmd, sock);
255 if (cmd->data) {
256 host->state = BRS;
1289335a 257 } else {
4020f2d7 258 host->state = READY;
1289335a 259 }
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260 goto change_state;
261 }
262 break;
263 case BRS:
264 if (tifm_sd_transfer_data(sock, host, host_status)) {
1289335a
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265 if (cmd->data->flags & MMC_DATA_WRITE) {
266 host->state = CARD;
267 } else {
268 if (no_dma) {
269 if (host->req->stop) {
270 tifm_sd_exec(host, host->req->stop);
271 host->state = SCMD;
272 } else {
273 host->state = READY;
274 }
4020f2d7 275 } else {
1289335a 276 host->state = FIFO;
4020f2d7 277 }
4020f2d7 278 }
1289335a 279 goto change_state;
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280 }
281 break;
282 case SCMD:
283 if (host_status & TIFM_MMCSD_EOC) {
284 tifm_sd_fetch_resp(host->req->stop, sock);
1289335a 285 host->state = READY;
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286 goto change_state;
287 }
288 break;
289 case CARD:
1289335a
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290 dev_dbg(&sock->dev, "waiting for CARD, have %zd blocks\n",
291 host->written_blocks);
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292 if (!(host->flags & CARD_BUSY)
293 && (host->written_blocks == cmd->data->blocks)) {
1289335a
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294 if (no_dma) {
295 if (host->req->stop) {
296 tifm_sd_exec(host, host->req->stop);
297 host->state = SCMD;
298 } else {
299 host->state = READY;
300 }
301 } else {
302 host->state = FIFO;
303 }
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304 goto change_state;
305 }
306 break;
307 case FIFO:
308 if (host->flags & FIFO_RDY) {
4020f2d7 309 host->flags &= ~FIFO_RDY;
1289335a
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310 if (host->req->stop) {
311 tifm_sd_exec(host, host->req->stop);
312 host->state = SCMD;
313 } else {
314 host->state = READY;
315 }
4020f2d7
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316 goto change_state;
317 }
318 break;
319 case READY:
320 queue_work(sock->wq, &host->cmd_handler);
321 return;
322 }
323
4020f2d7
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324}
325
326/* Called from interrupt handler */
327static unsigned int tifm_sd_signal_irq(struct tifm_dev *sock,
328 unsigned int sock_irq_status)
329{
330 struct tifm_sd *host;
331 unsigned int host_status = 0, fifo_status = 0;
332 int error_code = 0;
333
334 spin_lock(&sock->lock);
335 host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
4020f2d7
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336
337 if (sock_irq_status & FIFO_EVENT) {
338 fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
339 writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
340
341 host->flags |= fifo_status & FIFO_RDY;
342 }
343
344 if (sock_irq_status & CARD_EVENT) {
345 host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
346 writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
347
348 if (!(host->flags & HOST_REG))
349 queue_work(sock->wq, &host->cmd_handler);
350 if (!host->req)
351 goto done;
352
353 if (host_status & TIFM_MMCSD_ERRMASK) {
354 if (host_status & TIFM_MMCSD_CERR)
355 error_code = MMC_ERR_FAILED;
356 else if (host_status &
357 (TIFM_MMCSD_CTO | TIFM_MMCSD_DTO))
358 error_code = MMC_ERR_TIMEOUT;
359 else if (host_status &
360 (TIFM_MMCSD_CCRC | TIFM_MMCSD_DCRC))
361 error_code = MMC_ERR_BADCRC;
362
363 writel(TIFM_FIFO_INT_SETALL,
364 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
365 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
366
367 if (host->req->stop) {
368 if (host->state == SCMD) {
369 host->req->stop->error = error_code;
1289335a
AD
370 } else if (host->state == BRS
371 || host->state == CARD
372 || host->state == FIFO) {
4020f2d7
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373 host->req->cmd->error = error_code;
374 tifm_sd_exec(host, host->req->stop);
4020f2d7
AD
375 host->state = SCMD;
376 goto done;
377 } else {
378 host->req->cmd->error = error_code;
379 }
380 } else {
381 host->req->cmd->error = error_code;
382 }
383 host->state = READY;
384 }
385
386 if (host_status & TIFM_MMCSD_CB)
387 host->flags |= CARD_BUSY;
388 if ((host_status & TIFM_MMCSD_EOFB) &&
389 (host->flags & CARD_BUSY)) {
390 host->written_blocks++;
391 host->flags &= ~CARD_BUSY;
392 }
393 }
394
395 if (host->req)
396 tifm_sd_process_cmd(sock, host, host_status);
397done:
398 dev_dbg(&sock->dev, "host_status %x, fifo_status %x\n",
399 host_status, fifo_status);
400 spin_unlock(&sock->lock);
401 return sock_irq_status;
402}
403
404static void tifm_sd_prepare_data(struct tifm_sd *card, struct mmc_command *cmd)
405{
406 struct tifm_dev *sock = card->dev;
407 unsigned int dest_cnt;
408
409 /* DMA style IO */
410
411 writel(TIFM_FIFO_INT_SETALL,
412 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
f0d1b0b3 413 writel(ilog2(cmd->data->blksz) - 2,
4020f2d7
AD
414 sock->addr + SOCK_FIFO_PAGE_SIZE);
415 writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
416 writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
417
418 dest_cnt = (cmd->data->blocks) << 8;
419
420 writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
421
422 writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
423 writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
424
425 if (cmd->data->flags & MMC_DATA_WRITE) {
426 writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
427 writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
428 sock->addr + SOCK_DMA_CONTROL);
429 } else {
430 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
431 writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
432 }
433}
434
435static void tifm_sd_set_data_timeout(struct tifm_sd *host,
436 struct mmc_data *data)
437{
438 struct tifm_dev *sock = host->dev;
439 unsigned int data_timeout = data->timeout_clks;
440
441 if (fixed_timeout)
442 return;
443
444 data_timeout += data->timeout_ns /
445 ((1000000000 / host->clk_freq) * host->clk_div);
446 data_timeout *= 10; // call it fudge factor for now
447
448 if (data_timeout < 0xffff) {
449 writel((~TIFM_MMCSD_DPE) &
450 readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
451 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
452 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
453 } else {
454 writel(TIFM_MMCSD_DPE |
455 readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
456 sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
457 data_timeout = (data_timeout >> 10) + 1;
458 if(data_timeout > 0xffff)
459 data_timeout = 0; /* set to unlimited */
460 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
461 }
462}
463
464static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
465{
466 struct tifm_sd *host = mmc_priv(mmc);
467 struct tifm_dev *sock = host->dev;
468 unsigned long flags;
469 int sg_count = 0;
470 struct mmc_data *r_data = mrq->cmd->data;
471
472 spin_lock_irqsave(&sock->lock, flags);
473 if (host->flags & EJECT) {
474 spin_unlock_irqrestore(&sock->lock, flags);
475 goto err_out;
476 }
477
478 if (host->req) {
479 printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
480 spin_unlock_irqrestore(&sock->lock, flags);
481 goto err_out;
482 }
483
484 if (r_data) {
485 tifm_sd_set_data_timeout(host, r_data);
486
487 sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
488 mrq->cmd->flags & MMC_DATA_WRITE
489 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
490 if (sg_count != 1) {
491 printk(KERN_ERR DRIVER_NAME
492 ": scatterlist map failed\n");
493 spin_unlock_irqrestore(&sock->lock, flags);
494 goto err_out;
495 }
496
497 host->written_blocks = 0;
498 host->flags &= ~CARD_BUSY;
499 tifm_sd_prepare_data(host, mrq->cmd);
500 }
501
502 host->req = mrq;
0803dd0c 503 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
4020f2d7 504 host->state = CMD;
4020f2d7
AD
505 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
506 sock->addr + SOCK_CONTROL);
507 tifm_sd_exec(host, mrq->cmd);
508 spin_unlock_irqrestore(&sock->lock, flags);
509 return;
510
511err_out:
512 if (sg_count > 0)
513 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
514 (r_data->flags & MMC_DATA_WRITE)
515 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
516
517 mrq->cmd->error = MMC_ERR_TIMEOUT;
518 mmc_request_done(mmc, mrq);
519}
520
c4028958 521static void tifm_sd_end_cmd(struct work_struct *work)
4020f2d7 522{
c4028958 523 struct tifm_sd *host = container_of(work, struct tifm_sd, cmd_handler);
4020f2d7
AD
524 struct tifm_dev *sock = host->dev;
525 struct mmc_host *mmc = tifm_get_drvdata(sock);
526 struct mmc_request *mrq;
e069d79d 527 struct mmc_data *r_data = NULL;
4020f2d7
AD
528 unsigned long flags;
529
530 spin_lock_irqsave(&sock->lock, flags);
531
0803dd0c 532 del_timer(&host->timer);
4020f2d7 533 mrq = host->req;
e069d79d 534 host->req = NULL;
4020f2d7
AD
535 host->state = IDLE;
536
537 if (!mrq) {
538 printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
539 spin_unlock_irqrestore(&sock->lock, flags);
540 return;
541 }
542
543 r_data = mrq->cmd->data;
544 if (r_data) {
545 if (r_data->flags & MMC_DATA_WRITE) {
546 r_data->bytes_xfered = host->written_blocks *
547 r_data->blksz;
548 } else {
549 r_data->bytes_xfered = r_data->blocks -
550 readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
551 r_data->bytes_xfered *= r_data->blksz;
552 r_data->bytes_xfered += r_data->blksz -
553 readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
554 }
555 tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
556 (r_data->flags & MMC_DATA_WRITE)
557 ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
558 }
559
560 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
561 sock->addr + SOCK_CONTROL);
562
563 spin_unlock_irqrestore(&sock->lock, flags);
564 mmc_request_done(mmc, mrq);
565}
566
567static void tifm_sd_request_nodma(struct mmc_host *mmc, struct mmc_request *mrq)
568{
569 struct tifm_sd *host = mmc_priv(mmc);
570 struct tifm_dev *sock = host->dev;
571 unsigned long flags;
572 struct mmc_data *r_data = mrq->cmd->data;
4020f2d7
AD
573
574 spin_lock_irqsave(&sock->lock, flags);
575 if (host->flags & EJECT) {
576 spin_unlock_irqrestore(&sock->lock, flags);
577 goto err_out;
578 }
579
580 if (host->req) {
581 printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
582 spin_unlock_irqrestore(&sock->lock, flags);
583 goto err_out;
584 }
585
586 if (r_data) {
587 tifm_sd_set_data_timeout(host, r_data);
588
4020f2d7
AD
589 host->buffer_size = mrq->cmd->data->blocks *
590 mrq->cmd->data->blksz;
591
592 writel(TIFM_MMCSD_BUFINT |
593 readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
594 sock->addr + SOCK_MMCSD_INT_ENABLE);
595 writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8) |
596 (TIFM_MMCSD_FIFO_SIZE - 1),
597 sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
598
599 host->written_blocks = 0;
600 host->flags &= ~CARD_BUSY;
601 host->buffer_pos = 0;
602 writel(r_data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
603 writel(r_data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
604 }
605
606 host->req = mrq;
0803dd0c 607 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
4020f2d7 608 host->state = CMD;
4020f2d7
AD
609 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
610 sock->addr + SOCK_CONTROL);
611 tifm_sd_exec(host, mrq->cmd);
612 spin_unlock_irqrestore(&sock->lock, flags);
613 return;
614
615err_out:
4020f2d7
AD
616 mrq->cmd->error = MMC_ERR_TIMEOUT;
617 mmc_request_done(mmc, mrq);
618}
619
c4028958 620static void tifm_sd_end_cmd_nodma(struct work_struct *work)
4020f2d7 621{
c4028958 622 struct tifm_sd *host = container_of(work, struct tifm_sd, cmd_handler);
4020f2d7
AD
623 struct tifm_dev *sock = host->dev;
624 struct mmc_host *mmc = tifm_get_drvdata(sock);
625 struct mmc_request *mrq;
e069d79d 626 struct mmc_data *r_data = NULL;
4020f2d7
AD
627 unsigned long flags;
628
629 spin_lock_irqsave(&sock->lock, flags);
630
0803dd0c 631 del_timer(&host->timer);
4020f2d7 632 mrq = host->req;
e069d79d 633 host->req = NULL;
4020f2d7
AD
634 host->state = IDLE;
635
636 if (!mrq) {
637 printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
638 spin_unlock_irqrestore(&sock->lock, flags);
639 return;
640 }
641
642 r_data = mrq->cmd->data;
643 if (r_data) {
644 writel((~TIFM_MMCSD_BUFINT) &
645 readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
646 sock->addr + SOCK_MMCSD_INT_ENABLE);
647
648 if (r_data->flags & MMC_DATA_WRITE) {
649 r_data->bytes_xfered = host->written_blocks *
650 r_data->blksz;
651 } else {
652 r_data->bytes_xfered = r_data->blocks -
653 readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
654 r_data->bytes_xfered *= r_data->blksz;
655 r_data->bytes_xfered += r_data->blksz -
656 readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
657 }
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AD
658 host->buffer_pos = 0;
659 host->buffer_size = 0;
660 }
661
662 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
663 sock->addr + SOCK_CONTROL);
664
665 spin_unlock_irqrestore(&sock->lock, flags);
666
4020f2d7
AD
667 mmc_request_done(mmc, mrq);
668}
669
0803dd0c 670static void tifm_sd_abort(unsigned long data)
4020f2d7
AD
671{
672 printk(KERN_ERR DRIVER_NAME
0803dd0c
AD
673 ": card failed to respond for a long period of time");
674 tifm_eject(((struct tifm_sd*)data)->dev);
4020f2d7
AD
675}
676
677static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
678{
679 struct tifm_sd *host = mmc_priv(mmc);
680 struct tifm_dev *sock = host->dev;
681 unsigned int clk_div1, clk_div2;
682 unsigned long flags;
683
684 spin_lock_irqsave(&sock->lock, flags);
685
686 dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
687 ios->power_mode);
688 if (ios->bus_width == MMC_BUS_WIDTH_4) {
689 writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
690 sock->addr + SOCK_MMCSD_CONFIG);
691 } else {
692 writel((~TIFM_MMCSD_4BBUS) &
693 readl(sock->addr + SOCK_MMCSD_CONFIG),
694 sock->addr + SOCK_MMCSD_CONFIG);
695 }
696
697 if (ios->clock) {
698 clk_div1 = 20000000 / ios->clock;
699 if (!clk_div1)
700 clk_div1 = 1;
701
702 clk_div2 = 24000000 / ios->clock;
703 if (!clk_div2)
704 clk_div2 = 1;
705
706 if ((20000000 / clk_div1) > ios->clock)
707 clk_div1++;
708 if ((24000000 / clk_div2) > ios->clock)
709 clk_div2++;
710 if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
711 host->clk_freq = 20000000;
712 host->clk_div = clk_div1;
713 writel((~TIFM_CTRL_FAST_CLK) &
714 readl(sock->addr + SOCK_CONTROL),
715 sock->addr + SOCK_CONTROL);
716 } else {
717 host->clk_freq = 24000000;
718 host->clk_div = clk_div2;
719 writel(TIFM_CTRL_FAST_CLK |
720 readl(sock->addr + SOCK_CONTROL),
721 sock->addr + SOCK_CONTROL);
722 }
723 } else {
724 host->clk_div = 0;
725 }
726 host->clk_div &= TIFM_MMCSD_CLKMASK;
727 writel(host->clk_div | ((~TIFM_MMCSD_CLKMASK) &
728 readl(sock->addr + SOCK_MMCSD_CONFIG)),
729 sock->addr + SOCK_MMCSD_CONFIG);
730
731 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
732 host->flags |= OPENDRAIN;
733 else
734 host->flags &= ~OPENDRAIN;
735
736 /* chip_select : maybe later */
737 //vdd
738 //power is set before probe / after remove
739 //I believe, power_off when already marked for eject is sufficient to
740 // allow removal.
741 if ((host->flags & EJECT) && ios->power_mode == MMC_POWER_OFF) {
742 host->flags |= EJECT_DONE;
743 wake_up_all(&host->can_eject);
744 }
745
746 spin_unlock_irqrestore(&sock->lock, flags);
747}
748
749static int tifm_sd_ro(struct mmc_host *mmc)
750{
751 int rc;
752 struct tifm_sd *host = mmc_priv(mmc);
753 struct tifm_dev *sock = host->dev;
754 unsigned long flags;
755
756 spin_lock_irqsave(&sock->lock, flags);
757
758 host->flags |= (CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE));
759 rc = (host->flags & CARD_RO) ? 1 : 0;
760
761 spin_unlock_irqrestore(&sock->lock, flags);
762 return rc;
763}
764
765static struct mmc_host_ops tifm_sd_ops = {
766 .request = tifm_sd_request,
767 .set_ios = tifm_sd_ios,
768 .get_ro = tifm_sd_ro
769};
770
c4028958 771static void tifm_sd_register_host(struct work_struct *work)
4020f2d7 772{
c4028958 773 struct tifm_sd *host = container_of(work, struct tifm_sd, cmd_handler);
4020f2d7
AD
774 struct tifm_dev *sock = host->dev;
775 struct mmc_host *mmc = tifm_get_drvdata(sock);
776 unsigned long flags;
777
778 spin_lock_irqsave(&sock->lock, flags);
0803dd0c 779 del_timer(&host->timer);
4020f2d7
AD
780 host->flags |= HOST_REG;
781 PREPARE_WORK(&host->cmd_handler,
c4028958 782 no_dma ? tifm_sd_end_cmd_nodma : tifm_sd_end_cmd);
4020f2d7
AD
783 spin_unlock_irqrestore(&sock->lock, flags);
784 dev_dbg(&sock->dev, "adding host\n");
785 mmc_add_host(mmc);
786}
787
788static int tifm_sd_probe(struct tifm_dev *sock)
789{
790 struct mmc_host *mmc;
791 struct tifm_sd *host;
792 int rc = -EIO;
793
794 if (!(TIFM_SOCK_STATE_OCCUPIED &
795 readl(sock->addr + SOCK_PRESENT_STATE))) {
796 printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
797 return rc;
798 }
799
800 mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
801 if (!mmc)
802 return -ENOMEM;
803
804 host = mmc_priv(mmc);
805 host->dev = sock;
806 host->clk_div = 61;
807 init_waitqueue_head(&host->can_eject);
c4028958 808 INIT_WORK(&host->cmd_handler, tifm_sd_register_host);
0803dd0c 809 setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
4020f2d7
AD
810
811 tifm_set_drvdata(sock, mmc);
812 sock->signal_irq = tifm_sd_signal_irq;
813
814 host->clk_freq = 20000000;
815 host->timeout_jiffies = msecs_to_jiffies(1000);
816
817 tifm_sd_ops.request = no_dma ? tifm_sd_request_nodma : tifm_sd_request;
818 mmc->ops = &tifm_sd_ops;
819 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
820 mmc->caps = MMC_CAP_4_BIT_DATA;
821 mmc->f_min = 20000000 / 60;
822 mmc->f_max = 24000000;
823 mmc->max_hw_segs = 1;
824 mmc->max_phys_segs = 1;
825 mmc->max_sectors = 127;
826 mmc->max_seg_size = mmc->max_sectors << 11; //2k maximum hw block length
827
828 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
829 writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
830 writel(host->clk_div | TIFM_MMCSD_POWER,
831 sock->addr + SOCK_MMCSD_CONFIG);
832
833 for (rc = 0; rc < 50; rc++) {
834 /* Wait for reset ack */
835 if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
836 rc = 0;
837 break;
838 }
839 msleep(10);
840 }
841
842 if (rc) {
843 printk(KERN_ERR DRIVER_NAME
844 ": card not ready - probe failed\n");
845 mmc_free_host(mmc);
846 return -ENODEV;
847 }
848
849 writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
850 writel(host->clk_div | TIFM_MMCSD_POWER,
851 sock->addr + SOCK_MMCSD_CONFIG);
852 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
853 writel(TIFM_MMCSD_DATAMASK | TIFM_MMCSD_ERRMASK,
854 sock->addr + SOCK_MMCSD_INT_ENABLE);
855
856 writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO); // command timeout 64 clocks for now
857 writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
858 writel(host->clk_div | TIFM_MMCSD_POWER,
859 sock->addr + SOCK_MMCSD_CONFIG);
860
0803dd0c 861 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
4020f2d7
AD
862
863 return 0;
864}
865
866static int tifm_sd_host_is_down(struct tifm_dev *sock)
867{
868 struct mmc_host *mmc = tifm_get_drvdata(sock);
869 struct tifm_sd *host = mmc_priv(mmc);
870 unsigned long flags;
871 int rc = 0;
872
873 spin_lock_irqsave(&sock->lock, flags);
874 rc = (host->flags & EJECT_DONE);
875 spin_unlock_irqrestore(&sock->lock, flags);
876 return rc;
877}
878
879static void tifm_sd_remove(struct tifm_dev *sock)
880{
881 struct mmc_host *mmc = tifm_get_drvdata(sock);
882 struct tifm_sd *host = mmc_priv(mmc);
883 unsigned long flags;
884
0803dd0c 885 del_timer_sync(&host->timer);
4020f2d7
AD
886 spin_lock_irqsave(&sock->lock, flags);
887 host->flags |= EJECT;
888 if (host->req)
889 queue_work(sock->wq, &host->cmd_handler);
890 spin_unlock_irqrestore(&sock->lock, flags);
891 wait_event_timeout(host->can_eject, tifm_sd_host_is_down(sock),
892 host->timeout_jiffies);
893
894 if (host->flags & HOST_REG)
895 mmc_remove_host(mmc);
896
897 /* The meaning of the bit majority in this constant is unknown. */
898 writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
899 sock->addr + SOCK_CONTROL);
900 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
901 writel(TIFM_FIFO_INT_SETALL,
902 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
903 writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
904
e069d79d 905 tifm_set_drvdata(sock, NULL);
4020f2d7
AD
906 mmc_free_host(mmc);
907}
908
909static tifm_media_id tifm_sd_id_tbl[] = {
910 FM_SD, 0
911};
912
913static struct tifm_driver tifm_sd_driver = {
914 .driver = {
915 .name = DRIVER_NAME,
916 .owner = THIS_MODULE
917 },
918 .id_table = tifm_sd_id_tbl,
919 .probe = tifm_sd_probe,
920 .remove = tifm_sd_remove
921};
922
923static int __init tifm_sd_init(void)
924{
925 return tifm_register_driver(&tifm_sd_driver);
926}
927
928static void __exit tifm_sd_exit(void)
929{
930 tifm_unregister_driver(&tifm_sd_driver);
931}
932
933MODULE_AUTHOR("Alex Dubov");
934MODULE_DESCRIPTION("TI FlashMedia SD driver");
935MODULE_LICENSE("GPL");
936MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
937MODULE_VERSION(DRIVER_VERSION);
938
939module_init(tifm_sd_init);
940module_exit(tifm_sd_exit);