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[PATCH] make kernel/relay.c __user-clean
[net-next-2.6.git] / drivers / mmc / sdhci.c
CommitLineData
d129bceb
PO		 1/*
2 * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
d129bceb
PO		 10 */
11
d129bceb
PO		 12#include <linux/delay.h>
13#include <linux/highmem.h>
14#include <linux/pci.h>
15#include <linux/dma-mapping.h>
16
17#include <linux/mmc/host.h>
18#include <linux/mmc/protocol.h>
19
20#include <asm/scatterlist.h>
21
22#include "sdhci.h"
23
24#define DRIVER_NAME "sdhci"
2c5f3940 25#define DRIVER_VERSION "0.12"
d129bceb
PO		 26
27#define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
28
d129bceb 29#define DBG(f, x...) \
c6563178 30 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 31
67435274
PO		 32static unsigned int debug_nodma = 0;
33static unsigned int debug_forcedma = 0;
df673b22 34static unsigned int debug_quirks = 0;
67435274 35
645289dc 36#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
98608076 37#define SDHCI_QUIRK_FORCE_DMA (1<<1)
8a4da143
PO		 38/* Controller doesn't like some resets when there is no card inserted. */
39#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
645289dc 40
d129bceb 41static const struct pci_device_id pci_ids[] __devinitdata = {
645289dc
PO		 42 {
43 .vendor = PCI_VENDOR_ID_RICOH,
44 .device = PCI_DEVICE_ID_RICOH_R5C822,
45 .subvendor = PCI_VENDOR_ID_IBM,
46 .subdevice = PCI_ANY_ID,
98608076
PO		 47 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
48 SDHCI_QUIRK_FORCE_DMA,
49 },
50
51 {
52 .vendor = PCI_VENDOR_ID_RICOH,
53 .device = PCI_DEVICE_ID_RICOH_R5C822,
54 .subvendor = PCI_ANY_ID,
55 .subdevice = PCI_ANY_ID,
8a4da143
PO		 56 .driver_data = SDHCI_QUIRK_FORCE_DMA |
57 SDHCI_QUIRK_NO_CARD_NO_RESET,
98608076
PO		 58 },
59
60 {
61 .vendor = PCI_VENDOR_ID_TI,
62 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
63 .subvendor = PCI_ANY_ID,
64 .subdevice = PCI_ANY_ID,
65 .driver_data = SDHCI_QUIRK_FORCE_DMA,
645289dc
PO		 66 },
67
68 { /* Generic SD host controller */
69 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
70 },
71
d129bceb
PO		 72 { /* end: all zeroes */ },
73};
74
75MODULE_DEVICE_TABLE(pci, pci_ids);
76
77static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
78static void sdhci_finish_data(struct sdhci_host *);
79
80static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
81static void sdhci_finish_command(struct sdhci_host *);
82
83static void sdhci_dumpregs(struct sdhci_host *host)
84{
85 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
86
87 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
88 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
89 readw(host->ioaddr + SDHCI_HOST_VERSION));
90 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
91 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
92 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
93 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
94 readl(host->ioaddr + SDHCI_ARGUMENT),
95 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
96 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
97 readl(host->ioaddr + SDHCI_PRESENT_STATE),
98 readb(host->ioaddr + SDHCI_HOST_CONTROL));
99 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
100 readb(host->ioaddr + SDHCI_POWER_CONTROL),
101 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
102 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
103 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
104 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
105 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
106 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
107 readl(host->ioaddr + SDHCI_INT_STATUS));
108 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
109 readl(host->ioaddr + SDHCI_INT_ENABLE),
110 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
111 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
112 readw(host->ioaddr + SDHCI_ACMD12_ERR),
113 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
114 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
115 readl(host->ioaddr + SDHCI_CAPABILITIES),
116 readl(host->ioaddr + SDHCI_MAX_CURRENT));
117
118 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
119}
120
121/*****************************************************************************\
122 * *
123 * Low level functions *
124 * *
125\*****************************************************************************/
126
127static void sdhci_reset(struct sdhci_host *host, u8 mask)
128{
e16514d8
PO		 129 unsigned long timeout;
130
8a4da143
PO		 131 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
132 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
133 SDHCI_CARD_PRESENT))
134 return;
135 }
136
d129bceb
PO		 137 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
138
e16514d8 139 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 140 host->clock = 0;
141
e16514d8
PO		 142 /* Wait max 100 ms */
143 timeout = 100;
144
145 /* hw clears the bit when it's done */
146 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
147 if (timeout == 0) {
148 printk(KERN_ERR "%s: Reset 0x%x never completed. "
149 "Please report this to " BUGMAIL ".\n",
150 mmc_hostname(host->mmc), (int)mask);
151 sdhci_dumpregs(host);
152 return;
153 }
154 timeout--;
155 mdelay(1);
d129bceb
PO		 156 }
157}
158
159static void sdhci_init(struct sdhci_host *host)
160{
161 u32 intmask;
162
163 sdhci_reset(host, SDHCI_RESET_ALL);
164
3192a28f
PO		 165 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
166 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
167 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
168 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 169 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
3192a28f 170 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
d129bceb
PO		 171
172 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
173 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 174}
175
176static void sdhci_activate_led(struct sdhci_host *host)
177{
178 u8 ctrl;
179
180 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
181 ctrl |= SDHCI_CTRL_LED;
182 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
183}
184
185static void sdhci_deactivate_led(struct sdhci_host *host)
186{
187 u8 ctrl;
188
189 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
190 ctrl &= ~SDHCI_CTRL_LED;
191 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
192}
193
194/*****************************************************************************\
195 * *
196 * Core functions *
197 * *
198\*****************************************************************************/
199
200static inline char* sdhci_kmap_sg(struct sdhci_host* host)
201{
202 host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
203 return host->mapped_sg + host->cur_sg->offset;
204}
205
206static inline void sdhci_kunmap_sg(struct sdhci_host* host)
207{
208 kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
209}
210
211static inline int sdhci_next_sg(struct sdhci_host* host)
212{
213 /*
214 * Skip to next SG entry.
215 */
216 host->cur_sg++;
217 host->num_sg--;
218
219 /*
220 * Any entries left?
221 */
222 if (host->num_sg > 0) {
223 host->offset = 0;
224 host->remain = host->cur_sg->length;
225 }
226
227 return host->num_sg;
228}
229
a406f5a3 230static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 231{
a406f5a3
PO		 232 int blksize, chunk_remain;
233 u32 data;
d129bceb 234 char *buffer;
a406f5a3 235 int size;
d129bceb 236
a406f5a3 237 DBG("PIO reading\n");
d129bceb 238
a406f5a3
PO		 239 blksize = host->data->blksz;
240 chunk_remain = 0;
241 data = 0;
d129bceb
PO		 242
243 buffer = sdhci_kmap_sg(host) + host->offset;
244
a406f5a3
PO		 245 while (blksize) {
246 if (chunk_remain == 0) {
247 data = readl(host->ioaddr + SDHCI_BUFFER);
248 chunk_remain = min(blksize, 4);
249 }
d129bceb 250
a406f5a3
PO		 251 size = min(host->size, host->remain);
252 size = min(size, chunk_remain);
d129bceb 253
a406f5a3
PO		 254 chunk_remain -= size;
255 blksize -= size;
256 host->offset += size;
257 host->remain -= size;
258 host->size -= size;
259 while (size) {
260 *buffer = data & 0xFF;
261 buffer++;
262 data >>= 8;
263 size--;
264 }
d129bceb 265
a406f5a3
PO		 266 if (host->remain == 0) {
267 sdhci_kunmap_sg(host);
268 if (sdhci_next_sg(host) == 0) {
269 BUG_ON(blksize != 0);
270 return;
271 }
272 buffer = sdhci_kmap_sg(host);
d129bceb 273 }
a406f5a3 274 }
d129bceb 275
a406f5a3
PO		 276 sdhci_kunmap_sg(host);
277}
d129bceb 278
a406f5a3
PO		 279static void sdhci_write_block_pio(struct sdhci_host *host)
280{
281 int blksize, chunk_remain;
282 u32 data;
283 char *buffer;
284 int bytes, size;
d129bceb 285
a406f5a3
PO		 286 DBG("PIO writing\n");
287
288 blksize = host->data->blksz;
289 chunk_remain = 4;
290 data = 0;
d129bceb 291
a406f5a3
PO		 292 bytes = 0;
293 buffer = sdhci_kmap_sg(host) + host->offset;
d129bceb 294
a406f5a3
PO		 295 while (blksize) {
296 size = min(host->size, host->remain);
297 size = min(size, chunk_remain);
298
299 chunk_remain -= size;
300 blksize -= size;
d129bceb
PO		 301 host->offset += size;
302 host->remain -= size;
d129bceb 303 host->size -= size;
a406f5a3
PO		 304 while (size) {
305 data >>= 8;
306 data |= (u32)*buffer << 24;
307 buffer++;
308 size--;
309 }
310
311 if (chunk_remain == 0) {
312 writel(data, host->ioaddr + SDHCI_BUFFER);
313 chunk_remain = min(blksize, 4);
314 }
d129bceb
PO		 315
316 if (host->remain == 0) {
317 sdhci_kunmap_sg(host);
318 if (sdhci_next_sg(host) == 0) {
a406f5a3 319 BUG_ON(blksize != 0);
d129bceb
PO		 320 return;
321 }
322 buffer = sdhci_kmap_sg(host);
323 }
324 }
325
326 sdhci_kunmap_sg(host);
a406f5a3
PO		 327}
328
329static void sdhci_transfer_pio(struct sdhci_host *host)
330{
331 u32 mask;
332
333 BUG_ON(!host->data);
334
335 if (host->size == 0)
336 return;
337
338 if (host->data->flags & MMC_DATA_READ)
339 mask = SDHCI_DATA_AVAILABLE;
340 else
341 mask = SDHCI_SPACE_AVAILABLE;
342
343 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
344 if (host->data->flags & MMC_DATA_READ)
345 sdhci_read_block_pio(host);
346 else
347 sdhci_write_block_pio(host);
d129bceb 348
a406f5a3
PO		 349 if (host->size == 0)
350 break;
351
352 BUG_ON(host->num_sg == 0);
353 }
d129bceb 354
a406f5a3 355 DBG("PIO transfer complete.\n");
d129bceb
PO		 356}
357
358static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
359{
1c8cde92
PO		 360 u8 count;
361 unsigned target_timeout, current_timeout;
d129bceb
PO		 362
363 WARN_ON(host->data);
364
c7fa9963 365 if (data == NULL)
d129bceb 366 return;
d129bceb
PO		 367
368 DBG("blksz %04x blks %04x flags %08x\n",
a3fd4a1b 369 data->blksz, data->blocks, data->flags);
d129bceb
PO		 370 DBG("tsac %d ms nsac %d clk\n",
371 data->timeout_ns / 1000000, data->timeout_clks);
372
bab76961
PO		 373 /* Sanity checks */
374 BUG_ON(data->blksz * data->blocks > 524288);
1d676e02
PO		 375 BUG_ON(data->blksz > host->max_block);
376 BUG_ON(data->blocks > 65535);
d129bceb 377
1c8cde92
PO		 378 /* timeout in us */
379 target_timeout = data->timeout_ns / 1000 +
380 data->timeout_clks / host->clock;
d129bceb 381
1c8cde92
PO		 382 /*
383 * Figure out needed cycles.
384 * We do this in steps in order to fit inside a 32 bit int.
385 * The first step is the minimum timeout, which will have a
386 * minimum resolution of 6 bits:
387 * (1) 2^13*1000 > 2^22,
388 * (2) host->timeout_clk < 2^16
389 * =>
390 * (1) / (2) > 2^6
391 */
392 count = 0;
393 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
394 while (current_timeout < target_timeout) {
395 count++;
396 current_timeout <<= 1;
397 if (count >= 0xF)
398 break;
399 }
400
401 if (count >= 0xF) {
402 printk(KERN_WARNING "%s: Too large timeout requested!\n",
403 mmc_hostname(host->mmc));
404 count = 0xE;
405 }
406
407 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
d129bceb
PO		 408
409 if (host->flags & SDHCI_USE_DMA) {
410 int count;
411
412 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
413 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
414 BUG_ON(count != 1);
415
416 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
417 } else {
a3fd4a1b 418 host->size = data->blksz * data->blocks;
d129bceb
PO		 419
420 host->cur_sg = data->sg;
421 host->num_sg = data->sg_len;
422
423 host->offset = 0;
424 host->remain = host->cur_sg->length;
425 }
c7fa9963 426
bab76961
PO		 427 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
428 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
429 host->ioaddr + SDHCI_BLOCK_SIZE);
c7fa9963
PO		 430 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
431}
432
433static void sdhci_set_transfer_mode(struct sdhci_host *host,
434 struct mmc_data *data)
435{
436 u16 mode;
437
438 WARN_ON(host->data);
439
440 if (data == NULL)
441 return;
442
443 mode = SDHCI_TRNS_BLK_CNT_EN;
444 if (data->blocks > 1)
445 mode |= SDHCI_TRNS_MULTI;
446 if (data->flags & MMC_DATA_READ)
447 mode |= SDHCI_TRNS_READ;
448 if (host->flags & SDHCI_USE_DMA)
449 mode |= SDHCI_TRNS_DMA;
450
451 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
d129bceb
PO		 452}
453
454static void sdhci_finish_data(struct sdhci_host *host)
455{
456 struct mmc_data *data;
d129bceb
PO		 457 u16 blocks;
458
459 BUG_ON(!host->data);
460
461 data = host->data;
462 host->data = NULL;
463
464 if (host->flags & SDHCI_USE_DMA) {
465 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
466 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
d129bceb
PO		 467 }
468
469 /*
470 * Controller doesn't count down when in single block mode.
471 */
472 if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
473 blocks = 0;
474 else
475 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
a3fd4a1b 476 data->bytes_xfered = data->blksz * (data->blocks - blocks);
d129bceb
PO		 477
478 if ((data->error == MMC_ERR_NONE) && blocks) {
479 printk(KERN_ERR "%s: Controller signalled completion even "
480 "though there were blocks left. Please report this "
481 "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
482 data->error = MMC_ERR_FAILED;
4cca56c5 483 } else if (host->size != 0) {
d129bceb
PO		 484 printk(KERN_ERR "%s: %d bytes were left untransferred. "
485 "Please report this to " BUGMAIL ".\n",
486 mmc_hostname(host->mmc), host->size);
487 data->error = MMC_ERR_FAILED;
488 }
489
490 DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
491
492 if (data->stop) {
493 /*
494 * The controller needs a reset of internal state machines
495 * upon error conditions.
496 */
497 if (data->error != MMC_ERR_NONE) {
498 sdhci_reset(host, SDHCI_RESET_CMD);
499 sdhci_reset(host, SDHCI_RESET_DATA);
500 }
501
502 sdhci_send_command(host, data->stop);
503 } else
504 tasklet_schedule(&host->finish_tasklet);
505}
506
507static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
508{
509 int flags;
fd2208d7 510 u32 mask;
7cb2c76f 511 unsigned long timeout;
d129bceb
PO		 512
513 WARN_ON(host->cmd);
514
515 DBG("Sending cmd (%x)\n", cmd->opcode);
516
517 /* Wait max 10 ms */
7cb2c76f 518 timeout = 10;
fd2208d7
PO		 519
520 mask = SDHCI_CMD_INHIBIT;
521 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
522 mask |= SDHCI_DATA_INHIBIT;
523
524 /* We shouldn't wait for data inihibit for stop commands, even
525 though they might use busy signaling */
526 if (host->mrq->data && (cmd == host->mrq->data->stop))
527 mask &= ~SDHCI_DATA_INHIBIT;
528
529 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 530 if (timeout == 0) {
d129bceb 531 printk(KERN_ERR "%s: Controller never released "
fd2208d7 532 "inhibit bit(s). Please report this to "
d129bceb
PO		 533 BUGMAIL ".\n", mmc_hostname(host->mmc));
534 sdhci_dumpregs(host);
535 cmd->error = MMC_ERR_FAILED;
536 tasklet_schedule(&host->finish_tasklet);
537 return;
538 }
7cb2c76f
PO		 539 timeout--;
540 mdelay(1);
541 }
d129bceb
PO		 542
543 mod_timer(&host->timer, jiffies + 10 * HZ);
544
545 host->cmd = cmd;
546
547 sdhci_prepare_data(host, cmd->data);
548
549 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
550
c7fa9963
PO		 551 sdhci_set_transfer_mode(host, cmd->data);
552
d129bceb
PO		 553 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
554 printk(KERN_ERR "%s: Unsupported response type! "
555 "Please report this to " BUGMAIL ".\n",
556 mmc_hostname(host->mmc));
557 cmd->error = MMC_ERR_INVALID;
558 tasklet_schedule(&host->finish_tasklet);
559 return;
560 }
561
562 if (!(cmd->flags & MMC_RSP_PRESENT))
563 flags = SDHCI_CMD_RESP_NONE;
564 else if (cmd->flags & MMC_RSP_136)
565 flags = SDHCI_CMD_RESP_LONG;
566 else if (cmd->flags & MMC_RSP_BUSY)
567 flags = SDHCI_CMD_RESP_SHORT_BUSY;
568 else
569 flags = SDHCI_CMD_RESP_SHORT;
570
571 if (cmd->flags & MMC_RSP_CRC)
572 flags |= SDHCI_CMD_CRC;
573 if (cmd->flags & MMC_RSP_OPCODE)
574 flags |= SDHCI_CMD_INDEX;
575 if (cmd->data)
576 flags |= SDHCI_CMD_DATA;
577
fb61e289 578 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
d129bceb
PO		 579 host->ioaddr + SDHCI_COMMAND);
580}
581
582static void sdhci_finish_command(struct sdhci_host *host)
583{
584 int i;
585
586 BUG_ON(host->cmd == NULL);
587
588 if (host->cmd->flags & MMC_RSP_PRESENT) {
589 if (host->cmd->flags & MMC_RSP_136) {
590 /* CRC is stripped so we need to do some shifting. */
591 for (i = 0;i < 4;i++) {
592 host->cmd->resp[i] = readl(host->ioaddr +
593 SDHCI_RESPONSE + (3-i)*4) << 8;
594 if (i != 3)
595 host->cmd->resp[i] |=
596 readb(host->ioaddr +
597 SDHCI_RESPONSE + (3-i)*4-1);
598 }
599 } else {
600 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
601 }
602 }
603
604 host->cmd->error = MMC_ERR_NONE;
605
606 DBG("Ending cmd (%x)\n", host->cmd->opcode);
607
3192a28f 608 if (host->cmd->data)
d129bceb 609 host->data = host->cmd->data;
3192a28f 610 else
d129bceb
PO		 611 tasklet_schedule(&host->finish_tasklet);
612
613 host->cmd = NULL;
614}
615
616static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
617{
618 int div;
619 u16 clk;
7cb2c76f 620 unsigned long timeout;
d129bceb
PO		 621
622 if (clock == host->clock)
623 return;
624
625 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
626
627 if (clock == 0)
628 goto out;
629
630 for (div = 1;div < 256;div *= 2) {
631 if ((host->max_clk / div) <= clock)
632 break;
633 }
634 div >>= 1;
635
636 clk = div << SDHCI_DIVIDER_SHIFT;
637 clk |= SDHCI_CLOCK_INT_EN;
638 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
639
640 /* Wait max 10 ms */
7cb2c76f
PO		 641 timeout = 10;
642 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
643 & SDHCI_CLOCK_INT_STABLE)) {
644 if (timeout == 0) {
d129bceb
PO		 645 printk(KERN_ERR "%s: Internal clock never stabilised. "
646 "Please report this to " BUGMAIL ".\n",
647 mmc_hostname(host->mmc));
648 sdhci_dumpregs(host);
649 return;
650 }
7cb2c76f
PO		 651 timeout--;
652 mdelay(1);
653 }
d129bceb
PO		 654
655 clk |= SDHCI_CLOCK_CARD_EN;
656 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
657
658out:
659 host->clock = clock;
660}
661
146ad66e
PO		 662static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
663{
664 u8 pwr;
665
666 if (host->power == power)
667 return;
668
669 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
670
671 if (power == (unsigned short)-1)
672 goto out;
673
674 pwr = SDHCI_POWER_ON;
675
676 switch (power) {
677 case MMC_VDD_170:
678 case MMC_VDD_180:
679 case MMC_VDD_190:
680 pwr |= SDHCI_POWER_180;
681 break;
682 case MMC_VDD_290:
683 case MMC_VDD_300:
684 case MMC_VDD_310:
685 pwr |= SDHCI_POWER_300;
686 break;
687 case MMC_VDD_320:
688 case MMC_VDD_330:
689 case MMC_VDD_340:
690 pwr |= SDHCI_POWER_330;
691 break;
692 default:
693 BUG();
694 }
695
696 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
697
698out:
699 host->power = power;
700}
701
d129bceb
PO		 702/*****************************************************************************\
703 * *
704 * MMC callbacks *
705 * *
706\*****************************************************************************/
707
708static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
709{
710 struct sdhci_host *host;
711 unsigned long flags;
712
713 host = mmc_priv(mmc);
714
715 spin_lock_irqsave(&host->lock, flags);
716
717 WARN_ON(host->mrq != NULL);
718
719 sdhci_activate_led(host);
720
721 host->mrq = mrq;
722
723 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
724 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
725 tasklet_schedule(&host->finish_tasklet);
726 } else
727 sdhci_send_command(host, mrq->cmd);
728
5f25a66f 729 mmiowb();
d129bceb
PO		 730 spin_unlock_irqrestore(&host->lock, flags);
731}
732
733static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
734{
735 struct sdhci_host *host;
736 unsigned long flags;
737 u8 ctrl;
738
739 host = mmc_priv(mmc);
740
741 spin_lock_irqsave(&host->lock, flags);
742
d129bceb
PO		 743 /*
744 * Reset the chip on each power off.
745 * Should clear out any weird states.
746 */
747 if (ios->power_mode == MMC_POWER_OFF) {
748 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb 749 sdhci_init(host);
d129bceb
PO		 750 }
751
752 sdhci_set_clock(host, ios->clock);
753
754 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 755 sdhci_set_power(host, -1);
d129bceb 756 else
146ad66e 757 sdhci_set_power(host, ios->vdd);
d129bceb
PO		 758
759 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
760 if (ios->bus_width == MMC_BUS_WIDTH_4)
761 ctrl |= SDHCI_CTRL_4BITBUS;
762 else
763 ctrl &= ~SDHCI_CTRL_4BITBUS;
764 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
765
5f25a66f 766 mmiowb();
d129bceb
PO		 767 spin_unlock_irqrestore(&host->lock, flags);
768}
769
770static int sdhci_get_ro(struct mmc_host *mmc)
771{
772 struct sdhci_host *host;
773 unsigned long flags;
774 int present;
775
776 host = mmc_priv(mmc);
777
778 spin_lock_irqsave(&host->lock, flags);
779
780 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
781
782 spin_unlock_irqrestore(&host->lock, flags);
783
784 return !(present & SDHCI_WRITE_PROTECT);
785}
786
787static struct mmc_host_ops sdhci_ops = {
788 .request = sdhci_request,
789 .set_ios = sdhci_set_ios,
790 .get_ro = sdhci_get_ro,
791};
792
793/*****************************************************************************\
794 * *
795 * Tasklets *
796 * *
797\*****************************************************************************/
798
799static void sdhci_tasklet_card(unsigned long param)
800{
801 struct sdhci_host *host;
802 unsigned long flags;
803
804 host = (struct sdhci_host*)param;
805
806 spin_lock_irqsave(&host->lock, flags);
807
808 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
809 if (host->mrq) {
810 printk(KERN_ERR "%s: Card removed during transfer!\n",
811 mmc_hostname(host->mmc));
812 printk(KERN_ERR "%s: Resetting controller.\n",
813 mmc_hostname(host->mmc));
814
815 sdhci_reset(host, SDHCI_RESET_CMD);
816 sdhci_reset(host, SDHCI_RESET_DATA);
817
818 host->mrq->cmd->error = MMC_ERR_FAILED;
819 tasklet_schedule(&host->finish_tasklet);
820 }
821 }
822
823 spin_unlock_irqrestore(&host->lock, flags);
824
825 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
826}
827
828static void sdhci_tasklet_finish(unsigned long param)
829{
830 struct sdhci_host *host;
831 unsigned long flags;
832 struct mmc_request *mrq;
833
834 host = (struct sdhci_host*)param;
835
836 spin_lock_irqsave(&host->lock, flags);
837
838 del_timer(&host->timer);
839
840 mrq = host->mrq;
841
842 DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
843
844 /*
845 * The controller needs a reset of internal state machines
846 * upon error conditions.
847 */
848 if ((mrq->cmd->error != MMC_ERR_NONE) ||
849 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
850 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
645289dc
PO		 851
852 /* Some controllers need this kick or reset won't work here */
853 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
854 unsigned int clock;
855
856 /* This is to force an update */
857 clock = host->clock;
858 host->clock = 0;
859 sdhci_set_clock(host, clock);
860 }
861
862 /* Spec says we should do both at the same time, but Ricoh
863 controllers do not like that. */
d129bceb
PO		 864 sdhci_reset(host, SDHCI_RESET_CMD);
865 sdhci_reset(host, SDHCI_RESET_DATA);
866 }
867
868 host->mrq = NULL;
869 host->cmd = NULL;
870 host->data = NULL;
871
872 sdhci_deactivate_led(host);
873
5f25a66f 874 mmiowb();
d129bceb
PO		 875 spin_unlock_irqrestore(&host->lock, flags);
876
877 mmc_request_done(host->mmc, mrq);
878}
879
880static void sdhci_timeout_timer(unsigned long data)
881{
882 struct sdhci_host *host;
883 unsigned long flags;
884
885 host = (struct sdhci_host*)data;
886
887 spin_lock_irqsave(&host->lock, flags);
888
889 if (host->mrq) {
890 printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
891 "Please report this to " BUGMAIL ".\n",
892 mmc_hostname(host->mmc));
893 sdhci_dumpregs(host);
894
895 if (host->data) {
896 host->data->error = MMC_ERR_TIMEOUT;
897 sdhci_finish_data(host);
898 } else {
899 if (host->cmd)
900 host->cmd->error = MMC_ERR_TIMEOUT;
901 else
902 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
903
904 tasklet_schedule(&host->finish_tasklet);
905 }
906 }
907
5f25a66f 908 mmiowb();
d129bceb
PO		 909 spin_unlock_irqrestore(&host->lock, flags);
910}
911
912/*****************************************************************************\
913 * *
914 * Interrupt handling *
915 * *
916\*****************************************************************************/
917
918static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
919{
920 BUG_ON(intmask == 0);
921
922 if (!host->cmd) {
923 printk(KERN_ERR "%s: Got command interrupt even though no "
924 "command operation was in progress.\n",
925 mmc_hostname(host->mmc));
926 printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
927 mmc_hostname(host->mmc));
928 sdhci_dumpregs(host);
929 return;
930 }
931
932 if (intmask & SDHCI_INT_RESPONSE)
933 sdhci_finish_command(host);
934 else {
935 if (intmask & SDHCI_INT_TIMEOUT)
936 host->cmd->error = MMC_ERR_TIMEOUT;
937 else if (intmask & SDHCI_INT_CRC)
938 host->cmd->error = MMC_ERR_BADCRC;
939 else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
940 host->cmd->error = MMC_ERR_FAILED;
941 else
942 host->cmd->error = MMC_ERR_INVALID;
943
944 tasklet_schedule(&host->finish_tasklet);
945 }
946}
947
948static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
949{
950 BUG_ON(intmask == 0);
951
952 if (!host->data) {
953 /*
954 * A data end interrupt is sent together with the response
955 * for the stop command.
956 */
957 if (intmask & SDHCI_INT_DATA_END)
958 return;
959
960 printk(KERN_ERR "%s: Got data interrupt even though no "
961 "data operation was in progress.\n",
962 mmc_hostname(host->mmc));
963 printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
964 mmc_hostname(host->mmc));
965 sdhci_dumpregs(host);
966
967 return;
968 }
969
970 if (intmask & SDHCI_INT_DATA_TIMEOUT)
971 host->data->error = MMC_ERR_TIMEOUT;
972 else if (intmask & SDHCI_INT_DATA_CRC)
973 host->data->error = MMC_ERR_BADCRC;
974 else if (intmask & SDHCI_INT_DATA_END_BIT)
975 host->data->error = MMC_ERR_FAILED;
976
977 if (host->data->error != MMC_ERR_NONE)
978 sdhci_finish_data(host);
979 else {
a406f5a3 980 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 981 sdhci_transfer_pio(host);
982
983 if (intmask & SDHCI_INT_DATA_END)
984 sdhci_finish_data(host);
985 }
986}
987
7d12e780 988static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 989{
990 irqreturn_t result;
991 struct sdhci_host* host = dev_id;
992 u32 intmask;
993
994 spin_lock(&host->lock);
995
996 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
997
998 if (!intmask) {
999 result = IRQ_NONE;
1000 goto out;
1001 }
1002
1003 DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1004
3192a28f
PO		 1005 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1006 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1007 host->ioaddr + SDHCI_INT_STATUS);
d129bceb 1008 tasklet_schedule(&host->card_tasklet);
3192a28f 1009 }
d129bceb 1010
3192a28f 1011 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1012
3192a28f 1013 if (intmask & SDHCI_INT_CMD_MASK) {
d129bceb
PO		 1014 writel(intmask & SDHCI_INT_CMD_MASK,
1015 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1016 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1017 }
1018
1019 if (intmask & SDHCI_INT_DATA_MASK) {
d129bceb
PO		 1020 writel(intmask & SDHCI_INT_DATA_MASK,
1021 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1022 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1023 }
1024
1025 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1026
d129bceb 1027 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1028 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1029 mmc_hostname(host->mmc));
3192a28f 1030 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
d129bceb
PO		 1031 }
1032
3192a28f
PO		 1033 intmask &= SDHCI_INT_BUS_POWER;
1034
1035 if (intmask) {
1036 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
d129bceb 1037 "report this to " BUGMAIL ".\n",
3192a28f 1038 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1039 sdhci_dumpregs(host);
1040
d129bceb 1041 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1042 }
d129bceb
PO		 1043
1044 result = IRQ_HANDLED;
1045
5f25a66f 1046 mmiowb();
d129bceb
PO		 1047out:
1048 spin_unlock(&host->lock);
1049
1050 return result;
1051}
1052
1053/*****************************************************************************\
1054 * *
1055 * Suspend/resume *
1056 * *
1057\*****************************************************************************/
1058
1059#ifdef CONFIG_PM
1060
1061static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1062{
1063 struct sdhci_chip *chip;
1064 int i, ret;
1065
1066 chip = pci_get_drvdata(pdev);
1067 if (!chip)
1068 return 0;
1069
1070 DBG("Suspending...\n");
1071
1072 for (i = 0;i < chip->num_slots;i++) {
1073 if (!chip->hosts[i])
1074 continue;
1075 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1076 if (ret) {
1077 for (i--;i >= 0;i--)
1078 mmc_resume_host(chip->hosts[i]->mmc);
1079 return ret;
1080 }
1081 }
1082
1083 pci_save_state(pdev);
1084 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1085 pci_disable_device(pdev);
1086 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1087
1088 return 0;
1089}
1090
1091static int sdhci_resume (struct pci_dev *pdev)
1092{
1093 struct sdhci_chip *chip;
1094 int i, ret;
1095
1096 chip = pci_get_drvdata(pdev);
1097 if (!chip)
1098 return 0;
1099
1100 DBG("Resuming...\n");
1101
1102 pci_set_power_state(pdev, PCI_D0);
1103 pci_restore_state(pdev);
1104 pci_enable_device(pdev);
1105
1106 for (i = 0;i < chip->num_slots;i++) {
1107 if (!chip->hosts[i])
1108 continue;
1109 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1110 pci_set_master(pdev);
1111 sdhci_init(chip->hosts[i]);
5f25a66f 1112 mmiowb();
d129bceb
PO		 1113 ret = mmc_resume_host(chip->hosts[i]->mmc);
1114 if (ret)
1115 return ret;
1116 }
1117
1118 return 0;
1119}
1120
1121#else /* CONFIG_PM */
1122
1123#define sdhci_suspend NULL
1124#define sdhci_resume NULL
1125
1126#endif /* CONFIG_PM */
1127
1128/*****************************************************************************\
1129 * *
1130 * Device probing/removal *
1131 * *
1132\*****************************************************************************/
1133
1134static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1135{
1136 int ret;
4a965505 1137 unsigned int version;
d129bceb
PO		 1138 struct sdhci_chip *chip;
1139 struct mmc_host *mmc;
1140 struct sdhci_host *host;
1141
1142 u8 first_bar;
1143 unsigned int caps;
1144
1145 chip = pci_get_drvdata(pdev);
1146 BUG_ON(!chip);
1147
1148 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1149 if (ret)
1150 return ret;
1151
1152 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1153
1154 if (first_bar > 5) {
1155 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1156 return -ENODEV;
1157 }
1158
1159 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1160 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1161 return -ENODEV;
1162 }
1163
1164 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1165 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
1166 return -ENODEV;
1167 }
1168
67435274
PO		 1169 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1170 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1171 return -ENODEV;
1172 }
1173
1174 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1175 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1176 return -ENODEV;
1177 }
1178
d129bceb
PO		 1179 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1180 if (!mmc)
1181 return -ENOMEM;
1182
1183 host = mmc_priv(mmc);
1184 host->mmc = mmc;
1185
8a4da143
PO		 1186 host->chip = chip;
1187 chip->hosts[slot] = host;
1188
d129bceb
PO		 1189 host->bar = first_bar + slot;
1190
1191 host->addr = pci_resource_start(pdev, host->bar);
1192 host->irq = pdev->irq;
1193
1194 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1195
1196 snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1197
1198 ret = pci_request_region(pdev, host->bar, host->slot_descr);
1199 if (ret)
1200 goto free;
1201
1202 host->ioaddr = ioremap_nocache(host->addr,
1203 pci_resource_len(pdev, host->bar));
1204 if (!host->ioaddr) {
1205 ret = -ENOMEM;
1206 goto release;
1207 }
1208
d96649ed
PO		 1209 sdhci_reset(host, SDHCI_RESET_ALL);
1210
4a965505
PO		 1211 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1212 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1213 if (version != 0) {
1214 printk(KERN_ERR "%s: Unknown controller version (%d). "
8b1b2185 1215 "You may experience problems.\n", host->slot_descr,
4a965505 1216 version);
4a965505
PO		 1217 }
1218
d129bceb
PO		 1219 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1220
67435274
PO		 1221 if (debug_nodma)
1222 DBG("DMA forced off\n");
1223 else if (debug_forcedma) {
1224 DBG("DMA forced on\n");
1225 host->flags |= SDHCI_USE_DMA;
98608076
PO		 1226 } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1227 host->flags |= SDHCI_USE_DMA;
1228 else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
67435274
PO		 1229 DBG("Controller doesn't have DMA interface\n");
1230 else if (!(caps & SDHCI_CAN_DO_DMA))
1231 DBG("Controller doesn't have DMA capability\n");
1232 else
d129bceb
PO		 1233 host->flags |= SDHCI_USE_DMA;
1234
1235 if (host->flags & SDHCI_USE_DMA) {
1236 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1237 printk(KERN_WARNING "%s: No suitable DMA available. "
1238 "Falling back to PIO.\n", host->slot_descr);
1239 host->flags &= ~SDHCI_USE_DMA;
1240 }
1241 }
1242
1243 if (host->flags & SDHCI_USE_DMA)
1244 pci_set_master(pdev);
1245 else /* XXX: Hack to get MMC layer to avoid highmem */
1246 pdev->dma_mask = 0;
1247
8ef1a143
PO		 1248 host->max_clk =
1249 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1250 if (host->max_clk == 0) {
1251 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1252 "frequency.\n", host->slot_descr);
1253 ret = -ENODEV;
1254 goto unmap;
1255 }
d129bceb
PO		 1256 host->max_clk *= 1000000;
1257
1c8cde92
PO		 1258 host->timeout_clk =
1259 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1260 if (host->timeout_clk == 0) {
1261 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1262 "frequency.\n", host->slot_descr);
1263 ret = -ENODEV;
1264 goto unmap;
1265 }
1266 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1267 host->timeout_clk *= 1000;
d129bceb 1268
1d676e02
PO		 1269 host->max_block = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1270 if (host->max_block >= 3) {
1271 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1272 host->slot_descr);
1273 ret = -ENODEV;
1274 goto unmap;
1275 }
1276 host->max_block = 512 << host->max_block;
1277
d129bceb
PO		 1278 /*
1279 * Set host parameters.
1280 */
1281 mmc->ops = &sdhci_ops;
1282 mmc->f_min = host->max_clk / 256;
1283 mmc->f_max = host->max_clk;
42431acb 1284 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
d129bceb 1285
146ad66e
PO		 1286 mmc->ocr_avail = 0;
1287 if (caps & SDHCI_CAN_VDD_330)
1288 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1289 else if (caps & SDHCI_CAN_VDD_300)
1290 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1291 else if (caps & SDHCI_CAN_VDD_180)
1292 mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
1293
1294 if (mmc->ocr_avail == 0) {
1295 printk(KERN_ERR "%s: Hardware doesn't report any "
1296 "support voltages.\n", host->slot_descr);
1297 ret = -ENODEV;
1298 goto unmap;
1299 }
1300
d129bceb
PO		 1301 spin_lock_init(&host->lock);
1302
1303 /*
1304 * Maximum number of segments. Hardware cannot do scatter lists.
1305 */
1306 if (host->flags & SDHCI_USE_DMA)
1307 mmc->max_hw_segs = 1;
1308 else
1309 mmc->max_hw_segs = 16;
1310 mmc->max_phys_segs = 16;
1311
1312 /*
bab76961
PO		 1313 * Maximum number of sectors in one transfer. Limited by DMA boundary
1314 * size (512KiB), which means (512 KiB/512=) 1024 entries.
d129bceb 1315 */
bab76961 1316 mmc->max_sectors = 1024;
d129bceb
PO		 1317
1318 /*
1319 * Maximum segment size. Could be one segment with the maximum number
1320 * of sectors.
1321 */
1322 mmc->max_seg_size = mmc->max_sectors * 512;
1323
1324 /*
1325 * Init tasklets.
1326 */
1327 tasklet_init(&host->card_tasklet,
1328 sdhci_tasklet_card, (unsigned long)host);
1329 tasklet_init(&host->finish_tasklet,
1330 sdhci_tasklet_finish, (unsigned long)host);
1331
e474c66b 1332 setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
d129bceb 1333
dace1453 1334 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
d129bceb
PO		 1335 host->slot_descr, host);
1336 if (ret)
8ef1a143 1337 goto untasklet;
d129bceb
PO		 1338
1339 sdhci_init(host);
1340
1341#ifdef CONFIG_MMC_DEBUG
1342 sdhci_dumpregs(host);
1343#endif
1344
5f25a66f
PO		 1345 mmiowb();
1346
d129bceb
PO		 1347 mmc_add_host(mmc);
1348
1349 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1350 host->addr, host->irq,
1351 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1352
1353 return 0;
1354
8ef1a143 1355untasklet:
d129bceb
PO		 1356 tasklet_kill(&host->card_tasklet);
1357 tasklet_kill(&host->finish_tasklet);
8ef1a143 1358unmap:
d129bceb
PO		 1359 iounmap(host->ioaddr);
1360release:
1361 pci_release_region(pdev, host->bar);
1362free:
1363 mmc_free_host(mmc);
1364
1365 return ret;
1366}
1367
1368static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1369{
1370 struct sdhci_chip *chip;
1371 struct mmc_host *mmc;
1372 struct sdhci_host *host;
1373
1374 chip = pci_get_drvdata(pdev);
1375 host = chip->hosts[slot];
1376 mmc = host->mmc;
1377
1378 chip->hosts[slot] = NULL;
1379
1380 mmc_remove_host(mmc);
1381
1382 sdhci_reset(host, SDHCI_RESET_ALL);
1383
1384 free_irq(host->irq, host);
1385
1386 del_timer_sync(&host->timer);
1387
1388 tasklet_kill(&host->card_tasklet);
1389 tasklet_kill(&host->finish_tasklet);
1390
1391 iounmap(host->ioaddr);
1392
1393 pci_release_region(pdev, host->bar);
1394
1395 mmc_free_host(mmc);
1396}
1397
1398static int __devinit sdhci_probe(struct pci_dev *pdev,
1399 const struct pci_device_id *ent)
1400{
1401 int ret, i;
51f82bc0 1402 u8 slots, rev;
d129bceb
PO		 1403 struct sdhci_chip *chip;
1404
1405 BUG_ON(pdev == NULL);
1406 BUG_ON(ent == NULL);
1407
51f82bc0
PO		 1408 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1409
1410 printk(KERN_INFO DRIVER_NAME
1411 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1412 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1413 (int)rev);
d129bceb
PO		 1414
1415 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1416 if (ret)
1417 return ret;
1418
1419 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1420 DBG("found %d slot(s)\n", slots);
1421 if (slots == 0)
1422 return -ENODEV;
1423
1424 ret = pci_enable_device(pdev);
1425 if (ret)
1426 return ret;
1427
1428 chip = kzalloc(sizeof(struct sdhci_chip) +
1429 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1430 if (!chip) {
1431 ret = -ENOMEM;
1432 goto err;
1433 }
1434
1435 chip->pdev = pdev;
df673b22
PO		 1436 chip->quirks = ent->driver_data;
1437
1438 if (debug_quirks)
1439 chip->quirks = debug_quirks;
d129bceb
PO		 1440
1441 chip->num_slots = slots;
1442 pci_set_drvdata(pdev, chip);
1443
1444 for (i = 0;i < slots;i++) {
1445 ret = sdhci_probe_slot(pdev, i);
1446 if (ret) {
1447 for (i--;i >= 0;i--)
1448 sdhci_remove_slot(pdev, i);
1449 goto free;
1450 }
1451 }
1452
1453 return 0;
1454
1455free:
1456 pci_set_drvdata(pdev, NULL);
1457 kfree(chip);
1458
1459err:
1460 pci_disable_device(pdev);
1461 return ret;
1462}
1463
1464static void __devexit sdhci_remove(struct pci_dev *pdev)
1465{
1466 int i;
1467 struct sdhci_chip *chip;
1468
1469 chip = pci_get_drvdata(pdev);
1470
1471 if (chip) {
1472 for (i = 0;i < chip->num_slots;i++)
1473 sdhci_remove_slot(pdev, i);
1474
1475 pci_set_drvdata(pdev, NULL);
1476
1477 kfree(chip);
1478 }
1479
1480 pci_disable_device(pdev);
1481}
1482
1483static struct pci_driver sdhci_driver = {
1484 .name = DRIVER_NAME,
1485 .id_table = pci_ids,
1486 .probe = sdhci_probe,
1487 .remove = __devexit_p(sdhci_remove),
1488 .suspend = sdhci_suspend,
1489 .resume = sdhci_resume,
1490};
1491
1492/*****************************************************************************\
1493 * *
1494 * Driver init/exit *
1495 * *
1496\*****************************************************************************/
1497
1498static int __init sdhci_drv_init(void)
1499{
1500 printk(KERN_INFO DRIVER_NAME
1501 ": Secure Digital Host Controller Interface driver, "
1502 DRIVER_VERSION "\n");
1503 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1504
1505 return pci_register_driver(&sdhci_driver);
1506}
1507
1508static void __exit sdhci_drv_exit(void)
1509{
1510 DBG("Exiting\n");
1511
1512 pci_unregister_driver(&sdhci_driver);
1513}
1514
1515module_init(sdhci_drv_init);
1516module_exit(sdhci_drv_exit);
1517
67435274
PO		 1518module_param(debug_nodma, uint, 0444);
1519module_param(debug_forcedma, uint, 0444);
df673b22 1520module_param(debug_quirks, uint, 0444);
67435274 1521
d129bceb
PO		 1522MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1523MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1524MODULE_VERSION(DRIVER_VERSION);
1525MODULE_LICENSE("GPL");
67435274
PO		 1526
1527MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1528MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
df673b22 1529MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
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