[net-next-2.6.git] / drivers / mmc / host / sdhci.h

/*
 *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
 *
 * Header file for Host Controller registers and I/O accessors.
 *
 *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */
#ifndef __SDHCI_HW_H
#define __SDHCI_HW_H

#include <linux/scatterlist.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/io.h>

#include <linux/mmc/sdhci.h>

/*
 * Controller registers
 */

#define SDHCI_DMA_ADDRESS	0x00

#define SDHCI_BLOCK_SIZE	0x04
#define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))

#define SDHCI_BLOCK_COUNT	0x06

#define SDHCI_ARGUMENT		0x08

#define SDHCI_TRANSFER_MODE	0x0C
#define  SDHCI_TRNS_DMA		0x01
#define  SDHCI_TRNS_BLK_CNT_EN	0x02
#define  SDHCI_TRNS_ACMD12	0x04
#define  SDHCI_TRNS_READ	0x10
#define  SDHCI_TRNS_MULTI	0x20

#define SDHCI_COMMAND		0x0E
#define  SDHCI_CMD_RESP_MASK	0x03
#define  SDHCI_CMD_CRC		0x08
#define  SDHCI_CMD_INDEX	0x10
#define  SDHCI_CMD_DATA		0x20

#define  SDHCI_CMD_RESP_NONE	0x00
#define  SDHCI_CMD_RESP_LONG	0x01
#define  SDHCI_CMD_RESP_SHORT	0x02
#define  SDHCI_CMD_RESP_SHORT_BUSY 0x03

#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))

#define SDHCI_RESPONSE		0x10

#define SDHCI_BUFFER		0x20

#define SDHCI_PRESENT_STATE	0x24
#define  SDHCI_CMD_INHIBIT	0x00000001
#define  SDHCI_DATA_INHIBIT	0x00000002
#define  SDHCI_DOING_WRITE	0x00000100
#define  SDHCI_DOING_READ	0x00000200
#define  SDHCI_SPACE_AVAILABLE	0x00000400
#define  SDHCI_DATA_AVAILABLE	0x00000800
#define  SDHCI_CARD_PRESENT	0x00010000
#define  SDHCI_WRITE_PROTECT	0x00080000

#define SDHCI_HOST_CONTROL 	0x28
#define  SDHCI_CTRL_LED		0x01
#define  SDHCI_CTRL_4BITBUS	0x02
#define  SDHCI_CTRL_HISPD	0x04
#define  SDHCI_CTRL_DMA_MASK	0x18
#define   SDHCI_CTRL_SDMA	0x00
#define   SDHCI_CTRL_ADMA1	0x08
#define   SDHCI_CTRL_ADMA32	0x10
#define   SDHCI_CTRL_ADMA64	0x18
#define  SDHCI_CTRL_8BITBUS	0x20

#define SDHCI_POWER_CONTROL	0x29
#define  SDHCI_POWER_ON		0x01
#define  SDHCI_POWER_180	0x0A
#define  SDHCI_POWER_300	0x0C
#define  SDHCI_POWER_330	0x0E

#define SDHCI_BLOCK_GAP_CONTROL	0x2A

#define SDHCI_WAKE_UP_CONTROL	0x2B

#define SDHCI_CLOCK_CONTROL	0x2C
#define  SDHCI_DIVIDER_SHIFT	8
#define  SDHCI_DIVIDER_HI_SHIFT	6
#define  SDHCI_DIV_MASK	0xFF
#define  SDHCI_DIV_MASK_LEN	8
#define  SDHCI_DIV_HI_MASK	0x300
#define  SDHCI_CLOCK_CARD_EN	0x0004
#define  SDHCI_CLOCK_INT_STABLE	0x0002
#define  SDHCI_CLOCK_INT_EN	0x0001

#define SDHCI_TIMEOUT_CONTROL	0x2E

#define SDHCI_SOFTWARE_RESET	0x2F
#define  SDHCI_RESET_ALL	0x01
#define  SDHCI_RESET_CMD	0x02
#define  SDHCI_RESET_DATA	0x04

#define SDHCI_INT_STATUS	0x30
#define SDHCI_INT_ENABLE	0x34
#define SDHCI_SIGNAL_ENABLE	0x38
#define  SDHCI_INT_RESPONSE	0x00000001
#define  SDHCI_INT_DATA_END	0x00000002
#define  SDHCI_INT_DMA_END	0x00000008
#define  SDHCI_INT_SPACE_AVAIL	0x00000010
#define  SDHCI_INT_DATA_AVAIL	0x00000020
#define  SDHCI_INT_CARD_INSERT	0x00000040
#define  SDHCI_INT_CARD_REMOVE	0x00000080
#define  SDHCI_INT_CARD_INT	0x00000100
#define  SDHCI_INT_ERROR	0x00008000
#define  SDHCI_INT_TIMEOUT	0x00010000
#define  SDHCI_INT_CRC		0x00020000
#define  SDHCI_INT_END_BIT	0x00040000
#define  SDHCI_INT_INDEX	0x00080000
#define  SDHCI_INT_DATA_TIMEOUT	0x00100000
#define  SDHCI_INT_DATA_CRC	0x00200000
#define  SDHCI_INT_DATA_END_BIT	0x00400000
#define  SDHCI_INT_BUS_POWER	0x00800000
#define  SDHCI_INT_ACMD12ERR	0x01000000
#define  SDHCI_INT_ADMA_ERROR	0x02000000

#define  SDHCI_INT_NORMAL_MASK	0x00007FFF
#define  SDHCI_INT_ERROR_MASK	0xFFFF8000

#define  SDHCI_INT_CMD_MASK	(SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
		SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
#define  SDHCI_INT_DATA_MASK	(SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
		SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
		SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
		SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
#define SDHCI_INT_ALL_MASK	((unsigned int)-1)

#define SDHCI_ACMD12_ERR	0x3C

/* 3E-3F reserved */

#define SDHCI_CAPABILITIES	0x40
#define  SDHCI_TIMEOUT_CLK_MASK	0x0000003F
#define  SDHCI_TIMEOUT_CLK_SHIFT 0
#define  SDHCI_TIMEOUT_CLK_UNIT	0x00000080
#define  SDHCI_CLOCK_BASE_MASK	0x00003F00
#define  SDHCI_CLOCK_V3_BASE_MASK	0x0000FF00
#define  SDHCI_CLOCK_BASE_SHIFT	8
#define  SDHCI_MAX_BLOCK_MASK	0x00030000
#define  SDHCI_MAX_BLOCK_SHIFT  16
#define  SDHCI_CAN_DO_ADMA2	0x00080000
#define  SDHCI_CAN_DO_ADMA1	0x00100000
#define  SDHCI_CAN_DO_HISPD	0x00200000
#define  SDHCI_CAN_DO_SDMA	0x00400000
#define  SDHCI_CAN_VDD_330	0x01000000
#define  SDHCI_CAN_VDD_300	0x02000000
#define  SDHCI_CAN_VDD_180	0x04000000
#define  SDHCI_CAN_64BIT	0x10000000

/* 44-47 reserved for more caps */

#define SDHCI_MAX_CURRENT	0x48

/* 4C-4F reserved for more max current */

#define SDHCI_SET_ACMD12_ERROR	0x50
#define SDHCI_SET_INT_ERROR	0x52

#define SDHCI_ADMA_ERROR	0x54

/* 55-57 reserved */

#define SDHCI_ADMA_ADDRESS	0x58

/* 60-FB reserved */

#define SDHCI_SLOT_INT_STATUS	0xFC

#define SDHCI_HOST_VERSION	0xFE
#define  SDHCI_VENDOR_VER_MASK	0xFF00
#define  SDHCI_VENDOR_VER_SHIFT	8
#define  SDHCI_SPEC_VER_MASK	0x00FF
#define  SDHCI_SPEC_VER_SHIFT	0
#define   SDHCI_SPEC_100	0
#define   SDHCI_SPEC_200	1
#define   SDHCI_SPEC_300	2

/*
 * End of controller registers.
 */

#define SDHCI_MAX_DIV_SPEC_200	256
#define SDHCI_MAX_DIV_SPEC_300	2046

struct sdhci_ops {
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	u32		(*read_l)(struct sdhci_host *host, int reg);
	u16		(*read_w)(struct sdhci_host *host, int reg);
	u8		(*read_b)(struct sdhci_host *host, int reg);
	void		(*write_l)(struct sdhci_host *host, u32 val, int reg);
	void		(*write_w)(struct sdhci_host *host, u16 val, int reg);
	void		(*write_b)(struct sdhci_host *host, u8 val, int reg);
#endif

	void	(*set_clock)(struct sdhci_host *host, unsigned int clock);

	int		(*enable_dma)(struct sdhci_host *host);
	unsigned int	(*get_max_clock)(struct sdhci_host *host);
	unsigned int	(*get_min_clock)(struct sdhci_host *host);
	unsigned int	(*get_timeout_clock)(struct sdhci_host *host);
	void (*platform_send_init_74_clocks)(struct sdhci_host *host,
					     u8 power_mode);
	unsigned int    (*get_ro)(struct sdhci_host *host);
};

#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS

static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	if (unlikely(host->ops->write_l))
		host->ops->write_l(host, val, reg);
	else
		writel(val, host->ioaddr + reg);
}

static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	if (unlikely(host->ops->write_w))
		host->ops->write_w(host, val, reg);
	else
		writew(val, host->ioaddr + reg);
}

static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
	if (unlikely(host->ops->write_b))
		host->ops->write_b(host, val, reg);
	else
		writeb(val, host->ioaddr + reg);
}

static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_l))
		return host->ops->read_l(host, reg);
	else
		return readl(host->ioaddr + reg);
}

static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_w))
		return host->ops->read_w(host, reg);
	else
		return readw(host->ioaddr + reg);
}

static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
{
	if (unlikely(host->ops->read_b))
		return host->ops->read_b(host, reg);
	else
		return readb(host->ioaddr + reg);
}

#else

static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
{
	writel(val, host->ioaddr + reg);
}

static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
{
	writew(val, host->ioaddr + reg);
}

static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
	writeb(val, host->ioaddr + reg);
}

static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
{
	return readl(host->ioaddr + reg);
}

static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
{
	return readw(host->ioaddr + reg);
}

static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
{
	return readb(host->ioaddr + reg);
}

#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */

extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
	size_t priv_size);
extern void sdhci_free_host(struct sdhci_host *host);

static inline void *sdhci_priv(struct sdhci_host *host)
{
	return (void *)host->private;
}

extern void sdhci_card_detect(struct sdhci_host *host);
extern int sdhci_add_host(struct sdhci_host *host);
extern void sdhci_remove_host(struct sdhci_host *host, int dead);

#ifdef CONFIG_PM
extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
extern int sdhci_resume_host(struct sdhci_host *host);
#endif

#endif /* __SDHCI_HW_H */
Commit	Line	Data
d129bceb	1	/*
70f10482	2	* linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
d129bceb	3	*
1978fda8 GC	4	* Header file for Host Controller registers and I/O accessors.
1978fda8 GC	5	*
b69c9058	6	* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb PO	7	*
d129bceb PO	8	* This program is free software; you can redistribute it and/or modify
643f720c PO	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or (at
	11	* your option) any later version.
d129bceb	12	*/
1978fda8 GC	13	#ifndef __SDHCI_HW_H
1978fda8 GC	14	#define __SDHCI_HW_H
d129bceb	15
0c7ad106	16	#include <linux/scatterlist.h>
4e4141a5 AV	17	#include <linux/compiler.h>
	18	#include <linux/types.h>
	19	#include <linux/io.h>
0c7ad106	20
1978fda8 GC	21	#include <linux/mmc/sdhci.h>
1978fda8 GC	22
d129bceb PO	23	/*
	24	* Controller registers
	25	*/
	26
	27	#define SDHCI_DMA_ADDRESS 0x00
	28
	29	#define SDHCI_BLOCK_SIZE 0x04
bab76961	30	#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) \| (blksz & 0xFFF))
d129bceb PO	31
	32	#define SDHCI_BLOCK_COUNT 0x06
	33
	34	#define SDHCI_ARGUMENT 0x08
	35
	36	#define SDHCI_TRANSFER_MODE 0x0C
	37	#define SDHCI_TRNS_DMA 0x01
	38	#define SDHCI_TRNS_BLK_CNT_EN 0x02
	39	#define SDHCI_TRNS_ACMD12 0x04
	40	#define SDHCI_TRNS_READ 0x10
	41	#define SDHCI_TRNS_MULTI 0x20
	42
	43	#define SDHCI_COMMAND 0x0E
	44	#define SDHCI_CMD_RESP_MASK 0x03
	45	#define SDHCI_CMD_CRC 0x08
	46	#define SDHCI_CMD_INDEX 0x10
	47	#define SDHCI_CMD_DATA 0x20
	48
	49	#define SDHCI_CMD_RESP_NONE 0x00
	50	#define SDHCI_CMD_RESP_LONG 0x01
	51	#define SDHCI_CMD_RESP_SHORT 0x02
	52	#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
	53
	54	#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) \| (f & 0xff))
	55
	56	#define SDHCI_RESPONSE 0x10
	57
	58	#define SDHCI_BUFFER 0x20
	59
	60	#define SDHCI_PRESENT_STATE 0x24
	61	#define SDHCI_CMD_INHIBIT 0x00000001
	62	#define SDHCI_DATA_INHIBIT 0x00000002
	63	#define SDHCI_DOING_WRITE 0x00000100
	64	#define SDHCI_DOING_READ 0x00000200
	65	#define SDHCI_SPACE_AVAILABLE 0x00000400
	66	#define SDHCI_DATA_AVAILABLE 0x00000800
	67	#define SDHCI_CARD_PRESENT 0x00010000
	68	#define SDHCI_WRITE_PROTECT 0x00080000
	69
	70	#define SDHCI_HOST_CONTROL 0x28
	71	#define SDHCI_CTRL_LED 0x01
	72	#define SDHCI_CTRL_4BITBUS 0x02
077df884	73	#define SDHCI_CTRL_HISPD 0x04
2134a922 PO	74	#define SDHCI_CTRL_DMA_MASK 0x18
	75	#define SDHCI_CTRL_SDMA 0x00
	76	#define SDHCI_CTRL_ADMA1 0x08
	77	#define SDHCI_CTRL_ADMA32 0x10
	78	#define SDHCI_CTRL_ADMA64 0x18
ae6d6c92	79	#define SDHCI_CTRL_8BITBUS 0x20
d129bceb PO	80
d129bceb PO	81	#define SDHCI_POWER_CONTROL 0x29
146ad66e PO	82	#define SDHCI_POWER_ON 0x01
	83	#define SDHCI_POWER_180 0x0A
	84	#define SDHCI_POWER_300 0x0C
	85	#define SDHCI_POWER_330 0x0E
d129bceb PO	86
	87	#define SDHCI_BLOCK_GAP_CONTROL 0x2A
	88
2df3b71b	89	#define SDHCI_WAKE_UP_CONTROL 0x2B
d129bceb PO	90
	91	#define SDHCI_CLOCK_CONTROL 0x2C
	92	#define SDHCI_DIVIDER_SHIFT 8
85105c53 ZG	93	#define SDHCI_DIVIDER_HI_SHIFT 6
	94	#define SDHCI_DIV_MASK 0xFF
	95	#define SDHCI_DIV_MASK_LEN 8
	96	#define SDHCI_DIV_HI_MASK 0x300
d129bceb PO	97	#define SDHCI_CLOCK_CARD_EN 0x0004
	98	#define SDHCI_CLOCK_INT_STABLE 0x0002
	99	#define SDHCI_CLOCK_INT_EN 0x0001
	100
	101	#define SDHCI_TIMEOUT_CONTROL 0x2E
	102
	103	#define SDHCI_SOFTWARE_RESET 0x2F
	104	#define SDHCI_RESET_ALL 0x01
	105	#define SDHCI_RESET_CMD 0x02
	106	#define SDHCI_RESET_DATA 0x04
	107
	108	#define SDHCI_INT_STATUS 0x30
	109	#define SDHCI_INT_ENABLE 0x34
	110	#define SDHCI_SIGNAL_ENABLE 0x38
	111	#define SDHCI_INT_RESPONSE 0x00000001
	112	#define SDHCI_INT_DATA_END 0x00000002
	113	#define SDHCI_INT_DMA_END 0x00000008
a406f5a3 PO	114	#define SDHCI_INT_SPACE_AVAIL 0x00000010
a406f5a3 PO	115	#define SDHCI_INT_DATA_AVAIL 0x00000020
d129bceb PO	116	#define SDHCI_INT_CARD_INSERT 0x00000040
	117	#define SDHCI_INT_CARD_REMOVE 0x00000080
	118	#define SDHCI_INT_CARD_INT 0x00000100
964f9ce2	119	#define SDHCI_INT_ERROR 0x00008000
d129bceb PO	120	#define SDHCI_INT_TIMEOUT 0x00010000
	121	#define SDHCI_INT_CRC 0x00020000
	122	#define SDHCI_INT_END_BIT 0x00040000
	123	#define SDHCI_INT_INDEX 0x00080000
	124	#define SDHCI_INT_DATA_TIMEOUT 0x00100000
	125	#define SDHCI_INT_DATA_CRC 0x00200000
	126	#define SDHCI_INT_DATA_END_BIT 0x00400000
	127	#define SDHCI_INT_BUS_POWER 0x00800000
	128	#define SDHCI_INT_ACMD12ERR 0x01000000
2134a922	129	#define SDHCI_INT_ADMA_ERROR 0x02000000
d129bceb PO	130
	131	#define SDHCI_INT_NORMAL_MASK 0x00007FFF
	132	#define SDHCI_INT_ERROR_MASK 0xFFFF8000
	133
	134	#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE \| SDHCI_INT_TIMEOUT \| \
	135	SDHCI_INT_CRC \| SDHCI_INT_END_BIT \| SDHCI_INT_INDEX)
	136	#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END \| SDHCI_INT_DMA_END \| \
a406f5a3	137	SDHCI_INT_DATA_AVAIL \| SDHCI_INT_SPACE_AVAIL \| \
d129bceb	138	SDHCI_INT_DATA_TIMEOUT \| SDHCI_INT_DATA_CRC \| \
a751a7d6	139	SDHCI_INT_DATA_END_BIT \| SDHCI_INT_ADMA_ERROR)
7260cf5e	140	#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
d129bceb PO	141
	142	#define SDHCI_ACMD12_ERR 0x3C
	143
	144	/* 3E-3F reserved */
	145
	146	#define SDHCI_CAPABILITIES 0x40
1c8cde92 PO	147	#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
	148	#define SDHCI_TIMEOUT_CLK_SHIFT 0
	149	#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
d129bceb	150	#define SDHCI_CLOCK_BASE_MASK 0x00003F00
c4687d5f	151	#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
d129bceb	152	#define SDHCI_CLOCK_BASE_SHIFT 8
1d676e02 PO	153	#define SDHCI_MAX_BLOCK_MASK 0x00030000
1d676e02 PO	154	#define SDHCI_MAX_BLOCK_SHIFT 16
2134a922 PO	155	#define SDHCI_CAN_DO_ADMA2 0x00080000
2134a922 PO	156	#define SDHCI_CAN_DO_ADMA1 0x00100000
077df884	157	#define SDHCI_CAN_DO_HISPD 0x00200000
a13abc7b	158	#define SDHCI_CAN_DO_SDMA 0x00400000
146ad66e PO	159	#define SDHCI_CAN_VDD_330 0x01000000
	160	#define SDHCI_CAN_VDD_300 0x02000000
	161	#define SDHCI_CAN_VDD_180 0x04000000
2134a922	162	#define SDHCI_CAN_64BIT 0x10000000
d129bceb PO	163
	164	/* 44-47 reserved for more caps */
	165
	166	#define SDHCI_MAX_CURRENT 0x48
	167
	168	/* 4C-4F reserved for more max current */
	169
2134a922 PO	170	#define SDHCI_SET_ACMD12_ERROR 0x50
	171	#define SDHCI_SET_INT_ERROR 0x52
	172
	173	#define SDHCI_ADMA_ERROR 0x54
	174
	175	/* 55-57 reserved */
	176
	177	#define SDHCI_ADMA_ADDRESS 0x58
	178
	179	/* 60-FB reserved */
d129bceb PO	180
	181	#define SDHCI_SLOT_INT_STATUS 0xFC
	182
	183	#define SDHCI_HOST_VERSION 0xFE
4a965505 PO	184	#define SDHCI_VENDOR_VER_MASK 0xFF00
	185	#define SDHCI_VENDOR_VER_SHIFT 8
	186	#define SDHCI_SPEC_VER_MASK 0x00FF
	187	#define SDHCI_SPEC_VER_SHIFT 0
2134a922 PO	188	#define SDHCI_SPEC_100 0
2134a922 PO	189	#define SDHCI_SPEC_200 1
85105c53	190	#define SDHCI_SPEC_300 2
d129bceb	191
0397526d ZG	192	/*
	193	* End of controller registers.
	194	*/
	195
	196	#define SDHCI_MAX_DIV_SPEC_200 256
	197	#define SDHCI_MAX_DIV_SPEC_300 2046
	198
b8c86fc5	199	struct sdhci_ops {
4e4141a5	200	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
dc297c92 MF	201	u32 (read_l)(struct sdhci_host host, int reg);
	202	u16 (read_w)(struct sdhci_host host, int reg);
	203	u8 (read_b)(struct sdhci_host host, int reg);
	204	void (write_l)(struct sdhci_host host, u32 val, int reg);
	205	void (write_w)(struct sdhci_host host, u16 val, int reg);
	206	void (write_b)(struct sdhci_host host, u8 val, int reg);
4e4141a5 AV	207	#endif
4e4141a5 AV	208
8114634c AV	209	void (set_clock)(struct sdhci_host host, unsigned int clock);
8114634c AV	210
b8c86fc5	211	int (enable_dma)(struct sdhci_host host);
4240ff0a	212	unsigned int (get_max_clock)(struct sdhci_host host);
a9e58f25	213	unsigned int (get_min_clock)(struct sdhci_host host);
4240ff0a	214	unsigned int (get_timeout_clock)(struct sdhci_host host);
643a81ff PR	215	void (platform_send_init_74_clocks)(struct sdhci_host host,
643a81ff PR	216	u8 power_mode);
2dfb579c	217	unsigned int (get_ro)(struct sdhci_host host);
d129bceb	218	};
b8c86fc5	219
4e4141a5 AV	220	#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
	221
	222	static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	223	{
dc297c92 MF	224	if (unlikely(host->ops->write_l))
dc297c92 MF	225	host->ops->write_l(host, val, reg);
4e4141a5 AV	226	else
	227	writel(val, host->ioaddr + reg);
	228	}
	229
	230	static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	231	{
dc297c92 MF	232	if (unlikely(host->ops->write_w))
dc297c92 MF	233	host->ops->write_w(host, val, reg);
4e4141a5 AV	234	else
	235	writew(val, host->ioaddr + reg);
	236	}
	237
	238	static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
	239	{
dc297c92 MF	240	if (unlikely(host->ops->write_b))
dc297c92 MF	241	host->ops->write_b(host, val, reg);
4e4141a5 AV	242	else
	243	writeb(val, host->ioaddr + reg);
	244	}
	245
	246	static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
	247	{
dc297c92 MF	248	if (unlikely(host->ops->read_l))
dc297c92 MF	249	return host->ops->read_l(host, reg);
4e4141a5 AV	250	else
	251	return readl(host->ioaddr + reg);
	252	}
	253
	254	static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
	255	{
dc297c92 MF	256	if (unlikely(host->ops->read_w))
dc297c92 MF	257	return host->ops->read_w(host, reg);
4e4141a5 AV	258	else
	259	return readw(host->ioaddr + reg);
	260	}
	261
	262	static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
	263	{
dc297c92 MF	264	if (unlikely(host->ops->read_b))
dc297c92 MF	265	return host->ops->read_b(host, reg);
4e4141a5 AV	266	else
	267	return readb(host->ioaddr + reg);
	268	}
	269
	270	#else
	271
	272	static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
	273	{
	274	writel(val, host->ioaddr + reg);
	275	}
	276
	277	static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
	278	{
	279	writew(val, host->ioaddr + reg);
	280	}
	281
	282	static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
	283	{
	284	writeb(val, host->ioaddr + reg);
	285	}
	286
	287	static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
	288	{
	289	return readl(host->ioaddr + reg);
	290	}
	291
	292	static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
	293	{
	294	return readw(host->ioaddr + reg);
	295	}
	296
	297	static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
	298	{
	299	return readb(host->ioaddr + reg);
	300	}
	301
	302	#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
b8c86fc5 PO	303
	304	extern struct sdhci_host sdhci_alloc_host(struct device dev,
	305	size_t priv_size);
	306	extern void sdhci_free_host(struct sdhci_host *host);
	307
	308	static inline void sdhci_priv(struct sdhci_host host)
	309	{
	310	return (void *)host->private;
	311	}
	312
17866e14	313	extern void sdhci_card_detect(struct sdhci_host *host);
b8c86fc5	314	extern int sdhci_add_host(struct sdhci_host *host);
1e72859e	315	extern void sdhci_remove_host(struct sdhci_host *host, int dead);
b8c86fc5 PO	316
	317	#ifdef CONFIG_PM
	318	extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
	319	extern int sdhci_resume_host(struct sdhci_host *host);
	320	#endif
c0bba0d2	321
1978fda8	322	#endif /* __SDHCI_HW_H */