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[net-next-2.6.git] / drivers / mmc / host / sdhci.c
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d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
11763609 20#include <linux/scatterlist.h>
d129bceb 21
2f730fec
PO		 22#include <linux/leds.h>
23
d129bceb 24#include <linux/mmc/host.h>
d129bceb 25
d129bceb
PO		 26#include "sdhci.h"
27
28#define DRIVER_NAME "sdhci"
d129bceb 29
d129bceb 30#define DBG(f, x...) \
c6563178 31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 32
df673b22 33static unsigned int debug_quirks = 0;
67435274 34
d129bceb
PO		 35static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
36static void sdhci_finish_data(struct sdhci_host *);
37
38static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
39static void sdhci_finish_command(struct sdhci_host *);
40
41static void sdhci_dumpregs(struct sdhci_host *host)
42{
43 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
44
45 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
46 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
47 readw(host->ioaddr + SDHCI_HOST_VERSION));
48 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
49 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
50 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
51 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
52 readl(host->ioaddr + SDHCI_ARGUMENT),
53 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
54 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
55 readl(host->ioaddr + SDHCI_PRESENT_STATE),
56 readb(host->ioaddr + SDHCI_HOST_CONTROL));
57 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
58 readb(host->ioaddr + SDHCI_POWER_CONTROL),
59 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
60 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
2df3b71b 61 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
d129bceb
PO		 62 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
63 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
64 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
65 readl(host->ioaddr + SDHCI_INT_STATUS));
66 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
67 readl(host->ioaddr + SDHCI_INT_ENABLE),
68 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
69 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
70 readw(host->ioaddr + SDHCI_ACMD12_ERR),
71 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
72 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
73 readl(host->ioaddr + SDHCI_CAPABILITIES),
74 readl(host->ioaddr + SDHCI_MAX_CURRENT));
75
76 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
77}
78
79/*****************************************************************************\
80 * *
81 * Low level functions *
82 * *
83\*****************************************************************************/
84
85static void sdhci_reset(struct sdhci_host *host, u8 mask)
86{
e16514d8
PO		 87 unsigned long timeout;
88
b8c86fc5 89 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
8a4da143
PO		 90 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
91 SDHCI_CARD_PRESENT))
92 return;
93 }
94
d129bceb
PO		 95 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
96
e16514d8 97 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 98 host->clock = 0;
99
e16514d8
PO		 100 /* Wait max 100 ms */
101 timeout = 100;
102
103 /* hw clears the bit when it's done */
104 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
105 if (timeout == 0) {
acf1da45 106 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 107 mmc_hostname(host->mmc), (int)mask);
108 sdhci_dumpregs(host);
109 return;
110 }
111 timeout--;
112 mdelay(1);
d129bceb
PO		 113 }
114}
115
116static void sdhci_init(struct sdhci_host *host)
117{
118 u32 intmask;
119
120 sdhci_reset(host, SDHCI_RESET_ALL);
121
3192a28f
PO		 122 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
123 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
124 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
125 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 126 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
2134a922
PO		 127 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
128 SDHCI_INT_ADMA_ERROR;
d129bceb
PO		 129
130 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
131 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 132}
133
134static void sdhci_activate_led(struct sdhci_host *host)
135{
136 u8 ctrl;
137
138 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
139 ctrl |= SDHCI_CTRL_LED;
140 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
141}
142
143static void sdhci_deactivate_led(struct sdhci_host *host)
144{
145 u8 ctrl;
146
147 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
148 ctrl &= ~SDHCI_CTRL_LED;
149 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
150}
151
2f730fec
PO		 152#ifdef CONFIG_LEDS_CLASS
153static void sdhci_led_control(struct led_classdev *led,
154 enum led_brightness brightness)
155{
156 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
157 unsigned long flags;
158
159 spin_lock_irqsave(&host->lock, flags);
160
161 if (brightness == LED_OFF)
162 sdhci_deactivate_led(host);
163 else
164 sdhci_activate_led(host);
165
166 spin_unlock_irqrestore(&host->lock, flags);
167}
168#endif
169
d129bceb
PO		 170/*****************************************************************************\
171 * *
172 * Core functions *
173 * *
174\*****************************************************************************/
175
2a22b14e 176static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
d129bceb 177{
45711f1a 178 return sg_virt(host->cur_sg);
d129bceb
PO		 179}
180
181static inline int sdhci_next_sg(struct sdhci_host* host)
182{
183 /*
184 * Skip to next SG entry.
185 */
186 host->cur_sg++;
187 host->num_sg--;
188
189 /*
190 * Any entries left?
191 */
192 if (host->num_sg > 0) {
193 host->offset = 0;
194 host->remain = host->cur_sg->length;
195 }
196
197 return host->num_sg;
198}
199
a406f5a3 200static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 201{
a406f5a3
PO		 202 int blksize, chunk_remain;
203 u32 data;
d129bceb 204 char *buffer;
a406f5a3 205 int size;
d129bceb 206
a406f5a3 207 DBG("PIO reading\n");
d129bceb 208
a406f5a3
PO		 209 blksize = host->data->blksz;
210 chunk_remain = 0;
211 data = 0;
d129bceb 212
2a22b14e 213 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 214
a406f5a3
PO		 215 while (blksize) {
216 if (chunk_remain == 0) {
217 data = readl(host->ioaddr + SDHCI_BUFFER);
218 chunk_remain = min(blksize, 4);
219 }
d129bceb 220
14d836e7 221 size = min(host->remain, chunk_remain);
d129bceb 222
a406f5a3
PO		 223 chunk_remain -= size;
224 blksize -= size;
225 host->offset += size;
226 host->remain -= size;
14d836e7 227
a406f5a3
PO		 228 while (size) {
229 *buffer = data & 0xFF;
230 buffer++;
231 data >>= 8;
232 size--;
233 }
d129bceb 234
a406f5a3 235 if (host->remain == 0) {
a406f5a3
PO		 236 if (sdhci_next_sg(host) == 0) {
237 BUG_ON(blksize != 0);
238 return;
239 }
2a22b14e 240 buffer = sdhci_sg_to_buffer(host);
d129bceb 241 }
a406f5a3 242 }
a406f5a3 243}
d129bceb 244
a406f5a3
PO		 245static void sdhci_write_block_pio(struct sdhci_host *host)
246{
247 int blksize, chunk_remain;
248 u32 data;
249 char *buffer;
250 int bytes, size;
d129bceb 251
a406f5a3
PO		 252 DBG("PIO writing\n");
253
254 blksize = host->data->blksz;
255 chunk_remain = 4;
256 data = 0;
d129bceb 257
a406f5a3 258 bytes = 0;
2a22b14e 259 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 260
a406f5a3 261 while (blksize) {
14d836e7 262 size = min(host->remain, chunk_remain);
a406f5a3
PO		 263
264 chunk_remain -= size;
265 blksize -= size;
d129bceb
PO		 266 host->offset += size;
267 host->remain -= size;
14d836e7 268
a406f5a3
PO		 269 while (size) {
270 data >>= 8;
271 data |= (u32)*buffer << 24;
272 buffer++;
273 size--;
274 }
275
276 if (chunk_remain == 0) {
277 writel(data, host->ioaddr + SDHCI_BUFFER);
278 chunk_remain = min(blksize, 4);
279 }
d129bceb
PO		 280
281 if (host->remain == 0) {
d129bceb 282 if (sdhci_next_sg(host) == 0) {
a406f5a3 283 BUG_ON(blksize != 0);
d129bceb
PO		 284 return;
285 }
2a22b14e 286 buffer = sdhci_sg_to_buffer(host);
d129bceb
PO		 287 }
288 }
a406f5a3
PO		 289}
290
291static void sdhci_transfer_pio(struct sdhci_host *host)
292{
293 u32 mask;
294
295 BUG_ON(!host->data);
296
14d836e7 297 if (host->num_sg == 0)
a406f5a3
PO		 298 return;
299
300 if (host->data->flags & MMC_DATA_READ)
301 mask = SDHCI_DATA_AVAILABLE;
302 else
303 mask = SDHCI_SPACE_AVAILABLE;
304
305 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
306 if (host->data->flags & MMC_DATA_READ)
307 sdhci_read_block_pio(host);
308 else
309 sdhci_write_block_pio(host);
d129bceb 310
14d836e7 311 if (host->num_sg == 0)
a406f5a3 312 break;
a406f5a3 313 }
d129bceb 314
a406f5a3 315 DBG("PIO transfer complete.\n");
d129bceb
PO		 316}
317
2134a922
PO		 318static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
319{
320 local_irq_save(*flags);
321 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
322}
323
324static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
325{
326 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
327 local_irq_restore(*flags);
328}
329
8f1934ce 330static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 331 struct mmc_data *data)
332{
333 int direction;
334
335 u8 *desc;
336 u8 *align;
337 dma_addr_t addr;
338 dma_addr_t align_addr;
339 int len, offset;
340
341 struct scatterlist *sg;
342 int i;
343 char *buffer;
344 unsigned long flags;
345
346 /*
347 * The spec does not specify endianness of descriptor table.
348 * We currently guess that it is LE.
349 */
350
351 if (data->flags & MMC_DATA_READ)
352 direction = DMA_FROM_DEVICE;
353 else
354 direction = DMA_TO_DEVICE;
355
356 /*
357 * The ADMA descriptor table is mapped further down as we
358 * need to fill it with data first.
359 */
360
361 host->align_addr = dma_map_single(mmc_dev(host->mmc),
362 host->align_buffer, 128 * 4, direction);
8f1934ce
PO		 363 if (dma_mapping_error(host->align_addr))
364 goto fail;
2134a922
PO		 365 BUG_ON(host->align_addr & 0x3);
366
367 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
368 data->sg, data->sg_len, direction);
8f1934ce
PO		 369 if (host->sg_count == 0)
370 goto unmap_align;
2134a922
PO		 371
372 desc = host->adma_desc;
373 align = host->align_buffer;
374
375 align_addr = host->align_addr;
376
377 for_each_sg(data->sg, sg, host->sg_count, i) {
378 addr = sg_dma_address(sg);
379 len = sg_dma_len(sg);
380
381 /*
382 * The SDHCI specification states that ADMA
383 * addresses must be 32-bit aligned. If they
384 * aren't, then we use a bounce buffer for
385 * the (up to three) bytes that screw up the
386 * alignment.
387 */
388 offset = (4 - (addr & 0x3)) & 0x3;
389 if (offset) {
390 if (data->flags & MMC_DATA_WRITE) {
391 buffer = sdhci_kmap_atomic(sg, &flags);
392 memcpy(align, buffer, offset);
393 sdhci_kunmap_atomic(buffer, &flags);
394 }
395
396 desc[7] = (align_addr >> 24) & 0xff;
397 desc[6] = (align_addr >> 16) & 0xff;
398 desc[5] = (align_addr >> 8) & 0xff;
399 desc[4] = (align_addr >> 0) & 0xff;
400
401 BUG_ON(offset > 65536);
402
403 desc[3] = (offset >> 8) & 0xff;
404 desc[2] = (offset >> 0) & 0xff;
405
406 desc[1] = 0x00;
407 desc[0] = 0x21; /* tran, valid */
408
409 align += 4;
410 align_addr += 4;
411
412 desc += 8;
413
414 addr += offset;
415 len -= offset;
416 }
417
418 desc[7] = (addr >> 24) & 0xff;
419 desc[6] = (addr >> 16) & 0xff;
420 desc[5] = (addr >> 8) & 0xff;
421 desc[4] = (addr >> 0) & 0xff;
422
423 BUG_ON(len > 65536);
424
425 desc[3] = (len >> 8) & 0xff;
426 desc[2] = (len >> 0) & 0xff;
427
428 desc[1] = 0x00;
429 desc[0] = 0x21; /* tran, valid */
430
431 desc += 8;
432
433 /*
434 * If this triggers then we have a calculation bug
435 * somewhere. :/
436 */
437 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
438 }
439
440 /*
441 * Add a terminating entry.
442 */
443 desc[7] = 0;
444 desc[6] = 0;
445 desc[5] = 0;
446 desc[4] = 0;
447
448 desc[3] = 0;
449 desc[2] = 0;
450
451 desc[1] = 0x00;
452 desc[0] = 0x03; /* nop, end, valid */
453
454 /*
455 * Resync align buffer as we might have changed it.
456 */
457 if (data->flags & MMC_DATA_WRITE) {
458 dma_sync_single_for_device(mmc_dev(host->mmc),
459 host->align_addr, 128 * 4, direction);
460 }
461
462 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
463 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
8f1934ce
PO		 464 if (dma_mapping_error(host->align_addr))
465 goto unmap_entries;
2134a922 466 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 467
468 return 0;
469
470unmap_entries:
471 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
472 data->sg_len, direction);
473unmap_align:
474 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
475 128 * 4, direction);
476fail:
477 return -EINVAL;
2134a922
PO		 478}
479
480static void sdhci_adma_table_post(struct sdhci_host *host,
481 struct mmc_data *data)
482{
483 int direction;
484
485 struct scatterlist *sg;
486 int i, size;
487 u8 *align;
488 char *buffer;
489 unsigned long flags;
490
491 if (data->flags & MMC_DATA_READ)
492 direction = DMA_FROM_DEVICE;
493 else
494 direction = DMA_TO_DEVICE;
495
496 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
497 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
498
499 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
500 128 * 4, direction);
501
502 if (data->flags & MMC_DATA_READ) {
503 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
504 data->sg_len, direction);
505
506 align = host->align_buffer;
507
508 for_each_sg(data->sg, sg, host->sg_count, i) {
509 if (sg_dma_address(sg) & 0x3) {
510 size = 4 - (sg_dma_address(sg) & 0x3);
511
512 buffer = sdhci_kmap_atomic(sg, &flags);
513 memcpy(buffer, align, size);
514 sdhci_kunmap_atomic(buffer, &flags);
515
516 align += 4;
517 }
518 }
519 }
520
521 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
522 data->sg_len, direction);
523}
524
ee53ab5d 525static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
d129bceb 526{
1c8cde92
PO		 527 u8 count;
528 unsigned target_timeout, current_timeout;
d129bceb 529
ee53ab5d
PO		 530 /*
531 * If the host controller provides us with an incorrect timeout
532 * value, just skip the check and use 0xE. The hardware may take
533 * longer to time out, but that's much better than having a too-short
534 * timeout value.
535 */
536 if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL))
537 return 0xE;
e538fbe8 538
1c8cde92
PO		 539 /* timeout in us */
540 target_timeout = data->timeout_ns / 1000 +
541 data->timeout_clks / host->clock;
d129bceb 542
1c8cde92
PO		 543 /*
544 * Figure out needed cycles.
545 * We do this in steps in order to fit inside a 32 bit int.
546 * The first step is the minimum timeout, which will have a
547 * minimum resolution of 6 bits:
548 * (1) 2^13*1000 > 2^22,
549 * (2) host->timeout_clk < 2^16
550 * =>
551 * (1) / (2) > 2^6
552 */
553 count = 0;
554 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
555 while (current_timeout < target_timeout) {
556 count++;
557 current_timeout <<= 1;
558 if (count >= 0xF)
559 break;
560 }
561
562 if (count >= 0xF) {
563 printk(KERN_WARNING "%s: Too large timeout requested!\n",
564 mmc_hostname(host->mmc));
565 count = 0xE;
566 }
567
ee53ab5d
PO		 568 return count;
569}
570
571static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
572{
573 u8 count;
2134a922 574 u8 ctrl;
8f1934ce 575 int ret;
ee53ab5d
PO		 576
577 WARN_ON(host->data);
578
579 if (data == NULL)
580 return;
581
582 /* Sanity checks */
583 BUG_ON(data->blksz * data->blocks > 524288);
584 BUG_ON(data->blksz > host->mmc->max_blk_size);
585 BUG_ON(data->blocks > 65535);
586
587 host->data = data;
588 host->data_early = 0;
589
590 count = sdhci_calc_timeout(host, data);
1c8cde92 591 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
d129bceb 592
c9fddbc4
PO		 593 if (host->flags & SDHCI_USE_DMA)
594 host->flags |= SDHCI_REQ_USE_DMA;
595
2134a922
PO		 596 /*
597 * FIXME: This doesn't account for merging when mapping the
598 * scatterlist.
599 */
600 if (host->flags & SDHCI_REQ_USE_DMA) {
601 int broken, i;
602 struct scatterlist *sg;
603
604 broken = 0;
605 if (host->flags & SDHCI_USE_ADMA) {
606 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
607 broken = 1;
608 } else {
609 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
610 broken = 1;
611 }
612
613 if (unlikely(broken)) {
614 for_each_sg(data->sg, sg, data->sg_len, i) {
615 if (sg->length & 0x3) {
616 DBG("Reverting to PIO because of "
617 "transfer size (%d)\n",
618 sg->length);
619 host->flags &= ~SDHCI_REQ_USE_DMA;
620 break;
621 }
622 }
623 }
c9fddbc4
PO		 624 }
625
626 /*
627 * The assumption here being that alignment is the same after
628 * translation to device address space.
629 */
2134a922
PO		 630 if (host->flags & SDHCI_REQ_USE_DMA) {
631 int broken, i;
632 struct scatterlist *sg;
633
634 broken = 0;
635 if (host->flags & SDHCI_USE_ADMA) {
636 /*
637 * As we use 3 byte chunks to work around
638 * alignment problems, we need to check this
639 * quirk.
640 */
641 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
642 broken = 1;
643 } else {
644 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
645 broken = 1;
646 }
647
648 if (unlikely(broken)) {
649 for_each_sg(data->sg, sg, data->sg_len, i) {
650 if (sg->offset & 0x3) {
651 DBG("Reverting to PIO because of "
652 "bad alignment\n");
653 host->flags &= ~SDHCI_REQ_USE_DMA;
654 break;
655 }
656 }
657 }
658 }
659
8f1934ce
PO		 660 if (host->flags & SDHCI_REQ_USE_DMA) {
661 if (host->flags & SDHCI_USE_ADMA) {
662 ret = sdhci_adma_table_pre(host, data);
663 if (ret) {
664 /*
665 * This only happens when someone fed
666 * us an invalid request.
667 */
668 WARN_ON(1);
669 host->flags &= ~SDHCI_USE_DMA;
670 } else {
671 writel(host->adma_addr,
672 host->ioaddr + SDHCI_ADMA_ADDRESS);
673 }
674 } else {
c8b3e02e 675 int sg_cnt;
8f1934ce 676
c8b3e02e 677 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 678 data->sg, data->sg_len,
679 (data->flags & MMC_DATA_READ) ?
680 DMA_FROM_DEVICE :
681 DMA_TO_DEVICE);
c8b3e02e 682 if (sg_cnt == 0) {
8f1934ce
PO		 683 /*
684 * This only happens when someone fed
685 * us an invalid request.
686 */
687 WARN_ON(1);
688 host->flags &= ~SDHCI_USE_DMA;
689 } else {
690 WARN_ON(count != 1);
691 writel(sg_dma_address(data->sg),
692 host->ioaddr + SDHCI_DMA_ADDRESS);
693 }
694 }
695 }
696
2134a922
PO		 697 /*
698 * Always adjust the DMA selection as some controllers
699 * (e.g. JMicron) can't do PIO properly when the selection
700 * is ADMA.
701 */
702 if (host->version >= SDHCI_SPEC_200) {
703 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
704 ctrl &= ~SDHCI_CTRL_DMA_MASK;
705 if ((host->flags & SDHCI_REQ_USE_DMA) &&
706 (host->flags & SDHCI_USE_ADMA))
707 ctrl |= SDHCI_CTRL_ADMA32;
708 else
709 ctrl |= SDHCI_CTRL_SDMA;
710 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
c9fddbc4
PO		 711 }
712
8f1934ce 713 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
d129bceb
PO		 714 host->cur_sg = data->sg;
715 host->num_sg = data->sg_len;
716
717 host->offset = 0;
718 host->remain = host->cur_sg->length;
719 }
c7fa9963 720
bab76961
PO		 721 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
722 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
723 host->ioaddr + SDHCI_BLOCK_SIZE);
c7fa9963
PO		 724 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
725}
726
727static void sdhci_set_transfer_mode(struct sdhci_host *host,
728 struct mmc_data *data)
729{
730 u16 mode;
731
c7fa9963
PO		 732 if (data == NULL)
733 return;
734
e538fbe8
PO		 735 WARN_ON(!host->data);
736
c7fa9963
PO		 737 mode = SDHCI_TRNS_BLK_CNT_EN;
738 if (data->blocks > 1)
739 mode |= SDHCI_TRNS_MULTI;
740 if (data->flags & MMC_DATA_READ)
741 mode |= SDHCI_TRNS_READ;
c9fddbc4 742 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 743 mode |= SDHCI_TRNS_DMA;
744
745 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
d129bceb
PO		 746}
747
748static void sdhci_finish_data(struct sdhci_host *host)
749{
750 struct mmc_data *data;
d129bceb
PO		 751
752 BUG_ON(!host->data);
753
754 data = host->data;
755 host->data = NULL;
756
c9fddbc4 757 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 758 if (host->flags & SDHCI_USE_ADMA)
759 sdhci_adma_table_post(host, data);
760 else {
761 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
762 data->sg_len, (data->flags & MMC_DATA_READ) ?
763 DMA_FROM_DEVICE : DMA_TO_DEVICE);
764 }
d129bceb
PO		 765 }
766
767 /*
c9b74c5b
PO		 768 * The specification states that the block count register must
769 * be updated, but it does not specify at what point in the
770 * data flow. That makes the register entirely useless to read
771 * back so we have to assume that nothing made it to the card
772 * in the event of an error.
d129bceb 773 */
c9b74c5b
PO		 774 if (data->error)
775 data->bytes_xfered = 0;
d129bceb 776 else
c9b74c5b 777 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 778
d129bceb
PO		 779 if (data->stop) {
780 /*
781 * The controller needs a reset of internal state machines
782 * upon error conditions.
783 */
17b0429d 784 if (data->error) {
d129bceb
PO		 785 sdhci_reset(host, SDHCI_RESET_CMD);
786 sdhci_reset(host, SDHCI_RESET_DATA);
787 }
788
789 sdhci_send_command(host, data->stop);
790 } else
791 tasklet_schedule(&host->finish_tasklet);
792}
793
794static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
795{
796 int flags;
fd2208d7 797 u32 mask;
7cb2c76f 798 unsigned long timeout;
d129bceb
PO		 799
800 WARN_ON(host->cmd);
801
d129bceb 802 /* Wait max 10 ms */
7cb2c76f 803 timeout = 10;
fd2208d7
PO		 804
805 mask = SDHCI_CMD_INHIBIT;
806 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
807 mask |= SDHCI_DATA_INHIBIT;
808
809 /* We shouldn't wait for data inihibit for stop commands, even
810 though they might use busy signaling */
811 if (host->mrq->data && (cmd == host->mrq->data->stop))
812 mask &= ~SDHCI_DATA_INHIBIT;
813
814 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 815 if (timeout == 0) {
d129bceb 816 printk(KERN_ERR "%s: Controller never released "
acf1da45 817 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 818 sdhci_dumpregs(host);
17b0429d 819 cmd->error = -EIO;
d129bceb
PO		 820 tasklet_schedule(&host->finish_tasklet);
821 return;
822 }
7cb2c76f
PO		 823 timeout--;
824 mdelay(1);
825 }
d129bceb
PO		 826
827 mod_timer(&host->timer, jiffies + 10 * HZ);
828
829 host->cmd = cmd;
830
831 sdhci_prepare_data(host, cmd->data);
832
833 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
834
c7fa9963
PO		 835 sdhci_set_transfer_mode(host, cmd->data);
836
d129bceb 837 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 838 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 839 mmc_hostname(host->mmc));
17b0429d 840 cmd->error = -EINVAL;
d129bceb
PO		 841 tasklet_schedule(&host->finish_tasklet);
842 return;
843 }
844
845 if (!(cmd->flags & MMC_RSP_PRESENT))
846 flags = SDHCI_CMD_RESP_NONE;
847 else if (cmd->flags & MMC_RSP_136)
848 flags = SDHCI_CMD_RESP_LONG;
849 else if (cmd->flags & MMC_RSP_BUSY)
850 flags = SDHCI_CMD_RESP_SHORT_BUSY;
851 else
852 flags = SDHCI_CMD_RESP_SHORT;
853
854 if (cmd->flags & MMC_RSP_CRC)
855 flags |= SDHCI_CMD_CRC;
856 if (cmd->flags & MMC_RSP_OPCODE)
857 flags |= SDHCI_CMD_INDEX;
858 if (cmd->data)
859 flags |= SDHCI_CMD_DATA;
860
fb61e289 861 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
d129bceb
PO		 862 host->ioaddr + SDHCI_COMMAND);
863}
864
865static void sdhci_finish_command(struct sdhci_host *host)
866{
867 int i;
868
869 BUG_ON(host->cmd == NULL);
870
871 if (host->cmd->flags & MMC_RSP_PRESENT) {
872 if (host->cmd->flags & MMC_RSP_136) {
873 /* CRC is stripped so we need to do some shifting. */
874 for (i = 0;i < 4;i++) {
875 host->cmd->resp[i] = readl(host->ioaddr +
876 SDHCI_RESPONSE + (3-i)*4) << 8;
877 if (i != 3)
878 host->cmd->resp[i] |=
879 readb(host->ioaddr +
880 SDHCI_RESPONSE + (3-i)*4-1);
881 }
882 } else {
883 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
884 }
885 }
886
17b0429d 887 host->cmd->error = 0;
d129bceb 888
e538fbe8
PO		 889 if (host->data && host->data_early)
890 sdhci_finish_data(host);
891
892 if (!host->cmd->data)
d129bceb
PO		 893 tasklet_schedule(&host->finish_tasklet);
894
895 host->cmd = NULL;
896}
897
898static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
899{
900 int div;
901 u16 clk;
7cb2c76f 902 unsigned long timeout;
d129bceb
PO		 903
904 if (clock == host->clock)
905 return;
906
907 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
908
909 if (clock == 0)
910 goto out;
911
912 for (div = 1;div < 256;div *= 2) {
913 if ((host->max_clk / div) <= clock)
914 break;
915 }
916 div >>= 1;
917
918 clk = div << SDHCI_DIVIDER_SHIFT;
919 clk |= SDHCI_CLOCK_INT_EN;
920 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
921
922 /* Wait max 10 ms */
7cb2c76f
PO		 923 timeout = 10;
924 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
925 & SDHCI_CLOCK_INT_STABLE)) {
926 if (timeout == 0) {
acf1da45
PO		 927 printk(KERN_ERR "%s: Internal clock never "
928 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 929 sdhci_dumpregs(host);
930 return;
931 }
7cb2c76f
PO		 932 timeout--;
933 mdelay(1);
934 }
d129bceb
PO		 935
936 clk |= SDHCI_CLOCK_CARD_EN;
937 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
938
939out:
940 host->clock = clock;
941}
942
146ad66e
PO		 943static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
944{
945 u8 pwr;
946
947 if (host->power == power)
948 return;
949
9e9dc5f2
DS		 950 if (power == (unsigned short)-1) {
951 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e 952 goto out;
9e9dc5f2
DS		 953 }
954
955 /*
956 * Spec says that we should clear the power reg before setting
957 * a new value. Some controllers don't seem to like this though.
958 */
b8c86fc5 959 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
9e9dc5f2 960 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e
PO		 961
962 pwr = SDHCI_POWER_ON;
963
4be34c99 964 switch (1 << power) {
55556da0 965 case MMC_VDD_165_195:
146ad66e
PO		 966 pwr |= SDHCI_POWER_180;
967 break;
4be34c99
PL		 968 case MMC_VDD_29_30:
969 case MMC_VDD_30_31:
146ad66e
PO		 970 pwr |= SDHCI_POWER_300;
971 break;
4be34c99
PL		 972 case MMC_VDD_32_33:
973 case MMC_VDD_33_34:
146ad66e
PO		 974 pwr |= SDHCI_POWER_330;
975 break;
976 default:
977 BUG();
978 }
979
e08c1694 980 /*
c71f6512 981 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 982 * and set turn on power at the same time, so set the voltage first.
983 */
b8c86fc5 984 if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
e08c1694
AS		 985 writeb(pwr & ~SDHCI_POWER_ON,
986 host->ioaddr + SDHCI_POWER_CONTROL);
987
146ad66e
PO		 988 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
989
990out:
991 host->power = power;
992}
993
d129bceb
PO		 994/*****************************************************************************\
995 * *
996 * MMC callbacks *
997 * *
998\*****************************************************************************/
999
1000static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1001{
1002 struct sdhci_host *host;
1003 unsigned long flags;
1004
1005 host = mmc_priv(mmc);
1006
1007 spin_lock_irqsave(&host->lock, flags);
1008
1009 WARN_ON(host->mrq != NULL);
1010
2f730fec 1011#ifndef CONFIG_LEDS_CLASS
d129bceb 1012 sdhci_activate_led(host);
2f730fec 1013#endif
d129bceb
PO		 1014
1015 host->mrq = mrq;
1016
1e72859e
PO		 1017 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
1018 || (host->flags & SDHCI_DEVICE_DEAD)) {
17b0429d 1019 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1020 tasklet_schedule(&host->finish_tasklet);
1021 } else
1022 sdhci_send_command(host, mrq->cmd);
1023
5f25a66f 1024 mmiowb();
d129bceb
PO		 1025 spin_unlock_irqrestore(&host->lock, flags);
1026}
1027
1028static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1029{
1030 struct sdhci_host *host;
1031 unsigned long flags;
1032 u8 ctrl;
1033
1034 host = mmc_priv(mmc);
1035
1036 spin_lock_irqsave(&host->lock, flags);
1037
1e72859e
PO		 1038 if (host->flags & SDHCI_DEVICE_DEAD)
1039 goto out;
1040
d129bceb
PO		 1041 /*
1042 * Reset the chip on each power off.
1043 * Should clear out any weird states.
1044 */
1045 if (ios->power_mode == MMC_POWER_OFF) {
1046 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb 1047 sdhci_init(host);
d129bceb
PO		 1048 }
1049
1050 sdhci_set_clock(host, ios->clock);
1051
1052 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1053 sdhci_set_power(host, -1);
d129bceb 1054 else
146ad66e 1055 sdhci_set_power(host, ios->vdd);
d129bceb
PO		 1056
1057 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
cd9277c0 1058
d129bceb
PO		 1059 if (ios->bus_width == MMC_BUS_WIDTH_4)
1060 ctrl |= SDHCI_CTRL_4BITBUS;
1061 else
1062 ctrl &= ~SDHCI_CTRL_4BITBUS;
cd9277c0
PO		 1063
1064 if (ios->timing == MMC_TIMING_SD_HS)
1065 ctrl |= SDHCI_CTRL_HISPD;
1066 else
1067 ctrl &= ~SDHCI_CTRL_HISPD;
1068
d129bceb
PO		 1069 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
1070
b8352260
LD		 1071 /*
1072 * Some (ENE) controllers go apeshit on some ios operation,
1073 * signalling timeout and CRC errors even on CMD0. Resetting
1074 * it on each ios seems to solve the problem.
1075 */
b8c86fc5 1076 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1077 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1078
1e72859e 1079out:
5f25a66f 1080 mmiowb();
d129bceb
PO		 1081 spin_unlock_irqrestore(&host->lock, flags);
1082}
1083
1084static int sdhci_get_ro(struct mmc_host *mmc)
1085{
1086 struct sdhci_host *host;
1087 unsigned long flags;
1088 int present;
1089
1090 host = mmc_priv(mmc);
1091
1092 spin_lock_irqsave(&host->lock, flags);
1093
1e72859e
PO		 1094 if (host->flags & SDHCI_DEVICE_DEAD)
1095 present = 0;
1096 else
1097 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
d129bceb
PO		 1098
1099 spin_unlock_irqrestore(&host->lock, flags);
1100
1101 return !(present & SDHCI_WRITE_PROTECT);
1102}
1103
f75979b7
PO		 1104static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1105{
1106 struct sdhci_host *host;
1107 unsigned long flags;
1108 u32 ier;
1109
1110 host = mmc_priv(mmc);
1111
1112 spin_lock_irqsave(&host->lock, flags);
1113
1e72859e
PO		 1114 if (host->flags & SDHCI_DEVICE_DEAD)
1115 goto out;
1116
f75979b7
PO		 1117 ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
1118
1119 ier &= ~SDHCI_INT_CARD_INT;
1120 if (enable)
1121 ier |= SDHCI_INT_CARD_INT;
1122
1123 writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
1124 writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
1125
1e72859e 1126out:
f75979b7
PO		 1127 mmiowb();
1128
1129 spin_unlock_irqrestore(&host->lock, flags);
1130}
1131
ab7aefd0 1132static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1133 .request = sdhci_request,
1134 .set_ios = sdhci_set_ios,
1135 .get_ro = sdhci_get_ro,
f75979b7 1136 .enable_sdio_irq = sdhci_enable_sdio_irq,
d129bceb
PO		 1137};
1138
1139/*****************************************************************************\
1140 * *
1141 * Tasklets *
1142 * *
1143\*****************************************************************************/
1144
1145static void sdhci_tasklet_card(unsigned long param)
1146{
1147 struct sdhci_host *host;
1148 unsigned long flags;
1149
1150 host = (struct sdhci_host*)param;
1151
1152 spin_lock_irqsave(&host->lock, flags);
1153
1154 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1155 if (host->mrq) {
1156 printk(KERN_ERR "%s: Card removed during transfer!\n",
1157 mmc_hostname(host->mmc));
1158 printk(KERN_ERR "%s: Resetting controller.\n",
1159 mmc_hostname(host->mmc));
1160
1161 sdhci_reset(host, SDHCI_RESET_CMD);
1162 sdhci_reset(host, SDHCI_RESET_DATA);
1163
17b0429d 1164 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1165 tasklet_schedule(&host->finish_tasklet);
1166 }
1167 }
1168
1169 spin_unlock_irqrestore(&host->lock, flags);
1170
1171 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
1172}
1173
1174static void sdhci_tasklet_finish(unsigned long param)
1175{
1176 struct sdhci_host *host;
1177 unsigned long flags;
1178 struct mmc_request *mrq;
1179
1180 host = (struct sdhci_host*)param;
1181
1182 spin_lock_irqsave(&host->lock, flags);
1183
1184 del_timer(&host->timer);
1185
1186 mrq = host->mrq;
1187
d129bceb
PO		 1188 /*
1189 * The controller needs a reset of internal state machines
1190 * upon error conditions.
1191 */
1e72859e
PO		 1192 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1193 (mrq->cmd->error ||
1194 (mrq->data && (mrq->data->error ||
1195 (mrq->data->stop && mrq->data->stop->error))) ||
1196 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1197
1198 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1199 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1200 unsigned int clock;
1201
1202 /* This is to force an update */
1203 clock = host->clock;
1204 host->clock = 0;
1205 sdhci_set_clock(host, clock);
1206 }
1207
1208 /* Spec says we should do both at the same time, but Ricoh
1209 controllers do not like that. */
d129bceb
PO		 1210 sdhci_reset(host, SDHCI_RESET_CMD);
1211 sdhci_reset(host, SDHCI_RESET_DATA);
1212 }
1213
1214 host->mrq = NULL;
1215 host->cmd = NULL;
1216 host->data = NULL;
1217
2f730fec 1218#ifndef CONFIG_LEDS_CLASS
d129bceb 1219 sdhci_deactivate_led(host);
2f730fec 1220#endif
d129bceb 1221
5f25a66f 1222 mmiowb();
d129bceb
PO		 1223 spin_unlock_irqrestore(&host->lock, flags);
1224
1225 mmc_request_done(host->mmc, mrq);
1226}
1227
1228static void sdhci_timeout_timer(unsigned long data)
1229{
1230 struct sdhci_host *host;
1231 unsigned long flags;
1232
1233 host = (struct sdhci_host*)data;
1234
1235 spin_lock_irqsave(&host->lock, flags);
1236
1237 if (host->mrq) {
acf1da45
PO		 1238 printk(KERN_ERR "%s: Timeout waiting for hardware "
1239 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1240 sdhci_dumpregs(host);
1241
1242 if (host->data) {
17b0429d 1243 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1244 sdhci_finish_data(host);
1245 } else {
1246 if (host->cmd)
17b0429d 1247 host->cmd->error = -ETIMEDOUT;
d129bceb 1248 else
17b0429d 1249 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1250
1251 tasklet_schedule(&host->finish_tasklet);
1252 }
1253 }
1254
5f25a66f 1255 mmiowb();
d129bceb
PO		 1256 spin_unlock_irqrestore(&host->lock, flags);
1257}
1258
1259/*****************************************************************************\
1260 * *
1261 * Interrupt handling *
1262 * *
1263\*****************************************************************************/
1264
1265static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1266{
1267 BUG_ON(intmask == 0);
1268
1269 if (!host->cmd) {
b67ac3f3
PO		 1270 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1271 "though no command operation was in progress.\n",
1272 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1273 sdhci_dumpregs(host);
1274 return;
1275 }
1276
43b58b36 1277 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1278 host->cmd->error = -ETIMEDOUT;
1279 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1280 SDHCI_INT_INDEX))
1281 host->cmd->error = -EILSEQ;
43b58b36 1282
17b0429d 1283 if (host->cmd->error)
d129bceb 1284 tasklet_schedule(&host->finish_tasklet);
43b58b36
PO		 1285 else if (intmask & SDHCI_INT_RESPONSE)
1286 sdhci_finish_command(host);
d129bceb
PO		 1287}
1288
1289static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1290{
1291 BUG_ON(intmask == 0);
1292
1293 if (!host->data) {
1294 /*
1295 * A data end interrupt is sent together with the response
1296 * for the stop command.
1297 */
1298 if (intmask & SDHCI_INT_DATA_END)
1299 return;
1300
b67ac3f3
PO		 1301 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1302 "though no data operation was in progress.\n",
1303 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1304 sdhci_dumpregs(host);
1305
1306 return;
1307 }
1308
1309 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d
PO		 1310 host->data->error = -ETIMEDOUT;
1311 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1312 host->data->error = -EILSEQ;
2134a922
PO		 1313 else if (intmask & SDHCI_INT_ADMA_ERROR)
1314 host->data->error = -EIO;
d129bceb 1315
17b0429d 1316 if (host->data->error)
d129bceb
PO		 1317 sdhci_finish_data(host);
1318 else {
a406f5a3 1319 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1320 sdhci_transfer_pio(host);
1321
6ba736a1
PO		 1322 /*
1323 * We currently don't do anything fancy with DMA
1324 * boundaries, but as we can't disable the feature
1325 * we need to at least restart the transfer.
1326 */
1327 if (intmask & SDHCI_INT_DMA_END)
1328 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1329 host->ioaddr + SDHCI_DMA_ADDRESS);
1330
e538fbe8
PO		 1331 if (intmask & SDHCI_INT_DATA_END) {
1332 if (host->cmd) {
1333 /*
1334 * Data managed to finish before the
1335 * command completed. Make sure we do
1336 * things in the proper order.
1337 */
1338 host->data_early = 1;
1339 } else {
1340 sdhci_finish_data(host);
1341 }
1342 }
d129bceb
PO		 1343 }
1344}
1345
7d12e780 1346static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1347{
1348 irqreturn_t result;
1349 struct sdhci_host* host = dev_id;
1350 u32 intmask;
f75979b7 1351 int cardint = 0;
d129bceb
PO		 1352
1353 spin_lock(&host->lock);
1354
1355 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1356
62df67a5 1357 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1358 result = IRQ_NONE;
1359 goto out;
1360 }
1361
b69c9058
PO		 1362 DBG("*** %s got interrupt: 0x%08x\n",
1363 mmc_hostname(host->mmc), intmask);
d129bceb 1364
3192a28f
PO		 1365 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1366 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1367 host->ioaddr + SDHCI_INT_STATUS);
d129bceb 1368 tasklet_schedule(&host->card_tasklet);
3192a28f 1369 }
d129bceb 1370
3192a28f 1371 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1372
3192a28f 1373 if (intmask & SDHCI_INT_CMD_MASK) {
d129bceb
PO		 1374 writel(intmask & SDHCI_INT_CMD_MASK,
1375 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1376 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1377 }
1378
1379 if (intmask & SDHCI_INT_DATA_MASK) {
d129bceb
PO		 1380 writel(intmask & SDHCI_INT_DATA_MASK,
1381 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1382 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1383 }
1384
1385 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1386
964f9ce2
PO		 1387 intmask &= ~SDHCI_INT_ERROR;
1388
d129bceb 1389 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1390 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1391 mmc_hostname(host->mmc));
3192a28f 1392 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
d129bceb
PO		 1393 }
1394
9d26a5d3 1395 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 1396
f75979b7
PO		 1397 if (intmask & SDHCI_INT_CARD_INT)
1398 cardint = 1;
1399
1400 intmask &= ~SDHCI_INT_CARD_INT;
1401
3192a28f 1402 if (intmask) {
acf1da45 1403 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1404 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1405 sdhci_dumpregs(host);
1406
d129bceb 1407 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1408 }
d129bceb
PO		 1409
1410 result = IRQ_HANDLED;
1411
5f25a66f 1412 mmiowb();
d129bceb
PO		 1413out:
1414 spin_unlock(&host->lock);
1415
f75979b7
PO		 1416 /*
1417 * We have to delay this as it calls back into the driver.
1418 */
1419 if (cardint)
1420 mmc_signal_sdio_irq(host->mmc);
1421
d129bceb
PO		 1422 return result;
1423}
1424
1425/*****************************************************************************\
1426 * *
1427 * Suspend/resume *
1428 * *
1429\*****************************************************************************/
1430
1431#ifdef CONFIG_PM
1432
b8c86fc5 1433int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 1434{
b8c86fc5 1435 int ret;
a715dfc7 1436
b8c86fc5
PO		 1437 ret = mmc_suspend_host(host->mmc, state);
1438 if (ret)
1439 return ret;
a715dfc7 1440
b8c86fc5 1441 free_irq(host->irq, host);
d129bceb
PO		 1442
1443 return 0;
1444}
1445
b8c86fc5 1446EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 1447
b8c86fc5
PO		 1448int sdhci_resume_host(struct sdhci_host *host)
1449{
1450 int ret;
d129bceb 1451
b8c86fc5
PO		 1452 if (host->flags & SDHCI_USE_DMA) {
1453 if (host->ops->enable_dma)
1454 host->ops->enable_dma(host);
1455 }
d129bceb 1456
b8c86fc5
PO		 1457 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1458 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 1459 if (ret)
1460 return ret;
d129bceb 1461
b8c86fc5
PO		 1462 sdhci_init(host);
1463 mmiowb();
1464
1465 ret = mmc_resume_host(host->mmc);
1466 if (ret)
1467 return ret;
d129bceb
PO		 1468
1469 return 0;
1470}
1471
b8c86fc5 1472EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 1473
1474#endif /* CONFIG_PM */
1475
1476/*****************************************************************************\
1477 * *
b8c86fc5 1478 * Device allocation/registration *
d129bceb
PO		 1479 * *
1480\*****************************************************************************/
1481
b8c86fc5
PO		 1482struct sdhci_host *sdhci_alloc_host(struct device *dev,
1483 size_t priv_size)
d129bceb 1484{
d129bceb
PO		 1485 struct mmc_host *mmc;
1486 struct sdhci_host *host;
1487
b8c86fc5 1488 WARN_ON(dev == NULL);
d129bceb 1489
b8c86fc5 1490 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 1491 if (!mmc)
b8c86fc5 1492 return ERR_PTR(-ENOMEM);
d129bceb
PO		 1493
1494 host = mmc_priv(mmc);
1495 host->mmc = mmc;
1496
b8c86fc5
PO		 1497 return host;
1498}
8a4da143 1499
b8c86fc5 1500EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 1501
b8c86fc5
PO		 1502int sdhci_add_host(struct sdhci_host *host)
1503{
1504 struct mmc_host *mmc;
1505 unsigned int caps;
b8c86fc5 1506 int ret;
d129bceb 1507
b8c86fc5
PO		 1508 WARN_ON(host == NULL);
1509 if (host == NULL)
1510 return -EINVAL;
d129bceb 1511
b8c86fc5 1512 mmc = host->mmc;
d129bceb 1513
b8c86fc5
PO		 1514 if (debug_quirks)
1515 host->quirks = debug_quirks;
d129bceb 1516
d96649ed
PO		 1517 sdhci_reset(host, SDHCI_RESET_ALL);
1518
2134a922
PO		 1519 host->version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1520 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1521 >> SDHCI_SPEC_VER_SHIFT;
1522 if (host->version > SDHCI_SPEC_200) {
4a965505 1523 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 1524 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 1525 host->version);
4a965505
PO		 1526 }
1527
d129bceb
PO		 1528 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1529
b8c86fc5 1530 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
98608076 1531 host->flags |= SDHCI_USE_DMA;
67435274
PO		 1532 else if (!(caps & SDHCI_CAN_DO_DMA))
1533 DBG("Controller doesn't have DMA capability\n");
1534 else
d129bceb
PO		 1535 host->flags |= SDHCI_USE_DMA;
1536
b8c86fc5 1537 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
7c168e3d 1538 (host->flags & SDHCI_USE_DMA)) {
cee687ce 1539 DBG("Disabling DMA as it is marked broken\n");
7c168e3d
FT		 1540 host->flags &= ~SDHCI_USE_DMA;
1541 }
1542
2134a922
PO		 1543 if (host->flags & SDHCI_USE_DMA) {
1544 if ((host->version >= SDHCI_SPEC_200) &&
1545 (caps & SDHCI_CAN_DO_ADMA2))
1546 host->flags |= SDHCI_USE_ADMA;
1547 }
1548
1549 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1550 (host->flags & SDHCI_USE_ADMA)) {
1551 DBG("Disabling ADMA as it is marked broken\n");
1552 host->flags &= ~SDHCI_USE_ADMA;
1553 }
1554
d129bceb 1555 if (host->flags & SDHCI_USE_DMA) {
b8c86fc5
PO		 1556 if (host->ops->enable_dma) {
1557 if (host->ops->enable_dma(host)) {
1558 printk(KERN_WARNING "%s: No suitable DMA "
1559 "available. Falling back to PIO.\n",
1560 mmc_hostname(mmc));
2134a922 1561 host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA);
b8c86fc5 1562 }
d129bceb
PO		 1563 }
1564 }
1565
2134a922
PO		 1566 if (host->flags & SDHCI_USE_ADMA) {
1567 /*
1568 * We need to allocate descriptors for all sg entries
1569 * (128) and potentially one alignment transfer for
1570 * each of those entries.
1571 */
1572 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1573 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1574 if (!host->adma_desc || !host->align_buffer) {
1575 kfree(host->adma_desc);
1576 kfree(host->align_buffer);
1577 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1578 "buffers. Falling back to standard DMA.\n",
1579 mmc_hostname(mmc));
1580 host->flags &= ~SDHCI_USE_ADMA;
1581 }
1582 }
1583
b8c86fc5
PO		 1584 /* XXX: Hack to get MMC layer to avoid highmem */
1585 if (!(host->flags & SDHCI_USE_DMA))
c8b3e02e 1586 mmc_dev(host->mmc)->dma_mask = NULL;
d129bceb 1587
8ef1a143
PO		 1588 host->max_clk =
1589 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1590 if (host->max_clk == 0) {
1591 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
b69c9058 1592 "frequency.\n", mmc_hostname(mmc));
b8c86fc5 1593 return -ENODEV;
8ef1a143 1594 }
d129bceb
PO		 1595 host->max_clk *= 1000000;
1596
1c8cde92
PO		 1597 host->timeout_clk =
1598 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1599 if (host->timeout_clk == 0) {
1600 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
b69c9058 1601 "frequency.\n", mmc_hostname(mmc));
b8c86fc5 1602 return -ENODEV;
1c8cde92
PO		 1603 }
1604 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1605 host->timeout_clk *= 1000;
d129bceb
PO		 1606
1607 /*
1608 * Set host parameters.
1609 */
1610 mmc->ops = &sdhci_ops;
1611 mmc->f_min = host->max_clk / 256;
1612 mmc->f_max = host->max_clk;
c9b74c5b 1613 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
d129bceb 1614
cd9277c0
PO		 1615 if (caps & SDHCI_CAN_DO_HISPD)
1616 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1617
146ad66e
PO		 1618 mmc->ocr_avail = 0;
1619 if (caps & SDHCI_CAN_VDD_330)
1620 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1621 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1622 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1623 if (caps & SDHCI_CAN_VDD_180)
55556da0 1624 mmc->ocr_avail |= MMC_VDD_165_195;
146ad66e
PO		 1625
1626 if (mmc->ocr_avail == 0) {
1627 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 1628 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 1629 return -ENODEV;
146ad66e
PO		 1630 }
1631
d129bceb
PO		 1632 spin_lock_init(&host->lock);
1633
1634 /*
2134a922
PO		 1635 * Maximum number of segments. Depends on if the hardware
1636 * can do scatter/gather or not.
d129bceb 1637 */
2134a922
PO		 1638 if (host->flags & SDHCI_USE_ADMA)
1639 mmc->max_hw_segs = 128;
1640 else if (host->flags & SDHCI_USE_DMA)
d129bceb 1641 mmc->max_hw_segs = 1;
2134a922
PO		 1642 else /* PIO */
1643 mmc->max_hw_segs = 128;
1644 mmc->max_phys_segs = 128;
d129bceb
PO		 1645
1646 /*
bab76961 1647 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1648 * size (512KiB).
d129bceb 1649 */
55db890a 1650 mmc->max_req_size = 524288;
d129bceb
PO		 1651
1652 /*
1653 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 1654 * of bytes. When doing hardware scatter/gather, each entry cannot
1655 * be larger than 64 KiB though.
d129bceb 1656 */
2134a922
PO		 1657 if (host->flags & SDHCI_USE_ADMA)
1658 mmc->max_seg_size = 65536;
1659 else
1660 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1661
fe4a3c7a
PO		 1662 /*
1663 * Maximum block size. This varies from controller to controller and
1664 * is specified in the capabilities register.
1665 */
1666 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1667 if (mmc->max_blk_size >= 3) {
b69c9058
PO		 1668 printk(KERN_WARNING "%s: Invalid maximum block size, "
1669 "assuming 512 bytes\n", mmc_hostname(mmc));
03f8590d
DV		 1670 mmc->max_blk_size = 512;
1671 } else
1672 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 1673
55db890a
PO		 1674 /*
1675 * Maximum block count.
1676 */
1677 mmc->max_blk_count = 65535;
1678
d129bceb
PO		 1679 /*
1680 * Init tasklets.
1681 */
1682 tasklet_init(&host->card_tasklet,
1683 sdhci_tasklet_card, (unsigned long)host);
1684 tasklet_init(&host->finish_tasklet,
1685 sdhci_tasklet_finish, (unsigned long)host);
1686
e4cad1b5 1687 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1688
dace1453 1689 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 1690 mmc_hostname(mmc), host);
d129bceb 1691 if (ret)
8ef1a143 1692 goto untasklet;
d129bceb
PO		 1693
1694 sdhci_init(host);
1695
1696#ifdef CONFIG_MMC_DEBUG
1697 sdhci_dumpregs(host);
1698#endif
1699
2f730fec
PO		 1700#ifdef CONFIG_LEDS_CLASS
1701 host->led.name = mmc_hostname(mmc);
1702 host->led.brightness = LED_OFF;
1703 host->led.default_trigger = mmc_hostname(mmc);
1704 host->led.brightness_set = sdhci_led_control;
1705
b8c86fc5 1706 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 1707 if (ret)
1708 goto reset;
1709#endif
1710
5f25a66f
PO		 1711 mmiowb();
1712
d129bceb
PO		 1713 mmc_add_host(mmc);
1714
2134a922 1715 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n",
b8c86fc5 1716 mmc_hostname(mmc), host->hw_name, mmc_dev(mmc)->bus_id,
2134a922 1717 (host->flags & SDHCI_USE_ADMA)?"A":"",
d129bceb
PO		 1718 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1719
1720 return 0;
1721
2f730fec
PO		 1722#ifdef CONFIG_LEDS_CLASS
1723reset:
1724 sdhci_reset(host, SDHCI_RESET_ALL);
1725 free_irq(host->irq, host);
1726#endif
8ef1a143 1727untasklet:
d129bceb
PO		 1728 tasklet_kill(&host->card_tasklet);
1729 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 1730
1731 return ret;
1732}
1733
b8c86fc5 1734EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 1735
1e72859e 1736void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 1737{
1e72859e
PO		 1738 unsigned long flags;
1739
1740 if (dead) {
1741 spin_lock_irqsave(&host->lock, flags);
1742
1743 host->flags |= SDHCI_DEVICE_DEAD;
1744
1745 if (host->mrq) {
1746 printk(KERN_ERR "%s: Controller removed during "
1747 " transfer!\n", mmc_hostname(host->mmc));
1748
1749 host->mrq->cmd->error = -ENOMEDIUM;
1750 tasklet_schedule(&host->finish_tasklet);
1751 }
1752
1753 spin_unlock_irqrestore(&host->lock, flags);
1754 }
1755
b8c86fc5 1756 mmc_remove_host(host->mmc);
d129bceb 1757
2f730fec
PO		 1758#ifdef CONFIG_LEDS_CLASS
1759 led_classdev_unregister(&host->led);
1760#endif
1761
1e72859e
PO		 1762 if (!dead)
1763 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 1764
1765 free_irq(host->irq, host);
1766
1767 del_timer_sync(&host->timer);
1768
1769 tasklet_kill(&host->card_tasklet);
1770 tasklet_kill(&host->finish_tasklet);
2134a922
PO		 1771
1772 kfree(host->adma_desc);
1773 kfree(host->align_buffer);
1774
1775 host->adma_desc = NULL;
1776 host->align_buffer = NULL;
d129bceb
PO		 1777}
1778
b8c86fc5 1779EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 1780
b8c86fc5 1781void sdhci_free_host(struct sdhci_host *host)
d129bceb 1782{
b8c86fc5 1783 mmc_free_host(host->mmc);
d129bceb
PO		 1784}
1785
b8c86fc5 1786EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 1787
1788/*****************************************************************************\
1789 * *
1790 * Driver init/exit *
1791 * *
1792\*****************************************************************************/
1793
1794static int __init sdhci_drv_init(void)
1795{
1796 printk(KERN_INFO DRIVER_NAME
52fbf9c9 1797 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 1798 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1799
b8c86fc5 1800 return 0;
d129bceb
PO		 1801}
1802
1803static void __exit sdhci_drv_exit(void)
1804{
d129bceb
PO		 1805}
1806
1807module_init(sdhci_drv_init);
1808module_exit(sdhci_drv_exit);
1809
df673b22 1810module_param(debug_quirks, uint, 0444);
67435274 1811
d129bceb 1812MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
b8c86fc5 1813MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 1814MODULE_LICENSE("GPL");
67435274 1815
df673b22 1816MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Clone of davem's net-next-2.6 tree