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sdhci: remove custom controller name
[net-next-2.6.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
11763609 20#include <linux/scatterlist.h>
d129bceb
PO		 21
22#include <linux/mmc/host.h>
d129bceb 23
d129bceb
PO		 24#include "sdhci.h"
25
26#define DRIVER_NAME "sdhci"
d129bceb 27
d129bceb 28#define DBG(f, x...) \
c6563178 29 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 30
df673b22 31static unsigned int debug_quirks = 0;
67435274 32
dc93441b
PO		 33/*
34 * Different quirks to handle when the hardware deviates from a strict
35 * interpretation of the SDHCI specification.
36 */
37
38/* Controller doesn't honor resets unless we touch the clock register */
645289dc 39#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
dc93441b 40/* Controller has bad caps bits, but really supports DMA */
98608076 41#define SDHCI_QUIRK_FORCE_DMA (1<<1)
8a4da143
PO		 42/* Controller doesn't like some resets when there is no card inserted. */
43#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
dc93441b 44/* Controller doesn't like clearing the power reg before a change */
9e9dc5f2 45#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
dc93441b 46/* Controller has flaky internal state so reset it on each ios change */
b8352260 47#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
dc93441b 48/* Controller has an unusable DMA engine */
7c168e3d 49#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
c9fddbc4
PO		 50/* Controller can only DMA from 32-bit aligned addresses */
51#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<6)
52/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
53#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7)
84c46a53
PO		 54/* Controller needs to be reset after each request to stay stable */
55#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<8)
645289dc 56
d129bceb 57static const struct pci_device_id pci_ids[] __devinitdata = {
645289dc
PO		 58 {
59 .vendor = PCI_VENDOR_ID_RICOH,
60 .device = PCI_DEVICE_ID_RICOH_R5C822,
61 .subvendor = PCI_VENDOR_ID_IBM,
62 .subdevice = PCI_ANY_ID,
98608076
PO		 63 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
64 SDHCI_QUIRK_FORCE_DMA,
65 },
66
67 {
68 .vendor = PCI_VENDOR_ID_RICOH,
69 .device = PCI_DEVICE_ID_RICOH_R5C822,
70 .subvendor = PCI_ANY_ID,
71 .subdevice = PCI_ANY_ID,
8a4da143
PO		 72 .driver_data = SDHCI_QUIRK_FORCE_DMA |
73 SDHCI_QUIRK_NO_CARD_NO_RESET,
98608076
PO		 74 },
75
76 {
77 .vendor = PCI_VENDOR_ID_TI,
78 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
79 .subvendor = PCI_ANY_ID,
80 .subdevice = PCI_ANY_ID,
81 .driver_data = SDHCI_QUIRK_FORCE_DMA,
645289dc
PO		 82 },
83
9e9dc5f2
DS		 84 {
85 .vendor = PCI_VENDOR_ID_ENE,
86 .device = PCI_DEVICE_ID_ENE_CB712_SD,
87 .subvendor = PCI_ANY_ID,
88 .subdevice = PCI_ANY_ID,
7c168e3d
FT		 89 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
90 SDHCI_QUIRK_BROKEN_DMA,
9e9dc5f2
DS		 91 },
92
7de064eb
MK		 93 {
94 .vendor = PCI_VENDOR_ID_ENE,
95 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
96 .subvendor = PCI_ANY_ID,
97 .subdevice = PCI_ANY_ID,
7c168e3d
FT		 98 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
99 SDHCI_QUIRK_BROKEN_DMA,
7de064eb
MK		 100 },
101
b8352260
LD		 102 {
103 .vendor = PCI_VENDOR_ID_ENE,
104 .device = PCI_DEVICE_ID_ENE_CB714_SD,
105 .subvendor = PCI_ANY_ID,
106 .subdevice = PCI_ANY_ID,
107 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
108 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
109 },
110
111 {
112 .vendor = PCI_VENDOR_ID_ENE,
113 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
114 .subvendor = PCI_ANY_ID,
115 .subdevice = PCI_ANY_ID,
116 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
117 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
118 },
119
84c46a53
PO		 120 {
121 .vendor = PCI_VENDOR_ID_JMICRON,
122 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
123 .subvendor = PCI_ANY_ID,
124 .subdevice = PCI_ANY_ID,
125 .driver_data = SDHCI_QUIRK_32BIT_DMA_ADDR |
126 SDHCI_QUIRK_32BIT_DMA_SIZE |
127 SDHCI_QUIRK_RESET_AFTER_REQUEST,
128 },
129
645289dc
PO		 130 { /* Generic SD host controller */
131 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
132 },
133
d129bceb
PO		 134 { /* end: all zeroes */ },
135};
136
137MODULE_DEVICE_TABLE(pci, pci_ids);
138
139static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
140static void sdhci_finish_data(struct sdhci_host *);
141
142static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
143static void sdhci_finish_command(struct sdhci_host *);
144
145static void sdhci_dumpregs(struct sdhci_host *host)
146{
147 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
148
149 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
150 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
151 readw(host->ioaddr + SDHCI_HOST_VERSION));
152 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
153 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
154 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
155 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
156 readl(host->ioaddr + SDHCI_ARGUMENT),
157 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
158 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
159 readl(host->ioaddr + SDHCI_PRESENT_STATE),
160 readb(host->ioaddr + SDHCI_HOST_CONTROL));
161 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
162 readb(host->ioaddr + SDHCI_POWER_CONTROL),
163 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
164 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
2df3b71b 165 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
d129bceb
PO		 166 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
167 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
168 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
169 readl(host->ioaddr + SDHCI_INT_STATUS));
170 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
171 readl(host->ioaddr + SDHCI_INT_ENABLE),
172 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
173 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
174 readw(host->ioaddr + SDHCI_ACMD12_ERR),
175 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
176 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
177 readl(host->ioaddr + SDHCI_CAPABILITIES),
178 readl(host->ioaddr + SDHCI_MAX_CURRENT));
179
180 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
181}
182
183/*****************************************************************************\
184 * *
185 * Low level functions *
186 * *
187\*****************************************************************************/
188
189static void sdhci_reset(struct sdhci_host *host, u8 mask)
190{
e16514d8
PO		 191 unsigned long timeout;
192
8a4da143
PO		 193 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
194 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
195 SDHCI_CARD_PRESENT))
196 return;
197 }
198
d129bceb
PO		 199 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
200
e16514d8 201 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 202 host->clock = 0;
203
e16514d8
PO		 204 /* Wait max 100 ms */
205 timeout = 100;
206
207 /* hw clears the bit when it's done */
208 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
209 if (timeout == 0) {
acf1da45 210 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 211 mmc_hostname(host->mmc), (int)mask);
212 sdhci_dumpregs(host);
213 return;
214 }
215 timeout--;
216 mdelay(1);
d129bceb
PO		 217 }
218}
219
220static void sdhci_init(struct sdhci_host *host)
221{
222 u32 intmask;
223
224 sdhci_reset(host, SDHCI_RESET_ALL);
225
3192a28f
PO		 226 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
227 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
228 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
229 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
a406f5a3 230 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
3192a28f 231 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
d129bceb
PO		 232
233 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
234 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb
PO		 235}
236
237static void sdhci_activate_led(struct sdhci_host *host)
238{
239 u8 ctrl;
240
241 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
242 ctrl |= SDHCI_CTRL_LED;
243 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
244}
245
246static void sdhci_deactivate_led(struct sdhci_host *host)
247{
248 u8 ctrl;
249
250 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
251 ctrl &= ~SDHCI_CTRL_LED;
252 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
253}
254
255/*****************************************************************************\
256 * *
257 * Core functions *
258 * *
259\*****************************************************************************/
260
2a22b14e 261static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
d129bceb 262{
45711f1a 263 return sg_virt(host->cur_sg);
d129bceb
PO		 264}
265
266static inline int sdhci_next_sg(struct sdhci_host* host)
267{
268 /*
269 * Skip to next SG entry.
270 */
271 host->cur_sg++;
272 host->num_sg--;
273
274 /*
275 * Any entries left?
276 */
277 if (host->num_sg > 0) {
278 host->offset = 0;
279 host->remain = host->cur_sg->length;
280 }
281
282 return host->num_sg;
283}
284
a406f5a3 285static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 286{
a406f5a3
PO		 287 int blksize, chunk_remain;
288 u32 data;
d129bceb 289 char *buffer;
a406f5a3 290 int size;
d129bceb 291
a406f5a3 292 DBG("PIO reading\n");
d129bceb 293
a406f5a3
PO		 294 blksize = host->data->blksz;
295 chunk_remain = 0;
296 data = 0;
d129bceb 297
2a22b14e 298 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 299
a406f5a3
PO		 300 while (blksize) {
301 if (chunk_remain == 0) {
302 data = readl(host->ioaddr + SDHCI_BUFFER);
303 chunk_remain = min(blksize, 4);
304 }
d129bceb 305
14d836e7 306 size = min(host->remain, chunk_remain);
d129bceb 307
a406f5a3
PO		 308 chunk_remain -= size;
309 blksize -= size;
310 host->offset += size;
311 host->remain -= size;
14d836e7 312
a406f5a3
PO		 313 while (size) {
314 *buffer = data & 0xFF;
315 buffer++;
316 data >>= 8;
317 size--;
318 }
d129bceb 319
a406f5a3 320 if (host->remain == 0) {
a406f5a3
PO		 321 if (sdhci_next_sg(host) == 0) {
322 BUG_ON(blksize != 0);
323 return;
324 }
2a22b14e 325 buffer = sdhci_sg_to_buffer(host);
d129bceb 326 }
a406f5a3 327 }
a406f5a3 328}
d129bceb 329
a406f5a3
PO		 330static void sdhci_write_block_pio(struct sdhci_host *host)
331{
332 int blksize, chunk_remain;
333 u32 data;
334 char *buffer;
335 int bytes, size;
d129bceb 336
a406f5a3
PO		 337 DBG("PIO writing\n");
338
339 blksize = host->data->blksz;
340 chunk_remain = 4;
341 data = 0;
d129bceb 342
a406f5a3 343 bytes = 0;
2a22b14e 344 buffer = sdhci_sg_to_buffer(host) + host->offset;
d129bceb 345
a406f5a3 346 while (blksize) {
14d836e7 347 size = min(host->remain, chunk_remain);
a406f5a3
PO		 348
349 chunk_remain -= size;
350 blksize -= size;
d129bceb
PO		 351 host->offset += size;
352 host->remain -= size;
14d836e7 353
a406f5a3
PO		 354 while (size) {
355 data >>= 8;
356 data |= (u32)*buffer << 24;
357 buffer++;
358 size--;
359 }
360
361 if (chunk_remain == 0) {
362 writel(data, host->ioaddr + SDHCI_BUFFER);
363 chunk_remain = min(blksize, 4);
364 }
d129bceb
PO		 365
366 if (host->remain == 0) {
d129bceb 367 if (sdhci_next_sg(host) == 0) {
a406f5a3 368 BUG_ON(blksize != 0);
d129bceb
PO		 369 return;
370 }
2a22b14e 371 buffer = sdhci_sg_to_buffer(host);
d129bceb
PO		 372 }
373 }
a406f5a3
PO		 374}
375
376static void sdhci_transfer_pio(struct sdhci_host *host)
377{
378 u32 mask;
379
380 BUG_ON(!host->data);
381
14d836e7 382 if (host->num_sg == 0)
a406f5a3
PO		 383 return;
384
385 if (host->data->flags & MMC_DATA_READ)
386 mask = SDHCI_DATA_AVAILABLE;
387 else
388 mask = SDHCI_SPACE_AVAILABLE;
389
390 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
391 if (host->data->flags & MMC_DATA_READ)
392 sdhci_read_block_pio(host);
393 else
394 sdhci_write_block_pio(host);
d129bceb 395
14d836e7 396 if (host->num_sg == 0)
a406f5a3 397 break;
a406f5a3 398 }
d129bceb 399
a406f5a3 400 DBG("PIO transfer complete.\n");
d129bceb
PO		 401}
402
403static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
404{
1c8cde92
PO		 405 u8 count;
406 unsigned target_timeout, current_timeout;
d129bceb
PO		 407
408 WARN_ON(host->data);
409
c7fa9963 410 if (data == NULL)
d129bceb 411 return;
d129bceb 412
bab76961
PO		 413 /* Sanity checks */
414 BUG_ON(data->blksz * data->blocks > 524288);
fe4a3c7a 415 BUG_ON(data->blksz > host->mmc->max_blk_size);
1d676e02 416 BUG_ON(data->blocks > 65535);
d129bceb 417
e538fbe8
PO		 418 host->data = data;
419 host->data_early = 0;
420
1c8cde92
PO		 421 /* timeout in us */
422 target_timeout = data->timeout_ns / 1000 +
423 data->timeout_clks / host->clock;
d129bceb 424
1c8cde92
PO		 425 /*
426 * Figure out needed cycles.
427 * We do this in steps in order to fit inside a 32 bit int.
428 * The first step is the minimum timeout, which will have a
429 * minimum resolution of 6 bits:
430 * (1) 2^13*1000 > 2^22,
431 * (2) host->timeout_clk < 2^16
432 * =>
433 * (1) / (2) > 2^6
434 */
435 count = 0;
436 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
437 while (current_timeout < target_timeout) {
438 count++;
439 current_timeout <<= 1;
440 if (count >= 0xF)
441 break;
442 }
443
444 if (count >= 0xF) {
445 printk(KERN_WARNING "%s: Too large timeout requested!\n",
446 mmc_hostname(host->mmc));
447 count = 0xE;
448 }
449
450 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
d129bceb 451
c9fddbc4
PO		 452 if (host->flags & SDHCI_USE_DMA)
453 host->flags |= SDHCI_REQ_USE_DMA;
454
455 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
456 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
457 ((data->blksz * data->blocks) & 0x3))) {
458 DBG("Reverting to PIO because of transfer size (%d)\n",
459 data->blksz * data->blocks);
460 host->flags &= ~SDHCI_REQ_USE_DMA;
461 }
462
463 /*
464 * The assumption here being that alignment is the same after
465 * translation to device address space.
466 */
467 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
468 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
469 (data->sg->offset & 0x3))) {
470 DBG("Reverting to PIO because of bad alignment\n");
471 host->flags &= ~SDHCI_REQ_USE_DMA;
472 }
473
474 if (host->flags & SDHCI_REQ_USE_DMA) {
d129bceb
PO		 475 int count;
476
477 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
478 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
479 BUG_ON(count != 1);
480
481 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
482 } else {
d129bceb
PO		 483 host->cur_sg = data->sg;
484 host->num_sg = data->sg_len;
485
486 host->offset = 0;
487 host->remain = host->cur_sg->length;
488 }
c7fa9963 489
bab76961
PO		 490 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
491 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
492 host->ioaddr + SDHCI_BLOCK_SIZE);
c7fa9963
PO		 493 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
494}
495
496static void sdhci_set_transfer_mode(struct sdhci_host *host,
497 struct mmc_data *data)
498{
499 u16 mode;
500
c7fa9963
PO		 501 if (data == NULL)
502 return;
503
e538fbe8
PO		 504 WARN_ON(!host->data);
505
c7fa9963
PO		 506 mode = SDHCI_TRNS_BLK_CNT_EN;
507 if (data->blocks > 1)
508 mode |= SDHCI_TRNS_MULTI;
509 if (data->flags & MMC_DATA_READ)
510 mode |= SDHCI_TRNS_READ;
c9fddbc4 511 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 512 mode |= SDHCI_TRNS_DMA;
513
514 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
d129bceb
PO		 515}
516
517static void sdhci_finish_data(struct sdhci_host *host)
518{
519 struct mmc_data *data;
d129bceb
PO		 520 u16 blocks;
521
522 BUG_ON(!host->data);
523
524 data = host->data;
525 host->data = NULL;
526
c9fddbc4 527 if (host->flags & SDHCI_REQ_USE_DMA) {
d129bceb
PO		 528 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
529 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
d129bceb
PO		 530 }
531
532 /*
533 * Controller doesn't count down when in single block mode.
534 */
2b061973 535 if (data->blocks == 1)
17b0429d 536 blocks = (data->error == 0) ? 0 : 1;
d129bceb
PO		 537 else
538 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
a3fd4a1b 539 data->bytes_xfered = data->blksz * (data->blocks - blocks);
d129bceb 540
17b0429d 541 if (!data->error && blocks) {
d129bceb 542 printk(KERN_ERR "%s: Controller signalled completion even "
acf1da45
PO		 543 "though there were blocks left.\n",
544 mmc_hostname(host->mmc));
17b0429d 545 data->error = -EIO;
d129bceb
PO		 546 }
547
d129bceb
PO		 548 if (data->stop) {
549 /*
550 * The controller needs a reset of internal state machines
551 * upon error conditions.
552 */
17b0429d 553 if (data->error) {
d129bceb
PO		 554 sdhci_reset(host, SDHCI_RESET_CMD);
555 sdhci_reset(host, SDHCI_RESET_DATA);
556 }
557
558 sdhci_send_command(host, data->stop);
559 } else
560 tasklet_schedule(&host->finish_tasklet);
561}
562
563static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
564{
565 int flags;
fd2208d7 566 u32 mask;
7cb2c76f 567 unsigned long timeout;
d129bceb
PO		 568
569 WARN_ON(host->cmd);
570
d129bceb 571 /* Wait max 10 ms */
7cb2c76f 572 timeout = 10;
fd2208d7
PO		 573
574 mask = SDHCI_CMD_INHIBIT;
575 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
576 mask |= SDHCI_DATA_INHIBIT;
577
578 /* We shouldn't wait for data inihibit for stop commands, even
579 though they might use busy signaling */
580 if (host->mrq->data && (cmd == host->mrq->data->stop))
581 mask &= ~SDHCI_DATA_INHIBIT;
582
583 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 584 if (timeout == 0) {
d129bceb 585 printk(KERN_ERR "%s: Controller never released "
acf1da45 586 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 587 sdhci_dumpregs(host);
17b0429d 588 cmd->error = -EIO;
d129bceb
PO		 589 tasklet_schedule(&host->finish_tasklet);
590 return;
591 }
7cb2c76f
PO		 592 timeout--;
593 mdelay(1);
594 }
d129bceb
PO		 595
596 mod_timer(&host->timer, jiffies + 10 * HZ);
597
598 host->cmd = cmd;
599
600 sdhci_prepare_data(host, cmd->data);
601
602 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
603
c7fa9963
PO		 604 sdhci_set_transfer_mode(host, cmd->data);
605
d129bceb 606 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 607 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 608 mmc_hostname(host->mmc));
17b0429d 609 cmd->error = -EINVAL;
d129bceb
PO		 610 tasklet_schedule(&host->finish_tasklet);
611 return;
612 }
613
614 if (!(cmd->flags & MMC_RSP_PRESENT))
615 flags = SDHCI_CMD_RESP_NONE;
616 else if (cmd->flags & MMC_RSP_136)
617 flags = SDHCI_CMD_RESP_LONG;
618 else if (cmd->flags & MMC_RSP_BUSY)
619 flags = SDHCI_CMD_RESP_SHORT_BUSY;
620 else
621 flags = SDHCI_CMD_RESP_SHORT;
622
623 if (cmd->flags & MMC_RSP_CRC)
624 flags |= SDHCI_CMD_CRC;
625 if (cmd->flags & MMC_RSP_OPCODE)
626 flags |= SDHCI_CMD_INDEX;
627 if (cmd->data)
628 flags |= SDHCI_CMD_DATA;
629
fb61e289 630 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
d129bceb
PO		 631 host->ioaddr + SDHCI_COMMAND);
632}
633
634static void sdhci_finish_command(struct sdhci_host *host)
635{
636 int i;
637
638 BUG_ON(host->cmd == NULL);
639
640 if (host->cmd->flags & MMC_RSP_PRESENT) {
641 if (host->cmd->flags & MMC_RSP_136) {
642 /* CRC is stripped so we need to do some shifting. */
643 for (i = 0;i < 4;i++) {
644 host->cmd->resp[i] = readl(host->ioaddr +
645 SDHCI_RESPONSE + (3-i)*4) << 8;
646 if (i != 3)
647 host->cmd->resp[i] |=
648 readb(host->ioaddr +
649 SDHCI_RESPONSE + (3-i)*4-1);
650 }
651 } else {
652 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
653 }
654 }
655
17b0429d 656 host->cmd->error = 0;
d129bceb 657
e538fbe8
PO		 658 if (host->data && host->data_early)
659 sdhci_finish_data(host);
660
661 if (!host->cmd->data)
d129bceb
PO		 662 tasklet_schedule(&host->finish_tasklet);
663
664 host->cmd = NULL;
665}
666
667static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
668{
669 int div;
670 u16 clk;
7cb2c76f 671 unsigned long timeout;
d129bceb
PO		 672
673 if (clock == host->clock)
674 return;
675
676 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
677
678 if (clock == 0)
679 goto out;
680
681 for (div = 1;div < 256;div *= 2) {
682 if ((host->max_clk / div) <= clock)
683 break;
684 }
685 div >>= 1;
686
687 clk = div << SDHCI_DIVIDER_SHIFT;
688 clk |= SDHCI_CLOCK_INT_EN;
689 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
690
691 /* Wait max 10 ms */
7cb2c76f
PO		 692 timeout = 10;
693 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
694 & SDHCI_CLOCK_INT_STABLE)) {
695 if (timeout == 0) {
acf1da45
PO		 696 printk(KERN_ERR "%s: Internal clock never "
697 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 698 sdhci_dumpregs(host);
699 return;
700 }
7cb2c76f
PO		 701 timeout--;
702 mdelay(1);
703 }
d129bceb
PO		 704
705 clk |= SDHCI_CLOCK_CARD_EN;
706 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
707
708out:
709 host->clock = clock;
710}
711
146ad66e
PO		 712static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
713{
714 u8 pwr;
715
716 if (host->power == power)
717 return;
718
9e9dc5f2
DS		 719 if (power == (unsigned short)-1) {
720 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e 721 goto out;
9e9dc5f2
DS		 722 }
723
724 /*
725 * Spec says that we should clear the power reg before setting
726 * a new value. Some controllers don't seem to like this though.
727 */
728 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
729 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
146ad66e
PO		 730
731 pwr = SDHCI_POWER_ON;
732
4be34c99 733 switch (1 << power) {
55556da0 734 case MMC_VDD_165_195:
146ad66e
PO		 735 pwr |= SDHCI_POWER_180;
736 break;
4be34c99
PL		 737 case MMC_VDD_29_30:
738 case MMC_VDD_30_31:
146ad66e
PO		 739 pwr |= SDHCI_POWER_300;
740 break;
4be34c99
PL		 741 case MMC_VDD_32_33:
742 case MMC_VDD_33_34:
146ad66e
PO		 743 pwr |= SDHCI_POWER_330;
744 break;
745 default:
746 BUG();
747 }
748
749 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
750
751out:
752 host->power = power;
753}
754
d129bceb
PO		 755/*****************************************************************************\
756 * *
757 * MMC callbacks *
758 * *
759\*****************************************************************************/
760
761static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
762{
763 struct sdhci_host *host;
764 unsigned long flags;
765
766 host = mmc_priv(mmc);
767
768 spin_lock_irqsave(&host->lock, flags);
769
770 WARN_ON(host->mrq != NULL);
771
772 sdhci_activate_led(host);
773
774 host->mrq = mrq;
775
776 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
17b0429d 777 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 778 tasklet_schedule(&host->finish_tasklet);
779 } else
780 sdhci_send_command(host, mrq->cmd);
781
5f25a66f 782 mmiowb();
d129bceb
PO		 783 spin_unlock_irqrestore(&host->lock, flags);
784}
785
786static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
787{
788 struct sdhci_host *host;
789 unsigned long flags;
790 u8 ctrl;
791
792 host = mmc_priv(mmc);
793
794 spin_lock_irqsave(&host->lock, flags);
795
d129bceb
PO		 796 /*
797 * Reset the chip on each power off.
798 * Should clear out any weird states.
799 */
800 if (ios->power_mode == MMC_POWER_OFF) {
801 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
d129bceb 802 sdhci_init(host);
d129bceb
PO		 803 }
804
805 sdhci_set_clock(host, ios->clock);
806
807 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 808 sdhci_set_power(host, -1);
d129bceb 809 else
146ad66e 810 sdhci_set_power(host, ios->vdd);
d129bceb
PO		 811
812 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
cd9277c0 813
d129bceb
PO		 814 if (ios->bus_width == MMC_BUS_WIDTH_4)
815 ctrl |= SDHCI_CTRL_4BITBUS;
816 else
817 ctrl &= ~SDHCI_CTRL_4BITBUS;
cd9277c0
PO		 818
819 if (ios->timing == MMC_TIMING_SD_HS)
820 ctrl |= SDHCI_CTRL_HISPD;
821 else
822 ctrl &= ~SDHCI_CTRL_HISPD;
823
d129bceb
PO		 824 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
825
b8352260
LD		 826 /*
827 * Some (ENE) controllers go apeshit on some ios operation,
828 * signalling timeout and CRC errors even on CMD0. Resetting
829 * it on each ios seems to solve the problem.
830 */
831 if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
832 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
833
5f25a66f 834 mmiowb();
d129bceb
PO		 835 spin_unlock_irqrestore(&host->lock, flags);
836}
837
838static int sdhci_get_ro(struct mmc_host *mmc)
839{
840 struct sdhci_host *host;
841 unsigned long flags;
842 int present;
843
844 host = mmc_priv(mmc);
845
846 spin_lock_irqsave(&host->lock, flags);
847
848 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
849
850 spin_unlock_irqrestore(&host->lock, flags);
851
852 return !(present & SDHCI_WRITE_PROTECT);
853}
854
f75979b7
PO		 855static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
856{
857 struct sdhci_host *host;
858 unsigned long flags;
859 u32 ier;
860
861 host = mmc_priv(mmc);
862
863 spin_lock_irqsave(&host->lock, flags);
864
865 ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
866
867 ier &= ~SDHCI_INT_CARD_INT;
868 if (enable)
869 ier |= SDHCI_INT_CARD_INT;
870
871 writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
872 writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
873
874 mmiowb();
875
876 spin_unlock_irqrestore(&host->lock, flags);
877}
878
ab7aefd0 879static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 880 .request = sdhci_request,
881 .set_ios = sdhci_set_ios,
882 .get_ro = sdhci_get_ro,
f75979b7 883 .enable_sdio_irq = sdhci_enable_sdio_irq,
d129bceb
PO		 884};
885
886/*****************************************************************************\
887 * *
888 * Tasklets *
889 * *
890\*****************************************************************************/
891
892static void sdhci_tasklet_card(unsigned long param)
893{
894 struct sdhci_host *host;
895 unsigned long flags;
896
897 host = (struct sdhci_host*)param;
898
899 spin_lock_irqsave(&host->lock, flags);
900
901 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
902 if (host->mrq) {
903 printk(KERN_ERR "%s: Card removed during transfer!\n",
904 mmc_hostname(host->mmc));
905 printk(KERN_ERR "%s: Resetting controller.\n",
906 mmc_hostname(host->mmc));
907
908 sdhci_reset(host, SDHCI_RESET_CMD);
909 sdhci_reset(host, SDHCI_RESET_DATA);
910
17b0429d 911 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 912 tasklet_schedule(&host->finish_tasklet);
913 }
914 }
915
916 spin_unlock_irqrestore(&host->lock, flags);
917
918 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
919}
920
921static void sdhci_tasklet_finish(unsigned long param)
922{
923 struct sdhci_host *host;
924 unsigned long flags;
925 struct mmc_request *mrq;
926
927 host = (struct sdhci_host*)param;
928
929 spin_lock_irqsave(&host->lock, flags);
930
931 del_timer(&host->timer);
932
933 mrq = host->mrq;
934
d129bceb
PO		 935 /*
936 * The controller needs a reset of internal state machines
937 * upon error conditions.
938 */
17b0429d
PO		 939 if (mrq->cmd->error ||
940 (mrq->data && (mrq->data->error ||
84c46a53
PO		 941 (mrq->data->stop && mrq->data->stop->error))) ||
942 (host->chip->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
645289dc
PO		 943
944 /* Some controllers need this kick or reset won't work here */
945 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
946 unsigned int clock;
947
948 /* This is to force an update */
949 clock = host->clock;
950 host->clock = 0;
951 sdhci_set_clock(host, clock);
952 }
953
954 /* Spec says we should do both at the same time, but Ricoh
955 controllers do not like that. */
d129bceb
PO		 956 sdhci_reset(host, SDHCI_RESET_CMD);
957 sdhci_reset(host, SDHCI_RESET_DATA);
958 }
959
960 host->mrq = NULL;
961 host->cmd = NULL;
962 host->data = NULL;
963
964 sdhci_deactivate_led(host);
965
5f25a66f 966 mmiowb();
d129bceb
PO		 967 spin_unlock_irqrestore(&host->lock, flags);
968
969 mmc_request_done(host->mmc, mrq);
970}
971
972static void sdhci_timeout_timer(unsigned long data)
973{
974 struct sdhci_host *host;
975 unsigned long flags;
976
977 host = (struct sdhci_host*)data;
978
979 spin_lock_irqsave(&host->lock, flags);
980
981 if (host->mrq) {
acf1da45
PO		 982 printk(KERN_ERR "%s: Timeout waiting for hardware "
983 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 984 sdhci_dumpregs(host);
985
986 if (host->data) {
17b0429d 987 host->data->error = -ETIMEDOUT;
d129bceb
PO		 988 sdhci_finish_data(host);
989 } else {
990 if (host->cmd)
17b0429d 991 host->cmd->error = -ETIMEDOUT;
d129bceb 992 else
17b0429d 993 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 994
995 tasklet_schedule(&host->finish_tasklet);
996 }
997 }
998
5f25a66f 999 mmiowb();
d129bceb
PO		 1000 spin_unlock_irqrestore(&host->lock, flags);
1001}
1002
1003/*****************************************************************************\
1004 * *
1005 * Interrupt handling *
1006 * *
1007\*****************************************************************************/
1008
1009static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1010{
1011 BUG_ON(intmask == 0);
1012
1013 if (!host->cmd) {
b67ac3f3
PO		 1014 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1015 "though no command operation was in progress.\n",
1016 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1017 sdhci_dumpregs(host);
1018 return;
1019 }
1020
43b58b36 1021 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1022 host->cmd->error = -ETIMEDOUT;
1023 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1024 SDHCI_INT_INDEX))
1025 host->cmd->error = -EILSEQ;
43b58b36 1026
17b0429d 1027 if (host->cmd->error)
d129bceb 1028 tasklet_schedule(&host->finish_tasklet);
43b58b36
PO		 1029 else if (intmask & SDHCI_INT_RESPONSE)
1030 sdhci_finish_command(host);
d129bceb
PO		 1031}
1032
1033static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1034{
1035 BUG_ON(intmask == 0);
1036
1037 if (!host->data) {
1038 /*
1039 * A data end interrupt is sent together with the response
1040 * for the stop command.
1041 */
1042 if (intmask & SDHCI_INT_DATA_END)
1043 return;
1044
b67ac3f3
PO		 1045 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1046 "though no data operation was in progress.\n",
1047 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1048 sdhci_dumpregs(host);
1049
1050 return;
1051 }
1052
1053 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d
PO		 1054 host->data->error = -ETIMEDOUT;
1055 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1056 host->data->error = -EILSEQ;
d129bceb 1057
17b0429d 1058 if (host->data->error)
d129bceb
PO		 1059 sdhci_finish_data(host);
1060 else {
a406f5a3 1061 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1062 sdhci_transfer_pio(host);
1063
6ba736a1
PO		 1064 /*
1065 * We currently don't do anything fancy with DMA
1066 * boundaries, but as we can't disable the feature
1067 * we need to at least restart the transfer.
1068 */
1069 if (intmask & SDHCI_INT_DMA_END)
1070 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1071 host->ioaddr + SDHCI_DMA_ADDRESS);
1072
e538fbe8
PO		 1073 if (intmask & SDHCI_INT_DATA_END) {
1074 if (host->cmd) {
1075 /*
1076 * Data managed to finish before the
1077 * command completed. Make sure we do
1078 * things in the proper order.
1079 */
1080 host->data_early = 1;
1081 } else {
1082 sdhci_finish_data(host);
1083 }
1084 }
d129bceb
PO		 1085 }
1086}
1087
7d12e780 1088static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1089{
1090 irqreturn_t result;
1091 struct sdhci_host* host = dev_id;
1092 u32 intmask;
f75979b7 1093 int cardint = 0;
d129bceb
PO		 1094
1095 spin_lock(&host->lock);
1096
1097 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1098
62df67a5 1099 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1100 result = IRQ_NONE;
1101 goto out;
1102 }
1103
b69c9058
PO		 1104 DBG("*** %s got interrupt: 0x%08x\n",
1105 mmc_hostname(host->mmc), intmask);
d129bceb 1106
3192a28f
PO		 1107 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1108 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1109 host->ioaddr + SDHCI_INT_STATUS);
d129bceb 1110 tasklet_schedule(&host->card_tasklet);
3192a28f 1111 }
d129bceb 1112
3192a28f 1113 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1114
3192a28f 1115 if (intmask & SDHCI_INT_CMD_MASK) {
d129bceb
PO		 1116 writel(intmask & SDHCI_INT_CMD_MASK,
1117 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1118 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1119 }
1120
1121 if (intmask & SDHCI_INT_DATA_MASK) {
d129bceb
PO		 1122 writel(intmask & SDHCI_INT_DATA_MASK,
1123 host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1124 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1125 }
1126
1127 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1128
964f9ce2
PO		 1129 intmask &= ~SDHCI_INT_ERROR;
1130
d129bceb 1131 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1132 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1133 mmc_hostname(host->mmc));
3192a28f 1134 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
d129bceb
PO		 1135 }
1136
9d26a5d3 1137 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 1138
f75979b7
PO		 1139 if (intmask & SDHCI_INT_CARD_INT)
1140 cardint = 1;
1141
1142 intmask &= ~SDHCI_INT_CARD_INT;
1143
3192a28f 1144 if (intmask) {
acf1da45 1145 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1146 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1147 sdhci_dumpregs(host);
1148
d129bceb 1149 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
3192a28f 1150 }
d129bceb
PO		 1151
1152 result = IRQ_HANDLED;
1153
5f25a66f 1154 mmiowb();
d129bceb
PO		 1155out:
1156 spin_unlock(&host->lock);
1157
f75979b7
PO		 1158 /*
1159 * We have to delay this as it calls back into the driver.
1160 */
1161 if (cardint)
1162 mmc_signal_sdio_irq(host->mmc);
1163
d129bceb
PO		 1164 return result;
1165}
1166
1167/*****************************************************************************\
1168 * *
1169 * Suspend/resume *
1170 * *
1171\*****************************************************************************/
1172
1173#ifdef CONFIG_PM
1174
1175static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1176{
1177 struct sdhci_chip *chip;
1178 int i, ret;
1179
1180 chip = pci_get_drvdata(pdev);
1181 if (!chip)
1182 return 0;
1183
1184 DBG("Suspending...\n");
1185
1186 for (i = 0;i < chip->num_slots;i++) {
1187 if (!chip->hosts[i])
1188 continue;
1189 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1190 if (ret) {
1191 for (i--;i >= 0;i--)
1192 mmc_resume_host(chip->hosts[i]->mmc);
1193 return ret;
1194 }
1195 }
1196
1197 pci_save_state(pdev);
1198 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
a715dfc7
PO		 1199
1200 for (i = 0;i < chip->num_slots;i++) {
1201 if (!chip->hosts[i])
1202 continue;
1203 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1204 }
1205
d129bceb
PO		 1206 pci_disable_device(pdev);
1207 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1208
1209 return 0;
1210}
1211
1212static int sdhci_resume (struct pci_dev *pdev)
1213{
1214 struct sdhci_chip *chip;
1215 int i, ret;
1216
1217 chip = pci_get_drvdata(pdev);
1218 if (!chip)
1219 return 0;
1220
1221 DBG("Resuming...\n");
1222
1223 pci_set_power_state(pdev, PCI_D0);
1224 pci_restore_state(pdev);
df1c4b7b
PO		 1225 ret = pci_enable_device(pdev);
1226 if (ret)
1227 return ret;
d129bceb
PO		 1228
1229 for (i = 0;i < chip->num_slots;i++) {
1230 if (!chip->hosts[i])
1231 continue;
1232 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1233 pci_set_master(pdev);
a715dfc7 1234 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
b69c9058 1235 IRQF_SHARED, mmc_hostname(chip->hosts[i]->mmc),
a715dfc7
PO		 1236 chip->hosts[i]);
1237 if (ret)
1238 return ret;
d129bceb 1239 sdhci_init(chip->hosts[i]);
5f25a66f 1240 mmiowb();
d129bceb
PO		 1241 ret = mmc_resume_host(chip->hosts[i]->mmc);
1242 if (ret)
1243 return ret;
1244 }
1245
1246 return 0;
1247}
1248
1249#else /* CONFIG_PM */
1250
1251#define sdhci_suspend NULL
1252#define sdhci_resume NULL
1253
1254#endif /* CONFIG_PM */
1255
1256/*****************************************************************************\
1257 * *
1258 * Device probing/removal *
1259 * *
1260\*****************************************************************************/
1261
1262static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1263{
1264 int ret;
4a965505 1265 unsigned int version;
d129bceb
PO		 1266 struct sdhci_chip *chip;
1267 struct mmc_host *mmc;
1268 struct sdhci_host *host;
1269
1270 u8 first_bar;
1271 unsigned int caps;
1272
1273 chip = pci_get_drvdata(pdev);
1274 BUG_ON(!chip);
1275
1276 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1277 if (ret)
1278 return ret;
1279
1280 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1281
1282 if (first_bar > 5) {
1283 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1284 return -ENODEV;
1285 }
1286
1287 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1288 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1289 return -ENODEV;
1290 }
1291
1292 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
a98087cf
PO		 1293 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1294 "You may experience problems.\n");
d129bceb
PO		 1295 }
1296
67435274
PO		 1297 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1298 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1299 return -ENODEV;
1300 }
1301
1302 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1303 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1304 return -ENODEV;
1305 }
1306
d129bceb
PO		 1307 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1308 if (!mmc)
1309 return -ENOMEM;
1310
1311 host = mmc_priv(mmc);
1312 host->mmc = mmc;
1313
8a4da143
PO		 1314 host->chip = chip;
1315 chip->hosts[slot] = host;
1316
d129bceb
PO		 1317 host->bar = first_bar + slot;
1318
1319 host->addr = pci_resource_start(pdev, host->bar);
1320 host->irq = pdev->irq;
1321
1322 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1323
b69c9058 1324 ret = pci_request_region(pdev, host->bar, mmc_hostname(mmc));
d129bceb
PO		 1325 if (ret)
1326 goto free;
1327
1328 host->ioaddr = ioremap_nocache(host->addr,
1329 pci_resource_len(pdev, host->bar));
1330 if (!host->ioaddr) {
1331 ret = -ENOMEM;
1332 goto release;
1333 }
1334
d96649ed
PO		 1335 sdhci_reset(host, SDHCI_RESET_ALL);
1336
4a965505
PO		 1337 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1338 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
c6573c94 1339 if (version > 1) {
4a965505 1340 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 1341 "You may experience problems.\n", mmc_hostname(mmc),
4a965505 1342 version);
4a965505
PO		 1343 }
1344
d129bceb
PO		 1345 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1346
d6f8deec 1347 if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
98608076 1348 host->flags |= SDHCI_USE_DMA;
67435274
PO		 1349 else if (!(caps & SDHCI_CAN_DO_DMA))
1350 DBG("Controller doesn't have DMA capability\n");
1351 else
d129bceb
PO		 1352 host->flags |= SDHCI_USE_DMA;
1353
7c168e3d
FT		 1354 if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1355 (host->flags & SDHCI_USE_DMA)) {
cee687ce 1356 DBG("Disabling DMA as it is marked broken\n");
7c168e3d
FT		 1357 host->flags &= ~SDHCI_USE_DMA;
1358 }
1359
56e71efe
FT		 1360 if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1361 (host->flags & SDHCI_USE_DMA)) {
1362 printk(KERN_WARNING "%s: Will use DMA "
1363 "mode even though HW doesn't fully "
b69c9058 1364 "claim to support it.\n", mmc_hostname(mmc));
56e71efe
FT		 1365 }
1366
d129bceb
PO		 1367 if (host->flags & SDHCI_USE_DMA) {
1368 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1369 printk(KERN_WARNING "%s: No suitable DMA available. "
b69c9058 1370 "Falling back to PIO.\n", mmc_hostname(mmc));
d129bceb
PO		 1371 host->flags &= ~SDHCI_USE_DMA;
1372 }
1373 }
1374
1375 if (host->flags & SDHCI_USE_DMA)
1376 pci_set_master(pdev);
1377 else /* XXX: Hack to get MMC layer to avoid highmem */
1378 pdev->dma_mask = 0;
1379
8ef1a143
PO		 1380 host->max_clk =
1381 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1382 if (host->max_clk == 0) {
1383 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
b69c9058 1384 "frequency.\n", mmc_hostname(mmc));
8ef1a143
PO		 1385 ret = -ENODEV;
1386 goto unmap;
1387 }
d129bceb
PO		 1388 host->max_clk *= 1000000;
1389
1c8cde92
PO		 1390 host->timeout_clk =
1391 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1392 if (host->timeout_clk == 0) {
1393 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
b69c9058 1394 "frequency.\n", mmc_hostname(mmc));
1c8cde92
PO		 1395 ret = -ENODEV;
1396 goto unmap;
1397 }
1398 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1399 host->timeout_clk *= 1000;
d129bceb
PO		 1400
1401 /*
1402 * Set host parameters.
1403 */
1404 mmc->ops = &sdhci_ops;
1405 mmc->f_min = host->max_clk / 256;
1406 mmc->f_max = host->max_clk;
f75979b7 1407 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ;
d129bceb 1408
cd9277c0
PO		 1409 if (caps & SDHCI_CAN_DO_HISPD)
1410 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1411
146ad66e
PO		 1412 mmc->ocr_avail = 0;
1413 if (caps & SDHCI_CAN_VDD_330)
1414 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1415 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1416 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1417 if (caps & SDHCI_CAN_VDD_180)
55556da0 1418 mmc->ocr_avail |= MMC_VDD_165_195;
146ad66e
PO		 1419
1420 if (mmc->ocr_avail == 0) {
1421 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 1422 "support voltages.\n", mmc_hostname(mmc));
146ad66e
PO		 1423 ret = -ENODEV;
1424 goto unmap;
1425 }
1426
d129bceb
PO		 1427 spin_lock_init(&host->lock);
1428
1429 /*
1430 * Maximum number of segments. Hardware cannot do scatter lists.
1431 */
1432 if (host->flags & SDHCI_USE_DMA)
1433 mmc->max_hw_segs = 1;
1434 else
1435 mmc->max_hw_segs = 16;
1436 mmc->max_phys_segs = 16;
1437
1438 /*
bab76961 1439 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1440 * size (512KiB).
d129bceb 1441 */
55db890a 1442 mmc->max_req_size = 524288;
d129bceb
PO		 1443
1444 /*
1445 * Maximum segment size. Could be one segment with the maximum number
55db890a 1446 * of bytes.
d129bceb 1447 */
55db890a 1448 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1449
fe4a3c7a
PO		 1450 /*
1451 * Maximum block size. This varies from controller to controller and
1452 * is specified in the capabilities register.
1453 */
1454 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1455 if (mmc->max_blk_size >= 3) {
b69c9058
PO		 1456 printk(KERN_WARNING "%s: Invalid maximum block size, "
1457 "assuming 512 bytes\n", mmc_hostname(mmc));
03f8590d
DV		 1458 mmc->max_blk_size = 512;
1459 } else
1460 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 1461
55db890a
PO		 1462 /*
1463 * Maximum block count.
1464 */
1465 mmc->max_blk_count = 65535;
1466
d129bceb
PO		 1467 /*
1468 * Init tasklets.
1469 */
1470 tasklet_init(&host->card_tasklet,
1471 sdhci_tasklet_card, (unsigned long)host);
1472 tasklet_init(&host->finish_tasklet,
1473 sdhci_tasklet_finish, (unsigned long)host);
1474
e4cad1b5 1475 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1476
dace1453 1477 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 1478 mmc_hostname(mmc), host);
d129bceb 1479 if (ret)
8ef1a143 1480 goto untasklet;
d129bceb
PO		 1481
1482 sdhci_init(host);
1483
1484#ifdef CONFIG_MMC_DEBUG
1485 sdhci_dumpregs(host);
1486#endif
1487
5f25a66f
PO		 1488 mmiowb();
1489
d129bceb
PO		 1490 mmc_add_host(mmc);
1491
b69c9058
PO		 1492 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n",
1493 mmc_hostname(mmc), host->addr, host->irq,
d129bceb
PO		 1494 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1495
1496 return 0;
1497
8ef1a143 1498untasklet:
d129bceb
PO		 1499 tasklet_kill(&host->card_tasklet);
1500 tasklet_kill(&host->finish_tasklet);
8ef1a143 1501unmap:
d129bceb
PO		 1502 iounmap(host->ioaddr);
1503release:
1504 pci_release_region(pdev, host->bar);
1505free:
1506 mmc_free_host(mmc);
1507
1508 return ret;
1509}
1510
1511static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1512{
1513 struct sdhci_chip *chip;
1514 struct mmc_host *mmc;
1515 struct sdhci_host *host;
1516
1517 chip = pci_get_drvdata(pdev);
1518 host = chip->hosts[slot];
1519 mmc = host->mmc;
1520
1521 chip->hosts[slot] = NULL;
1522
1523 mmc_remove_host(mmc);
1524
1525 sdhci_reset(host, SDHCI_RESET_ALL);
1526
1527 free_irq(host->irq, host);
1528
1529 del_timer_sync(&host->timer);
1530
1531 tasklet_kill(&host->card_tasklet);
1532 tasklet_kill(&host->finish_tasklet);
1533
1534 iounmap(host->ioaddr);
1535
1536 pci_release_region(pdev, host->bar);
1537
1538 mmc_free_host(mmc);
1539}
1540
1541static int __devinit sdhci_probe(struct pci_dev *pdev,
1542 const struct pci_device_id *ent)
1543{
1544 int ret, i;
51f82bc0 1545 u8 slots, rev;
d129bceb
PO		 1546 struct sdhci_chip *chip;
1547
1548 BUG_ON(pdev == NULL);
1549 BUG_ON(ent == NULL);
1550
51f82bc0
PO		 1551 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1552
1553 printk(KERN_INFO DRIVER_NAME
1554 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1555 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1556 (int)rev);
d129bceb
PO		 1557
1558 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1559 if (ret)
1560 return ret;
1561
1562 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1563 DBG("found %d slot(s)\n", slots);
1564 if (slots == 0)
1565 return -ENODEV;
1566
1567 ret = pci_enable_device(pdev);
1568 if (ret)
1569 return ret;
1570
1571 chip = kzalloc(sizeof(struct sdhci_chip) +
1572 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1573 if (!chip) {
1574 ret = -ENOMEM;
1575 goto err;
1576 }
1577
1578 chip->pdev = pdev;
df673b22
PO		 1579 chip->quirks = ent->driver_data;
1580
1581 if (debug_quirks)
1582 chip->quirks = debug_quirks;
d129bceb
PO		 1583
1584 chip->num_slots = slots;
1585 pci_set_drvdata(pdev, chip);
1586
1587 for (i = 0;i < slots;i++) {
1588 ret = sdhci_probe_slot(pdev, i);
1589 if (ret) {
1590 for (i--;i >= 0;i--)
1591 sdhci_remove_slot(pdev, i);
1592 goto free;
1593 }
1594 }
1595
1596 return 0;
1597
1598free:
1599 pci_set_drvdata(pdev, NULL);
1600 kfree(chip);
1601
1602err:
1603 pci_disable_device(pdev);
1604 return ret;
1605}
1606
1607static void __devexit sdhci_remove(struct pci_dev *pdev)
1608{
1609 int i;
1610 struct sdhci_chip *chip;
1611
1612 chip = pci_get_drvdata(pdev);
1613
1614 if (chip) {
1615 for (i = 0;i < chip->num_slots;i++)
1616 sdhci_remove_slot(pdev, i);
1617
1618 pci_set_drvdata(pdev, NULL);
1619
1620 kfree(chip);
1621 }
1622
1623 pci_disable_device(pdev);
1624}
1625
1626static struct pci_driver sdhci_driver = {
1627 .name = DRIVER_NAME,
1628 .id_table = pci_ids,
1629 .probe = sdhci_probe,
1630 .remove = __devexit_p(sdhci_remove),
1631 .suspend = sdhci_suspend,
1632 .resume = sdhci_resume,
1633};
1634
1635/*****************************************************************************\
1636 * *
1637 * Driver init/exit *
1638 * *
1639\*****************************************************************************/
1640
1641static int __init sdhci_drv_init(void)
1642{
1643 printk(KERN_INFO DRIVER_NAME
52fbf9c9 1644 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 1645 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1646
1647 return pci_register_driver(&sdhci_driver);
1648}
1649
1650static void __exit sdhci_drv_exit(void)
1651{
1652 DBG("Exiting\n");
1653
1654 pci_unregister_driver(&sdhci_driver);
1655}
1656
1657module_init(sdhci_drv_init);
1658module_exit(sdhci_drv_exit);
1659
df673b22 1660module_param(debug_quirks, uint, 0444);
67435274 1661
d129bceb
PO		 1662MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1663MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
d129bceb 1664MODULE_LICENSE("GPL");
67435274 1665
df673b22 1666MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
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