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sdhci: Add support for card-detection polling
[net-next-2.6.git] / drivers / mmc / host / sdhci.c
CommitLineData
d129bceb 1/*
70f10482 2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
d129bceb 3 *
b69c9058 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
d129bceb
PO		 5 *
6 * This program is free software; you can redistribute it and/or modify
643f720c
PO		 7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
84c46a53
PO		 10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
d129bceb
PO		 14 */
15
d129bceb
PO		 16#include <linux/delay.h>
17#include <linux/highmem.h>
b8c86fc5 18#include <linux/io.h>
d129bceb 19#include <linux/dma-mapping.h>
11763609 20#include <linux/scatterlist.h>
d129bceb 21
2f730fec
PO		 22#include <linux/leds.h>
23
d129bceb 24#include <linux/mmc/host.h>
d129bceb 25
d129bceb
PO		 26#include "sdhci.h"
27
28#define DRIVER_NAME "sdhci"
d129bceb 29
d129bceb 30#define DBG(f, x...) \
c6563178 31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
d129bceb 32
f9134319
PO		 33#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
34 defined(CONFIG_MMC_SDHCI_MODULE))
35#define SDHCI_USE_LEDS_CLASS
36#endif
37
df673b22 38static unsigned int debug_quirks = 0;
67435274 39
d129bceb
PO		 40static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
41static void sdhci_finish_data(struct sdhci_host *);
42
43static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
44static void sdhci_finish_command(struct sdhci_host *);
45
46static void sdhci_dumpregs(struct sdhci_host *host)
47{
48 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
49
50 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
4e4141a5
AV		 51 sdhci_readl(host, SDHCI_DMA_ADDRESS),
52 sdhci_readw(host, SDHCI_HOST_VERSION));
d129bceb 53 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
4e4141a5
AV		 54 sdhci_readw(host, SDHCI_BLOCK_SIZE),
55 sdhci_readw(host, SDHCI_BLOCK_COUNT));
d129bceb 56 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
4e4141a5
AV		 57 sdhci_readl(host, SDHCI_ARGUMENT),
58 sdhci_readw(host, SDHCI_TRANSFER_MODE));
d129bceb 59 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
4e4141a5
AV		 60 sdhci_readl(host, SDHCI_PRESENT_STATE),
61 sdhci_readb(host, SDHCI_HOST_CONTROL));
d129bceb 62 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
4e4141a5
AV		 63 sdhci_readb(host, SDHCI_POWER_CONTROL),
64 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
d129bceb 65 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
4e4141a5
AV		 66 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
67 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
d129bceb 68 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
4e4141a5
AV		 69 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
70 sdhci_readl(host, SDHCI_INT_STATUS));
d129bceb 71 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
4e4141a5
AV		 72 sdhci_readl(host, SDHCI_INT_ENABLE),
73 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
d129bceb 74 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
4e4141a5
AV		 75 sdhci_readw(host, SDHCI_ACMD12_ERR),
76 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
d129bceb 77 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
4e4141a5
AV		 78 sdhci_readl(host, SDHCI_CAPABILITIES),
79 sdhci_readl(host, SDHCI_MAX_CURRENT));
d129bceb
PO		 80
81 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
82}
83
84/*****************************************************************************\
85 * *
86 * Low level functions *
87 * *
88\*****************************************************************************/
89
7260cf5e
AV		 90static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
91{
92 u32 ier;
93
94 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
95 ier &= ~clear;
96 ier |= set;
97 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
98 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
99}
100
101static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
102{
103 sdhci_clear_set_irqs(host, 0, irqs);
104}
105
106static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
107{
108 sdhci_clear_set_irqs(host, irqs, 0);
109}
110
111static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
112{
113 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
114
68d1fb7e
AV		 115 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
116 return;
117
7260cf5e
AV		 118 if (enable)
119 sdhci_unmask_irqs(host, irqs);
120 else
121 sdhci_mask_irqs(host, irqs);
122}
123
124static void sdhci_enable_card_detection(struct sdhci_host *host)
125{
126 sdhci_set_card_detection(host, true);
127}
128
129static void sdhci_disable_card_detection(struct sdhci_host *host)
130{
131 sdhci_set_card_detection(host, false);
132}
133
d129bceb
PO		 134static void sdhci_reset(struct sdhci_host *host, u8 mask)
135{
e16514d8
PO		 136 unsigned long timeout;
137
b8c86fc5 138 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
4e4141a5 139 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
8a4da143
PO		 140 SDHCI_CARD_PRESENT))
141 return;
142 }
143
4e4141a5 144 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
d129bceb 145
e16514d8 146 if (mask & SDHCI_RESET_ALL)
d129bceb
PO		 147 host->clock = 0;
148
e16514d8
PO		 149 /* Wait max 100 ms */
150 timeout = 100;
151
152 /* hw clears the bit when it's done */
4e4141a5 153 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
e16514d8 154 if (timeout == 0) {
acf1da45 155 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
e16514d8
PO		 156 mmc_hostname(host->mmc), (int)mask);
157 sdhci_dumpregs(host);
158 return;
159 }
160 timeout--;
161 mdelay(1);
d129bceb
PO		 162 }
163}
164
165static void sdhci_init(struct sdhci_host *host)
166{
d129bceb
PO		 167 sdhci_reset(host, SDHCI_RESET_ALL);
168
7260cf5e
AV		 169 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
170 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
3192a28f
PO		 171 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
172 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
6aa943ab 173 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
7260cf5e 174}
d129bceb 175
7260cf5e
AV		 176static void sdhci_reinit(struct sdhci_host *host)
177{
178 sdhci_init(host);
179 sdhci_enable_card_detection(host);
d129bceb
PO		 180}
181
182static void sdhci_activate_led(struct sdhci_host *host)
183{
184 u8 ctrl;
185
4e4141a5 186 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 187 ctrl |= SDHCI_CTRL_LED;
4e4141a5 188 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 189}
190
191static void sdhci_deactivate_led(struct sdhci_host *host)
192{
193 u8 ctrl;
194
4e4141a5 195 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
d129bceb 196 ctrl &= ~SDHCI_CTRL_LED;
4e4141a5 197 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb
PO		 198}
199
f9134319 200#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 201static void sdhci_led_control(struct led_classdev *led,
202 enum led_brightness brightness)
203{
204 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
205 unsigned long flags;
206
207 spin_lock_irqsave(&host->lock, flags);
208
209 if (brightness == LED_OFF)
210 sdhci_deactivate_led(host);
211 else
212 sdhci_activate_led(host);
213
214 spin_unlock_irqrestore(&host->lock, flags);
215}
216#endif
217
d129bceb
PO		 218/*****************************************************************************\
219 * *
220 * Core functions *
221 * *
222\*****************************************************************************/
223
a406f5a3 224static void sdhci_read_block_pio(struct sdhci_host *host)
d129bceb 225{
7659150c
PO		 226 unsigned long flags;
227 size_t blksize, len, chunk;
7244b85b 228 u32 uninitialized_var(scratch);
7659150c 229 u8 *buf;
d129bceb 230
a406f5a3 231 DBG("PIO reading\n");
d129bceb 232
a406f5a3 233 blksize = host->data->blksz;
7659150c 234 chunk = 0;
d129bceb 235
7659150c 236 local_irq_save(flags);
d129bceb 237
a406f5a3 238 while (blksize) {
7659150c
PO		 239 if (!sg_miter_next(&host->sg_miter))
240 BUG();
d129bceb 241
7659150c 242 len = min(host->sg_miter.length, blksize);
d129bceb 243
7659150c
PO		 244 blksize -= len;
245 host->sg_miter.consumed = len;
14d836e7 246
7659150c 247 buf = host->sg_miter.addr;
d129bceb 248
7659150c
PO		 249 while (len) {
250 if (chunk == 0) {
4e4141a5 251 scratch = sdhci_readl(host, SDHCI_BUFFER);
7659150c 252 chunk = 4;
a406f5a3 253 }
7659150c
PO		 254
255 *buf = scratch & 0xFF;
256
257 buf++;
258 scratch >>= 8;
259 chunk--;
260 len--;
d129bceb 261 }
a406f5a3 262 }
7659150c
PO		 263
264 sg_miter_stop(&host->sg_miter);
265
266 local_irq_restore(flags);
a406f5a3 267}
d129bceb 268
a406f5a3
PO		 269static void sdhci_write_block_pio(struct sdhci_host *host)
270{
7659150c
PO		 271 unsigned long flags;
272 size_t blksize, len, chunk;
273 u32 scratch;
274 u8 *buf;
d129bceb 275
a406f5a3
PO		 276 DBG("PIO writing\n");
277
278 blksize = host->data->blksz;
7659150c
PO		 279 chunk = 0;
280 scratch = 0;
d129bceb 281
7659150c 282 local_irq_save(flags);
d129bceb 283
a406f5a3 284 while (blksize) {
7659150c
PO		 285 if (!sg_miter_next(&host->sg_miter))
286 BUG();
a406f5a3 287
7659150c
PO		 288 len = min(host->sg_miter.length, blksize);
289
290 blksize -= len;
291 host->sg_miter.consumed = len;
292
293 buf = host->sg_miter.addr;
d129bceb 294
7659150c
PO		 295 while (len) {
296 scratch |= (u32)*buf << (chunk * 8);
297
298 buf++;
299 chunk++;
300 len--;
301
302 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
4e4141a5 303 sdhci_writel(host, scratch, SDHCI_BUFFER);
7659150c
PO		 304 chunk = 0;
305 scratch = 0;
d129bceb 306 }
d129bceb
PO		 307 }
308 }
7659150c
PO		 309
310 sg_miter_stop(&host->sg_miter);
311
312 local_irq_restore(flags);
a406f5a3
PO		 313}
314
315static void sdhci_transfer_pio(struct sdhci_host *host)
316{
317 u32 mask;
318
319 BUG_ON(!host->data);
320
7659150c 321 if (host->blocks == 0)
a406f5a3
PO		 322 return;
323
324 if (host->data->flags & MMC_DATA_READ)
325 mask = SDHCI_DATA_AVAILABLE;
326 else
327 mask = SDHCI_SPACE_AVAILABLE;
328
4a3cba32
PO		 329 /*
330 * Some controllers (JMicron JMB38x) mess up the buffer bits
331 * for transfers < 4 bytes. As long as it is just one block,
332 * we can ignore the bits.
333 */
334 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
335 (host->data->blocks == 1))
336 mask = ~0;
337
4e4141a5 338 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
a406f5a3
PO		 339 if (host->data->flags & MMC_DATA_READ)
340 sdhci_read_block_pio(host);
341 else
342 sdhci_write_block_pio(host);
d129bceb 343
7659150c
PO		 344 host->blocks--;
345 if (host->blocks == 0)
a406f5a3 346 break;
a406f5a3 347 }
d129bceb 348
a406f5a3 349 DBG("PIO transfer complete.\n");
d129bceb
PO		 350}
351
2134a922
PO		 352static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
353{
354 local_irq_save(*flags);
355 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
356}
357
358static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
359{
360 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
361 local_irq_restore(*flags);
362}
363
8f1934ce 364static int sdhci_adma_table_pre(struct sdhci_host *host,
2134a922
PO		 365 struct mmc_data *data)
366{
367 int direction;
368
369 u8 *desc;
370 u8 *align;
371 dma_addr_t addr;
372 dma_addr_t align_addr;
373 int len, offset;
374
375 struct scatterlist *sg;
376 int i;
377 char *buffer;
378 unsigned long flags;
379
380 /*
381 * The spec does not specify endianness of descriptor table.
382 * We currently guess that it is LE.
383 */
384
385 if (data->flags & MMC_DATA_READ)
386 direction = DMA_FROM_DEVICE;
387 else
388 direction = DMA_TO_DEVICE;
389
390 /*
391 * The ADMA descriptor table is mapped further down as we
392 * need to fill it with data first.
393 */
394
395 host->align_addr = dma_map_single(mmc_dev(host->mmc),
396 host->align_buffer, 128 * 4, direction);
8d8bb39b 397 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
8f1934ce 398 goto fail;
2134a922
PO		 399 BUG_ON(host->align_addr & 0x3);
400
401 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
402 data->sg, data->sg_len, direction);
8f1934ce
PO		 403 if (host->sg_count == 0)
404 goto unmap_align;
2134a922
PO		 405
406 desc = host->adma_desc;
407 align = host->align_buffer;
408
409 align_addr = host->align_addr;
410
411 for_each_sg(data->sg, sg, host->sg_count, i) {
412 addr = sg_dma_address(sg);
413 len = sg_dma_len(sg);
414
415 /*
416 * The SDHCI specification states that ADMA
417 * addresses must be 32-bit aligned. If they
418 * aren't, then we use a bounce buffer for
419 * the (up to three) bytes that screw up the
420 * alignment.
421 */
422 offset = (4 - (addr & 0x3)) & 0x3;
423 if (offset) {
424 if (data->flags & MMC_DATA_WRITE) {
425 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 426 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 427 memcpy(align, buffer, offset);
428 sdhci_kunmap_atomic(buffer, &flags);
429 }
430
431 desc[7] = (align_addr >> 24) & 0xff;
432 desc[6] = (align_addr >> 16) & 0xff;
433 desc[5] = (align_addr >> 8) & 0xff;
434 desc[4] = (align_addr >> 0) & 0xff;
435
436 BUG_ON(offset > 65536);
437
438 desc[3] = (offset >> 8) & 0xff;
439 desc[2] = (offset >> 0) & 0xff;
440
441 desc[1] = 0x00;
442 desc[0] = 0x21; /* tran, valid */
443
444 align += 4;
445 align_addr += 4;
446
447 desc += 8;
448
449 addr += offset;
450 len -= offset;
451 }
452
453 desc[7] = (addr >> 24) & 0xff;
454 desc[6] = (addr >> 16) & 0xff;
455 desc[5] = (addr >> 8) & 0xff;
456 desc[4] = (addr >> 0) & 0xff;
457
458 BUG_ON(len > 65536);
459
460 desc[3] = (len >> 8) & 0xff;
461 desc[2] = (len >> 0) & 0xff;
462
463 desc[1] = 0x00;
464 desc[0] = 0x21; /* tran, valid */
465
466 desc += 8;
467
468 /*
469 * If this triggers then we have a calculation bug
470 * somewhere. :/
471 */
472 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
473 }
474
475 /*
476 * Add a terminating entry.
477 */
478 desc[7] = 0;
479 desc[6] = 0;
480 desc[5] = 0;
481 desc[4] = 0;
482
483 desc[3] = 0;
484 desc[2] = 0;
485
486 desc[1] = 0x00;
487 desc[0] = 0x03; /* nop, end, valid */
488
489 /*
490 * Resync align buffer as we might have changed it.
491 */
492 if (data->flags & MMC_DATA_WRITE) {
493 dma_sync_single_for_device(mmc_dev(host->mmc),
494 host->align_addr, 128 * 4, direction);
495 }
496
497 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
498 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
980167b7 499 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
8f1934ce 500 goto unmap_entries;
2134a922 501 BUG_ON(host->adma_addr & 0x3);
8f1934ce
PO		 502
503 return 0;
504
505unmap_entries:
506 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
507 data->sg_len, direction);
508unmap_align:
509 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
510 128 * 4, direction);
511fail:
512 return -EINVAL;
2134a922
PO		 513}
514
515static void sdhci_adma_table_post(struct sdhci_host *host,
516 struct mmc_data *data)
517{
518 int direction;
519
520 struct scatterlist *sg;
521 int i, size;
522 u8 *align;
523 char *buffer;
524 unsigned long flags;
525
526 if (data->flags & MMC_DATA_READ)
527 direction = DMA_FROM_DEVICE;
528 else
529 direction = DMA_TO_DEVICE;
530
531 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
532 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
533
534 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
535 128 * 4, direction);
536
537 if (data->flags & MMC_DATA_READ) {
538 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
539 data->sg_len, direction);
540
541 align = host->align_buffer;
542
543 for_each_sg(data->sg, sg, host->sg_count, i) {
544 if (sg_dma_address(sg) & 0x3) {
545 size = 4 - (sg_dma_address(sg) & 0x3);
546
547 buffer = sdhci_kmap_atomic(sg, &flags);
6cefd05f 548 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
2134a922
PO		 549 memcpy(buffer, align, size);
550 sdhci_kunmap_atomic(buffer, &flags);
551
552 align += 4;
553 }
554 }
555 }
556
557 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
558 data->sg_len, direction);
559}
560
ee53ab5d 561static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
d129bceb 562{
1c8cde92
PO		 563 u8 count;
564 unsigned target_timeout, current_timeout;
d129bceb 565
ee53ab5d
PO		 566 /*
567 * If the host controller provides us with an incorrect timeout
568 * value, just skip the check and use 0xE. The hardware may take
569 * longer to time out, but that's much better than having a too-short
570 * timeout value.
571 */
572 if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL))
573 return 0xE;
e538fbe8 574
1c8cde92
PO		 575 /* timeout in us */
576 target_timeout = data->timeout_ns / 1000 +
577 data->timeout_clks / host->clock;
d129bceb 578
1c8cde92
PO		 579 /*
580 * Figure out needed cycles.
581 * We do this in steps in order to fit inside a 32 bit int.
582 * The first step is the minimum timeout, which will have a
583 * minimum resolution of 6 bits:
584 * (1) 2^13*1000 > 2^22,
585 * (2) host->timeout_clk < 2^16
586 * =>
587 * (1) / (2) > 2^6
588 */
589 count = 0;
590 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
591 while (current_timeout < target_timeout) {
592 count++;
593 current_timeout <<= 1;
594 if (count >= 0xF)
595 break;
596 }
597
598 if (count >= 0xF) {
599 printk(KERN_WARNING "%s: Too large timeout requested!\n",
600 mmc_hostname(host->mmc));
601 count = 0xE;
602 }
603
ee53ab5d
PO		 604 return count;
605}
606
6aa943ab
AV		 607static void sdhci_set_transfer_irqs(struct sdhci_host *host)
608{
609 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
610 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
611
612 if (host->flags & SDHCI_REQ_USE_DMA)
613 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
614 else
615 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
616}
617
ee53ab5d
PO		 618static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
619{
620 u8 count;
2134a922 621 u8 ctrl;
8f1934ce 622 int ret;
ee53ab5d
PO		 623
624 WARN_ON(host->data);
625
626 if (data == NULL)
627 return;
628
629 /* Sanity checks */
630 BUG_ON(data->blksz * data->blocks > 524288);
631 BUG_ON(data->blksz > host->mmc->max_blk_size);
632 BUG_ON(data->blocks > 65535);
633
634 host->data = data;
635 host->data_early = 0;
636
637 count = sdhci_calc_timeout(host, data);
4e4141a5 638 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
d129bceb 639
c9fddbc4
PO		 640 if (host->flags & SDHCI_USE_DMA)
641 host->flags |= SDHCI_REQ_USE_DMA;
642
2134a922
PO		 643 /*
644 * FIXME: This doesn't account for merging when mapping the
645 * scatterlist.
646 */
647 if (host->flags & SDHCI_REQ_USE_DMA) {
648 int broken, i;
649 struct scatterlist *sg;
650
651 broken = 0;
652 if (host->flags & SDHCI_USE_ADMA) {
653 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
654 broken = 1;
655 } else {
656 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
657 broken = 1;
658 }
659
660 if (unlikely(broken)) {
661 for_each_sg(data->sg, sg, data->sg_len, i) {
662 if (sg->length & 0x3) {
663 DBG("Reverting to PIO because of "
664 "transfer size (%d)\n",
665 sg->length);
666 host->flags &= ~SDHCI_REQ_USE_DMA;
667 break;
668 }
669 }
670 }
c9fddbc4
PO		 671 }
672
673 /*
674 * The assumption here being that alignment is the same after
675 * translation to device address space.
676 */
2134a922
PO		 677 if (host->flags & SDHCI_REQ_USE_DMA) {
678 int broken, i;
679 struct scatterlist *sg;
680
681 broken = 0;
682 if (host->flags & SDHCI_USE_ADMA) {
683 /*
684 * As we use 3 byte chunks to work around
685 * alignment problems, we need to check this
686 * quirk.
687 */
688 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
689 broken = 1;
690 } else {
691 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
692 broken = 1;
693 }
694
695 if (unlikely(broken)) {
696 for_each_sg(data->sg, sg, data->sg_len, i) {
697 if (sg->offset & 0x3) {
698 DBG("Reverting to PIO because of "
699 "bad alignment\n");
700 host->flags &= ~SDHCI_REQ_USE_DMA;
701 break;
702 }
703 }
704 }
705 }
706
8f1934ce
PO		 707 if (host->flags & SDHCI_REQ_USE_DMA) {
708 if (host->flags & SDHCI_USE_ADMA) {
709 ret = sdhci_adma_table_pre(host, data);
710 if (ret) {
711 /*
712 * This only happens when someone fed
713 * us an invalid request.
714 */
715 WARN_ON(1);
ebd6d357 716 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 717 } else {
4e4141a5
AV		 718 sdhci_writel(host, host->adma_addr,
719 SDHCI_ADMA_ADDRESS);
8f1934ce
PO		 720 }
721 } else {
c8b3e02e 722 int sg_cnt;
8f1934ce 723
c8b3e02e 724 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
8f1934ce
PO		 725 data->sg, data->sg_len,
726 (data->flags & MMC_DATA_READ) ?
727 DMA_FROM_DEVICE :
728 DMA_TO_DEVICE);
c8b3e02e 729 if (sg_cnt == 0) {
8f1934ce
PO		 730 /*
731 * This only happens when someone fed
732 * us an invalid request.
733 */
734 WARN_ON(1);
ebd6d357 735 host->flags &= ~SDHCI_REQ_USE_DMA;
8f1934ce 736 } else {
719a61b4 737 WARN_ON(sg_cnt != 1);
4e4141a5
AV		 738 sdhci_writel(host, sg_dma_address(data->sg),
739 SDHCI_DMA_ADDRESS);
8f1934ce
PO		 740 }
741 }
742 }
743
2134a922
PO		 744 /*
745 * Always adjust the DMA selection as some controllers
746 * (e.g. JMicron) can't do PIO properly when the selection
747 * is ADMA.
748 */
749 if (host->version >= SDHCI_SPEC_200) {
4e4141a5 750 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2134a922
PO		 751 ctrl &= ~SDHCI_CTRL_DMA_MASK;
752 if ((host->flags & SDHCI_REQ_USE_DMA) &&
753 (host->flags & SDHCI_USE_ADMA))
754 ctrl |= SDHCI_CTRL_ADMA32;
755 else
756 ctrl |= SDHCI_CTRL_SDMA;
4e4141a5 757 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
c9fddbc4
PO		 758 }
759
8f1934ce 760 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
7659150c
PO		 761 sg_miter_start(&host->sg_miter,
762 data->sg, data->sg_len, SG_MITER_ATOMIC);
763 host->blocks = data->blocks;
d129bceb 764 }
c7fa9963 765
6aa943ab
AV		 766 sdhci_set_transfer_irqs(host);
767
bab76961 768 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
4e4141a5
AV		 769 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
770 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
c7fa9963
PO		 771}
772
773static void sdhci_set_transfer_mode(struct sdhci_host *host,
774 struct mmc_data *data)
775{
776 u16 mode;
777
c7fa9963
PO		 778 if (data == NULL)
779 return;
780
e538fbe8
PO		 781 WARN_ON(!host->data);
782
c7fa9963
PO		 783 mode = SDHCI_TRNS_BLK_CNT_EN;
784 if (data->blocks > 1)
785 mode |= SDHCI_TRNS_MULTI;
786 if (data->flags & MMC_DATA_READ)
787 mode |= SDHCI_TRNS_READ;
c9fddbc4 788 if (host->flags & SDHCI_REQ_USE_DMA)
c7fa9963
PO		 789 mode |= SDHCI_TRNS_DMA;
790
4e4141a5 791 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
d129bceb
PO		 792}
793
794static void sdhci_finish_data(struct sdhci_host *host)
795{
796 struct mmc_data *data;
d129bceb
PO		 797
798 BUG_ON(!host->data);
799
800 data = host->data;
801 host->data = NULL;
802
c9fddbc4 803 if (host->flags & SDHCI_REQ_USE_DMA) {
2134a922
PO		 804 if (host->flags & SDHCI_USE_ADMA)
805 sdhci_adma_table_post(host, data);
806 else {
807 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
808 data->sg_len, (data->flags & MMC_DATA_READ) ?
809 DMA_FROM_DEVICE : DMA_TO_DEVICE);
810 }
d129bceb
PO		 811 }
812
813 /*
c9b74c5b
PO		 814 * The specification states that the block count register must
815 * be updated, but it does not specify at what point in the
816 * data flow. That makes the register entirely useless to read
817 * back so we have to assume that nothing made it to the card
818 * in the event of an error.
d129bceb 819 */
c9b74c5b
PO		 820 if (data->error)
821 data->bytes_xfered = 0;
d129bceb 822 else
c9b74c5b 823 data->bytes_xfered = data->blksz * data->blocks;
d129bceb 824
d129bceb
PO		 825 if (data->stop) {
826 /*
827 * The controller needs a reset of internal state machines
828 * upon error conditions.
829 */
17b0429d 830 if (data->error) {
d129bceb
PO		 831 sdhci_reset(host, SDHCI_RESET_CMD);
832 sdhci_reset(host, SDHCI_RESET_DATA);
833 }
834
835 sdhci_send_command(host, data->stop);
836 } else
837 tasklet_schedule(&host->finish_tasklet);
838}
839
840static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
841{
842 int flags;
fd2208d7 843 u32 mask;
7cb2c76f 844 unsigned long timeout;
d129bceb
PO		 845
846 WARN_ON(host->cmd);
847
d129bceb 848 /* Wait max 10 ms */
7cb2c76f 849 timeout = 10;
fd2208d7
PO		 850
851 mask = SDHCI_CMD_INHIBIT;
852 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
853 mask |= SDHCI_DATA_INHIBIT;
854
855 /* We shouldn't wait for data inihibit for stop commands, even
856 though they might use busy signaling */
857 if (host->mrq->data && (cmd == host->mrq->data->stop))
858 mask &= ~SDHCI_DATA_INHIBIT;
859
4e4141a5 860 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
7cb2c76f 861 if (timeout == 0) {
d129bceb 862 printk(KERN_ERR "%s: Controller never released "
acf1da45 863 "inhibit bit(s).\n", mmc_hostname(host->mmc));
d129bceb 864 sdhci_dumpregs(host);
17b0429d 865 cmd->error = -EIO;
d129bceb
PO		 866 tasklet_schedule(&host->finish_tasklet);
867 return;
868 }
7cb2c76f
PO		 869 timeout--;
870 mdelay(1);
871 }
d129bceb
PO		 872
873 mod_timer(&host->timer, jiffies + 10 * HZ);
874
875 host->cmd = cmd;
876
877 sdhci_prepare_data(host, cmd->data);
878
4e4141a5 879 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
d129bceb 880
c7fa9963
PO		 881 sdhci_set_transfer_mode(host, cmd->data);
882
d129bceb 883 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
acf1da45 884 printk(KERN_ERR "%s: Unsupported response type!\n",
d129bceb 885 mmc_hostname(host->mmc));
17b0429d 886 cmd->error = -EINVAL;
d129bceb
PO		 887 tasklet_schedule(&host->finish_tasklet);
888 return;
889 }
890
891 if (!(cmd->flags & MMC_RSP_PRESENT))
892 flags = SDHCI_CMD_RESP_NONE;
893 else if (cmd->flags & MMC_RSP_136)
894 flags = SDHCI_CMD_RESP_LONG;
895 else if (cmd->flags & MMC_RSP_BUSY)
896 flags = SDHCI_CMD_RESP_SHORT_BUSY;
897 else
898 flags = SDHCI_CMD_RESP_SHORT;
899
900 if (cmd->flags & MMC_RSP_CRC)
901 flags |= SDHCI_CMD_CRC;
902 if (cmd->flags & MMC_RSP_OPCODE)
903 flags |= SDHCI_CMD_INDEX;
904 if (cmd->data)
905 flags |= SDHCI_CMD_DATA;
906
4e4141a5 907 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
d129bceb
PO		 908}
909
910static void sdhci_finish_command(struct sdhci_host *host)
911{
912 int i;
913
914 BUG_ON(host->cmd == NULL);
915
916 if (host->cmd->flags & MMC_RSP_PRESENT) {
917 if (host->cmd->flags & MMC_RSP_136) {
918 /* CRC is stripped so we need to do some shifting. */
919 for (i = 0;i < 4;i++) {
4e4141a5 920 host->cmd->resp[i] = sdhci_readl(host,
d129bceb
PO		 921 SDHCI_RESPONSE + (3-i)*4) << 8;
922 if (i != 3)
923 host->cmd->resp[i] |=
4e4141a5 924 sdhci_readb(host,
d129bceb
PO		 925 SDHCI_RESPONSE + (3-i)*4-1);
926 }
927 } else {
4e4141a5 928 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
d129bceb
PO		 929 }
930 }
931
17b0429d 932 host->cmd->error = 0;
d129bceb 933
e538fbe8
PO		 934 if (host->data && host->data_early)
935 sdhci_finish_data(host);
936
937 if (!host->cmd->data)
d129bceb
PO		 938 tasklet_schedule(&host->finish_tasklet);
939
940 host->cmd = NULL;
941}
942
943static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
944{
945 int div;
946 u16 clk;
7cb2c76f 947 unsigned long timeout;
d129bceb
PO		 948
949 if (clock == host->clock)
950 return;
951
4e4141a5 952 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 953
954 if (clock == 0)
955 goto out;
956
957 for (div = 1;div < 256;div *= 2) {
958 if ((host->max_clk / div) <= clock)
959 break;
960 }
961 div >>= 1;
962
963 clk = div << SDHCI_DIVIDER_SHIFT;
964 clk |= SDHCI_CLOCK_INT_EN;
4e4141a5 965 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 966
967 /* Wait max 10 ms */
7cb2c76f 968 timeout = 10;
4e4141a5 969 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7cb2c76f
PO		 970 & SDHCI_CLOCK_INT_STABLE)) {
971 if (timeout == 0) {
acf1da45
PO		 972 printk(KERN_ERR "%s: Internal clock never "
973 "stabilised.\n", mmc_hostname(host->mmc));
d129bceb
PO		 974 sdhci_dumpregs(host);
975 return;
976 }
7cb2c76f
PO		 977 timeout--;
978 mdelay(1);
979 }
d129bceb
PO		 980
981 clk |= SDHCI_CLOCK_CARD_EN;
4e4141a5 982 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
d129bceb
PO		 983
984out:
985 host->clock = clock;
986}
987
146ad66e
PO		 988static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
989{
990 u8 pwr;
991
992 if (host->power == power)
993 return;
994
9e9dc5f2 995 if (power == (unsigned short)-1) {
4e4141a5 996 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e 997 goto out;
9e9dc5f2
DS		 998 }
999
1000 /*
1001 * Spec says that we should clear the power reg before setting
1002 * a new value. Some controllers don't seem to like this though.
1003 */
b8c86fc5 1004 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
4e4141a5 1005 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
146ad66e
PO		 1006
1007 pwr = SDHCI_POWER_ON;
1008
4be34c99 1009 switch (1 << power) {
55556da0 1010 case MMC_VDD_165_195:
146ad66e
PO		 1011 pwr |= SDHCI_POWER_180;
1012 break;
4be34c99
PL		 1013 case MMC_VDD_29_30:
1014 case MMC_VDD_30_31:
146ad66e
PO		 1015 pwr |= SDHCI_POWER_300;
1016 break;
4be34c99
PL		 1017 case MMC_VDD_32_33:
1018 case MMC_VDD_33_34:
146ad66e
PO		 1019 pwr |= SDHCI_POWER_330;
1020 break;
1021 default:
1022 BUG();
1023 }
1024
e08c1694 1025 /*
c71f6512 1026 * At least the Marvell CaFe chip gets confused if we set the voltage
e08c1694
AS		 1027 * and set turn on power at the same time, so set the voltage first.
1028 */
b8c86fc5 1029 if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
4e4141a5 1030 sdhci_writeb(host, pwr & ~SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
e08c1694 1031
4e4141a5 1032 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
146ad66e
PO		 1033
1034out:
1035 host->power = power;
1036}
1037
d129bceb
PO		 1038/*****************************************************************************\
1039 * *
1040 * MMC callbacks *
1041 * *
1042\*****************************************************************************/
1043
1044static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1045{
1046 struct sdhci_host *host;
68d1fb7e 1047 bool present;
d129bceb
PO		 1048 unsigned long flags;
1049
1050 host = mmc_priv(mmc);
1051
1052 spin_lock_irqsave(&host->lock, flags);
1053
1054 WARN_ON(host->mrq != NULL);
1055
f9134319 1056#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1057 sdhci_activate_led(host);
2f730fec 1058#endif
d129bceb
PO		 1059
1060 host->mrq = mrq;
1061
68d1fb7e
AV		 1062 /* If polling, assume that the card is always present. */
1063 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1064 present = true;
1065 else
1066 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1067 SDHCI_CARD_PRESENT;
1068
1069 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
17b0429d 1070 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1071 tasklet_schedule(&host->finish_tasklet);
1072 } else
1073 sdhci_send_command(host, mrq->cmd);
1074
5f25a66f 1075 mmiowb();
d129bceb
PO		 1076 spin_unlock_irqrestore(&host->lock, flags);
1077}
1078
1079static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1080{
1081 struct sdhci_host *host;
1082 unsigned long flags;
1083 u8 ctrl;
1084
1085 host = mmc_priv(mmc);
1086
1087 spin_lock_irqsave(&host->lock, flags);
1088
1e72859e
PO		 1089 if (host->flags & SDHCI_DEVICE_DEAD)
1090 goto out;
1091
d129bceb
PO		 1092 /*
1093 * Reset the chip on each power off.
1094 * Should clear out any weird states.
1095 */
1096 if (ios->power_mode == MMC_POWER_OFF) {
4e4141a5 1097 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
7260cf5e 1098 sdhci_reinit(host);
d129bceb
PO		 1099 }
1100
1101 sdhci_set_clock(host, ios->clock);
1102
1103 if (ios->power_mode == MMC_POWER_OFF)
146ad66e 1104 sdhci_set_power(host, -1);
d129bceb 1105 else
146ad66e 1106 sdhci_set_power(host, ios->vdd);
d129bceb 1107
4e4141a5 1108 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
cd9277c0 1109
d129bceb
PO		 1110 if (ios->bus_width == MMC_BUS_WIDTH_4)
1111 ctrl |= SDHCI_CTRL_4BITBUS;
1112 else
1113 ctrl &= ~SDHCI_CTRL_4BITBUS;
cd9277c0
PO		 1114
1115 if (ios->timing == MMC_TIMING_SD_HS)
1116 ctrl |= SDHCI_CTRL_HISPD;
1117 else
1118 ctrl &= ~SDHCI_CTRL_HISPD;
1119
4e4141a5 1120 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
d129bceb 1121
b8352260
LD		 1122 /*
1123 * Some (ENE) controllers go apeshit on some ios operation,
1124 * signalling timeout and CRC errors even on CMD0. Resetting
1125 * it on each ios seems to solve the problem.
1126 */
b8c86fc5 1127 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
b8352260
LD		 1128 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1129
1e72859e 1130out:
5f25a66f 1131 mmiowb();
d129bceb
PO		 1132 spin_unlock_irqrestore(&host->lock, flags);
1133}
1134
1135static int sdhci_get_ro(struct mmc_host *mmc)
1136{
1137 struct sdhci_host *host;
1138 unsigned long flags;
1139 int present;
1140
1141 host = mmc_priv(mmc);
1142
1143 spin_lock_irqsave(&host->lock, flags);
1144
1e72859e
PO		 1145 if (host->flags & SDHCI_DEVICE_DEAD)
1146 present = 0;
1147 else
4e4141a5 1148 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
d129bceb
PO		 1149
1150 spin_unlock_irqrestore(&host->lock, flags);
1151
1152 return !(present & SDHCI_WRITE_PROTECT);
1153}
1154
f75979b7
PO		 1155static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1156{
1157 struct sdhci_host *host;
1158 unsigned long flags;
f75979b7
PO		 1159
1160 host = mmc_priv(mmc);
1161
1162 spin_lock_irqsave(&host->lock, flags);
1163
1e72859e
PO		 1164 if (host->flags & SDHCI_DEVICE_DEAD)
1165 goto out;
1166
f75979b7 1167 if (enable)
7260cf5e
AV		 1168 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1169 else
1170 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1e72859e 1171out:
f75979b7
PO		 1172 mmiowb();
1173
1174 spin_unlock_irqrestore(&host->lock, flags);
1175}
1176
ab7aefd0 1177static const struct mmc_host_ops sdhci_ops = {
d129bceb
PO		 1178 .request = sdhci_request,
1179 .set_ios = sdhci_set_ios,
1180 .get_ro = sdhci_get_ro,
f75979b7 1181 .enable_sdio_irq = sdhci_enable_sdio_irq,
d129bceb
PO		 1182};
1183
1184/*****************************************************************************\
1185 * *
1186 * Tasklets *
1187 * *
1188\*****************************************************************************/
1189
1190static void sdhci_tasklet_card(unsigned long param)
1191{
1192 struct sdhci_host *host;
1193 unsigned long flags;
1194
1195 host = (struct sdhci_host*)param;
1196
1197 spin_lock_irqsave(&host->lock, flags);
1198
4e4141a5 1199 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
d129bceb
PO		 1200 if (host->mrq) {
1201 printk(KERN_ERR "%s: Card removed during transfer!\n",
1202 mmc_hostname(host->mmc));
1203 printk(KERN_ERR "%s: Resetting controller.\n",
1204 mmc_hostname(host->mmc));
1205
1206 sdhci_reset(host, SDHCI_RESET_CMD);
1207 sdhci_reset(host, SDHCI_RESET_DATA);
1208
17b0429d 1209 host->mrq->cmd->error = -ENOMEDIUM;
d129bceb
PO		 1210 tasklet_schedule(&host->finish_tasklet);
1211 }
1212 }
1213
1214 spin_unlock_irqrestore(&host->lock, flags);
1215
04cf585d 1216 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
d129bceb
PO		 1217}
1218
1219static void sdhci_tasklet_finish(unsigned long param)
1220{
1221 struct sdhci_host *host;
1222 unsigned long flags;
1223 struct mmc_request *mrq;
1224
1225 host = (struct sdhci_host*)param;
1226
1227 spin_lock_irqsave(&host->lock, flags);
1228
1229 del_timer(&host->timer);
1230
1231 mrq = host->mrq;
1232
d129bceb
PO		 1233 /*
1234 * The controller needs a reset of internal state machines
1235 * upon error conditions.
1236 */
1e72859e
PO		 1237 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1238 (mrq->cmd->error ||
1239 (mrq->data && (mrq->data->error ||
1240 (mrq->data->stop && mrq->data->stop->error))) ||
1241 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
645289dc
PO		 1242
1243 /* Some controllers need this kick or reset won't work here */
b8c86fc5 1244 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
645289dc
PO		 1245 unsigned int clock;
1246
1247 /* This is to force an update */
1248 clock = host->clock;
1249 host->clock = 0;
1250 sdhci_set_clock(host, clock);
1251 }
1252
1253 /* Spec says we should do both at the same time, but Ricoh
1254 controllers do not like that. */
d129bceb
PO		 1255 sdhci_reset(host, SDHCI_RESET_CMD);
1256 sdhci_reset(host, SDHCI_RESET_DATA);
1257 }
1258
1259 host->mrq = NULL;
1260 host->cmd = NULL;
1261 host->data = NULL;
1262
f9134319 1263#ifndef SDHCI_USE_LEDS_CLASS
d129bceb 1264 sdhci_deactivate_led(host);
2f730fec 1265#endif
d129bceb 1266
5f25a66f 1267 mmiowb();
d129bceb
PO		 1268 spin_unlock_irqrestore(&host->lock, flags);
1269
1270 mmc_request_done(host->mmc, mrq);
1271}
1272
1273static void sdhci_timeout_timer(unsigned long data)
1274{
1275 struct sdhci_host *host;
1276 unsigned long flags;
1277
1278 host = (struct sdhci_host*)data;
1279
1280 spin_lock_irqsave(&host->lock, flags);
1281
1282 if (host->mrq) {
acf1da45
PO		 1283 printk(KERN_ERR "%s: Timeout waiting for hardware "
1284 "interrupt.\n", mmc_hostname(host->mmc));
d129bceb
PO		 1285 sdhci_dumpregs(host);
1286
1287 if (host->data) {
17b0429d 1288 host->data->error = -ETIMEDOUT;
d129bceb
PO		 1289 sdhci_finish_data(host);
1290 } else {
1291 if (host->cmd)
17b0429d 1292 host->cmd->error = -ETIMEDOUT;
d129bceb 1293 else
17b0429d 1294 host->mrq->cmd->error = -ETIMEDOUT;
d129bceb
PO		 1295
1296 tasklet_schedule(&host->finish_tasklet);
1297 }
1298 }
1299
5f25a66f 1300 mmiowb();
d129bceb
PO		 1301 spin_unlock_irqrestore(&host->lock, flags);
1302}
1303
1304/*****************************************************************************\
1305 * *
1306 * Interrupt handling *
1307 * *
1308\*****************************************************************************/
1309
1310static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1311{
1312 BUG_ON(intmask == 0);
1313
1314 if (!host->cmd) {
b67ac3f3
PO		 1315 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1316 "though no command operation was in progress.\n",
1317 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1318 sdhci_dumpregs(host);
1319 return;
1320 }
1321
43b58b36 1322 if (intmask & SDHCI_INT_TIMEOUT)
17b0429d
PO		 1323 host->cmd->error = -ETIMEDOUT;
1324 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1325 SDHCI_INT_INDEX))
1326 host->cmd->error = -EILSEQ;
43b58b36 1327
e809517f 1328 if (host->cmd->error) {
d129bceb 1329 tasklet_schedule(&host->finish_tasklet);
e809517f
PO		 1330 return;
1331 }
1332
1333 /*
1334 * The host can send and interrupt when the busy state has
1335 * ended, allowing us to wait without wasting CPU cycles.
1336 * Unfortunately this is overloaded on the "data complete"
1337 * interrupt, so we need to take some care when handling
1338 * it.
1339 *
1340 * Note: The 1.0 specification is a bit ambiguous about this
1341 * feature so there might be some problems with older
1342 * controllers.
1343 */
1344 if (host->cmd->flags & MMC_RSP_BUSY) {
1345 if (host->cmd->data)
1346 DBG("Cannot wait for busy signal when also "
1347 "doing a data transfer");
f945405c 1348 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
e809517f 1349 return;
f945405c
BD		 1350
1351 /* The controller does not support the end-of-busy IRQ,
1352 * fall through and take the SDHCI_INT_RESPONSE */
e809517f
PO		 1353 }
1354
1355 if (intmask & SDHCI_INT_RESPONSE)
43b58b36 1356 sdhci_finish_command(host);
d129bceb
PO		 1357}
1358
1359static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1360{
1361 BUG_ON(intmask == 0);
1362
1363 if (!host->data) {
1364 /*
e809517f
PO		 1365 * The "data complete" interrupt is also used to
1366 * indicate that a busy state has ended. See comment
1367 * above in sdhci_cmd_irq().
d129bceb 1368 */
e809517f
PO		 1369 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1370 if (intmask & SDHCI_INT_DATA_END) {
1371 sdhci_finish_command(host);
1372 return;
1373 }
1374 }
d129bceb 1375
b67ac3f3
PO		 1376 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1377 "though no data operation was in progress.\n",
1378 mmc_hostname(host->mmc), (unsigned)intmask);
d129bceb
PO		 1379 sdhci_dumpregs(host);
1380
1381 return;
1382 }
1383
1384 if (intmask & SDHCI_INT_DATA_TIMEOUT)
17b0429d
PO		 1385 host->data->error = -ETIMEDOUT;
1386 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1387 host->data->error = -EILSEQ;
2134a922
PO		 1388 else if (intmask & SDHCI_INT_ADMA_ERROR)
1389 host->data->error = -EIO;
d129bceb 1390
17b0429d 1391 if (host->data->error)
d129bceb
PO		 1392 sdhci_finish_data(host);
1393 else {
a406f5a3 1394 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
d129bceb
PO		 1395 sdhci_transfer_pio(host);
1396
6ba736a1
PO		 1397 /*
1398 * We currently don't do anything fancy with DMA
1399 * boundaries, but as we can't disable the feature
1400 * we need to at least restart the transfer.
1401 */
1402 if (intmask & SDHCI_INT_DMA_END)
4e4141a5
AV		 1403 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1404 SDHCI_DMA_ADDRESS);
6ba736a1 1405
e538fbe8
PO		 1406 if (intmask & SDHCI_INT_DATA_END) {
1407 if (host->cmd) {
1408 /*
1409 * Data managed to finish before the
1410 * command completed. Make sure we do
1411 * things in the proper order.
1412 */
1413 host->data_early = 1;
1414 } else {
1415 sdhci_finish_data(host);
1416 }
1417 }
d129bceb
PO		 1418 }
1419}
1420
7d12e780 1421static irqreturn_t sdhci_irq(int irq, void *dev_id)
d129bceb
PO		 1422{
1423 irqreturn_t result;
1424 struct sdhci_host* host = dev_id;
1425 u32 intmask;
f75979b7 1426 int cardint = 0;
d129bceb
PO		 1427
1428 spin_lock(&host->lock);
1429
4e4141a5 1430 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
d129bceb 1431
62df67a5 1432 if (!intmask || intmask == 0xffffffff) {
d129bceb
PO		 1433 result = IRQ_NONE;
1434 goto out;
1435 }
1436
b69c9058
PO		 1437 DBG("*** %s got interrupt: 0x%08x\n",
1438 mmc_hostname(host->mmc), intmask);
d129bceb 1439
3192a28f 1440 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
4e4141a5
AV		 1441 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1442 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
d129bceb 1443 tasklet_schedule(&host->card_tasklet);
3192a28f 1444 }
d129bceb 1445
3192a28f 1446 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
d129bceb 1447
3192a28f 1448 if (intmask & SDHCI_INT_CMD_MASK) {
4e4141a5
AV		 1449 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1450 SDHCI_INT_STATUS);
3192a28f 1451 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
d129bceb
PO		 1452 }
1453
1454 if (intmask & SDHCI_INT_DATA_MASK) {
4e4141a5
AV		 1455 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1456 SDHCI_INT_STATUS);
3192a28f 1457 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
d129bceb
PO		 1458 }
1459
1460 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1461
964f9ce2
PO		 1462 intmask &= ~SDHCI_INT_ERROR;
1463
d129bceb 1464 if (intmask & SDHCI_INT_BUS_POWER) {
3192a28f 1465 printk(KERN_ERR "%s: Card is consuming too much power!\n",
d129bceb 1466 mmc_hostname(host->mmc));
4e4141a5 1467 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
d129bceb
PO		 1468 }
1469
9d26a5d3 1470 intmask &= ~SDHCI_INT_BUS_POWER;
3192a28f 1471
f75979b7
PO		 1472 if (intmask & SDHCI_INT_CARD_INT)
1473 cardint = 1;
1474
1475 intmask &= ~SDHCI_INT_CARD_INT;
1476
3192a28f 1477 if (intmask) {
acf1da45 1478 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
3192a28f 1479 mmc_hostname(host->mmc), intmask);
d129bceb
PO		 1480 sdhci_dumpregs(host);
1481
4e4141a5 1482 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3192a28f 1483 }
d129bceb
PO		 1484
1485 result = IRQ_HANDLED;
1486
5f25a66f 1487 mmiowb();
d129bceb
PO		 1488out:
1489 spin_unlock(&host->lock);
1490
f75979b7
PO		 1491 /*
1492 * We have to delay this as it calls back into the driver.
1493 */
1494 if (cardint)
1495 mmc_signal_sdio_irq(host->mmc);
1496
d129bceb
PO		 1497 return result;
1498}
1499
1500/*****************************************************************************\
1501 * *
1502 * Suspend/resume *
1503 * *
1504\*****************************************************************************/
1505
1506#ifdef CONFIG_PM
1507
b8c86fc5 1508int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
d129bceb 1509{
b8c86fc5 1510 int ret;
a715dfc7 1511
7260cf5e
AV		 1512 sdhci_disable_card_detection(host);
1513
b8c86fc5
PO		 1514 ret = mmc_suspend_host(host->mmc, state);
1515 if (ret)
1516 return ret;
a715dfc7 1517
b8c86fc5 1518 free_irq(host->irq, host);
d129bceb
PO		 1519
1520 return 0;
1521}
1522
b8c86fc5 1523EXPORT_SYMBOL_GPL(sdhci_suspend_host);
d129bceb 1524
b8c86fc5
PO		 1525int sdhci_resume_host(struct sdhci_host *host)
1526{
1527 int ret;
d129bceb 1528
b8c86fc5
PO		 1529 if (host->flags & SDHCI_USE_DMA) {
1530 if (host->ops->enable_dma)
1531 host->ops->enable_dma(host);
1532 }
d129bceb 1533
b8c86fc5
PO		 1534 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1535 mmc_hostname(host->mmc), host);
df1c4b7b
PO		 1536 if (ret)
1537 return ret;
d129bceb 1538
b8c86fc5
PO		 1539 sdhci_init(host);
1540 mmiowb();
1541
1542 ret = mmc_resume_host(host->mmc);
1543 if (ret)
1544 return ret;
d129bceb 1545
7260cf5e
AV		 1546 sdhci_enable_card_detection(host);
1547
d129bceb
PO		 1548 return 0;
1549}
1550
b8c86fc5 1551EXPORT_SYMBOL_GPL(sdhci_resume_host);
d129bceb
PO		 1552
1553#endif /* CONFIG_PM */
1554
1555/*****************************************************************************\
1556 * *
b8c86fc5 1557 * Device allocation/registration *
d129bceb
PO		 1558 * *
1559\*****************************************************************************/
1560
b8c86fc5
PO		 1561struct sdhci_host *sdhci_alloc_host(struct device *dev,
1562 size_t priv_size)
d129bceb 1563{
d129bceb
PO		 1564 struct mmc_host *mmc;
1565 struct sdhci_host *host;
1566
b8c86fc5 1567 WARN_ON(dev == NULL);
d129bceb 1568
b8c86fc5 1569 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
d129bceb 1570 if (!mmc)
b8c86fc5 1571 return ERR_PTR(-ENOMEM);
d129bceb
PO		 1572
1573 host = mmc_priv(mmc);
1574 host->mmc = mmc;
1575
b8c86fc5
PO		 1576 return host;
1577}
8a4da143 1578
b8c86fc5 1579EXPORT_SYMBOL_GPL(sdhci_alloc_host);
d129bceb 1580
b8c86fc5
PO		 1581int sdhci_add_host(struct sdhci_host *host)
1582{
1583 struct mmc_host *mmc;
1584 unsigned int caps;
b8c86fc5 1585 int ret;
d129bceb 1586
b8c86fc5
PO		 1587 WARN_ON(host == NULL);
1588 if (host == NULL)
1589 return -EINVAL;
d129bceb 1590
b8c86fc5 1591 mmc = host->mmc;
d129bceb 1592
b8c86fc5
PO		 1593 if (debug_quirks)
1594 host->quirks = debug_quirks;
d129bceb 1595
d96649ed
PO		 1596 sdhci_reset(host, SDHCI_RESET_ALL);
1597
4e4141a5 1598 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2134a922
PO		 1599 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1600 >> SDHCI_SPEC_VER_SHIFT;
1601 if (host->version > SDHCI_SPEC_200) {
4a965505 1602 printk(KERN_ERR "%s: Unknown controller version (%d). "
b69c9058 1603 "You may experience problems.\n", mmc_hostname(mmc),
2134a922 1604 host->version);
4a965505
PO		 1605 }
1606
4e4141a5 1607 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
d129bceb 1608
b8c86fc5 1609 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
98608076 1610 host->flags |= SDHCI_USE_DMA;
67435274
PO		 1611 else if (!(caps & SDHCI_CAN_DO_DMA))
1612 DBG("Controller doesn't have DMA capability\n");
1613 else
d129bceb
PO		 1614 host->flags |= SDHCI_USE_DMA;
1615
b8c86fc5 1616 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
7c168e3d 1617 (host->flags & SDHCI_USE_DMA)) {
cee687ce 1618 DBG("Disabling DMA as it is marked broken\n");
7c168e3d
FT		 1619 host->flags &= ~SDHCI_USE_DMA;
1620 }
1621
2134a922
PO		 1622 if (host->flags & SDHCI_USE_DMA) {
1623 if ((host->version >= SDHCI_SPEC_200) &&
1624 (caps & SDHCI_CAN_DO_ADMA2))
1625 host->flags |= SDHCI_USE_ADMA;
1626 }
1627
1628 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1629 (host->flags & SDHCI_USE_ADMA)) {
1630 DBG("Disabling ADMA as it is marked broken\n");
1631 host->flags &= ~SDHCI_USE_ADMA;
1632 }
1633
d129bceb 1634 if (host->flags & SDHCI_USE_DMA) {
b8c86fc5
PO		 1635 if (host->ops->enable_dma) {
1636 if (host->ops->enable_dma(host)) {
1637 printk(KERN_WARNING "%s: No suitable DMA "
1638 "available. Falling back to PIO.\n",
1639 mmc_hostname(mmc));
2134a922 1640 host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA);
b8c86fc5 1641 }
d129bceb
PO		 1642 }
1643 }
1644
2134a922
PO		 1645 if (host->flags & SDHCI_USE_ADMA) {
1646 /*
1647 * We need to allocate descriptors for all sg entries
1648 * (128) and potentially one alignment transfer for
1649 * each of those entries.
1650 */
1651 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1652 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1653 if (!host->adma_desc || !host->align_buffer) {
1654 kfree(host->adma_desc);
1655 kfree(host->align_buffer);
1656 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1657 "buffers. Falling back to standard DMA.\n",
1658 mmc_hostname(mmc));
1659 host->flags &= ~SDHCI_USE_ADMA;
1660 }
1661 }
1662
7659150c
PO		 1663 /*
1664 * If we use DMA, then it's up to the caller to set the DMA
1665 * mask, but PIO does not need the hw shim so we set a new
1666 * mask here in that case.
1667 */
1668 if (!(host->flags & SDHCI_USE_DMA)) {
1669 host->dma_mask = DMA_BIT_MASK(64);
1670 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1671 }
d129bceb 1672
8ef1a143
PO		 1673 host->max_clk =
1674 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1675 if (host->max_clk == 0) {
1676 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
b69c9058 1677 "frequency.\n", mmc_hostname(mmc));
b8c86fc5 1678 return -ENODEV;
8ef1a143 1679 }
d129bceb
PO		 1680 host->max_clk *= 1000000;
1681
1c8cde92
PO		 1682 host->timeout_clk =
1683 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1684 if (host->timeout_clk == 0) {
1685 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
b69c9058 1686 "frequency.\n", mmc_hostname(mmc));
b8c86fc5 1687 return -ENODEV;
1c8cde92
PO		 1688 }
1689 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1690 host->timeout_clk *= 1000;
d129bceb
PO		 1691
1692 /*
1693 * Set host parameters.
1694 */
1695 mmc->ops = &sdhci_ops;
1696 mmc->f_min = host->max_clk / 256;
1697 mmc->f_max = host->max_clk;
c9b74c5b 1698 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
d129bceb 1699
86a6a874 1700 if (caps & SDHCI_CAN_DO_HISPD)
cd9277c0
PO		 1701 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1702
68d1fb7e
AV		 1703 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1704 mmc->caps |= MMC_CAP_NEEDS_POLL;
1705
146ad66e
PO		 1706 mmc->ocr_avail = 0;
1707 if (caps & SDHCI_CAN_VDD_330)
1708 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
c70840e8 1709 if (caps & SDHCI_CAN_VDD_300)
146ad66e 1710 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
c70840e8 1711 if (caps & SDHCI_CAN_VDD_180)
55556da0 1712 mmc->ocr_avail |= MMC_VDD_165_195;
146ad66e
PO		 1713
1714 if (mmc->ocr_avail == 0) {
1715 printk(KERN_ERR "%s: Hardware doesn't report any "
b69c9058 1716 "support voltages.\n", mmc_hostname(mmc));
b8c86fc5 1717 return -ENODEV;
146ad66e
PO		 1718 }
1719
d129bceb
PO		 1720 spin_lock_init(&host->lock);
1721
1722 /*
2134a922
PO		 1723 * Maximum number of segments. Depends on if the hardware
1724 * can do scatter/gather or not.
d129bceb 1725 */
2134a922
PO		 1726 if (host->flags & SDHCI_USE_ADMA)
1727 mmc->max_hw_segs = 128;
1728 else if (host->flags & SDHCI_USE_DMA)
d129bceb 1729 mmc->max_hw_segs = 1;
2134a922
PO		 1730 else /* PIO */
1731 mmc->max_hw_segs = 128;
1732 mmc->max_phys_segs = 128;
d129bceb
PO		 1733
1734 /*
bab76961 1735 * Maximum number of sectors in one transfer. Limited by DMA boundary
55db890a 1736 * size (512KiB).
d129bceb 1737 */
55db890a 1738 mmc->max_req_size = 524288;
d129bceb
PO		 1739
1740 /*
1741 * Maximum segment size. Could be one segment with the maximum number
2134a922
PO		 1742 * of bytes. When doing hardware scatter/gather, each entry cannot
1743 * be larger than 64 KiB though.
d129bceb 1744 */
2134a922
PO		 1745 if (host->flags & SDHCI_USE_ADMA)
1746 mmc->max_seg_size = 65536;
1747 else
1748 mmc->max_seg_size = mmc->max_req_size;
d129bceb 1749
fe4a3c7a
PO		 1750 /*
1751 * Maximum block size. This varies from controller to controller and
1752 * is specified in the capabilities register.
1753 */
1754 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1755 if (mmc->max_blk_size >= 3) {
b69c9058
PO		 1756 printk(KERN_WARNING "%s: Invalid maximum block size, "
1757 "assuming 512 bytes\n", mmc_hostname(mmc));
03f8590d
DV		 1758 mmc->max_blk_size = 512;
1759 } else
1760 mmc->max_blk_size = 512 << mmc->max_blk_size;
fe4a3c7a 1761
55db890a
PO		 1762 /*
1763 * Maximum block count.
1764 */
1765 mmc->max_blk_count = 65535;
1766
d129bceb
PO		 1767 /*
1768 * Init tasklets.
1769 */
1770 tasklet_init(&host->card_tasklet,
1771 sdhci_tasklet_card, (unsigned long)host);
1772 tasklet_init(&host->finish_tasklet,
1773 sdhci_tasklet_finish, (unsigned long)host);
1774
e4cad1b5 1775 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
d129bceb 1776
dace1453 1777 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
b69c9058 1778 mmc_hostname(mmc), host);
d129bceb 1779 if (ret)
8ef1a143 1780 goto untasklet;
d129bceb
PO		 1781
1782 sdhci_init(host);
1783
1784#ifdef CONFIG_MMC_DEBUG
1785 sdhci_dumpregs(host);
1786#endif
1787
f9134319 1788#ifdef SDHCI_USE_LEDS_CLASS
5dbace0c
HS		 1789 snprintf(host->led_name, sizeof(host->led_name),
1790 "%s::", mmc_hostname(mmc));
1791 host->led.name = host->led_name;
2f730fec
PO		 1792 host->led.brightness = LED_OFF;
1793 host->led.default_trigger = mmc_hostname(mmc);
1794 host->led.brightness_set = sdhci_led_control;
1795
b8c86fc5 1796 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2f730fec
PO		 1797 if (ret)
1798 goto reset;
1799#endif
1800
5f25a66f
PO		 1801 mmiowb();
1802
d129bceb
PO		 1803 mmc_add_host(mmc);
1804
2134a922 1805 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n",
d1b26863 1806 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2134a922 1807 (host->flags & SDHCI_USE_ADMA)?"A":"",
d129bceb
PO		 1808 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1809
7260cf5e
AV		 1810 sdhci_enable_card_detection(host);
1811
d129bceb
PO		 1812 return 0;
1813
f9134319 1814#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 1815reset:
1816 sdhci_reset(host, SDHCI_RESET_ALL);
1817 free_irq(host->irq, host);
1818#endif
8ef1a143 1819untasklet:
d129bceb
PO		 1820 tasklet_kill(&host->card_tasklet);
1821 tasklet_kill(&host->finish_tasklet);
d129bceb
PO		 1822
1823 return ret;
1824}
1825
b8c86fc5 1826EXPORT_SYMBOL_GPL(sdhci_add_host);
d129bceb 1827
1e72859e 1828void sdhci_remove_host(struct sdhci_host *host, int dead)
b8c86fc5 1829{
1e72859e
PO		 1830 unsigned long flags;
1831
1832 if (dead) {
1833 spin_lock_irqsave(&host->lock, flags);
1834
1835 host->flags |= SDHCI_DEVICE_DEAD;
1836
1837 if (host->mrq) {
1838 printk(KERN_ERR "%s: Controller removed during "
1839 " transfer!\n", mmc_hostname(host->mmc));
1840
1841 host->mrq->cmd->error = -ENOMEDIUM;
1842 tasklet_schedule(&host->finish_tasklet);
1843 }
1844
1845 spin_unlock_irqrestore(&host->lock, flags);
1846 }
1847
7260cf5e
AV		 1848 sdhci_disable_card_detection(host);
1849
b8c86fc5 1850 mmc_remove_host(host->mmc);
d129bceb 1851
f9134319 1852#ifdef SDHCI_USE_LEDS_CLASS
2f730fec
PO		 1853 led_classdev_unregister(&host->led);
1854#endif
1855
1e72859e
PO		 1856 if (!dead)
1857 sdhci_reset(host, SDHCI_RESET_ALL);
d129bceb
PO		 1858
1859 free_irq(host->irq, host);
1860
1861 del_timer_sync(&host->timer);
1862
1863 tasklet_kill(&host->card_tasklet);
1864 tasklet_kill(&host->finish_tasklet);
2134a922
PO		 1865
1866 kfree(host->adma_desc);
1867 kfree(host->align_buffer);
1868
1869 host->adma_desc = NULL;
1870 host->align_buffer = NULL;
d129bceb
PO		 1871}
1872
b8c86fc5 1873EXPORT_SYMBOL_GPL(sdhci_remove_host);
d129bceb 1874
b8c86fc5 1875void sdhci_free_host(struct sdhci_host *host)
d129bceb 1876{
b8c86fc5 1877 mmc_free_host(host->mmc);
d129bceb
PO		 1878}
1879
b8c86fc5 1880EXPORT_SYMBOL_GPL(sdhci_free_host);
d129bceb
PO		 1881
1882/*****************************************************************************\
1883 * *
1884 * Driver init/exit *
1885 * *
1886\*****************************************************************************/
1887
1888static int __init sdhci_drv_init(void)
1889{
1890 printk(KERN_INFO DRIVER_NAME
52fbf9c9 1891 ": Secure Digital Host Controller Interface driver\n");
d129bceb
PO		 1892 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1893
b8c86fc5 1894 return 0;
d129bceb
PO		 1895}
1896
1897static void __exit sdhci_drv_exit(void)
1898{
d129bceb
PO		 1899}
1900
1901module_init(sdhci_drv_init);
1902module_exit(sdhci_drv_exit);
1903
df673b22 1904module_param(debug_quirks, uint, 0444);
67435274 1905
d129bceb 1906MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
b8c86fc5 1907MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
d129bceb 1908MODULE_LICENSE("GPL");
67435274 1909
df673b22 1910MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
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