[net-next-2.6.git] / drivers / mmc / host / pxamci.c

/*
 *  linux/drivers/mmc/pxa.c - PXA MMCI driver
 *
 *  Copyright (C) 2003 Russell King, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This hardware is really sick:
 *   - No way to clear interrupts.
 *   - Have to turn off the clock whenever we touch the device.
 *   - Doesn't tell you how many data blocks were transferred.
 *  Yuck!
 *
 *	1 and 3 byte data transfers not supported
 *	max block length up to 1023
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/mmc/host.h>

#include <asm/dma.h>
#include <asm/io.h>
#include <asm/scatterlist.h>
#include <asm/sizes.h>

#include <asm/arch/pxa-regs.h>
#include <asm/arch/mmc.h>

#include "pxamci.h"

#define DRIVER_NAME	"pxa2xx-mci"

#define NR_SG	1

struct pxamci_host {
	struct mmc_host		*mmc;
	spinlock_t		lock;
	struct resource		*res;
	void __iomem		*base;
	int			irq;
	int			dma;
	unsigned int		clkrt;
	unsigned int		cmdat;
	unsigned int		imask;
	unsigned int		power_mode;
	struct pxamci_platform_data *pdata;

	struct mmc_request	*mrq;
	struct mmc_command	*cmd;
	struct mmc_data		*data;

	dma_addr_t		sg_dma;
	struct pxa_dma_desc	*sg_cpu;
	unsigned int		dma_len;

	unsigned int		dma_dir;
};

static void pxamci_stop_clock(struct pxamci_host *host)
{
	if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
		unsigned long timeout = 10000;
		unsigned int v;

		writel(STOP_CLOCK, host->base + MMC_STRPCL);

		do {
			v = readl(host->base + MMC_STAT);
			if (!(v & STAT_CLK_EN))
				break;
			udelay(1);
		} while (timeout--);

		if (v & STAT_CLK_EN)
			dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
	}
}

static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
{
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);
	host->imask &= ~mask;
	writel(host->imask, host->base + MMC_I_MASK);
	spin_unlock_irqrestore(&host->lock, flags);
}

static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
{
	unsigned long flags;

	spin_lock_irqsave(&host->lock, flags);
	host->imask |= mask;
	writel(host->imask, host->base + MMC_I_MASK);
	spin_unlock_irqrestore(&host->lock, flags);
}

static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
{
	unsigned int nob = data->blocks;
	unsigned long long clks;
	unsigned int timeout;
	u32 dcmd;
	int i;

	host->data = data;

	if (data->flags & MMC_DATA_STREAM)
		nob = 0xffff;

	writel(nob, host->base + MMC_NOB);
	writel(data->blksz, host->base + MMC_BLKLEN);

	clks = (unsigned long long)data->timeout_ns * CLOCKRATE;
	do_div(clks, 1000000000UL);
	timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
	writel((timeout + 255) / 256, host->base + MMC_RDTO);

	if (data->flags & MMC_DATA_READ) {
		host->dma_dir = DMA_FROM_DEVICE;
		dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
		DRCMRTXMMC = 0;
		DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
	} else {
		host->dma_dir = DMA_TO_DEVICE;
		dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
		DRCMRRXMMC = 0;
		DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
	}

	dcmd |= DCMD_BURST32 | DCMD_WIDTH1;

	host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
				   host->dma_dir);

	for (i = 0; i < host->dma_len; i++) {
		if (data->flags & MMC_DATA_READ) {
			host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
			host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
		} else {
			host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
			host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
		}
		host->sg_cpu[i].dcmd = dcmd | sg_dma_len(&data->sg[i]);
		host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
					sizeof(struct pxa_dma_desc);
	}
	host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
	wmb();

	DDADR(host->dma) = host->sg_dma;
	DCSR(host->dma) = DCSR_RUN;
}

static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
{
	WARN_ON(host->cmd != NULL);
	host->cmd = cmd;

	if (cmd->flags & MMC_RSP_BUSY)
		cmdat |= CMDAT_BUSY;

#define RSP_TYPE(x)	((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
	switch (RSP_TYPE(mmc_resp_type(cmd))) {
	case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
		cmdat |= CMDAT_RESP_SHORT;
		break;
	case RSP_TYPE(MMC_RSP_R3):
		cmdat |= CMDAT_RESP_R3;
		break;
	case RSP_TYPE(MMC_RSP_R2):
		cmdat |= CMDAT_RESP_R2;
		break;
	default:
		break;
	}

	writel(cmd->opcode, host->base + MMC_CMD);
	writel(cmd->arg >> 16, host->base + MMC_ARGH);
	writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
	writel(cmdat, host->base + MMC_CMDAT);
	writel(host->clkrt, host->base + MMC_CLKRT);

	writel(START_CLOCK, host->base + MMC_STRPCL);

	pxamci_enable_irq(host, END_CMD_RES);
}

static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
{
	host->mrq = NULL;
	host->cmd = NULL;
	host->data = NULL;
	mmc_request_done(host->mmc, mrq);
}

static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
{
	struct mmc_command *cmd = host->cmd;
	int i;
	u32 v;

	if (!cmd)
		return 0;

	host->cmd = NULL;

	/*
	 * Did I mention this is Sick.  We always need to
	 * discard the upper 8 bits of the first 16-bit word.
	 */
	v = readl(host->base + MMC_RES) & 0xffff;
	for (i = 0; i < 4; i++) {
		u32 w1 = readl(host->base + MMC_RES) & 0xffff;
		u32 w2 = readl(host->base + MMC_RES) & 0xffff;
		cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
		v = w2;
	}

	if (stat & STAT_TIME_OUT_RESPONSE) {
		cmd->error = MMC_ERR_TIMEOUT;
	} else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
#ifdef CONFIG_PXA27x
		/*
		 * workaround for erratum #42:
		 * Intel PXA27x Family Processor Specification Update Rev 001
		 */
		if (cmd->opcode == MMC_ALL_SEND_CID ||
		    cmd->opcode == MMC_SEND_CSD ||
		    cmd->opcode == MMC_SEND_CID) {
			/* a bogus CRC error can appear if the msb of
			   the 15 byte response is a one */
			if ((cmd->resp[0] & 0x80000000) == 0)
				cmd->error = MMC_ERR_BADCRC;
		} else {
			pr_debug("ignoring CRC from command %d - *risky*\n",cmd->opcode);
		}
#else
		cmd->error = MMC_ERR_BADCRC;
#endif
	}

	pxamci_disable_irq(host, END_CMD_RES);
	if (host->data && cmd->error == MMC_ERR_NONE) {
		pxamci_enable_irq(host, DATA_TRAN_DONE);
	} else {
		pxamci_finish_request(host, host->mrq);
	}

	return 1;
}

static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
{
	struct mmc_data *data = host->data;

	if (!data)
		return 0;

	DCSR(host->dma) = 0;
	dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
		     host->dma_dir);

	if (stat & STAT_READ_TIME_OUT)
		data->error = MMC_ERR_TIMEOUT;
	else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
		data->error = MMC_ERR_BADCRC;

	/*
	 * There appears to be a hardware design bug here.  There seems to
	 * be no way to find out how much data was transferred to the card.
	 * This means that if there was an error on any block, we mark all
	 * data blocks as being in error.
	 */
	if (data->error == MMC_ERR_NONE)
		data->bytes_xfered = data->blocks * data->blksz;
	else
		data->bytes_xfered = 0;

	pxamci_disable_irq(host, DATA_TRAN_DONE);

	host->data = NULL;
	if (host->mrq->stop) {
		pxamci_stop_clock(host);
		pxamci_start_cmd(host, host->mrq->stop, 0);
	} else {
		pxamci_finish_request(host, host->mrq);
	}

	return 1;
}

static irqreturn_t pxamci_irq(int irq, void *devid)
{
	struct pxamci_host *host = devid;
	unsigned int ireg;
	int handled = 0;

	ireg = readl(host->base + MMC_I_REG);

	if (ireg) {
		unsigned stat = readl(host->base + MMC_STAT);

		pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);

		if (ireg & END_CMD_RES)
			handled |= pxamci_cmd_done(host, stat);
		if (ireg & DATA_TRAN_DONE)
			handled |= pxamci_data_done(host, stat);
	}

	return IRQ_RETVAL(handled);
}

static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
	struct pxamci_host *host = mmc_priv(mmc);
	unsigned int cmdat;

	WARN_ON(host->mrq != NULL);

	host->mrq = mrq;

	pxamci_stop_clock(host);

	cmdat = host->cmdat;
	host->cmdat &= ~CMDAT_INIT;

	if (mrq->data) {
		pxamci_setup_data(host, mrq->data);

		cmdat &= ~CMDAT_BUSY;
		cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
		if (mrq->data->flags & MMC_DATA_WRITE)
			cmdat |= CMDAT_WRITE;

		if (mrq->data->flags & MMC_DATA_STREAM)
			cmdat |= CMDAT_STREAM;
	}

	pxamci_start_cmd(host, mrq->cmd, cmdat);
}

static int pxamci_get_ro(struct mmc_host *mmc)
{
	struct pxamci_host *host = mmc_priv(mmc);

	if (host->pdata && host->pdata->get_ro)
		return host->pdata->get_ro(mmc_dev(mmc));
	/* Host doesn't support read only detection so assume writeable */
	return 0;
}

static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct pxamci_host *host = mmc_priv(mmc);

	if (ios->clock) {
		unsigned int clk = CLOCKRATE / ios->clock;
		if (CLOCKRATE / clk > ios->clock)
			clk <<= 1;
		host->clkrt = fls(clk) - 1;
		pxa_set_cken(CKEN_MMC, 1);

		/*
		 * we write clkrt on the next command
		 */
	} else {
		pxamci_stop_clock(host);
		pxa_set_cken(CKEN_MMC, 0);
	}

	if (host->power_mode != ios->power_mode) {
		host->power_mode = ios->power_mode;

		if (host->pdata && host->pdata->setpower)
			host->pdata->setpower(mmc_dev(mmc), ios->vdd);

		if (ios->power_mode == MMC_POWER_ON)
			host->cmdat |= CMDAT_INIT;
	}

	pr_debug("PXAMCI: clkrt = %x cmdat = %x\n",
		 host->clkrt, host->cmdat);
}

static const struct mmc_host_ops pxamci_ops = {
	.request	= pxamci_request,
	.get_ro		= pxamci_get_ro,
	.set_ios	= pxamci_set_ios,
};

static void pxamci_dma_irq(int dma, void *devid)
{
	printk(KERN_ERR "DMA%d: IRQ???\n", dma);
	DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
}

static irqreturn_t pxamci_detect_irq(int irq, void *devid)
{
	struct pxamci_host *host = mmc_priv(devid);

	mmc_detect_change(devid, host->pdata->detect_delay);
	return IRQ_HANDLED;
}

static int pxamci_probe(struct platform_device *pdev)
{
	struct mmc_host *mmc;
	struct pxamci_host *host = NULL;
	struct resource *r;
	int ret, irq;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	irq = platform_get_irq(pdev, 0);
	if (!r || irq < 0)
		return -ENXIO;

	r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
	if (!r)
		return -EBUSY;

	mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
	if (!mmc) {
		ret = -ENOMEM;
		goto out;
	}

	mmc->ops = &pxamci_ops;
	mmc->f_min = CLOCKRATE_MIN;
	mmc->f_max = CLOCKRATE_MAX;

	/*
	 * We can do SG-DMA, but we don't because we never know how much
	 * data we successfully wrote to the card.
	 */
	mmc->max_phys_segs = NR_SG;

	/*
	 * Our hardware DMA can handle a maximum of one page per SG entry.
	 */
	mmc->max_seg_size = PAGE_SIZE;

	/*
	 * Block length register is 10 bits.
	 */
	mmc->max_blk_size = 1023;

	/*
	 * Block count register is 16 bits.
	 */
	mmc->max_blk_count = 65535;

	host = mmc_priv(mmc);
	host->mmc = mmc;
	host->dma = -1;
	host->pdata = pdev->dev.platform_data;
	mmc->ocr_avail = host->pdata ?
			 host->pdata->ocr_mask :
			 MMC_VDD_32_33|MMC_VDD_33_34;

	host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
	if (!host->sg_cpu) {
		ret = -ENOMEM;
		goto out;
	}

	spin_lock_init(&host->lock);
	host->res = r;
	host->irq = irq;
	host->imask = MMC_I_MASK_ALL;

	host->base = ioremap(r->start, SZ_4K);
	if (!host->base) {
		ret = -ENOMEM;
		goto out;
	}

	/*
	 * Ensure that the host controller is shut down, and setup
	 * with our defaults.
	 */
	pxamci_stop_clock(host);
	writel(0, host->base + MMC_SPI);
	writel(64, host->base + MMC_RESTO);
	writel(host->imask, host->base + MMC_I_MASK);

	host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
				    pxamci_dma_irq, host);
	if (host->dma < 0) {
		ret = -EBUSY;
		goto out;
	}

	ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
	if (ret)
		goto out;

	platform_set_drvdata(pdev, mmc);

	if (host->pdata && host->pdata->init)
		host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);

	mmc_add_host(mmc);

	return 0;

 out:
	if (host) {
		if (host->dma >= 0)
			pxa_free_dma(host->dma);
		if (host->base)
			iounmap(host->base);
		if (host->sg_cpu)
			dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
	}
	if (mmc)
		mmc_free_host(mmc);
	release_resource(r);
	return ret;
}

static int pxamci_remove(struct platform_device *pdev)
{
	struct mmc_host *mmc = platform_get_drvdata(pdev);

	platform_set_drvdata(pdev, NULL);

	if (mmc) {
		struct pxamci_host *host = mmc_priv(mmc);

		if (host->pdata && host->pdata->exit)
			host->pdata->exit(&pdev->dev, mmc);

		mmc_remove_host(mmc);

		pxamci_stop_clock(host);
		writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
		       END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
		       host->base + MMC_I_MASK);

		DRCMRRXMMC = 0;
		DRCMRTXMMC = 0;

		free_irq(host->irq, host);
		pxa_free_dma(host->dma);
		iounmap(host->base);
		dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);

		release_resource(host->res);

		mmc_free_host(mmc);
	}
	return 0;
}

#ifdef CONFIG_PM
static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
{
	struct mmc_host *mmc = platform_get_drvdata(dev);
	int ret = 0;

	if (mmc)
		ret = mmc_suspend_host(mmc, state);

	return ret;
}

static int pxamci_resume(struct platform_device *dev)
{
	struct mmc_host *mmc = platform_get_drvdata(dev);
	int ret = 0;

	if (mmc)
		ret = mmc_resume_host(mmc);

	return ret;
}
#else
#define pxamci_suspend	NULL
#define pxamci_resume	NULL
#endif

static struct platform_driver pxamci_driver = {
	.probe		= pxamci_probe,
	.remove		= pxamci_remove,
	.suspend	= pxamci_suspend,
	.resume		= pxamci_resume,
	.driver		= {
		.name	= DRIVER_NAME,
	},
};

static int __init pxamci_init(void)
{
	return platform_driver_register(&pxamci_driver);
}

static void __exit pxamci_exit(void)
{
	platform_driver_unregister(&pxamci_driver);
}

module_init(pxamci_init);
module_exit(pxamci_exit);

MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/drivers/mmc/pxa.c - PXA MMCI driver
	3	*
	4	* Copyright (C) 2003 Russell King, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This hardware is really sick:
	11	* - No way to clear interrupts.
	12	* - Have to turn off the clock whenever we touch the device.
	13	* - Doesn't tell you how many data blocks were transferred.
	14	* Yuck!
	15	*
	16	* 1 and 3 byte data transfers not supported
	17	* max block length up to 1023
	18	*/
1da177e4 LT	19	#include <linux/module.h>
	20	#include <linux/init.h>
	21	#include <linux/ioport.h>
d052d1be	22	#include <linux/platform_device.h>
1da177e4 LT	23	#include <linux/delay.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/dma-mapping.h>
	26	#include <linux/mmc/host.h>
1da177e4 LT	27
	28	#include <asm/dma.h>
	29	#include <asm/io.h>
1da177e4 LT	30	#include <asm/scatterlist.h>
	31	#include <asm/sizes.h>
	32
	33	#include <asm/arch/pxa-regs.h>
	34	#include <asm/arch/mmc.h>
	35
	36	#include "pxamci.h"
	37
1da177e4 LT	38	#define DRIVER_NAME "pxa2xx-mci"
	39
	40	#define NR_SG 1
	41
	42	struct pxamci_host {
	43	struct mmc_host *mmc;
	44	spinlock_t lock;
	45	struct resource *res;
	46	void __iomem *base;
	47	int irq;
	48	int dma;
	49	unsigned int clkrt;
	50	unsigned int cmdat;
	51	unsigned int imask;
	52	unsigned int power_mode;
	53	struct pxamci_platform_data *pdata;
	54
	55	struct mmc_request *mrq;
	56	struct mmc_command *cmd;
	57	struct mmc_data *data;
	58
	59	dma_addr_t sg_dma;
	60	struct pxa_dma_desc *sg_cpu;
	61	unsigned int dma_len;
	62
	63	unsigned int dma_dir;
	64	};
	65
1da177e4 LT	66	static void pxamci_stop_clock(struct pxamci_host *host)
	67	{
	68	if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
	69	unsigned long timeout = 10000;
	70	unsigned int v;
	71
	72	writel(STOP_CLOCK, host->base + MMC_STRPCL);
	73
	74	do {
	75	v = readl(host->base + MMC_STAT);
	76	if (!(v & STAT_CLK_EN))
	77	break;
	78	udelay(1);
	79	} while (timeout--);
	80
	81	if (v & STAT_CLK_EN)
	82	dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
	83	}
	84	}
	85
	86	static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
	87	{
	88	unsigned long flags;
	89
	90	spin_lock_irqsave(&host->lock, flags);
	91	host->imask &= ~mask;
	92	writel(host->imask, host->base + MMC_I_MASK);
	93	spin_unlock_irqrestore(&host->lock, flags);
	94	}
	95
	96	static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
	97	{
	98	unsigned long flags;
	99
	100	spin_lock_irqsave(&host->lock, flags);
	101	host->imask \|= mask;
	102	writel(host->imask, host->base + MMC_I_MASK);
	103	spin_unlock_irqrestore(&host->lock, flags);
	104	}
	105
	106	static void pxamci_setup_data(struct pxamci_host host, struct mmc_data data)
	107	{
	108	unsigned int nob = data->blocks;
3d63abe5	109	unsigned long long clks;
1da177e4 LT	110	unsigned int timeout;
	111	u32 dcmd;
	112	int i;
	113
	114	host->data = data;
	115
	116	if (data->flags & MMC_DATA_STREAM)
	117	nob = 0xffff;
	118
	119	writel(nob, host->base + MMC_NOB);
2c171bf1	120	writel(data->blksz, host->base + MMC_BLKLEN);
1da177e4	121
3d63abe5 RK	122	clks = (unsigned long long)data->timeout_ns * CLOCKRATE;
	123	do_div(clks, 1000000000UL);
	124	timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
1da177e4 LT	125	writel((timeout + 255) / 256, host->base + MMC_RDTO);
	126
	127	if (data->flags & MMC_DATA_READ) {
	128	host->dma_dir = DMA_FROM_DEVICE;
	129	dcmd = DCMD_INCTRGADDR \| DCMD_FLOWTRG;
	130	DRCMRTXMMC = 0;
	131	DRCMRRXMMC = host->dma \| DRCMR_MAPVLD;
	132	} else {
	133	host->dma_dir = DMA_TO_DEVICE;
	134	dcmd = DCMD_INCSRCADDR \| DCMD_FLOWSRC;
	135	DRCMRRXMMC = 0;
	136	DRCMRTXMMC = host->dma \| DRCMR_MAPVLD;
	137	}
	138
	139	dcmd \|= DCMD_BURST32 \| DCMD_WIDTH1;
	140
	141	host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
	142	host->dma_dir);
	143
	144	for (i = 0; i < host->dma_len; i++) {
	145	if (data->flags & MMC_DATA_READ) {
	146	host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
	147	host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
	148	} else {
	149	host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
	150	host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
	151	}
	152	host->sg_cpu[i].dcmd = dcmd \| sg_dma_len(&data->sg[i]);
	153	host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
	154	sizeof(struct pxa_dma_desc);
	155	}
	156	host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
	157	wmb();
	158
	159	DDADR(host->dma) = host->sg_dma;
	160	DCSR(host->dma) = DCSR_RUN;
	161	}
	162
	163	static void pxamci_start_cmd(struct pxamci_host host, struct mmc_command cmd, unsigned int cmdat)
	164	{
	165	WARN_ON(host->cmd != NULL);
	166	host->cmd = cmd;
	167
	168	if (cmd->flags & MMC_RSP_BUSY)
	169	cmdat \|= CMDAT_BUSY;
	170
e9225176 RK	171	#define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY\|MMC_RSP_OPCODE))
e9225176 RK	172	switch (RSP_TYPE(mmc_resp_type(cmd))) {
6f949909	173	case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */
1da177e4 LT	174	cmdat \|= CMDAT_RESP_SHORT;
1da177e4 LT	175	break;
e9225176	176	case RSP_TYPE(MMC_RSP_R3):
1da177e4 LT	177	cmdat \|= CMDAT_RESP_R3;
1da177e4 LT	178	break;
e9225176	179	case RSP_TYPE(MMC_RSP_R2):
1da177e4 LT	180	cmdat \|= CMDAT_RESP_R2;
	181	break;
	182	default:
	183	break;
	184	}
	185
	186	writel(cmd->opcode, host->base + MMC_CMD);
	187	writel(cmd->arg >> 16, host->base + MMC_ARGH);
	188	writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
	189	writel(cmdat, host->base + MMC_CMDAT);
	190	writel(host->clkrt, host->base + MMC_CLKRT);
	191
	192	writel(START_CLOCK, host->base + MMC_STRPCL);
	193
	194	pxamci_enable_irq(host, END_CMD_RES);
	195	}
	196
	197	static void pxamci_finish_request(struct pxamci_host host, struct mmc_request mrq)
	198	{
1da177e4 LT	199	host->mrq = NULL;
	200	host->cmd = NULL;
	201	host->data = NULL;
	202	mmc_request_done(host->mmc, mrq);
	203	}
	204
	205	static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
	206	{
	207	struct mmc_command *cmd = host->cmd;
	208	int i;
	209	u32 v;
	210
	211	if (!cmd)
	212	return 0;
	213
	214	host->cmd = NULL;
	215
	216	/*
	217	* Did I mention this is Sick. We always need to
	218	* discard the upper 8 bits of the first 16-bit word.
	219	*/
	220	v = readl(host->base + MMC_RES) & 0xffff;
	221	for (i = 0; i < 4; i++) {
	222	u32 w1 = readl(host->base + MMC_RES) & 0xffff;
	223	u32 w2 = readl(host->base + MMC_RES) & 0xffff;
	224	cmd->resp[i] = v << 24 \| w1 << 8 \| w2 >> 8;
	225	v = w2;
	226	}
	227
	228	if (stat & STAT_TIME_OUT_RESPONSE) {
	229	cmd->error = MMC_ERR_TIMEOUT;
	230	} else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
	231	#ifdef CONFIG_PXA27x
	232	/*
	233	* workaround for erratum #42:
	234	* Intel PXA27x Family Processor Specification Update Rev 001
	235	*/
	236	if (cmd->opcode == MMC_ALL_SEND_CID \|\|
	237	cmd->opcode == MMC_SEND_CSD \|\|
	238	cmd->opcode == MMC_SEND_CID) {
	239	/* a bogus CRC error can appear if the msb of
	240	the 15 byte response is a one */
	241	if ((cmd->resp[0] & 0x80000000) == 0)
	242	cmd->error = MMC_ERR_BADCRC;
	243	} else {
c6563178	244	pr_debug("ignoring CRC from command %d - risky\n",cmd->opcode);
1da177e4 LT	245	}
	246	#else
	247	cmd->error = MMC_ERR_BADCRC;
	248	#endif
	249	}
	250
	251	pxamci_disable_irq(host, END_CMD_RES);
	252	if (host->data && cmd->error == MMC_ERR_NONE) {
	253	pxamci_enable_irq(host, DATA_TRAN_DONE);
	254	} else {
	255	pxamci_finish_request(host, host->mrq);
	256	}
	257
	258	return 1;
	259	}
	260
	261	static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
	262	{
	263	struct mmc_data *data = host->data;
	264
	265	if (!data)
	266	return 0;
	267
	268	DCSR(host->dma) = 0;
	269	dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
	270	host->dma_dir);
	271
	272	if (stat & STAT_READ_TIME_OUT)
	273	data->error = MMC_ERR_TIMEOUT;
	274	else if (stat & (STAT_CRC_READ_ERROR\|STAT_CRC_WRITE_ERROR))
	275	data->error = MMC_ERR_BADCRC;
	276
	277	/*
	278	* There appears to be a hardware design bug here. There seems to
	279	* be no way to find out how much data was transferred to the card.
	280	* This means that if there was an error on any block, we mark all
	281	* data blocks as being in error.
	282	*/
	283	if (data->error == MMC_ERR_NONE)
2c171bf1	284	data->bytes_xfered = data->blocks * data->blksz;
1da177e4 LT	285	else
	286	data->bytes_xfered = 0;
	287
	288	pxamci_disable_irq(host, DATA_TRAN_DONE);
	289
	290	host->data = NULL;
58741e8b	291	if (host->mrq->stop) {
1da177e4 LT	292	pxamci_stop_clock(host);
	293	pxamci_start_cmd(host, host->mrq->stop, 0);
	294	} else {
	295	pxamci_finish_request(host, host->mrq);
	296	}
	297
	298	return 1;
	299	}
	300
7d12e780	301	static irqreturn_t pxamci_irq(int irq, void *devid)
1da177e4 LT	302	{
	303	struct pxamci_host *host = devid;
	304	unsigned int ireg;
	305	int handled = 0;
	306
	307	ireg = readl(host->base + MMC_I_REG);
	308
1da177e4 LT	309	if (ireg) {
	310	unsigned stat = readl(host->base + MMC_STAT);
	311
d78e9079	312	pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat);
1da177e4 LT	313
	314	if (ireg & END_CMD_RES)
	315	handled \|= pxamci_cmd_done(host, stat);
	316	if (ireg & DATA_TRAN_DONE)
	317	handled \|= pxamci_data_done(host, stat);
	318	}
	319
	320	return IRQ_RETVAL(handled);
	321	}
	322
	323	static void pxamci_request(struct mmc_host mmc, struct mmc_request mrq)
	324	{
	325	struct pxamci_host *host = mmc_priv(mmc);
	326	unsigned int cmdat;
	327
	328	WARN_ON(host->mrq != NULL);
	329
	330	host->mrq = mrq;
	331
	332	pxamci_stop_clock(host);
	333
	334	cmdat = host->cmdat;
	335	host->cmdat &= ~CMDAT_INIT;
	336
	337	if (mrq->data) {
	338	pxamci_setup_data(host, mrq->data);
	339
	340	cmdat &= ~CMDAT_BUSY;
	341	cmdat \|= CMDAT_DATAEN \| CMDAT_DMAEN;
	342	if (mrq->data->flags & MMC_DATA_WRITE)
	343	cmdat \|= CMDAT_WRITE;
	344
	345	if (mrq->data->flags & MMC_DATA_STREAM)
	346	cmdat \|= CMDAT_STREAM;
	347	}
	348
	349	pxamci_start_cmd(host, mrq->cmd, cmdat);
	350	}
	351
e619524f RP	352	static int pxamci_get_ro(struct mmc_host *mmc)
	353	{
	354	struct pxamci_host *host = mmc_priv(mmc);
	355
	356	if (host->pdata && host->pdata->get_ro)
9e86619b	357	return host->pdata->get_ro(mmc_dev(mmc));
e619524f RP	358	/* Host doesn't support read only detection so assume writeable */
	359	return 0;
	360	}
	361
1da177e4 LT	362	static void pxamci_set_ios(struct mmc_host mmc, struct mmc_ios ios)
	363	{
	364	struct pxamci_host *host = mmc_priv(mmc);
	365
1da177e4 LT	366	if (ios->clock) {
	367	unsigned int clk = CLOCKRATE / ios->clock;
	368	if (CLOCKRATE / clk > ios->clock)
	369	clk <<= 1;
	370	host->clkrt = fls(clk) - 1;
7053acbd	371	pxa_set_cken(CKEN_MMC, 1);
1da177e4 LT	372
	373	/*
	374	* we write clkrt on the next command
	375	*/
	376	} else {
	377	pxamci_stop_clock(host);
7053acbd	378	pxa_set_cken(CKEN_MMC, 0);
1da177e4 LT	379	}
	380
	381	if (host->power_mode != ios->power_mode) {
	382	host->power_mode = ios->power_mode;
	383
	384	if (host->pdata && host->pdata->setpower)
9e86619b	385	host->pdata->setpower(mmc_dev(mmc), ios->vdd);
1da177e4 LT	386
	387	if (ios->power_mode == MMC_POWER_ON)
	388	host->cmdat \|= CMDAT_INIT;
	389	}
	390
d78e9079	391	pr_debug("PXAMCI: clkrt = %x cmdat = %x\n",
c6563178	392	host->clkrt, host->cmdat);
1da177e4 LT	393	}
1da177e4 LT	394
ab7aefd0	395	static const struct mmc_host_ops pxamci_ops = {
1da177e4	396	.request = pxamci_request,
e619524f	397	.get_ro = pxamci_get_ro,
1da177e4 LT	398	.set_ios = pxamci_set_ios,
	399	};
	400
7d12e780	401	static void pxamci_dma_irq(int dma, void *devid)
1da177e4 LT	402	{
	403	printk(KERN_ERR "DMA%d: IRQ???\n", dma);
	404	DCSR(dma) = DCSR_STARTINTR\|DCSR_ENDINTR\|DCSR_BUSERR;
	405	}
	406
7d12e780	407	static irqreturn_t pxamci_detect_irq(int irq, void *devid)
1da177e4	408	{
c26971cb RP	409	struct pxamci_host *host = mmc_priv(devid);
	410
	411	mmc_detect_change(devid, host->pdata->detect_delay);
1da177e4 LT	412	return IRQ_HANDLED;
	413	}
	414
3ae5eaec	415	static int pxamci_probe(struct platform_device *pdev)
1da177e4	416	{
1da177e4 LT	417	struct mmc_host *mmc;
	418	struct pxamci_host *host = NULL;
	419	struct resource *r;
	420	int ret, irq;
	421
	422	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	423	irq = platform_get_irq(pdev, 0);
48944738	424	if (!r \|\| irq < 0)
1da177e4 LT	425	return -ENXIO;
	426
	427	r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
	428	if (!r)
	429	return -EBUSY;
	430
3ae5eaec	431	mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
1da177e4 LT	432	if (!mmc) {
	433	ret = -ENOMEM;
	434	goto out;
	435	}
	436
	437	mmc->ops = &pxamci_ops;
	438	mmc->f_min = CLOCKRATE_MIN;
	439	mmc->f_max = CLOCKRATE_MAX;
	440
	441	/*
	442	* We can do SG-DMA, but we don't because we never know how much
	443	* data we successfully wrote to the card.
	444	*/
	445	mmc->max_phys_segs = NR_SG;
	446
	447	/*
	448	* Our hardware DMA can handle a maximum of one page per SG entry.
	449	*/
	450	mmc->max_seg_size = PAGE_SIZE;
	451
fe4a3c7a PO	452	/*
	453	* Block length register is 10 bits.
	454	*/
	455	mmc->max_blk_size = 1023;
	456
55db890a PO	457	/*
	458	* Block count register is 16 bits.
	459	*/
	460	mmc->max_blk_count = 65535;
	461
1da177e4 LT	462	host = mmc_priv(mmc);
	463	host->mmc = mmc;
	464	host->dma = -1;
	465	host->pdata = pdev->dev.platform_data;
	466	mmc->ocr_avail = host->pdata ?
	467	host->pdata->ocr_mask :
	468	MMC_VDD_32_33\|MMC_VDD_33_34;
	469
3ae5eaec	470	host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
1da177e4 LT	471	if (!host->sg_cpu) {
	472	ret = -ENOMEM;
	473	goto out;
	474	}
	475
	476	spin_lock_init(&host->lock);
	477	host->res = r;
	478	host->irq = irq;
	479	host->imask = MMC_I_MASK_ALL;
	480
	481	host->base = ioremap(r->start, SZ_4K);
	482	if (!host->base) {
	483	ret = -ENOMEM;
	484	goto out;
	485	}
	486
	487	/*
	488	* Ensure that the host controller is shut down, and setup
	489	* with our defaults.
	490	*/
	491	pxamci_stop_clock(host);
	492	writel(0, host->base + MMC_SPI);
	493	writel(64, host->base + MMC_RESTO);
	494	writel(host->imask, host->base + MMC_I_MASK);
	495
	496	host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
	497	pxamci_dma_irq, host);
	498	if (host->dma < 0) {
	499	ret = -EBUSY;
	500	goto out;
	501	}
	502
	503	ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
	504	if (ret)
	505	goto out;
	506
3ae5eaec	507	platform_set_drvdata(pdev, mmc);
1da177e4 LT	508
1da177e4 LT	509	if (host->pdata && host->pdata->init)
3ae5eaec	510	host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
1da177e4 LT	511
	512	mmc_add_host(mmc);
	513
	514	return 0;
	515
	516	out:
	517	if (host) {
	518	if (host->dma >= 0)
	519	pxa_free_dma(host->dma);
	520	if (host->base)
	521	iounmap(host->base);
	522	if (host->sg_cpu)
3ae5eaec	523	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1da177e4 LT	524	}
	525	if (mmc)
	526	mmc_free_host(mmc);
	527	release_resource(r);
	528	return ret;
	529	}
	530
3ae5eaec	531	static int pxamci_remove(struct platform_device *pdev)
1da177e4	532	{
3ae5eaec	533	struct mmc_host *mmc = platform_get_drvdata(pdev);
1da177e4	534
3ae5eaec	535	platform_set_drvdata(pdev, NULL);
1da177e4 LT	536
	537	if (mmc) {
	538	struct pxamci_host *host = mmc_priv(mmc);
	539
	540	if (host->pdata && host->pdata->exit)
3ae5eaec	541	host->pdata->exit(&pdev->dev, mmc);
1da177e4 LT	542
	543	mmc_remove_host(mmc);
	544
	545	pxamci_stop_clock(host);
	546	writel(TXFIFO_WR_REQ\|RXFIFO_RD_REQ\|CLK_IS_OFF\|STOP_CMD\|
	547	END_CMD_RES\|PRG_DONE\|DATA_TRAN_DONE,
	548	host->base + MMC_I_MASK);
	549
	550	DRCMRRXMMC = 0;
	551	DRCMRTXMMC = 0;
	552
	553	free_irq(host->irq, host);
	554	pxa_free_dma(host->dma);
	555	iounmap(host->base);
3ae5eaec	556	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1da177e4 LT	557
	558	release_resource(host->res);
	559
	560	mmc_free_host(mmc);
	561	}
	562	return 0;
	563	}
	564
	565	#ifdef CONFIG_PM
3ae5eaec	566	static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
1da177e4	567	{
3ae5eaec	568	struct mmc_host *mmc = platform_get_drvdata(dev);
1da177e4 LT	569	int ret = 0;
1da177e4 LT	570
9480e307	571	if (mmc)
1da177e4 LT	572	ret = mmc_suspend_host(mmc, state);
	573
	574	return ret;
	575	}
	576
3ae5eaec	577	static int pxamci_resume(struct platform_device *dev)
1da177e4	578	{
3ae5eaec	579	struct mmc_host *mmc = platform_get_drvdata(dev);
1da177e4 LT	580	int ret = 0;
1da177e4 LT	581
9480e307	582	if (mmc)
1da177e4 LT	583	ret = mmc_resume_host(mmc);
	584
	585	return ret;
	586	}
	587	#else
	588	#define pxamci_suspend NULL
	589	#define pxamci_resume NULL
	590	#endif
	591
3ae5eaec	592	static struct platform_driver pxamci_driver = {
1da177e4 LT	593	.probe = pxamci_probe,
	594	.remove = pxamci_remove,
	595	.suspend = pxamci_suspend,
	596	.resume = pxamci_resume,
3ae5eaec RK	597	.driver = {
	598	.name = DRIVER_NAME,
	599	},
1da177e4 LT	600	};
	601
	602	static int __init pxamci_init(void)
	603	{
3ae5eaec	604	return platform_driver_register(&pxamci_driver);
1da177e4 LT	605	}
	606
	607	static void __exit pxamci_exit(void)
	608	{
3ae5eaec	609	platform_driver_unregister(&pxamci_driver);
1da177e4 LT	610	}
	611
	612	module_init(pxamci_init);
	613	module_exit(pxamci_exit);
	614
	615	MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
	616	MODULE_LICENSE("GPL");