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a45c6cb8 MC |
1 | /* |
2 | * drivers/mmc/host/omap_hsmmc.c | |
3 | * | |
4 | * Driver for OMAP2430/3430 MMC controller. | |
5 | * | |
6 | * Copyright (C) 2007 Texas Instruments. | |
7 | * | |
8 | * Authors: | |
9 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
10 | * Madhusudhan <madhu.cr@ti.com> | |
11 | * Mohit Jalori <mjalori@ti.com> | |
12 | * | |
13 | * This file is licensed under the terms of the GNU General Public License | |
14 | * version 2. This program is licensed "as is" without any warranty of any | |
15 | * kind, whether express or implied. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/workqueue.h> | |
25 | #include <linux/timer.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/mmc/host.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/semaphore.h> | |
30 | #include <mach/dma.h> | |
31 | #include <mach/hardware.h> | |
32 | #include <mach/board.h> | |
33 | #include <mach/mmc.h> | |
34 | #include <mach/cpu.h> | |
35 | ||
36 | /* OMAP HSMMC Host Controller Registers */ | |
37 | #define OMAP_HSMMC_SYSCONFIG 0x0010 | |
38 | #define OMAP_HSMMC_CON 0x002C | |
39 | #define OMAP_HSMMC_BLK 0x0104 | |
40 | #define OMAP_HSMMC_ARG 0x0108 | |
41 | #define OMAP_HSMMC_CMD 0x010C | |
42 | #define OMAP_HSMMC_RSP10 0x0110 | |
43 | #define OMAP_HSMMC_RSP32 0x0114 | |
44 | #define OMAP_HSMMC_RSP54 0x0118 | |
45 | #define OMAP_HSMMC_RSP76 0x011C | |
46 | #define OMAP_HSMMC_DATA 0x0120 | |
47 | #define OMAP_HSMMC_HCTL 0x0128 | |
48 | #define OMAP_HSMMC_SYSCTL 0x012C | |
49 | #define OMAP_HSMMC_STAT 0x0130 | |
50 | #define OMAP_HSMMC_IE 0x0134 | |
51 | #define OMAP_HSMMC_ISE 0x0138 | |
52 | #define OMAP_HSMMC_CAPA 0x0140 | |
53 | ||
54 | #define VS18 (1 << 26) | |
55 | #define VS30 (1 << 25) | |
56 | #define SDVS18 (0x5 << 9) | |
57 | #define SDVS30 (0x6 << 9) | |
eb250826 | 58 | #define SDVS33 (0x7 << 9) |
1b331e69 | 59 | #define SDVS_MASK 0x00000E00 |
a45c6cb8 MC |
60 | #define SDVSCLR 0xFFFFF1FF |
61 | #define SDVSDET 0x00000400 | |
62 | #define AUTOIDLE 0x1 | |
63 | #define SDBP (1 << 8) | |
64 | #define DTO 0xe | |
65 | #define ICE 0x1 | |
66 | #define ICS 0x2 | |
67 | #define CEN (1 << 2) | |
68 | #define CLKD_MASK 0x0000FFC0 | |
69 | #define CLKD_SHIFT 6 | |
70 | #define DTO_MASK 0x000F0000 | |
71 | #define DTO_SHIFT 16 | |
72 | #define INT_EN_MASK 0x307F0033 | |
73 | #define INIT_STREAM (1 << 1) | |
74 | #define DP_SELECT (1 << 21) | |
75 | #define DDIR (1 << 4) | |
76 | #define DMA_EN 0x1 | |
77 | #define MSBS (1 << 5) | |
78 | #define BCE (1 << 1) | |
79 | #define FOUR_BIT (1 << 1) | |
73153010 | 80 | #define DW8 (1 << 5) |
a45c6cb8 MC |
81 | #define CC 0x1 |
82 | #define TC 0x02 | |
83 | #define OD 0x1 | |
84 | #define ERR (1 << 15) | |
85 | #define CMD_TIMEOUT (1 << 16) | |
86 | #define DATA_TIMEOUT (1 << 20) | |
87 | #define CMD_CRC (1 << 17) | |
88 | #define DATA_CRC (1 << 21) | |
89 | #define CARD_ERR (1 << 28) | |
90 | #define STAT_CLEAR 0xFFFFFFFF | |
91 | #define INIT_STREAM_CMD 0x00000000 | |
92 | #define DUAL_VOLT_OCR_BIT 7 | |
93 | #define SRC (1 << 25) | |
94 | #define SRD (1 << 26) | |
95 | ||
96 | /* | |
97 | * FIXME: Most likely all the data using these _DEVID defines should come | |
98 | * from the platform_data, or implemented in controller and slot specific | |
99 | * functions. | |
100 | */ | |
101 | #define OMAP_MMC1_DEVID 0 | |
102 | #define OMAP_MMC2_DEVID 1 | |
f3e2f1dd | 103 | #define OMAP_MMC3_DEVID 2 |
a45c6cb8 | 104 | |
a45c6cb8 MC |
105 | #define MMC_TIMEOUT_MS 20 |
106 | #define OMAP_MMC_MASTER_CLOCK 96000000 | |
107 | #define DRIVER_NAME "mmci-omap-hs" | |
108 | ||
109 | /* | |
110 | * One controller can have multiple slots, like on some omap boards using | |
111 | * omap.c controller driver. Luckily this is not currently done on any known | |
112 | * omap_hsmmc.c device. | |
113 | */ | |
114 | #define mmc_slot(host) (host->pdata->slots[host->slot_id]) | |
115 | ||
116 | /* | |
117 | * MMC Host controller read/write API's | |
118 | */ | |
119 | #define OMAP_HSMMC_READ(base, reg) \ | |
120 | __raw_readl((base) + OMAP_HSMMC_##reg) | |
121 | ||
122 | #define OMAP_HSMMC_WRITE(base, reg, val) \ | |
123 | __raw_writel((val), (base) + OMAP_HSMMC_##reg) | |
124 | ||
125 | struct mmc_omap_host { | |
126 | struct device *dev; | |
127 | struct mmc_host *mmc; | |
128 | struct mmc_request *mrq; | |
129 | struct mmc_command *cmd; | |
130 | struct mmc_data *data; | |
131 | struct clk *fclk; | |
132 | struct clk *iclk; | |
133 | struct clk *dbclk; | |
134 | struct semaphore sem; | |
135 | struct work_struct mmc_carddetect_work; | |
136 | void __iomem *base; | |
137 | resource_size_t mapbase; | |
138 | unsigned int id; | |
139 | unsigned int dma_len; | |
0ccd76d4 | 140 | unsigned int dma_sg_idx; |
a45c6cb8 | 141 | unsigned char bus_mode; |
a45c6cb8 MC |
142 | u32 *buffer; |
143 | u32 bytesleft; | |
144 | int suspended; | |
145 | int irq; | |
146 | int carddetect; | |
147 | int use_dma, dma_ch; | |
f3e2f1dd | 148 | int dma_line_tx, dma_line_rx; |
a45c6cb8 MC |
149 | int slot_id; |
150 | int dbclk_enabled; | |
4a694dc9 | 151 | int response_busy; |
a45c6cb8 MC |
152 | struct omap_mmc_platform_data *pdata; |
153 | }; | |
154 | ||
155 | /* | |
156 | * Stop clock to the card | |
157 | */ | |
158 | static void omap_mmc_stop_clock(struct mmc_omap_host *host) | |
159 | { | |
160 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
161 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); | |
162 | if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) | |
163 | dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); | |
164 | } | |
165 | ||
166 | /* | |
167 | * Send init stream sequence to card | |
168 | * before sending IDLE command | |
169 | */ | |
170 | static void send_init_stream(struct mmc_omap_host *host) | |
171 | { | |
172 | int reg = 0; | |
173 | unsigned long timeout; | |
174 | ||
175 | disable_irq(host->irq); | |
176 | OMAP_HSMMC_WRITE(host->base, CON, | |
177 | OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); | |
178 | OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); | |
179 | ||
180 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
181 | while ((reg != CC) && time_before(jiffies, timeout)) | |
182 | reg = OMAP_HSMMC_READ(host->base, STAT) & CC; | |
183 | ||
184 | OMAP_HSMMC_WRITE(host->base, CON, | |
185 | OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); | |
186 | enable_irq(host->irq); | |
187 | } | |
188 | ||
189 | static inline | |
190 | int mmc_omap_cover_is_closed(struct mmc_omap_host *host) | |
191 | { | |
192 | int r = 1; | |
193 | ||
194 | if (host->pdata->slots[host->slot_id].get_cover_state) | |
195 | r = host->pdata->slots[host->slot_id].get_cover_state(host->dev, | |
196 | host->slot_id); | |
197 | return r; | |
198 | } | |
199 | ||
200 | static ssize_t | |
201 | mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr, | |
202 | char *buf) | |
203 | { | |
204 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
205 | struct mmc_omap_host *host = mmc_priv(mmc); | |
206 | ||
207 | return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" : | |
208 | "open"); | |
209 | } | |
210 | ||
211 | static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL); | |
212 | ||
213 | static ssize_t | |
214 | mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr, | |
215 | char *buf) | |
216 | { | |
217 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
218 | struct mmc_omap_host *host = mmc_priv(mmc); | |
219 | struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id]; | |
220 | ||
e68fdabc | 221 | return sprintf(buf, "%s\n", slot.name); |
a45c6cb8 MC |
222 | } |
223 | ||
224 | static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL); | |
225 | ||
226 | /* | |
227 | * Configure the response type and send the cmd. | |
228 | */ | |
229 | static void | |
230 | mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd, | |
231 | struct mmc_data *data) | |
232 | { | |
233 | int cmdreg = 0, resptype = 0, cmdtype = 0; | |
234 | ||
235 | dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", | |
236 | mmc_hostname(host->mmc), cmd->opcode, cmd->arg); | |
237 | host->cmd = cmd; | |
238 | ||
239 | /* | |
240 | * Clear status bits and enable interrupts | |
241 | */ | |
242 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
243 | OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); | |
244 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
245 | ||
4a694dc9 | 246 | host->response_busy = 0; |
a45c6cb8 MC |
247 | if (cmd->flags & MMC_RSP_PRESENT) { |
248 | if (cmd->flags & MMC_RSP_136) | |
249 | resptype = 1; | |
4a694dc9 AH |
250 | else if (cmd->flags & MMC_RSP_BUSY) { |
251 | resptype = 3; | |
252 | host->response_busy = 1; | |
253 | } else | |
a45c6cb8 MC |
254 | resptype = 2; |
255 | } | |
256 | ||
257 | /* | |
258 | * Unlike OMAP1 controller, the cmdtype does not seem to be based on | |
259 | * ac, bc, adtc, bcr. Only commands ending an open ended transfer need | |
260 | * a val of 0x3, rest 0x0. | |
261 | */ | |
262 | if (cmd == host->mrq->stop) | |
263 | cmdtype = 0x3; | |
264 | ||
265 | cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); | |
266 | ||
267 | if (data) { | |
268 | cmdreg |= DP_SELECT | MSBS | BCE; | |
269 | if (data->flags & MMC_DATA_READ) | |
270 | cmdreg |= DDIR; | |
271 | else | |
272 | cmdreg &= ~(DDIR); | |
273 | } | |
274 | ||
275 | if (host->use_dma) | |
276 | cmdreg |= DMA_EN; | |
277 | ||
278 | OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); | |
279 | OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); | |
280 | } | |
281 | ||
0ccd76d4 JY |
282 | static int |
283 | mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data) | |
284 | { | |
285 | if (data->flags & MMC_DATA_WRITE) | |
286 | return DMA_TO_DEVICE; | |
287 | else | |
288 | return DMA_FROM_DEVICE; | |
289 | } | |
290 | ||
a45c6cb8 MC |
291 | /* |
292 | * Notify the transfer complete to MMC core | |
293 | */ | |
294 | static void | |
295 | mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data) | |
296 | { | |
4a694dc9 AH |
297 | if (!data) { |
298 | struct mmc_request *mrq = host->mrq; | |
299 | ||
300 | host->mrq = NULL; | |
4a694dc9 AH |
301 | mmc_request_done(host->mmc, mrq); |
302 | return; | |
303 | } | |
304 | ||
a45c6cb8 MC |
305 | host->data = NULL; |
306 | ||
307 | if (host->use_dma && host->dma_ch != -1) | |
308 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, | |
0ccd76d4 | 309 | mmc_omap_get_dma_dir(host, data)); |
a45c6cb8 MC |
310 | |
311 | if (!data->error) | |
312 | data->bytes_xfered += data->blocks * (data->blksz); | |
313 | else | |
314 | data->bytes_xfered = 0; | |
315 | ||
316 | if (!data->stop) { | |
317 | host->mrq = NULL; | |
318 | mmc_request_done(host->mmc, data->mrq); | |
319 | return; | |
320 | } | |
321 | mmc_omap_start_command(host, data->stop, NULL); | |
322 | } | |
323 | ||
324 | /* | |
325 | * Notify the core about command completion | |
326 | */ | |
327 | static void | |
328 | mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd) | |
329 | { | |
330 | host->cmd = NULL; | |
331 | ||
332 | if (cmd->flags & MMC_RSP_PRESENT) { | |
333 | if (cmd->flags & MMC_RSP_136) { | |
334 | /* response type 2 */ | |
335 | cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); | |
336 | cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); | |
337 | cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); | |
338 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); | |
339 | } else { | |
340 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
341 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); | |
342 | } | |
343 | } | |
4a694dc9 | 344 | if ((host->data == NULL && !host->response_busy) || cmd->error) { |
a45c6cb8 MC |
345 | host->mrq = NULL; |
346 | mmc_request_done(host->mmc, cmd->mrq); | |
347 | } | |
348 | } | |
349 | ||
350 | /* | |
351 | * DMA clean up for command errors | |
352 | */ | |
82788ff5 | 353 | static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno) |
a45c6cb8 | 354 | { |
82788ff5 | 355 | host->data->error = errno; |
a45c6cb8 MC |
356 | |
357 | if (host->use_dma && host->dma_ch != -1) { | |
358 | dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len, | |
0ccd76d4 | 359 | mmc_omap_get_dma_dir(host, host->data)); |
a45c6cb8 MC |
360 | omap_free_dma(host->dma_ch); |
361 | host->dma_ch = -1; | |
362 | up(&host->sem); | |
363 | } | |
364 | host->data = NULL; | |
a45c6cb8 MC |
365 | } |
366 | ||
367 | /* | |
368 | * Readable error output | |
369 | */ | |
370 | #ifdef CONFIG_MMC_DEBUG | |
371 | static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status) | |
372 | { | |
373 | /* --- means reserved bit without definition at documentation */ | |
374 | static const char *mmc_omap_status_bits[] = { | |
375 | "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ", | |
376 | "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC", | |
377 | "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---", | |
378 | "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---" | |
379 | }; | |
380 | char res[256]; | |
381 | char *buf = res; | |
382 | int len, i; | |
383 | ||
384 | len = sprintf(buf, "MMC IRQ 0x%x :", status); | |
385 | buf += len; | |
386 | ||
387 | for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++) | |
388 | if (status & (1 << i)) { | |
389 | len = sprintf(buf, " %s", mmc_omap_status_bits[i]); | |
390 | buf += len; | |
391 | } | |
392 | ||
393 | dev_dbg(mmc_dev(host->mmc), "%s\n", res); | |
394 | } | |
395 | #endif /* CONFIG_MMC_DEBUG */ | |
396 | ||
3ebf74b1 JP |
397 | /* |
398 | * MMC controller internal state machines reset | |
399 | * | |
400 | * Used to reset command or data internal state machines, using respectively | |
401 | * SRC or SRD bit of SYSCTL register | |
402 | * Can be called from interrupt context | |
403 | */ | |
404 | static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host, | |
405 | unsigned long bit) | |
406 | { | |
407 | unsigned long i = 0; | |
408 | unsigned long limit = (loops_per_jiffy * | |
409 | msecs_to_jiffies(MMC_TIMEOUT_MS)); | |
410 | ||
411 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
412 | OMAP_HSMMC_READ(host->base, SYSCTL) | bit); | |
413 | ||
414 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && | |
415 | (i++ < limit)) | |
416 | cpu_relax(); | |
417 | ||
418 | if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) | |
419 | dev_err(mmc_dev(host->mmc), | |
420 | "Timeout waiting on controller reset in %s\n", | |
421 | __func__); | |
422 | } | |
a45c6cb8 MC |
423 | |
424 | /* | |
425 | * MMC controller IRQ handler | |
426 | */ | |
427 | static irqreturn_t mmc_omap_irq(int irq, void *dev_id) | |
428 | { | |
429 | struct mmc_omap_host *host = dev_id; | |
430 | struct mmc_data *data; | |
431 | int end_cmd = 0, end_trans = 0, status; | |
432 | ||
4a694dc9 | 433 | if (host->mrq == NULL) { |
a45c6cb8 MC |
434 | OMAP_HSMMC_WRITE(host->base, STAT, |
435 | OMAP_HSMMC_READ(host->base, STAT)); | |
00adadc1 KH |
436 | /* Flush posted write */ |
437 | OMAP_HSMMC_READ(host->base, STAT); | |
a45c6cb8 MC |
438 | return IRQ_HANDLED; |
439 | } | |
440 | ||
441 | data = host->data; | |
442 | status = OMAP_HSMMC_READ(host->base, STAT); | |
443 | dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); | |
444 | ||
445 | if (status & ERR) { | |
446 | #ifdef CONFIG_MMC_DEBUG | |
447 | mmc_omap_report_irq(host, status); | |
448 | #endif | |
449 | if ((status & CMD_TIMEOUT) || | |
450 | (status & CMD_CRC)) { | |
451 | if (host->cmd) { | |
452 | if (status & CMD_TIMEOUT) { | |
3ebf74b1 | 453 | mmc_omap_reset_controller_fsm(host, SRC); |
a45c6cb8 MC |
454 | host->cmd->error = -ETIMEDOUT; |
455 | } else { | |
456 | host->cmd->error = -EILSEQ; | |
457 | } | |
458 | end_cmd = 1; | |
459 | } | |
4a694dc9 AH |
460 | if (host->data || host->response_busy) { |
461 | if (host->data) | |
462 | mmc_dma_cleanup(host, -ETIMEDOUT); | |
463 | host->response_busy = 0; | |
3ebf74b1 | 464 | mmc_omap_reset_controller_fsm(host, SRD); |
c232f457 | 465 | } |
a45c6cb8 MC |
466 | } |
467 | if ((status & DATA_TIMEOUT) || | |
468 | (status & DATA_CRC)) { | |
4a694dc9 AH |
469 | if (host->data || host->response_busy) { |
470 | int err = (status & DATA_TIMEOUT) ? | |
471 | -ETIMEDOUT : -EILSEQ; | |
472 | ||
473 | if (host->data) | |
474 | mmc_dma_cleanup(host, err); | |
a45c6cb8 | 475 | else |
4a694dc9 AH |
476 | host->mrq->cmd->error = err; |
477 | host->response_busy = 0; | |
3ebf74b1 | 478 | mmc_omap_reset_controller_fsm(host, SRD); |
a45c6cb8 MC |
479 | end_trans = 1; |
480 | } | |
481 | } | |
482 | if (status & CARD_ERR) { | |
483 | dev_dbg(mmc_dev(host->mmc), | |
484 | "Ignoring card err CMD%d\n", host->cmd->opcode); | |
485 | if (host->cmd) | |
486 | end_cmd = 1; | |
487 | if (host->data) | |
488 | end_trans = 1; | |
489 | } | |
490 | } | |
491 | ||
492 | OMAP_HSMMC_WRITE(host->base, STAT, status); | |
00adadc1 KH |
493 | /* Flush posted write */ |
494 | OMAP_HSMMC_READ(host->base, STAT); | |
a45c6cb8 | 495 | |
a8fe29d8 | 496 | if (end_cmd || ((status & CC) && host->cmd)) |
a45c6cb8 MC |
497 | mmc_omap_cmd_done(host, host->cmd); |
498 | if (end_trans || (status & TC)) | |
499 | mmc_omap_xfer_done(host, data); | |
500 | ||
501 | return IRQ_HANDLED; | |
502 | } | |
503 | ||
e13bb300 AH |
504 | static void set_sd_bus_power(struct mmc_omap_host *host) |
505 | { | |
506 | unsigned long i; | |
507 | ||
508 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
509 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
510 | for (i = 0; i < loops_per_jiffy; i++) { | |
511 | if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) | |
512 | break; | |
513 | cpu_relax(); | |
514 | } | |
515 | } | |
516 | ||
a45c6cb8 | 517 | /* |
eb250826 DB |
518 | * Switch MMC interface voltage ... only relevant for MMC1. |
519 | * | |
520 | * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. | |
521 | * The MMC2 transceiver controls are used instead of DAT4..DAT7. | |
522 | * Some chips, like eMMC ones, use internal transceivers. | |
a45c6cb8 MC |
523 | */ |
524 | static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd) | |
525 | { | |
526 | u32 reg_val = 0; | |
527 | int ret; | |
528 | ||
529 | /* Disable the clocks */ | |
530 | clk_disable(host->fclk); | |
531 | clk_disable(host->iclk); | |
532 | clk_disable(host->dbclk); | |
533 | ||
534 | /* Turn the power off */ | |
535 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); | |
536 | if (ret != 0) | |
537 | goto err; | |
538 | ||
539 | /* Turn the power ON with given VDD 1.8 or 3.0v */ | |
540 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); | |
541 | if (ret != 0) | |
542 | goto err; | |
543 | ||
544 | clk_enable(host->fclk); | |
545 | clk_enable(host->iclk); | |
546 | clk_enable(host->dbclk); | |
547 | ||
548 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
549 | OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); | |
550 | reg_val = OMAP_HSMMC_READ(host->base, HCTL); | |
eb250826 | 551 | |
a45c6cb8 MC |
552 | /* |
553 | * If a MMC dual voltage card is detected, the set_ios fn calls | |
554 | * this fn with VDD bit set for 1.8V. Upon card removal from the | |
555 | * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. | |
556 | * | |
eb250826 DB |
557 | * Cope with a bit of slop in the range ... per data sheets: |
558 | * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, | |
559 | * but recommended values are 1.71V to 1.89V | |
560 | * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, | |
561 | * but recommended values are 2.7V to 3.3V | |
562 | * | |
563 | * Board setup code shouldn't permit anything very out-of-range. | |
564 | * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the | |
565 | * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. | |
a45c6cb8 | 566 | */ |
eb250826 | 567 | if ((1 << vdd) <= MMC_VDD_23_24) |
a45c6cb8 | 568 | reg_val |= SDVS18; |
eb250826 DB |
569 | else |
570 | reg_val |= SDVS30; | |
a45c6cb8 MC |
571 | |
572 | OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); | |
e13bb300 | 573 | set_sd_bus_power(host); |
a45c6cb8 MC |
574 | |
575 | return 0; | |
576 | err: | |
577 | dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); | |
578 | return ret; | |
579 | } | |
580 | ||
581 | /* | |
582 | * Work Item to notify the core about card insertion/removal | |
583 | */ | |
584 | static void mmc_omap_detect(struct work_struct *work) | |
585 | { | |
586 | struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, | |
587 | mmc_carddetect_work); | |
249d0fa9 DB |
588 | struct omap_mmc_slot_data *slot = &mmc_slot(host); |
589 | ||
e1a55f5e AH |
590 | if (mmc_slot(host).card_detect) |
591 | host->carddetect = slot->card_detect(slot->card_detect_irq); | |
592 | else | |
593 | host->carddetect = -ENOSYS; | |
a45c6cb8 MC |
594 | |
595 | sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); | |
596 | if (host->carddetect) { | |
597 | mmc_detect_change(host->mmc, (HZ * 200) / 1000); | |
598 | } else { | |
3ebf74b1 | 599 | mmc_omap_reset_controller_fsm(host, SRD); |
a45c6cb8 MC |
600 | mmc_detect_change(host->mmc, (HZ * 50) / 1000); |
601 | } | |
602 | } | |
603 | ||
604 | /* | |
605 | * ISR for handling card insertion and removal | |
606 | */ | |
607 | static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id) | |
608 | { | |
609 | struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id; | |
610 | ||
a45c6cb8 MC |
611 | schedule_work(&host->mmc_carddetect_work); |
612 | ||
613 | return IRQ_HANDLED; | |
614 | } | |
615 | ||
0ccd76d4 JY |
616 | static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host, |
617 | struct mmc_data *data) | |
618 | { | |
619 | int sync_dev; | |
620 | ||
f3e2f1dd GI |
621 | if (data->flags & MMC_DATA_WRITE) |
622 | sync_dev = host->dma_line_tx; | |
623 | else | |
624 | sync_dev = host->dma_line_rx; | |
0ccd76d4 JY |
625 | return sync_dev; |
626 | } | |
627 | ||
628 | static void mmc_omap_config_dma_params(struct mmc_omap_host *host, | |
629 | struct mmc_data *data, | |
630 | struct scatterlist *sgl) | |
631 | { | |
632 | int blksz, nblk, dma_ch; | |
633 | ||
634 | dma_ch = host->dma_ch; | |
635 | if (data->flags & MMC_DATA_WRITE) { | |
636 | omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
637 | (host->mapbase + OMAP_HSMMC_DATA), 0, 0); | |
638 | omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, | |
639 | sg_dma_address(sgl), 0, 0); | |
640 | } else { | |
641 | omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
642 | (host->mapbase + OMAP_HSMMC_DATA), 0, 0); | |
643 | omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, | |
644 | sg_dma_address(sgl), 0, 0); | |
645 | } | |
646 | ||
647 | blksz = host->data->blksz; | |
648 | nblk = sg_dma_len(sgl) / blksz; | |
649 | ||
650 | omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, | |
651 | blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, | |
652 | mmc_omap_get_dma_sync_dev(host, data), | |
653 | !(data->flags & MMC_DATA_WRITE)); | |
654 | ||
655 | omap_start_dma(dma_ch); | |
656 | } | |
657 | ||
a45c6cb8 MC |
658 | /* |
659 | * DMA call back function | |
660 | */ | |
661 | static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data) | |
662 | { | |
663 | struct mmc_omap_host *host = data; | |
664 | ||
665 | if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ) | |
666 | dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n"); | |
667 | ||
668 | if (host->dma_ch < 0) | |
669 | return; | |
670 | ||
0ccd76d4 JY |
671 | host->dma_sg_idx++; |
672 | if (host->dma_sg_idx < host->dma_len) { | |
673 | /* Fire up the next transfer. */ | |
674 | mmc_omap_config_dma_params(host, host->data, | |
675 | host->data->sg + host->dma_sg_idx); | |
676 | return; | |
677 | } | |
678 | ||
a45c6cb8 MC |
679 | omap_free_dma(host->dma_ch); |
680 | host->dma_ch = -1; | |
681 | /* | |
682 | * DMA Callback: run in interrupt context. | |
85b84322 | 683 | * mutex_unlock will throw a kernel warning if used. |
a45c6cb8 MC |
684 | */ |
685 | up(&host->sem); | |
686 | } | |
687 | ||
a45c6cb8 MC |
688 | /* |
689 | * Routine to configure and start DMA for the MMC card | |
690 | */ | |
691 | static int | |
692 | mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req) | |
693 | { | |
0ccd76d4 | 694 | int dma_ch = 0, ret = 0, err = 1, i; |
a45c6cb8 MC |
695 | struct mmc_data *data = req->data; |
696 | ||
0ccd76d4 JY |
697 | /* Sanity check: all the SG entries must be aligned by block size. */ |
698 | for (i = 0; i < host->dma_len; i++) { | |
699 | struct scatterlist *sgl; | |
700 | ||
701 | sgl = data->sg + i; | |
702 | if (sgl->length % data->blksz) | |
703 | return -EINVAL; | |
704 | } | |
705 | if ((data->blksz % 4) != 0) | |
706 | /* REVISIT: The MMC buffer increments only when MSB is written. | |
707 | * Return error for blksz which is non multiple of four. | |
708 | */ | |
709 | return -EINVAL; | |
710 | ||
a45c6cb8 MC |
711 | /* |
712 | * If for some reason the DMA transfer is still active, | |
713 | * we wait for timeout period and free the dma | |
714 | */ | |
715 | if (host->dma_ch != -1) { | |
716 | set_current_state(TASK_UNINTERRUPTIBLE); | |
717 | schedule_timeout(100); | |
718 | if (down_trylock(&host->sem)) { | |
719 | omap_free_dma(host->dma_ch); | |
720 | host->dma_ch = -1; | |
721 | up(&host->sem); | |
722 | return err; | |
723 | } | |
724 | } else { | |
725 | if (down_trylock(&host->sem)) | |
726 | return err; | |
727 | } | |
728 | ||
0ccd76d4 JY |
729 | ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD", |
730 | mmc_omap_dma_cb,host, &dma_ch); | |
a45c6cb8 | 731 | if (ret != 0) { |
0ccd76d4 | 732 | dev_err(mmc_dev(host->mmc), |
a45c6cb8 MC |
733 | "%s: omap_request_dma() failed with %d\n", |
734 | mmc_hostname(host->mmc), ret); | |
735 | return ret; | |
736 | } | |
737 | ||
738 | host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, | |
0ccd76d4 | 739 | data->sg_len, mmc_omap_get_dma_dir(host, data)); |
a45c6cb8 | 740 | host->dma_ch = dma_ch; |
0ccd76d4 | 741 | host->dma_sg_idx = 0; |
a45c6cb8 | 742 | |
0ccd76d4 | 743 | mmc_omap_config_dma_params(host, data, data->sg); |
a45c6cb8 | 744 | |
a45c6cb8 MC |
745 | return 0; |
746 | } | |
747 | ||
748 | static void set_data_timeout(struct mmc_omap_host *host, | |
749 | struct mmc_request *req) | |
750 | { | |
751 | unsigned int timeout, cycle_ns; | |
752 | uint32_t reg, clkd, dto = 0; | |
753 | ||
754 | reg = OMAP_HSMMC_READ(host->base, SYSCTL); | |
755 | clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; | |
756 | if (clkd == 0) | |
757 | clkd = 1; | |
758 | ||
759 | cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); | |
760 | timeout = req->data->timeout_ns / cycle_ns; | |
761 | timeout += req->data->timeout_clks; | |
762 | if (timeout) { | |
763 | while ((timeout & 0x80000000) == 0) { | |
764 | dto += 1; | |
765 | timeout <<= 1; | |
766 | } | |
767 | dto = 31 - dto; | |
768 | timeout <<= 1; | |
769 | if (timeout && dto) | |
770 | dto += 1; | |
771 | if (dto >= 13) | |
772 | dto -= 13; | |
773 | else | |
774 | dto = 0; | |
775 | if (dto > 14) | |
776 | dto = 14; | |
777 | } | |
778 | ||
779 | reg &= ~DTO_MASK; | |
780 | reg |= dto << DTO_SHIFT; | |
781 | OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); | |
782 | } | |
783 | ||
784 | /* | |
785 | * Configure block length for MMC/SD cards and initiate the transfer. | |
786 | */ | |
787 | static int | |
788 | mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) | |
789 | { | |
790 | int ret; | |
791 | host->data = req->data; | |
792 | ||
793 | if (req->data == NULL) { | |
a45c6cb8 MC |
794 | OMAP_HSMMC_WRITE(host->base, BLK, 0); |
795 | return 0; | |
796 | } | |
797 | ||
798 | OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) | |
799 | | (req->data->blocks << 16)); | |
800 | set_data_timeout(host, req); | |
801 | ||
a45c6cb8 MC |
802 | if (host->use_dma) { |
803 | ret = mmc_omap_start_dma_transfer(host, req); | |
804 | if (ret != 0) { | |
805 | dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); | |
806 | return ret; | |
807 | } | |
808 | } | |
809 | return 0; | |
810 | } | |
811 | ||
812 | /* | |
813 | * Request function. for read/write operation | |
814 | */ | |
815 | static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req) | |
816 | { | |
817 | struct mmc_omap_host *host = mmc_priv(mmc); | |
818 | ||
819 | WARN_ON(host->mrq != NULL); | |
820 | host->mrq = req; | |
821 | mmc_omap_prepare_data(host, req); | |
822 | mmc_omap_start_command(host, req->cmd, req->data); | |
823 | } | |
824 | ||
825 | ||
826 | /* Routine to configure clock values. Exposed API to core */ | |
827 | static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
828 | { | |
829 | struct mmc_omap_host *host = mmc_priv(mmc); | |
830 | u16 dsor = 0; | |
831 | unsigned long regval; | |
832 | unsigned long timeout; | |
73153010 | 833 | u32 con; |
a45c6cb8 MC |
834 | |
835 | switch (ios->power_mode) { | |
836 | case MMC_POWER_OFF: | |
837 | mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); | |
a45c6cb8 MC |
838 | break; |
839 | case MMC_POWER_UP: | |
840 | mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd); | |
841 | break; | |
842 | } | |
843 | ||
73153010 | 844 | con = OMAP_HSMMC_READ(host->base, CON); |
a45c6cb8 | 845 | switch (mmc->ios.bus_width) { |
73153010 JL |
846 | case MMC_BUS_WIDTH_8: |
847 | OMAP_HSMMC_WRITE(host->base, CON, con | DW8); | |
848 | break; | |
a45c6cb8 | 849 | case MMC_BUS_WIDTH_4: |
73153010 | 850 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); |
a45c6cb8 MC |
851 | OMAP_HSMMC_WRITE(host->base, HCTL, |
852 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); | |
853 | break; | |
854 | case MMC_BUS_WIDTH_1: | |
73153010 | 855 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); |
a45c6cb8 MC |
856 | OMAP_HSMMC_WRITE(host->base, HCTL, |
857 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); | |
858 | break; | |
859 | } | |
860 | ||
861 | if (host->id == OMAP_MMC1_DEVID) { | |
eb250826 DB |
862 | /* Only MMC1 can interface at 3V without some flavor |
863 | * of external transceiver; but they all handle 1.8V. | |
864 | */ | |
a45c6cb8 MC |
865 | if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && |
866 | (ios->vdd == DUAL_VOLT_OCR_BIT)) { | |
867 | /* | |
868 | * The mmc_select_voltage fn of the core does | |
869 | * not seem to set the power_mode to | |
870 | * MMC_POWER_UP upon recalculating the voltage. | |
871 | * vdd 1.8v. | |
872 | */ | |
873 | if (omap_mmc_switch_opcond(host, ios->vdd) != 0) | |
874 | dev_dbg(mmc_dev(host->mmc), | |
875 | "Switch operation failed\n"); | |
876 | } | |
877 | } | |
878 | ||
879 | if (ios->clock) { | |
880 | dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; | |
881 | if (dsor < 1) | |
882 | dsor = 1; | |
883 | ||
884 | if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) | |
885 | dsor++; | |
886 | ||
887 | if (dsor > 250) | |
888 | dsor = 250; | |
889 | } | |
890 | omap_mmc_stop_clock(host); | |
891 | regval = OMAP_HSMMC_READ(host->base, SYSCTL); | |
892 | regval = regval & ~(CLKD_MASK); | |
893 | regval = regval | (dsor << 6) | (DTO << 16); | |
894 | OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); | |
895 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
896 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); | |
897 | ||
898 | /* Wait till the ICS bit is set */ | |
899 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
900 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2 | |
901 | && time_before(jiffies, timeout)) | |
902 | msleep(1); | |
903 | ||
904 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
905 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); | |
906 | ||
907 | if (ios->power_mode == MMC_POWER_ON) | |
908 | send_init_stream(host); | |
909 | ||
910 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
911 | OMAP_HSMMC_WRITE(host->base, CON, | |
912 | OMAP_HSMMC_READ(host->base, CON) | OD); | |
913 | } | |
914 | ||
915 | static int omap_hsmmc_get_cd(struct mmc_host *mmc) | |
916 | { | |
917 | struct mmc_omap_host *host = mmc_priv(mmc); | |
918 | struct omap_mmc_platform_data *pdata = host->pdata; | |
919 | ||
920 | if (!pdata->slots[0].card_detect) | |
921 | return -ENOSYS; | |
922 | return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq); | |
923 | } | |
924 | ||
925 | static int omap_hsmmc_get_ro(struct mmc_host *mmc) | |
926 | { | |
927 | struct mmc_omap_host *host = mmc_priv(mmc); | |
928 | struct omap_mmc_platform_data *pdata = host->pdata; | |
929 | ||
930 | if (!pdata->slots[0].get_ro) | |
931 | return -ENOSYS; | |
932 | return pdata->slots[0].get_ro(host->dev, 0); | |
933 | } | |
934 | ||
1b331e69 KK |
935 | static void omap_hsmmc_init(struct mmc_omap_host *host) |
936 | { | |
937 | u32 hctl, capa, value; | |
938 | ||
939 | /* Only MMC1 supports 3.0V */ | |
940 | if (host->id == OMAP_MMC1_DEVID) { | |
941 | hctl = SDVS30; | |
942 | capa = VS30 | VS18; | |
943 | } else { | |
944 | hctl = SDVS18; | |
945 | capa = VS18; | |
946 | } | |
947 | ||
948 | value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; | |
949 | OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); | |
950 | ||
951 | value = OMAP_HSMMC_READ(host->base, CAPA); | |
952 | OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); | |
953 | ||
954 | /* Set the controller to AUTO IDLE mode */ | |
955 | value = OMAP_HSMMC_READ(host->base, SYSCONFIG); | |
956 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); | |
957 | ||
958 | /* Set SD bus power bit */ | |
e13bb300 | 959 | set_sd_bus_power(host); |
1b331e69 KK |
960 | } |
961 | ||
a45c6cb8 MC |
962 | static struct mmc_host_ops mmc_omap_ops = { |
963 | .request = omap_mmc_request, | |
964 | .set_ios = omap_mmc_set_ios, | |
965 | .get_cd = omap_hsmmc_get_cd, | |
966 | .get_ro = omap_hsmmc_get_ro, | |
967 | /* NYET -- enable_sdio_irq */ | |
968 | }; | |
969 | ||
970 | static int __init omap_mmc_probe(struct platform_device *pdev) | |
971 | { | |
972 | struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; | |
973 | struct mmc_host *mmc; | |
974 | struct mmc_omap_host *host = NULL; | |
975 | struct resource *res; | |
976 | int ret = 0, irq; | |
a45c6cb8 MC |
977 | |
978 | if (pdata == NULL) { | |
979 | dev_err(&pdev->dev, "Platform Data is missing\n"); | |
980 | return -ENXIO; | |
981 | } | |
982 | ||
983 | if (pdata->nr_slots == 0) { | |
984 | dev_err(&pdev->dev, "No Slots\n"); | |
985 | return -ENXIO; | |
986 | } | |
987 | ||
988 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
989 | irq = platform_get_irq(pdev, 0); | |
990 | if (res == NULL || irq < 0) | |
991 | return -ENXIO; | |
992 | ||
993 | res = request_mem_region(res->start, res->end - res->start + 1, | |
994 | pdev->name); | |
995 | if (res == NULL) | |
996 | return -EBUSY; | |
997 | ||
998 | mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev); | |
999 | if (!mmc) { | |
1000 | ret = -ENOMEM; | |
1001 | goto err; | |
1002 | } | |
1003 | ||
1004 | host = mmc_priv(mmc); | |
1005 | host->mmc = mmc; | |
1006 | host->pdata = pdata; | |
1007 | host->dev = &pdev->dev; | |
1008 | host->use_dma = 1; | |
1009 | host->dev->dma_mask = &pdata->dma_mask; | |
1010 | host->dma_ch = -1; | |
1011 | host->irq = irq; | |
1012 | host->id = pdev->id; | |
1013 | host->slot_id = 0; | |
1014 | host->mapbase = res->start; | |
1015 | host->base = ioremap(host->mapbase, SZ_4K); | |
1016 | ||
1017 | platform_set_drvdata(pdev, host); | |
1018 | INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect); | |
1019 | ||
1020 | mmc->ops = &mmc_omap_ops; | |
1021 | mmc->f_min = 400000; | |
1022 | mmc->f_max = 52000000; | |
1023 | ||
1024 | sema_init(&host->sem, 1); | |
1025 | ||
6f7607cc | 1026 | host->iclk = clk_get(&pdev->dev, "ick"); |
a45c6cb8 MC |
1027 | if (IS_ERR(host->iclk)) { |
1028 | ret = PTR_ERR(host->iclk); | |
1029 | host->iclk = NULL; | |
1030 | goto err1; | |
1031 | } | |
6f7607cc | 1032 | host->fclk = clk_get(&pdev->dev, "fck"); |
a45c6cb8 MC |
1033 | if (IS_ERR(host->fclk)) { |
1034 | ret = PTR_ERR(host->fclk); | |
1035 | host->fclk = NULL; | |
1036 | clk_put(host->iclk); | |
1037 | goto err1; | |
1038 | } | |
1039 | ||
1040 | if (clk_enable(host->fclk) != 0) { | |
1041 | clk_put(host->iclk); | |
1042 | clk_put(host->fclk); | |
1043 | goto err1; | |
1044 | } | |
1045 | ||
1046 | if (clk_enable(host->iclk) != 0) { | |
1047 | clk_disable(host->fclk); | |
1048 | clk_put(host->iclk); | |
1049 | clk_put(host->fclk); | |
1050 | goto err1; | |
1051 | } | |
1052 | ||
1053 | host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); | |
1054 | /* | |
1055 | * MMC can still work without debounce clock. | |
1056 | */ | |
1057 | if (IS_ERR(host->dbclk)) | |
1058 | dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n"); | |
1059 | else | |
1060 | if (clk_enable(host->dbclk) != 0) | |
1061 | dev_dbg(mmc_dev(host->mmc), "Enabling debounce" | |
1062 | " clk failed\n"); | |
1063 | else | |
1064 | host->dbclk_enabled = 1; | |
1065 | ||
0ccd76d4 JY |
1066 | /* Since we do only SG emulation, we can have as many segs |
1067 | * as we want. */ | |
1068 | mmc->max_phys_segs = 1024; | |
1069 | mmc->max_hw_segs = 1024; | |
1070 | ||
a45c6cb8 MC |
1071 | mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ |
1072 | mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ | |
1073 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1074 | mmc->max_seg_size = mmc->max_req_size; | |
1075 | ||
a45c6cb8 MC |
1076 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED; |
1077 | ||
73153010 JL |
1078 | if (pdata->slots[host->slot_id].wires >= 8) |
1079 | mmc->caps |= MMC_CAP_8_BIT_DATA; | |
1080 | else if (pdata->slots[host->slot_id].wires >= 4) | |
a45c6cb8 MC |
1081 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
1082 | ||
1b331e69 | 1083 | omap_hsmmc_init(host); |
a45c6cb8 | 1084 | |
f3e2f1dd GI |
1085 | /* Select DMA lines */ |
1086 | switch (host->id) { | |
1087 | case OMAP_MMC1_DEVID: | |
1088 | host->dma_line_tx = OMAP24XX_DMA_MMC1_TX; | |
1089 | host->dma_line_rx = OMAP24XX_DMA_MMC1_RX; | |
1090 | break; | |
1091 | case OMAP_MMC2_DEVID: | |
1092 | host->dma_line_tx = OMAP24XX_DMA_MMC2_TX; | |
1093 | host->dma_line_rx = OMAP24XX_DMA_MMC2_RX; | |
1094 | break; | |
1095 | case OMAP_MMC3_DEVID: | |
1096 | host->dma_line_tx = OMAP34XX_DMA_MMC3_TX; | |
1097 | host->dma_line_rx = OMAP34XX_DMA_MMC3_RX; | |
1098 | break; | |
1099 | default: | |
1100 | dev_err(mmc_dev(host->mmc), "Invalid MMC id\n"); | |
1101 | goto err_irq; | |
1102 | } | |
a45c6cb8 MC |
1103 | |
1104 | /* Request IRQ for MMC operations */ | |
1105 | ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED, | |
1106 | mmc_hostname(mmc), host); | |
1107 | if (ret) { | |
1108 | dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); | |
1109 | goto err_irq; | |
1110 | } | |
1111 | ||
b583f26d | 1112 | /* initialize power supplies, gpios, etc */ |
a45c6cb8 MC |
1113 | if (pdata->init != NULL) { |
1114 | if (pdata->init(&pdev->dev) != 0) { | |
b583f26d | 1115 | dev_dbg(mmc_dev(host->mmc), "late init error\n"); |
a45c6cb8 MC |
1116 | goto err_irq_cd_init; |
1117 | } | |
1118 | } | |
b583f26d | 1119 | mmc->ocr_avail = mmc_slot(host).ocr_mask; |
a45c6cb8 MC |
1120 | |
1121 | /* Request IRQ for card detect */ | |
e1a55f5e | 1122 | if ((mmc_slot(host).card_detect_irq)) { |
a45c6cb8 MC |
1123 | ret = request_irq(mmc_slot(host).card_detect_irq, |
1124 | omap_mmc_cd_handler, | |
1125 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | |
1126 | | IRQF_DISABLED, | |
1127 | mmc_hostname(mmc), host); | |
1128 | if (ret) { | |
1129 | dev_dbg(mmc_dev(host->mmc), | |
1130 | "Unable to grab MMC CD IRQ\n"); | |
1131 | goto err_irq_cd; | |
1132 | } | |
1133 | } | |
1134 | ||
1135 | OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); | |
1136 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
1137 | ||
1138 | mmc_add_host(mmc); | |
1139 | ||
1140 | if (host->pdata->slots[host->slot_id].name != NULL) { | |
1141 | ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); | |
1142 | if (ret < 0) | |
1143 | goto err_slot_name; | |
1144 | } | |
e1a55f5e AH |
1145 | if (mmc_slot(host).card_detect_irq && |
1146 | host->pdata->slots[host->slot_id].get_cover_state) { | |
a45c6cb8 MC |
1147 | ret = device_create_file(&mmc->class_dev, |
1148 | &dev_attr_cover_switch); | |
1149 | if (ret < 0) | |
1150 | goto err_cover_switch; | |
1151 | } | |
1152 | ||
1153 | return 0; | |
1154 | ||
1155 | err_cover_switch: | |
1156 | device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); | |
1157 | err_slot_name: | |
1158 | mmc_remove_host(mmc); | |
1159 | err_irq_cd: | |
1160 | free_irq(mmc_slot(host).card_detect_irq, host); | |
1161 | err_irq_cd_init: | |
1162 | free_irq(host->irq, host); | |
1163 | err_irq: | |
1164 | clk_disable(host->fclk); | |
1165 | clk_disable(host->iclk); | |
1166 | clk_put(host->fclk); | |
1167 | clk_put(host->iclk); | |
1168 | if (host->dbclk_enabled) { | |
1169 | clk_disable(host->dbclk); | |
1170 | clk_put(host->dbclk); | |
1171 | } | |
1172 | ||
1173 | err1: | |
1174 | iounmap(host->base); | |
1175 | err: | |
1176 | dev_dbg(mmc_dev(host->mmc), "Probe Failed\n"); | |
1177 | release_mem_region(res->start, res->end - res->start + 1); | |
1178 | if (host) | |
1179 | mmc_free_host(mmc); | |
1180 | return ret; | |
1181 | } | |
1182 | ||
1183 | static int omap_mmc_remove(struct platform_device *pdev) | |
1184 | { | |
1185 | struct mmc_omap_host *host = platform_get_drvdata(pdev); | |
1186 | struct resource *res; | |
1187 | ||
1188 | if (host) { | |
1189 | mmc_remove_host(host->mmc); | |
1190 | if (host->pdata->cleanup) | |
1191 | host->pdata->cleanup(&pdev->dev); | |
1192 | free_irq(host->irq, host); | |
1193 | if (mmc_slot(host).card_detect_irq) | |
1194 | free_irq(mmc_slot(host).card_detect_irq, host); | |
1195 | flush_scheduled_work(); | |
1196 | ||
1197 | clk_disable(host->fclk); | |
1198 | clk_disable(host->iclk); | |
1199 | clk_put(host->fclk); | |
1200 | clk_put(host->iclk); | |
1201 | if (host->dbclk_enabled) { | |
1202 | clk_disable(host->dbclk); | |
1203 | clk_put(host->dbclk); | |
1204 | } | |
1205 | ||
1206 | mmc_free_host(host->mmc); | |
1207 | iounmap(host->base); | |
1208 | } | |
1209 | ||
1210 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1211 | if (res) | |
1212 | release_mem_region(res->start, res->end - res->start + 1); | |
1213 | platform_set_drvdata(pdev, NULL); | |
1214 | ||
1215 | return 0; | |
1216 | } | |
1217 | ||
1218 | #ifdef CONFIG_PM | |
1219 | static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state) | |
1220 | { | |
1221 | int ret = 0; | |
1222 | struct mmc_omap_host *host = platform_get_drvdata(pdev); | |
1223 | ||
1224 | if (host && host->suspended) | |
1225 | return 0; | |
1226 | ||
1227 | if (host) { | |
1228 | ret = mmc_suspend_host(host->mmc, state); | |
1229 | if (ret == 0) { | |
1230 | host->suspended = 1; | |
1231 | ||
1232 | OMAP_HSMMC_WRITE(host->base, ISE, 0); | |
1233 | OMAP_HSMMC_WRITE(host->base, IE, 0); | |
1234 | ||
1235 | if (host->pdata->suspend) { | |
1236 | ret = host->pdata->suspend(&pdev->dev, | |
1237 | host->slot_id); | |
1238 | if (ret) | |
1239 | dev_dbg(mmc_dev(host->mmc), | |
1240 | "Unable to handle MMC board" | |
1241 | " level suspend\n"); | |
1242 | } | |
1243 | ||
0683af48 JL |
1244 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1245 | OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); | |
a45c6cb8 MC |
1246 | clk_disable(host->fclk); |
1247 | clk_disable(host->iclk); | |
1248 | clk_disable(host->dbclk); | |
1249 | } | |
1250 | ||
1251 | } | |
1252 | return ret; | |
1253 | } | |
1254 | ||
1255 | /* Routine to resume the MMC device */ | |
1256 | static int omap_mmc_resume(struct platform_device *pdev) | |
1257 | { | |
1258 | int ret = 0; | |
1259 | struct mmc_omap_host *host = platform_get_drvdata(pdev); | |
1260 | ||
1261 | if (host && !host->suspended) | |
1262 | return 0; | |
1263 | ||
1264 | if (host) { | |
1265 | ||
1266 | ret = clk_enable(host->fclk); | |
1267 | if (ret) | |
1268 | goto clk_en_err; | |
1269 | ||
1270 | ret = clk_enable(host->iclk); | |
1271 | if (ret) { | |
1272 | clk_disable(host->fclk); | |
1273 | clk_put(host->fclk); | |
1274 | goto clk_en_err; | |
1275 | } | |
1276 | ||
1277 | if (clk_enable(host->dbclk) != 0) | |
1278 | dev_dbg(mmc_dev(host->mmc), | |
1279 | "Enabling debounce clk failed\n"); | |
1280 | ||
1b331e69 KK |
1281 | omap_hsmmc_init(host); |
1282 | ||
a45c6cb8 MC |
1283 | if (host->pdata->resume) { |
1284 | ret = host->pdata->resume(&pdev->dev, host->slot_id); | |
1285 | if (ret) | |
1286 | dev_dbg(mmc_dev(host->mmc), | |
1287 | "Unmask interrupt failed\n"); | |
1288 | } | |
1289 | ||
1290 | /* Notify the core to resume the host */ | |
1291 | ret = mmc_resume_host(host->mmc); | |
1292 | if (ret == 0) | |
1293 | host->suspended = 0; | |
1294 | } | |
1295 | ||
1296 | return ret; | |
1297 | ||
1298 | clk_en_err: | |
1299 | dev_dbg(mmc_dev(host->mmc), | |
1300 | "Failed to enable MMC clocks during resume\n"); | |
1301 | return ret; | |
1302 | } | |
1303 | ||
1304 | #else | |
1305 | #define omap_mmc_suspend NULL | |
1306 | #define omap_mmc_resume NULL | |
1307 | #endif | |
1308 | ||
1309 | static struct platform_driver omap_mmc_driver = { | |
1310 | .probe = omap_mmc_probe, | |
1311 | .remove = omap_mmc_remove, | |
1312 | .suspend = omap_mmc_suspend, | |
1313 | .resume = omap_mmc_resume, | |
1314 | .driver = { | |
1315 | .name = DRIVER_NAME, | |
1316 | .owner = THIS_MODULE, | |
1317 | }, | |
1318 | }; | |
1319 | ||
1320 | static int __init omap_mmc_init(void) | |
1321 | { | |
1322 | /* Register the MMC driver */ | |
1323 | return platform_driver_register(&omap_mmc_driver); | |
1324 | } | |
1325 | ||
1326 | static void __exit omap_mmc_cleanup(void) | |
1327 | { | |
1328 | /* Unregister MMC driver */ | |
1329 | platform_driver_unregister(&omap_mmc_driver); | |
1330 | } | |
1331 | ||
1332 | module_init(omap_mmc_init); | |
1333 | module_exit(omap_mmc_cleanup); | |
1334 | ||
1335 | MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); | |
1336 | MODULE_LICENSE("GPL"); | |
1337 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
1338 | MODULE_AUTHOR("Texas Instruments Inc"); |