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ARM: OMAP: mmc-twl4030: add context loss counter support
[net-next-2.6.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
30#include <linux/io.h>
31#include <linux/semaphore.h>
32#include <mach/dma.h>
33#include <mach/hardware.h>
34#include <mach/board.h>
35#include <mach/mmc.h>
36#include <mach/cpu.h>
37
38/* OMAP HSMMC Host Controller Registers */
39#define OMAP_HSMMC_SYSCONFIG 0x0010
40#define OMAP_HSMMC_CON 0x002C
41#define OMAP_HSMMC_BLK 0x0104
42#define OMAP_HSMMC_ARG 0x0108
43#define OMAP_HSMMC_CMD 0x010C
44#define OMAP_HSMMC_RSP10 0x0110
45#define OMAP_HSMMC_RSP32 0x0114
46#define OMAP_HSMMC_RSP54 0x0118
47#define OMAP_HSMMC_RSP76 0x011C
48#define OMAP_HSMMC_DATA 0x0120
49#define OMAP_HSMMC_HCTL 0x0128
50#define OMAP_HSMMC_SYSCTL 0x012C
51#define OMAP_HSMMC_STAT 0x0130
52#define OMAP_HSMMC_IE 0x0134
53#define OMAP_HSMMC_ISE 0x0138
54#define OMAP_HSMMC_CAPA 0x0140
55
56#define VS18 (1 << 26)
57#define VS30 (1 << 25)
58#define SDVS18 (0x5 << 9)
59#define SDVS30 (0x6 << 9)
eb250826 60#define SDVS33 (0x7 << 9)
1b331e69 61#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 62#define SDVSCLR 0xFFFFF1FF
63#define SDVSDET 0x00000400
64#define AUTOIDLE 0x1
65#define SDBP (1 << 8)
66#define DTO 0xe
67#define ICE 0x1
68#define ICS 0x2
69#define CEN (1 << 2)
70#define CLKD_MASK 0x0000FFC0
71#define CLKD_SHIFT 6
72#define DTO_MASK 0x000F0000
73#define DTO_SHIFT 16
74#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 75#define BWR_ENABLE (1 << 4)
76#define BRR_ENABLE (1 << 5)
a45c6cb8
MC		 77#define INIT_STREAM (1 << 1)
78#define DP_SELECT (1 << 21)
79#define DDIR (1 << 4)
80#define DMA_EN 0x1
81#define MSBS (1 << 5)
82#define BCE (1 << 1)
83#define FOUR_BIT (1 << 1)
73153010 84#define DW8 (1 << 5)
a45c6cb8
MC		 85#define CC 0x1
86#define TC 0x02
87#define OD 0x1
88#define ERR (1 << 15)
89#define CMD_TIMEOUT (1 << 16)
90#define DATA_TIMEOUT (1 << 20)
91#define CMD_CRC (1 << 17)
92#define DATA_CRC (1 << 21)
93#define CARD_ERR (1 << 28)
94#define STAT_CLEAR 0xFFFFFFFF
95#define INIT_STREAM_CMD 0x00000000
96#define DUAL_VOLT_OCR_BIT 7
97#define SRC (1 << 25)
98#define SRD (1 << 26)
99
100/*
101 * FIXME: Most likely all the data using these _DEVID defines should come
102 * from the platform_data, or implemented in controller and slot specific
103 * functions.
104 */
105#define OMAP_MMC1_DEVID 0
106#define OMAP_MMC2_DEVID 1
f3e2f1dd 107#define OMAP_MMC3_DEVID 2
a45c6cb8 108
a45c6cb8
MC		 109#define MMC_TIMEOUT_MS 20
110#define OMAP_MMC_MASTER_CLOCK 96000000
111#define DRIVER_NAME "mmci-omap-hs"
112
113/*
114 * One controller can have multiple slots, like on some omap boards using
115 * omap.c controller driver. Luckily this is not currently done on any known
116 * omap_hsmmc.c device.
117 */
118#define mmc_slot(host) (host->pdata->slots[host->slot_id])
119
120/*
121 * MMC Host controller read/write API's
122 */
123#define OMAP_HSMMC_READ(base, reg) \
124 __raw_readl((base) + OMAP_HSMMC_##reg)
125
126#define OMAP_HSMMC_WRITE(base, reg, val) \
127 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
128
129struct mmc_omap_host {
130 struct device *dev;
131 struct mmc_host *mmc;
132 struct mmc_request *mrq;
133 struct mmc_command *cmd;
134 struct mmc_data *data;
135 struct clk *fclk;
136 struct clk *iclk;
137 struct clk *dbclk;
138 struct semaphore sem;
139 struct work_struct mmc_carddetect_work;
140 void __iomem *base;
141 resource_size_t mapbase;
142 unsigned int id;
143 unsigned int dma_len;
0ccd76d4 144 unsigned int dma_sg_idx;
a45c6cb8 145 unsigned char bus_mode;
a45c6cb8
MC		 146 u32 *buffer;
147 u32 bytesleft;
148 int suspended;
149 int irq;
150 int carddetect;
151 int use_dma, dma_ch;
f3e2f1dd 152 int dma_line_tx, dma_line_rx;
a45c6cb8
MC		 153 int slot_id;
154 int dbclk_enabled;
4a694dc9 155 int response_busy;
a45c6cb8
MC		 156 struct omap_mmc_platform_data *pdata;
157};
158
159/*
160 * Stop clock to the card
161 */
162static void omap_mmc_stop_clock(struct mmc_omap_host *host)
163{
164 OMAP_HSMMC_WRITE(host->base, SYSCTL,
165 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
166 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
167 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
168}
169
170/*
171 * Send init stream sequence to card
172 * before sending IDLE command
173 */
174static void send_init_stream(struct mmc_omap_host *host)
175{
176 int reg = 0;
177 unsigned long timeout;
178
179 disable_irq(host->irq);
180 OMAP_HSMMC_WRITE(host->base, CON,
181 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
182 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
183
184 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
185 while ((reg != CC) && time_before(jiffies, timeout))
186 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
187
188 OMAP_HSMMC_WRITE(host->base, CON,
189 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
190 enable_irq(host->irq);
191}
192
193static inline
194int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
195{
196 int r = 1;
197
198 if (host->pdata->slots[host->slot_id].get_cover_state)
199 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
200 host->slot_id);
201 return r;
202}
203
204static ssize_t
205mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
206 char *buf)
207{
208 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
209 struct mmc_omap_host *host = mmc_priv(mmc);
210
211 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
212 "open");
213}
214
215static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
216
217static ssize_t
218mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
219 char *buf)
220{
221 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
222 struct mmc_omap_host *host = mmc_priv(mmc);
223 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
224
e68fdabc 225 return sprintf(buf, "%s\n", slot.name);
a45c6cb8
MC		 226}
227
228static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
229
230/*
231 * Configure the response type and send the cmd.
232 */
233static void
234mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
235 struct mmc_data *data)
236{
237 int cmdreg = 0, resptype = 0, cmdtype = 0;
238
239 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
240 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
241 host->cmd = cmd;
242
243 /*
244 * Clear status bits and enable interrupts
245 */
246 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
247 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
ccdfe3a6
AG		 248
249 if (host->use_dma)
250 OMAP_HSMMC_WRITE(host->base, IE,
251 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
252 else
253 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8 254
4a694dc9 255 host->response_busy = 0;
a45c6cb8
MC		 256 if (cmd->flags & MMC_RSP_PRESENT) {
257 if (cmd->flags & MMC_RSP_136)
258 resptype = 1;
4a694dc9
AH		 259 else if (cmd->flags & MMC_RSP_BUSY) {
260 resptype = 3;
261 host->response_busy = 1;
262 } else
a45c6cb8
MC		 263 resptype = 2;
264 }
265
266 /*
267 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
268 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
269 * a val of 0x3, rest 0x0.
270 */
271 if (cmd == host->mrq->stop)
272 cmdtype = 0x3;
273
274 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
275
276 if (data) {
277 cmdreg |= DP_SELECT | MSBS | BCE;
278 if (data->flags & MMC_DATA_READ)
279 cmdreg |= DDIR;
280 else
281 cmdreg &= ~(DDIR);
282 }
283
284 if (host->use_dma)
285 cmdreg |= DMA_EN;
286
287 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
288 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
289}
290
0ccd76d4
JY		 291static int
292mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
293{
294 if (data->flags & MMC_DATA_WRITE)
295 return DMA_TO_DEVICE;
296 else
297 return DMA_FROM_DEVICE;
298}
299
a45c6cb8
MC		 300/*
301 * Notify the transfer complete to MMC core
302 */
303static void
304mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
305{
4a694dc9
AH		 306 if (!data) {
307 struct mmc_request *mrq = host->mrq;
308
309 host->mrq = NULL;
4a694dc9
AH		 310 mmc_request_done(host->mmc, mrq);
311 return;
312 }
313
a45c6cb8
MC		 314 host->data = NULL;
315
316 if (host->use_dma && host->dma_ch != -1)
317 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
0ccd76d4 318 mmc_omap_get_dma_dir(host, data));
a45c6cb8
MC		 319
320 if (!data->error)
321 data->bytes_xfered += data->blocks * (data->blksz);
322 else
323 data->bytes_xfered = 0;
324
325 if (!data->stop) {
326 host->mrq = NULL;
327 mmc_request_done(host->mmc, data->mrq);
328 return;
329 }
330 mmc_omap_start_command(host, data->stop, NULL);
331}
332
333/*
334 * Notify the core about command completion
335 */
336static void
337mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
338{
339 host->cmd = NULL;
340
341 if (cmd->flags & MMC_RSP_PRESENT) {
342 if (cmd->flags & MMC_RSP_136) {
343 /* response type 2 */
344 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
345 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
346 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
347 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
348 } else {
349 /* response types 1, 1b, 3, 4, 5, 6 */
350 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
351 }
352 }
4a694dc9 353 if ((host->data == NULL && !host->response_busy) || cmd->error) {
a45c6cb8
MC		 354 host->mrq = NULL;
355 mmc_request_done(host->mmc, cmd->mrq);
356 }
357}
358
359/*
360 * DMA clean up for command errors
361 */
82788ff5 362static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
a45c6cb8 363{
82788ff5 364 host->data->error = errno;
a45c6cb8
MC		 365
366 if (host->use_dma && host->dma_ch != -1) {
367 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
0ccd76d4 368 mmc_omap_get_dma_dir(host, host->data));
a45c6cb8
MC		 369 omap_free_dma(host->dma_ch);
370 host->dma_ch = -1;
371 up(&host->sem);
372 }
373 host->data = NULL;
a45c6cb8
MC		 374}
375
376/*
377 * Readable error output
378 */
379#ifdef CONFIG_MMC_DEBUG
380static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
381{
382 /* --- means reserved bit without definition at documentation */
383 static const char *mmc_omap_status_bits[] = {
384 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
385 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
386 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
387 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
388 };
389 char res[256];
390 char *buf = res;
391 int len, i;
392
393 len = sprintf(buf, "MMC IRQ 0x%x :", status);
394 buf += len;
395
396 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
397 if (status & (1 << i)) {
398 len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
399 buf += len;
400 }
401
402 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
403}
404#endif /* CONFIG_MMC_DEBUG */
405
3ebf74b1
JP		 406/*
407 * MMC controller internal state machines reset
408 *
409 * Used to reset command or data internal state machines, using respectively
410 * SRC or SRD bit of SYSCTL register
411 * Can be called from interrupt context
412 */
413static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
414 unsigned long bit)
415{
416 unsigned long i = 0;
417 unsigned long limit = (loops_per_jiffy *
418 msecs_to_jiffies(MMC_TIMEOUT_MS));
419
420 OMAP_HSMMC_WRITE(host->base, SYSCTL,
421 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
422
423 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
424 (i++ < limit))
425 cpu_relax();
426
427 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
428 dev_err(mmc_dev(host->mmc),
429 "Timeout waiting on controller reset in %s\n",
430 __func__);
431}
a45c6cb8
MC		 432
433/*
434 * MMC controller IRQ handler
435 */
436static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
437{
438 struct mmc_omap_host *host = dev_id;
439 struct mmc_data *data;
440 int end_cmd = 0, end_trans = 0, status;
441
4a694dc9 442 if (host->mrq == NULL) {
a45c6cb8
MC		 443 OMAP_HSMMC_WRITE(host->base, STAT,
444 OMAP_HSMMC_READ(host->base, STAT));
00adadc1
KH		 445 /* Flush posted write */
446 OMAP_HSMMC_READ(host->base, STAT);
a45c6cb8
MC		 447 return IRQ_HANDLED;
448 }
449
450 data = host->data;
451 status = OMAP_HSMMC_READ(host->base, STAT);
452 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
453
454 if (status & ERR) {
455#ifdef CONFIG_MMC_DEBUG
456 mmc_omap_report_irq(host, status);
457#endif
458 if ((status & CMD_TIMEOUT) ||
459 (status & CMD_CRC)) {
460 if (host->cmd) {
461 if (status & CMD_TIMEOUT) {
3ebf74b1 462 mmc_omap_reset_controller_fsm(host, SRC);
a45c6cb8
MC		 463 host->cmd->error = -ETIMEDOUT;
464 } else {
465 host->cmd->error = -EILSEQ;
466 }
467 end_cmd = 1;
468 }
4a694dc9
AH		 469 if (host->data || host->response_busy) {
470 if (host->data)
471 mmc_dma_cleanup(host, -ETIMEDOUT);
472 host->response_busy = 0;
3ebf74b1 473 mmc_omap_reset_controller_fsm(host, SRD);
c232f457 474 }
a45c6cb8
MC		 475 }
476 if ((status & DATA_TIMEOUT) ||
477 (status & DATA_CRC)) {
4a694dc9
AH		 478 if (host->data || host->response_busy) {
479 int err = (status & DATA_TIMEOUT) ?
480 -ETIMEDOUT : -EILSEQ;
481
482 if (host->data)
483 mmc_dma_cleanup(host, err);
a45c6cb8 484 else
4a694dc9
AH		 485 host->mrq->cmd->error = err;
486 host->response_busy = 0;
3ebf74b1 487 mmc_omap_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 488 end_trans = 1;
489 }
490 }
491 if (status & CARD_ERR) {
492 dev_dbg(mmc_dev(host->mmc),
493 "Ignoring card err CMD%d\n", host->cmd->opcode);
494 if (host->cmd)
495 end_cmd = 1;
496 if (host->data)
497 end_trans = 1;
498 }
499 }
500
501 OMAP_HSMMC_WRITE(host->base, STAT, status);
00adadc1
KH		 502 /* Flush posted write */
503 OMAP_HSMMC_READ(host->base, STAT);
a45c6cb8 504
a8fe29d8 505 if (end_cmd || ((status & CC) && host->cmd))
a45c6cb8
MC		 506 mmc_omap_cmd_done(host, host->cmd);
507 if (end_trans || (status & TC))
508 mmc_omap_xfer_done(host, data);
509
510 return IRQ_HANDLED;
511}
512
e13bb300
AH		 513static void set_sd_bus_power(struct mmc_omap_host *host)
514{
515 unsigned long i;
516
517 OMAP_HSMMC_WRITE(host->base, HCTL,
518 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
519 for (i = 0; i < loops_per_jiffy; i++) {
520 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
521 break;
522 cpu_relax();
523 }
524}
525
a45c6cb8 526/*
eb250826
DB		 527 * Switch MMC interface voltage ... only relevant for MMC1.
528 *
529 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
530 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
531 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8
MC		 532 */
533static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
534{
535 u32 reg_val = 0;
536 int ret;
537
538 /* Disable the clocks */
539 clk_disable(host->fclk);
540 clk_disable(host->iclk);
541 clk_disable(host->dbclk);
542
543 /* Turn the power off */
544 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
545 if (ret != 0)
546 goto err;
547
548 /* Turn the power ON with given VDD 1.8 or 3.0v */
549 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
550 if (ret != 0)
551 goto err;
552
553 clk_enable(host->fclk);
554 clk_enable(host->iclk);
555 clk_enable(host->dbclk);
556
557 OMAP_HSMMC_WRITE(host->base, HCTL,
558 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
559 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 560
a45c6cb8
MC		 561 /*
562 * If a MMC dual voltage card is detected, the set_ios fn calls
563 * this fn with VDD bit set for 1.8V. Upon card removal from the
564 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
565 *
eb250826
DB		 566 * Cope with a bit of slop in the range ... per data sheets:
567 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
568 * but recommended values are 1.71V to 1.89V
569 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
570 * but recommended values are 2.7V to 3.3V
571 *
572 * Board setup code shouldn't permit anything very out-of-range.
573 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
574 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 575 */
eb250826 576 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 577 reg_val |= SDVS18;
eb250826
DB		 578 else
579 reg_val |= SDVS30;
a45c6cb8
MC		 580
581 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 582 set_sd_bus_power(host);
a45c6cb8
MC		 583
584 return 0;
585err:
586 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
587 return ret;
588}
589
590/*
591 * Work Item to notify the core about card insertion/removal
592 */
593static void mmc_omap_detect(struct work_struct *work)
594{
595 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
596 mmc_carddetect_work);
249d0fa9
DB		 597 struct omap_mmc_slot_data *slot = &mmc_slot(host);
598
e1a55f5e
AH		 599 if (mmc_slot(host).card_detect)
600 host->carddetect = slot->card_detect(slot->card_detect_irq);
601 else
602 host->carddetect = -ENOSYS;
a45c6cb8
MC		 603
604 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
605 if (host->carddetect) {
606 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
607 } else {
5e2ea617 608 mmc_host_enable(host->mmc);
3ebf74b1 609 mmc_omap_reset_controller_fsm(host, SRD);
5e2ea617 610 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 611 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
612 }
613}
614
615/*
616 * ISR for handling card insertion and removal
617 */
618static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
619{
620 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
621
a45c6cb8
MC		 622 schedule_work(&host->mmc_carddetect_work);
623
624 return IRQ_HANDLED;
625}
626
0ccd76d4
JY		 627static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
628 struct mmc_data *data)
629{
630 int sync_dev;
631
f3e2f1dd
GI		 632 if (data->flags & MMC_DATA_WRITE)
633 sync_dev = host->dma_line_tx;
634 else
635 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 636 return sync_dev;
637}
638
639static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
640 struct mmc_data *data,
641 struct scatterlist *sgl)
642{
643 int blksz, nblk, dma_ch;
644
645 dma_ch = host->dma_ch;
646 if (data->flags & MMC_DATA_WRITE) {
647 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
648 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
649 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
650 sg_dma_address(sgl), 0, 0);
651 } else {
652 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
653 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
654 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
655 sg_dma_address(sgl), 0, 0);
656 }
657
658 blksz = host->data->blksz;
659 nblk = sg_dma_len(sgl) / blksz;
660
661 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
662 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
663 mmc_omap_get_dma_sync_dev(host, data),
664 !(data->flags & MMC_DATA_WRITE));
665
666 omap_start_dma(dma_ch);
667}
668
a45c6cb8
MC		 669/*
670 * DMA call back function
671 */
672static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
673{
674 struct mmc_omap_host *host = data;
675
676 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
677 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
678
679 if (host->dma_ch < 0)
680 return;
681
0ccd76d4
JY		 682 host->dma_sg_idx++;
683 if (host->dma_sg_idx < host->dma_len) {
684 /* Fire up the next transfer. */
685 mmc_omap_config_dma_params(host, host->data,
686 host->data->sg + host->dma_sg_idx);
687 return;
688 }
689
a45c6cb8
MC		 690 omap_free_dma(host->dma_ch);
691 host->dma_ch = -1;
692 /*
693 * DMA Callback: run in interrupt context.
85b84322 694 * mutex_unlock will throw a kernel warning if used.
a45c6cb8
MC		 695 */
696 up(&host->sem);
697}
698
a45c6cb8
MC		 699/*
700 * Routine to configure and start DMA for the MMC card
701 */
702static int
703mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
704{
0ccd76d4 705 int dma_ch = 0, ret = 0, err = 1, i;
a45c6cb8
MC		 706 struct mmc_data *data = req->data;
707
0ccd76d4
JY		 708 /* Sanity check: all the SG entries must be aligned by block size. */
709 for (i = 0; i < host->dma_len; i++) {
710 struct scatterlist *sgl;
711
712 sgl = data->sg + i;
713 if (sgl->length % data->blksz)
714 return -EINVAL;
715 }
716 if ((data->blksz % 4) != 0)
717 /* REVISIT: The MMC buffer increments only when MSB is written.
718 * Return error for blksz which is non multiple of four.
719 */
720 return -EINVAL;
721
a45c6cb8
MC		 722 /*
723 * If for some reason the DMA transfer is still active,
724 * we wait for timeout period and free the dma
725 */
726 if (host->dma_ch != -1) {
727 set_current_state(TASK_UNINTERRUPTIBLE);
728 schedule_timeout(100);
729 if (down_trylock(&host->sem)) {
730 omap_free_dma(host->dma_ch);
731 host->dma_ch = -1;
732 up(&host->sem);
733 return err;
734 }
735 } else {
736 if (down_trylock(&host->sem))
737 return err;
738 }
739
0ccd76d4
JY		 740 ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
741 mmc_omap_dma_cb,host, &dma_ch);
a45c6cb8 742 if (ret != 0) {
0ccd76d4 743 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 744 "%s: omap_request_dma() failed with %d\n",
745 mmc_hostname(host->mmc), ret);
746 return ret;
747 }
748
749 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
0ccd76d4 750 data->sg_len, mmc_omap_get_dma_dir(host, data));
a45c6cb8 751 host->dma_ch = dma_ch;
0ccd76d4 752 host->dma_sg_idx = 0;
a45c6cb8 753
0ccd76d4 754 mmc_omap_config_dma_params(host, data, data->sg);
a45c6cb8 755
a45c6cb8
MC		 756 return 0;
757}
758
759static void set_data_timeout(struct mmc_omap_host *host,
760 struct mmc_request *req)
761{
762 unsigned int timeout, cycle_ns;
763 uint32_t reg, clkd, dto = 0;
764
765 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
766 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
767 if (clkd == 0)
768 clkd = 1;
769
770 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
771 timeout = req->data->timeout_ns / cycle_ns;
772 timeout += req->data->timeout_clks;
773 if (timeout) {
774 while ((timeout & 0x80000000) == 0) {
775 dto += 1;
776 timeout <<= 1;
777 }
778 dto = 31 - dto;
779 timeout <<= 1;
780 if (timeout && dto)
781 dto += 1;
782 if (dto >= 13)
783 dto -= 13;
784 else
785 dto = 0;
786 if (dto > 14)
787 dto = 14;
788 }
789
790 reg &= ~DTO_MASK;
791 reg |= dto << DTO_SHIFT;
792 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
793}
794
795/*
796 * Configure block length for MMC/SD cards and initiate the transfer.
797 */
798static int
799mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
800{
801 int ret;
802 host->data = req->data;
803
804 if (req->data == NULL) {
a45c6cb8
MC		 805 OMAP_HSMMC_WRITE(host->base, BLK, 0);
806 return 0;
807 }
808
809 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
810 | (req->data->blocks << 16));
811 set_data_timeout(host, req);
812
a45c6cb8
MC		 813 if (host->use_dma) {
814 ret = mmc_omap_start_dma_transfer(host, req);
815 if (ret != 0) {
816 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
817 return ret;
818 }
819 }
820 return 0;
821}
822
5e2ea617
AH		 823static int omap_mmc_enable(struct mmc_host *mmc)
824{
825 struct mmc_omap_host *host = mmc_priv(mmc);
826 int err;
827
828 err = clk_enable(host->fclk);
829 if (err)
830 return err;
831 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
832 return 0;
833}
834
835static int omap_mmc_disable(struct mmc_host *mmc, int lazy)
836{
837 struct mmc_omap_host *host = mmc_priv(mmc);
838
839 clk_disable(host->fclk);
840 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
841 return 0;
842}
843
a45c6cb8
MC		 844/*
845 * Request function. for read/write operation
846 */
847static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
848{
849 struct mmc_omap_host *host = mmc_priv(mmc);
850
851 WARN_ON(host->mrq != NULL);
852 host->mrq = req;
853 mmc_omap_prepare_data(host, req);
854 mmc_omap_start_command(host, req->cmd, req->data);
855}
856
857
858/* Routine to configure clock values. Exposed API to core */
859static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
860{
861 struct mmc_omap_host *host = mmc_priv(mmc);
862 u16 dsor = 0;
863 unsigned long regval;
864 unsigned long timeout;
73153010 865 u32 con;
a45c6cb8 866
5e2ea617
AH		 867 mmc_host_enable(host->mmc);
868
a45c6cb8
MC		 869 switch (ios->power_mode) {
870 case MMC_POWER_OFF:
871 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 872 break;
873 case MMC_POWER_UP:
874 mmc_slot(host).set_power(host->dev, host->slot_id, 1, ios->vdd);
875 break;
876 }
877
73153010 878 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 879 switch (mmc->ios.bus_width) {
73153010
JL		 880 case MMC_BUS_WIDTH_8:
881 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
882 break;
a45c6cb8 883 case MMC_BUS_WIDTH_4:
73153010 884 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 885 OMAP_HSMMC_WRITE(host->base, HCTL,
886 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
887 break;
888 case MMC_BUS_WIDTH_1:
73153010 889 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 890 OMAP_HSMMC_WRITE(host->base, HCTL,
891 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
892 break;
893 }
894
895 if (host->id == OMAP_MMC1_DEVID) {
eb250826
DB		 896 /* Only MMC1 can interface at 3V without some flavor
897 * of external transceiver; but they all handle 1.8V.
898 */
a45c6cb8
MC		 899 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
900 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
901 /*
902 * The mmc_select_voltage fn of the core does
903 * not seem to set the power_mode to
904 * MMC_POWER_UP upon recalculating the voltage.
905 * vdd 1.8v.
906 */
907 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
908 dev_dbg(mmc_dev(host->mmc),
909 "Switch operation failed\n");
910 }
911 }
912
913 if (ios->clock) {
914 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
915 if (dsor < 1)
916 dsor = 1;
917
918 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
919 dsor++;
920
921 if (dsor > 250)
922 dsor = 250;
923 }
924 omap_mmc_stop_clock(host);
925 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
926 regval = regval & ~(CLKD_MASK);
927 regval = regval | (dsor << 6) | (DTO << 16);
928 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
929 OMAP_HSMMC_WRITE(host->base, SYSCTL,
930 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
931
932 /* Wait till the ICS bit is set */
933 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
934 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
935 && time_before(jiffies, timeout))
936 msleep(1);
937
938 OMAP_HSMMC_WRITE(host->base, SYSCTL,
939 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
940
941 if (ios->power_mode == MMC_POWER_ON)
942 send_init_stream(host);
943
944 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
945 OMAP_HSMMC_WRITE(host->base, CON,
946 OMAP_HSMMC_READ(host->base, CON) | OD);
5e2ea617
AH		 947
948 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 949}
950
951static int omap_hsmmc_get_cd(struct mmc_host *mmc)
952{
953 struct mmc_omap_host *host = mmc_priv(mmc);
954 struct omap_mmc_platform_data *pdata = host->pdata;
955
956 if (!pdata->slots[0].card_detect)
957 return -ENOSYS;
958 return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
959}
960
961static int omap_hsmmc_get_ro(struct mmc_host *mmc)
962{
963 struct mmc_omap_host *host = mmc_priv(mmc);
964 struct omap_mmc_platform_data *pdata = host->pdata;
965
966 if (!pdata->slots[0].get_ro)
967 return -ENOSYS;
968 return pdata->slots[0].get_ro(host->dev, 0);
969}
970
1b331e69
KK		 971static void omap_hsmmc_init(struct mmc_omap_host *host)
972{
973 u32 hctl, capa, value;
974
975 /* Only MMC1 supports 3.0V */
976 if (host->id == OMAP_MMC1_DEVID) {
977 hctl = SDVS30;
978 capa = VS30 | VS18;
979 } else {
980 hctl = SDVS18;
981 capa = VS18;
982 }
983
984 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
985 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
986
987 value = OMAP_HSMMC_READ(host->base, CAPA);
988 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
989
990 /* Set the controller to AUTO IDLE mode */
991 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
992 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
993
994 /* Set SD bus power bit */
e13bb300 995 set_sd_bus_power(host);
1b331e69
KK		 996}
997
a45c6cb8 998static struct mmc_host_ops mmc_omap_ops = {
5e2ea617
AH		 999 .enable = omap_mmc_enable,
1000 .disable = omap_mmc_disable,
a45c6cb8
MC		 1001 .request = omap_mmc_request,
1002 .set_ios = omap_mmc_set_ios,
1003 .get_cd = omap_hsmmc_get_cd,
1004 .get_ro = omap_hsmmc_get_ro,
1005 /* NYET -- enable_sdio_irq */
1006};
1007
d900f712
DK		 1008#ifdef CONFIG_DEBUG_FS
1009
1010static int mmc_regs_show(struct seq_file *s, void *data)
1011{
1012 struct mmc_host *mmc = s->private;
1013 struct mmc_omap_host *host = mmc_priv(mmc);
1014
5e2ea617
AH		 1015 seq_printf(s, "mmc%d:\n"
1016 " enabled:\t%d\n"
1017 " nesting_cnt:\t%d\n"
1018 "\nregs:\n",
1019 mmc->index, mmc->enabled ? 1 : 0, mmc->nesting_cnt);
1020
1021 if (clk_enable(host->fclk) != 0) {
1022 seq_printf(s, "can't read the regs\n");
1023 goto err;
1024 }
d900f712
DK		 1025
1026 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1027 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1028 seq_printf(s, "CON:\t\t0x%08x\n",
1029 OMAP_HSMMC_READ(host->base, CON));
1030 seq_printf(s, "HCTL:\t\t0x%08x\n",
1031 OMAP_HSMMC_READ(host->base, HCTL));
1032 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1033 OMAP_HSMMC_READ(host->base, SYSCTL));
1034 seq_printf(s, "IE:\t\t0x%08x\n",
1035 OMAP_HSMMC_READ(host->base, IE));
1036 seq_printf(s, "ISE:\t\t0x%08x\n",
1037 OMAP_HSMMC_READ(host->base, ISE));
1038 seq_printf(s, "CAPA:\t\t0x%08x\n",
1039 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1040
1041 clk_disable(host->fclk);
1042err:
d900f712
DK		 1043 return 0;
1044}
1045
1046static int mmc_regs_open(struct inode *inode, struct file *file)
1047{
1048 return single_open(file, mmc_regs_show, inode->i_private);
1049}
1050
1051static const struct file_operations mmc_regs_fops = {
1052 .open = mmc_regs_open,
1053 .read = seq_read,
1054 .llseek = seq_lseek,
1055 .release = single_release,
1056};
1057
1058static void omap_mmc_debugfs(struct mmc_host *mmc)
1059{
1060 if (mmc->debugfs_root)
1061 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1062 mmc, &mmc_regs_fops);
1063}
1064
1065#else
1066
1067static void omap_mmc_debugfs(struct mmc_host *mmc)
1068{
1069}
1070
1071#endif
1072
a45c6cb8
MC		 1073static int __init omap_mmc_probe(struct platform_device *pdev)
1074{
1075 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1076 struct mmc_host *mmc;
1077 struct mmc_omap_host *host = NULL;
1078 struct resource *res;
1079 int ret = 0, irq;
a45c6cb8
MC		 1080
1081 if (pdata == NULL) {
1082 dev_err(&pdev->dev, "Platform Data is missing\n");
1083 return -ENXIO;
1084 }
1085
1086 if (pdata->nr_slots == 0) {
1087 dev_err(&pdev->dev, "No Slots\n");
1088 return -ENXIO;
1089 }
1090
1091 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1092 irq = platform_get_irq(pdev, 0);
1093 if (res == NULL || irq < 0)
1094 return -ENXIO;
1095
1096 res = request_mem_region(res->start, res->end - res->start + 1,
1097 pdev->name);
1098 if (res == NULL)
1099 return -EBUSY;
1100
1101 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1102 if (!mmc) {
1103 ret = -ENOMEM;
1104 goto err;
1105 }
1106
1107 host = mmc_priv(mmc);
1108 host->mmc = mmc;
1109 host->pdata = pdata;
1110 host->dev = &pdev->dev;
1111 host->use_dma = 1;
1112 host->dev->dma_mask = &pdata->dma_mask;
1113 host->dma_ch = -1;
1114 host->irq = irq;
1115 host->id = pdev->id;
1116 host->slot_id = 0;
1117 host->mapbase = res->start;
1118 host->base = ioremap(host->mapbase, SZ_4K);
1119
1120 platform_set_drvdata(pdev, host);
1121 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1122
1123 mmc->ops = &mmc_omap_ops;
1124 mmc->f_min = 400000;
1125 mmc->f_max = 52000000;
1126
1127 sema_init(&host->sem, 1);
1128
6f7607cc 1129 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 1130 if (IS_ERR(host->iclk)) {
1131 ret = PTR_ERR(host->iclk);
1132 host->iclk = NULL;
1133 goto err1;
1134 }
6f7607cc 1135 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1136 if (IS_ERR(host->fclk)) {
1137 ret = PTR_ERR(host->fclk);
1138 host->fclk = NULL;
1139 clk_put(host->iclk);
1140 goto err1;
1141 }
1142
5e2ea617
AH		 1143 mmc->caps |= MMC_CAP_DISABLE;
1144 mmc_set_disable_delay(mmc, 100);
1145 if (mmc_host_enable(host->mmc) != 0) {
a45c6cb8
MC		 1146 clk_put(host->iclk);
1147 clk_put(host->fclk);
1148 goto err1;
1149 }
1150
1151 if (clk_enable(host->iclk) != 0) {
5e2ea617 1152 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1153 clk_put(host->iclk);
1154 clk_put(host->fclk);
1155 goto err1;
1156 }
1157
1158 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1159 /*
1160 * MMC can still work without debounce clock.
1161 */
1162 if (IS_ERR(host->dbclk))
1163 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1164 else
1165 if (clk_enable(host->dbclk) != 0)
1166 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1167 " clk failed\n");
1168 else
1169 host->dbclk_enabled = 1;
1170
0ccd76d4
JY		 1171 /* Since we do only SG emulation, we can have as many segs
1172 * as we want. */
1173 mmc->max_phys_segs = 1024;
1174 mmc->max_hw_segs = 1024;
1175
a45c6cb8
MC		 1176 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1177 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1178 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1179 mmc->max_seg_size = mmc->max_req_size;
1180
a45c6cb8
MC		 1181 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1182
73153010
JL		 1183 if (pdata->slots[host->slot_id].wires >= 8)
1184 mmc->caps |= MMC_CAP_8_BIT_DATA;
1185 else if (pdata->slots[host->slot_id].wires >= 4)
a45c6cb8
MC		 1186 mmc->caps |= MMC_CAP_4_BIT_DATA;
1187
1b331e69 1188 omap_hsmmc_init(host);
a45c6cb8 1189
f3e2f1dd
GI		 1190 /* Select DMA lines */
1191 switch (host->id) {
1192 case OMAP_MMC1_DEVID:
1193 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1194 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1195 break;
1196 case OMAP_MMC2_DEVID:
1197 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1198 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1199 break;
1200 case OMAP_MMC3_DEVID:
1201 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1202 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1203 break;
1204 default:
1205 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1206 goto err_irq;
1207 }
a45c6cb8
MC		 1208
1209 /* Request IRQ for MMC operations */
1210 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1211 mmc_hostname(mmc), host);
1212 if (ret) {
1213 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1214 goto err_irq;
1215 }
1216
b583f26d 1217 /* initialize power supplies, gpios, etc */
a45c6cb8
MC		 1218 if (pdata->init != NULL) {
1219 if (pdata->init(&pdev->dev) != 0) {
b583f26d 1220 dev_dbg(mmc_dev(host->mmc), "late init error\n");
a45c6cb8
MC		 1221 goto err_irq_cd_init;
1222 }
1223 }
b583f26d 1224 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1225
1226 /* Request IRQ for card detect */
e1a55f5e 1227 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8
MC		 1228 ret = request_irq(mmc_slot(host).card_detect_irq,
1229 omap_mmc_cd_handler,
1230 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1231 | IRQF_DISABLED,
1232 mmc_hostname(mmc), host);
1233 if (ret) {
1234 dev_dbg(mmc_dev(host->mmc),
1235 "Unable to grab MMC CD IRQ\n");
1236 goto err_irq_cd;
1237 }
1238 }
1239
1240 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1241 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1242
5e2ea617
AH		 1243 mmc_host_lazy_disable(host->mmc);
1244
a45c6cb8
MC		 1245 mmc_add_host(mmc);
1246
1247 if (host->pdata->slots[host->slot_id].name != NULL) {
1248 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1249 if (ret < 0)
1250 goto err_slot_name;
1251 }
e1a55f5e
AH		 1252 if (mmc_slot(host).card_detect_irq &&
1253 host->pdata->slots[host->slot_id].get_cover_state) {
a45c6cb8
MC		 1254 ret = device_create_file(&mmc->class_dev,
1255 &dev_attr_cover_switch);
1256 if (ret < 0)
1257 goto err_cover_switch;
1258 }
1259
d900f712
DK		 1260 omap_mmc_debugfs(mmc);
1261
a45c6cb8
MC		 1262 return 0;
1263
1264err_cover_switch:
1265 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1266err_slot_name:
1267 mmc_remove_host(mmc);
1268err_irq_cd:
1269 free_irq(mmc_slot(host).card_detect_irq, host);
1270err_irq_cd_init:
1271 free_irq(host->irq, host);
1272err_irq:
5e2ea617 1273 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1274 clk_disable(host->iclk);
1275 clk_put(host->fclk);
1276 clk_put(host->iclk);
1277 if (host->dbclk_enabled) {
1278 clk_disable(host->dbclk);
1279 clk_put(host->dbclk);
1280 }
1281
1282err1:
1283 iounmap(host->base);
1284err:
1285 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1286 release_mem_region(res->start, res->end - res->start + 1);
1287 if (host)
1288 mmc_free_host(mmc);
1289 return ret;
1290}
1291
1292static int omap_mmc_remove(struct platform_device *pdev)
1293{
1294 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1295 struct resource *res;
1296
1297 if (host) {
5e2ea617 1298 mmc_host_enable(host->mmc);
a45c6cb8
MC		 1299 mmc_remove_host(host->mmc);
1300 if (host->pdata->cleanup)
1301 host->pdata->cleanup(&pdev->dev);
1302 free_irq(host->irq, host);
1303 if (mmc_slot(host).card_detect_irq)
1304 free_irq(mmc_slot(host).card_detect_irq, host);
1305 flush_scheduled_work();
1306
5e2ea617 1307 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1308 clk_disable(host->iclk);
1309 clk_put(host->fclk);
1310 clk_put(host->iclk);
1311 if (host->dbclk_enabled) {
1312 clk_disable(host->dbclk);
1313 clk_put(host->dbclk);
1314 }
1315
1316 mmc_free_host(host->mmc);
1317 iounmap(host->base);
1318 }
1319
1320 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1321 if (res)
1322 release_mem_region(res->start, res->end - res->start + 1);
1323 platform_set_drvdata(pdev, NULL);
1324
1325 return 0;
1326}
1327
1328#ifdef CONFIG_PM
1329static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1330{
1331 int ret = 0;
1332 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1333
1334 if (host && host->suspended)
1335 return 0;
1336
1337 if (host) {
5e2ea617 1338 mmc_host_enable(host->mmc);
a45c6cb8
MC		 1339 ret = mmc_suspend_host(host->mmc, state);
1340 if (ret == 0) {
1341 host->suspended = 1;
1342
1343 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1344 OMAP_HSMMC_WRITE(host->base, IE, 0);
1345
1346 if (host->pdata->suspend) {
1347 ret = host->pdata->suspend(&pdev->dev,
1348 host->slot_id);
1349 if (ret)
1350 dev_dbg(mmc_dev(host->mmc),
1351 "Unable to handle MMC board"
1352 " level suspend\n");
1353 }
1354
0683af48
JL		 1355 OMAP_HSMMC_WRITE(host->base, HCTL,
1356 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 1357 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1358 clk_disable(host->iclk);
1359 clk_disable(host->dbclk);
5e2ea617
AH		 1360 } else
1361 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1362
1363 }
1364 return ret;
1365}
1366
1367/* Routine to resume the MMC device */
1368static int omap_mmc_resume(struct platform_device *pdev)
1369{
1370 int ret = 0;
1371 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1372
1373 if (host && !host->suspended)
1374 return 0;
1375
1376 if (host) {
1377
5e2ea617 1378 if (mmc_host_enable(host->mmc) != 0)
a45c6cb8
MC		 1379 goto clk_en_err;
1380
1381 ret = clk_enable(host->iclk);
1382 if (ret) {
5e2ea617 1383 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1384 clk_put(host->fclk);
1385 goto clk_en_err;
1386 }
1387
1388 if (clk_enable(host->dbclk) != 0)
1389 dev_dbg(mmc_dev(host->mmc),
1390 "Enabling debounce clk failed\n");
1391
1b331e69
KK		 1392 omap_hsmmc_init(host);
1393
a45c6cb8
MC		 1394 if (host->pdata->resume) {
1395 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1396 if (ret)
1397 dev_dbg(mmc_dev(host->mmc),
1398 "Unmask interrupt failed\n");
1399 }
1400
1401 /* Notify the core to resume the host */
1402 ret = mmc_resume_host(host->mmc);
1403 if (ret == 0)
1404 host->suspended = 0;
5e2ea617 1405 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1406 }
1407
1408 return ret;
1409
1410clk_en_err:
1411 dev_dbg(mmc_dev(host->mmc),
1412 "Failed to enable MMC clocks during resume\n");
1413 return ret;
1414}
1415
1416#else
1417#define omap_mmc_suspend NULL
1418#define omap_mmc_resume NULL
1419#endif
1420
1421static struct platform_driver omap_mmc_driver = {
a45c6cb8
MC		 1422 .remove = omap_mmc_remove,
1423 .suspend = omap_mmc_suspend,
1424 .resume = omap_mmc_resume,
1425 .driver = {
1426 .name = DRIVER_NAME,
1427 .owner = THIS_MODULE,
1428 },
1429};
1430
1431static int __init omap_mmc_init(void)
1432{
1433 /* Register the MMC driver */
f400cd8c 1434 return platform_driver_probe(&omap_mmc_driver, omap_mmc_probe);
a45c6cb8
MC		 1435}
1436
1437static void __exit omap_mmc_cleanup(void)
1438{
1439 /* Unregister MMC driver */
1440 platform_driver_unregister(&omap_mmc_driver);
1441}
1442
1443module_init(omap_mmc_init);
1444module_exit(omap_mmc_cleanup);
1445
1446MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1447MODULE_LICENSE("GPL");
1448MODULE_ALIAS("platform:" DRIVER_NAME);
1449MODULE_AUTHOR("Texas Instruments Inc");
Clone of davem's net-next-2.6 tree