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imxmmc: Remove unused variables
[net-next-2.6.git] / drivers / mmc / host / imxmmc.c
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56ca9040 1/*
70f10482 2 * linux/drivers/mmc/host/imxmmc.c - Motorola i.MX MMCI driver
56ca9040
PP		 3 *
4 * Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
5 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
6 *
7 * derived from pxamci.c by Russell King
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
56ca9040 13 */
56ca9040 14
56ca9040
PP		 15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/ioport.h>
18#include <linux/platform_device.h>
19#include <linux/interrupt.h>
20#include <linux/blkdev.h>
21#include <linux/dma-mapping.h>
22#include <linux/mmc/host.h>
23#include <linux/mmc/card.h>
56ca9040 24#include <linux/delay.h>
38a41fdf 25#include <linux/clk.h>
4b7c0e4c 26#include <linux/io.h>
56ca9040
PP		 27
28#include <asm/dma.h>
56ca9040
PP		 29#include <asm/irq.h>
30#include <asm/sizes.h>
a09e64fb
RK		 31#include <mach/mmc.h>
32#include <mach/imx-dma.h>
56ca9040
PP		 33
34#include "imxmmc.h"
35
36#define DRIVER_NAME "imx-mmc"
37
38#define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
4b7c0e4c
MKB		 39 INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
40 INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
56ca9040
PP		 41
42struct imxmci_host {
43 struct mmc_host *mmc;
44 spinlock_t lock;
45 struct resource *res;
46 int irq;
47 imx_dmach_t dma;
56ca9040
PP		 48 volatile unsigned int imask;
49 unsigned int power_mode;
50 unsigned int present;
51 struct imxmmc_platform_data *pdata;
52
53 struct mmc_request *req;
54 struct mmc_command *cmd;
55 struct mmc_data *data;
56
57 struct timer_list timer;
58 struct tasklet_struct tasklet;
59 unsigned int status_reg;
60 unsigned long pending_events;
4b7c0e4c 61 /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */
56ca9040
PP		 62 u16 *data_ptr;
63 unsigned int data_cnt;
64 atomic_t stuck_timeout;
65
66 unsigned int dma_nents;
67 unsigned int dma_size;
68 unsigned int dma_dir;
69 int dma_allocated;
70
71 unsigned char actual_bus_width;
148f93d5
PP		 72
73 int prev_cmd_code;
38a41fdf
SH		 74
75 struct clk *clk;
56ca9040
PP		 76};
77
78#define IMXMCI_PEND_IRQ_b 0
79#define IMXMCI_PEND_DMA_END_b 1
80#define IMXMCI_PEND_DMA_ERR_b 2
81#define IMXMCI_PEND_WAIT_RESP_b 3
82#define IMXMCI_PEND_DMA_DATA_b 4
83#define IMXMCI_PEND_CPU_DATA_b 5
84#define IMXMCI_PEND_CARD_XCHG_b 6
85#define IMXMCI_PEND_SET_INIT_b 7
81d38428 86#define IMXMCI_PEND_STARTED_b 8
56ca9040
PP		 87
88#define IMXMCI_PEND_IRQ_m (1 << IMXMCI_PEND_IRQ_b)
89#define IMXMCI_PEND_DMA_END_m (1 << IMXMCI_PEND_DMA_END_b)
90#define IMXMCI_PEND_DMA_ERR_m (1 << IMXMCI_PEND_DMA_ERR_b)
91#define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
92#define IMXMCI_PEND_DMA_DATA_m (1 << IMXMCI_PEND_DMA_DATA_b)
93#define IMXMCI_PEND_CPU_DATA_m (1 << IMXMCI_PEND_CPU_DATA_b)
94#define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
95#define IMXMCI_PEND_SET_INIT_m (1 << IMXMCI_PEND_SET_INIT_b)
81d38428 96#define IMXMCI_PEND_STARTED_m (1 << IMXMCI_PEND_STARTED_b)
56ca9040
PP		 97
98static void imxmci_stop_clock(struct imxmci_host *host)
99{
100 int i = 0;
101 MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK;
4b7c0e4c
MKB		 102 while (i < 0x1000) {
103 if (!(i & 0x7f))
56ca9040
PP		 104 MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK;
105
4b7c0e4c 106 if (!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
56ca9040 107 /* Check twice before cut */
4b7c0e4c 108 if (!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
56ca9040
PP		 109 return;
110 }
111
112 i++;
113 }
114 dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n");
115}
116
81d38428 117static int imxmci_start_clock(struct imxmci_host *host)
56ca9040 118{
81d38428
PP		 119 unsigned int trials = 0;
120 unsigned int delay_limit = 128;
121 unsigned long flags;
122
56ca9040 123 MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK;
56ca9040 124
81d38428
PP		 125 clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
126
127 /*
128 * Command start of the clock, this usually succeeds in less
129 * then 6 delay loops, but during card detection (low clockrate)
130 * it takes up to 5000 delay loops and sometimes fails for the first time
131 */
132 MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
133
134 do {
135 unsigned int delay = delay_limit;
136
4b7c0e4c
MKB		 137 while (delay--) {
138 if (MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
81d38428 139 /* Check twice before cut */
4b7c0e4c 140 if (MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
81d38428
PP		 141 return 0;
142
4b7c0e4c 143 if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
81d38428 144 return 0;
56ca9040
PP		 145 }
146
81d38428
PP		 147 local_irq_save(flags);
148 /*
149 * Ensure, that request is not doubled under all possible circumstances.
150 * It is possible, that cock running state is missed, because some other
151 * IRQ or schedule delays this function execution and the clocks has
152 * been already stopped by other means (response processing, SDHC HW)
153 */
4b7c0e4c 154 if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
81d38428
PP		 155 MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
156 local_irq_restore(flags);
157
4b7c0e4c 158 } while (++trials < 256);
81d38428
PP		 159
160 dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
161
162 return -1;
56ca9040
PP		 163}
164
165static void imxmci_softreset(void)
166{
167 /* reset sequence */
168 MMC_STR_STP_CLK = 0x8;
169 MMC_STR_STP_CLK = 0xD;
170 MMC_STR_STP_CLK = 0x5;
171 MMC_STR_STP_CLK = 0x5;
172 MMC_STR_STP_CLK = 0x5;
173 MMC_STR_STP_CLK = 0x5;
174 MMC_STR_STP_CLK = 0x5;
175 MMC_STR_STP_CLK = 0x5;
176 MMC_STR_STP_CLK = 0x5;
177 MMC_STR_STP_CLK = 0x5;
178
179 MMC_RES_TO = 0xff;
180 MMC_BLK_LEN = 512;
181 MMC_NOB = 1;
182}
183
184static int imxmci_busy_wait_for_status(struct imxmci_host *host,
4b7c0e4c
MKB		 185 unsigned int *pstat, unsigned int stat_mask,
186 int timeout, const char *where)
56ca9040 187{
4b7c0e4c
MKB		 188 int loops = 0;
189
190 while (!(*pstat & stat_mask)) {
191 loops += 2;
192 if (loops >= timeout) {
56ca9040
PP		 193 dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
194 where, *pstat, stat_mask);
195 return -1;
196 }
197 udelay(2);
198 *pstat |= MMC_STATUS;
199 }
4b7c0e4c 200 if (!loops)
56ca9040
PP		 201 return 0;
202
2c171bf1 203 /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
4b7c0e4c 204 if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000))
2c171bf1 205 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
4b7c0e4c 206 loops, where, *pstat, stat_mask);
56ca9040
PP		 207 return loops;
208}
209
210static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
211{
212 unsigned int nob = data->blocks;
a3fd4a1b 213 unsigned int blksz = data->blksz;
56ca9040
PP		 214 unsigned int datasz = nob * blksz;
215 int i;
216
217 if (data->flags & MMC_DATA_STREAM)
218 nob = 0xffff;
219
220 host->data = data;
221 data->bytes_xfered = 0;
222
223 MMC_NOB = nob;
224 MMC_BLK_LEN = blksz;
225
226 /*
227 * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
228 * We are in big troubles for non-512 byte transfers according to note in the paragraph
229 * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
230 * The situation is even more complex in reality. The SDHC in not able to handle wll
231 * partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
232 * This is required for SCR read at least.
233 */
148f93d5 234 if (datasz < 512) {
56ca9040
PP		 235 host->dma_size = datasz;
236 if (data->flags & MMC_DATA_READ) {
237 host->dma_dir = DMA_FROM_DEVICE;
238
239 /* Hack to enable read SCR */
148f93d5
PP		 240 MMC_NOB = 1;
241 MMC_BLK_LEN = 512;
56ca9040
PP		 242 } else {
243 host->dma_dir = DMA_TO_DEVICE;
244 }
245
246 /* Convert back to virtual address */
4b7c0e4c 247 host->data_ptr = (u16 *)sg_virt(data->sg);
56ca9040
PP		 248 host->data_cnt = 0;
249
250 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
251 set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
252
253 return;
254 }
255
256 if (data->flags & MMC_DATA_READ) {
257 host->dma_dir = DMA_FROM_DEVICE;
258 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
4b7c0e4c 259 data->sg_len, host->dma_dir);
56ca9040
PP		 260
261 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
4b7c0e4c 262 host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
56ca9040
PP		 263
264 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
265 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
266 } else {
267 host->dma_dir = DMA_TO_DEVICE;
268
269 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
4b7c0e4c 270 data->sg_len, host->dma_dir);
56ca9040
PP		 271
272 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
4b7c0e4c 273 host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
56ca9040
PP		 274
275 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
276 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
277 }
278
279#if 1 /* This code is there only for consistency checking and can be disabled in future */
280 host->dma_size = 0;
4b7c0e4c
MKB		 281 for (i = 0; i < host->dma_nents; i++)
282 host->dma_size += data->sg[i].length;
56ca9040
PP		 283
284 if (datasz > host->dma_size) {
285 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
4b7c0e4c 286 datasz, host->dma_size);
56ca9040
PP		 287 }
288#endif
289
290 host->dma_size = datasz;
291
292 wmb();
293
4b7c0e4c 294 if (host->actual_bus_width == MMC_BUS_WIDTH_4)
56ca9040
PP		 295 BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */
296 else
297 BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */
298
299 RSSR(host->dma) = DMA_REQ_SDHC;
300
301 set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
302 clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
303
304 /* start DMA engine for read, write is delayed after initial response */
4b7c0e4c 305 if (host->dma_dir == DMA_FROM_DEVICE)
56ca9040 306 imx_dma_enable(host->dma);
56ca9040
PP		 307}
308
309static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
310{
311 unsigned long flags;
312 u32 imask;
313
314 WARN_ON(host->cmd != NULL);
315 host->cmd = cmd;
316
2c171bf1
PP		 317 /* Ensure, that clock are stopped else command programming and start fails */
318 imxmci_stop_clock(host);
319
56ca9040
PP		 320 if (cmd->flags & MMC_RSP_BUSY)
321 cmdat |= CMD_DAT_CONT_BUSY;
322
323 switch (mmc_resp_type(cmd)) {
324 case MMC_RSP_R1: /* short CRC, OPCODE */
325 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
326 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
327 break;
328 case MMC_RSP_R2: /* long 136 bit + CRC */
329 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
330 break;
331 case MMC_RSP_R3: /* short */
332 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
333 break;
56ca9040
PP		 334 default:
335 break;
336 }
337
4b7c0e4c 338 if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events))
56ca9040
PP		 339 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
340
4b7c0e4c 341 if (host->actual_bus_width == MMC_BUS_WIDTH_4)
56ca9040
PP		 342 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
343
344 MMC_CMD = cmd->opcode;
345 MMC_ARGH = cmd->arg >> 16;
346 MMC_ARGL = cmd->arg & 0xffff;
347 MMC_CMD_DAT_CONT = cmdat;
348
349 atomic_set(&host->stuck_timeout, 0);
350 set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
351
352
353 imask = IMXMCI_INT_MASK_DEFAULT;
354 imask &= ~INT_MASK_END_CMD_RES;
4b7c0e4c
MKB		 355 if (cmdat & CMD_DAT_CONT_DATA_ENABLE) {
356 /* imask &= ~INT_MASK_BUF_READY; */
56ca9040 357 imask &= ~INT_MASK_DATA_TRAN;
4b7c0e4c 358 if (cmdat & CMD_DAT_CONT_WRITE)
56ca9040 359 imask &= ~INT_MASK_WRITE_OP_DONE;
4b7c0e4c 360 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
56ca9040
PP		 361 imask &= ~INT_MASK_BUF_READY;
362 }
363
364 spin_lock_irqsave(&host->lock, flags);
365 host->imask = imask;
366 MMC_INT_MASK = host->imask;
367 spin_unlock_irqrestore(&host->lock, flags);
368
369 dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
370 cmd->opcode, cmd->opcode, imask);
371
372 imxmci_start_clock(host);
373}
374
375static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req)
376{
377 unsigned long flags;
378
379 spin_lock_irqsave(&host->lock, flags);
380
381 host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
4b7c0e4c 382 IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
56ca9040
PP		 383
384 host->imask = IMXMCI_INT_MASK_DEFAULT;
385 MMC_INT_MASK = host->imask;
386
387 spin_unlock_irqrestore(&host->lock, flags);
388
4b7c0e4c 389 if (req && req->cmd)
148f93d5
PP		 390 host->prev_cmd_code = req->cmd->opcode;
391
56ca9040
PP		 392 host->req = NULL;
393 host->cmd = NULL;
394 host->data = NULL;
395 mmc_request_done(host->mmc, req);
396}
397
398static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
399{
400 struct mmc_data *data = host->data;
401 int data_error;
402
4b7c0e4c 403 if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
56ca9040
PP		 404 imx_dma_disable(host->dma);
405 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
406 host->dma_dir);
407 }
408
4b7c0e4c
MKB		 409 if (stat & STATUS_ERR_MASK) {
410 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat);
411 if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
17b0429d 412 data->error = -EILSEQ;
4b7c0e4c 413 else if (stat & STATUS_TIME_OUT_READ)
17b0429d 414 data->error = -ETIMEDOUT;
56ca9040 415 else
17b0429d 416 data->error = -EIO;
56ca9040
PP		 417 } else {
418 data->bytes_xfered = host->dma_size;
419 }
420
421 data_error = data->error;
422
423 host->data = NULL;
424
425 return data_error;
426}
427
428static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
429{
430 struct mmc_command *cmd = host->cmd;
431 int i;
4b7c0e4c 432 u32 a, b, c;
56ca9040
PP		 433 struct mmc_data *data = host->data;
434
435 if (!cmd)
436 return 0;
437
438 host->cmd = NULL;
439
440 if (stat & STATUS_TIME_OUT_RESP) {
441 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
17b0429d 442 cmd->error = -ETIMEDOUT;
56ca9040
PP		 443 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
444 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
17b0429d 445 cmd->error = -EILSEQ;
56ca9040
PP		 446 }
447
4b7c0e4c
MKB		 448 if (cmd->flags & MMC_RSP_PRESENT) {
449 if (cmd->flags & MMC_RSP_136) {
56ca9040 450 for (i = 0; i < 4; i++) {
4b7c0e4c
MKB		 451 u32 d = MMC_RES_FIFO & 0xffff;
452 u32 e = MMC_RES_FIFO & 0xffff;
453 cmd->resp[i] = d << 16 | e;
56ca9040
PP		 454 }
455 } else {
456 a = MMC_RES_FIFO & 0xffff;
457 b = MMC_RES_FIFO & 0xffff;
458 c = MMC_RES_FIFO & 0xffff;
4b7c0e4c 459 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
56ca9040
PP		 460 }
461 }
462
463 dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
464 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
465
17b0429d 466 if (data && !cmd->error && !(stat & STATUS_ERR_MASK)) {
56ca9040
PP		 467 if (host->req->data->flags & MMC_DATA_WRITE) {
468
469 /* Wait for FIFO to be empty before starting DMA write */
470
471 stat = MMC_STATUS;
4b7c0e4c
MKB		 472 if (imxmci_busy_wait_for_status(host, &stat,
473 STATUS_APPL_BUFF_FE,
474 40, "imxmci_cmd_done DMA WR") < 0) {
17b0429d 475 cmd->error = -EIO;
56ca9040 476 imxmci_finish_data(host, stat);
4b7c0e4c 477 if (host->req)
56ca9040
PP		 478 imxmci_finish_request(host, host->req);
479 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
4b7c0e4c 480 stat);
56ca9040
PP		 481 return 0;
482 }
483
4b7c0e4c 484 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
56ca9040 485 imx_dma_enable(host->dma);
56ca9040
PP		 486 }
487 } else {
488 struct mmc_request *req;
489 imxmci_stop_clock(host);
490 req = host->req;
491
4b7c0e4c 492 if (data)
56ca9040
PP		 493 imxmci_finish_data(host, stat);
494
4b7c0e4c 495 if (req)
56ca9040 496 imxmci_finish_request(host, req);
4b7c0e4c 497 else
56ca9040 498 dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
56ca9040
PP		 499 }
500
501 return 1;
502}
503
504static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
505{
506 struct mmc_data *data = host->data;
507 int data_error;
508
509 if (!data)
510 return 0;
511
512 data_error = imxmci_finish_data(host, stat);
513
58741e8b 514 if (host->req->stop) {
56ca9040
PP		 515 imxmci_stop_clock(host);
516 imxmci_start_cmd(host, host->req->stop, 0);
517 } else {
518 struct mmc_request *req;
519 req = host->req;
4b7c0e4c 520 if (req)
56ca9040 521 imxmci_finish_request(host, req);
4b7c0e4c 522 else
56ca9040 523 dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
56ca9040
PP		 524 }
525
526 return 1;
527}
528
529static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
530{
531 int i;
532 int burst_len;
56ca9040
PP		 533 int trans_done = 0;
534 unsigned int stat = *pstat;
535
4b7c0e4c 536 if (host->actual_bus_width != MMC_BUS_WIDTH_4)
56ca9040
PP		 537 burst_len = 16;
538 else
539 burst_len = 64;
540
541 /* This is unfortunately required */
542 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
543 stat);
544
148f93d5
PP		 545 udelay(20); /* required for clocks < 8MHz*/
546
4b7c0e4c 547 if (host->dma_dir == DMA_FROM_DEVICE) {
56ca9040 548 imxmci_busy_wait_for_status(host, &stat,
4b7c0e4c
MKB		 549 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
550 STATUS_TIME_OUT_READ,
551 50, "imxmci_cpu_driven_data read");
56ca9040 552
4b7c0e4c
MKB		 553 while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
554 !(stat & STATUS_TIME_OUT_READ) &&
555 (host->data_cnt < 512)) {
148f93d5
PP		 556
557 udelay(20); /* required for clocks < 8MHz*/
56ca9040 558
4b7c0e4c 559 for (i = burst_len; i >= 2 ; i -= 2) {
148f93d5
PP		 560 u16 data;
561 data = MMC_BUFFER_ACCESS;
562 udelay(10); /* required for clocks < 8MHz*/
4b7c0e4c 563 if (host->data_cnt+2 <= host->dma_size) {
148f93d5
PP		 564 *(host->data_ptr++) = data;
565 } else {
4b7c0e4c
MKB		 566 if (host->data_cnt < host->dma_size)
567 *(u8 *)(host->data_ptr) = data;
148f93d5
PP		 568 }
569 host->data_cnt += 2;
56ca9040
PP		 570 }
571
56ca9040
PP		 572 stat = MMC_STATUS;
573
148f93d5
PP		 574 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
575 host->data_cnt, burst_len, stat);
56ca9040 576 }
148f93d5 577
4b7c0e4c 578 if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
148f93d5
PP		 579 trans_done = 1;
580
4b7c0e4c 581 if (host->dma_size & 0x1ff)
148f93d5
PP		 582 stat &= ~STATUS_CRC_READ_ERR;
583
4b7c0e4c 584 if (stat & STATUS_TIME_OUT_READ) {
2cb3320b
PP		 585 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
586 stat);
587 trans_done = -1;
588 }
589
56ca9040
PP		 590 } else {
591 imxmci_busy_wait_for_status(host, &stat,
4b7c0e4c
MKB		 592 STATUS_APPL_BUFF_FE,
593 20, "imxmci_cpu_driven_data write");
56ca9040 594
4b7c0e4c
MKB		 595 while ((stat & STATUS_APPL_BUFF_FE) &&
596 (host->data_cnt < host->dma_size)) {
597 if (burst_len >= host->dma_size - host->data_cnt) {
56ca9040
PP		 598 burst_len = host->dma_size - host->data_cnt;
599 host->data_cnt = host->dma_size;
600 trans_done = 1;
601 } else {
602 host->data_cnt += burst_len;
603 }
604
4b7c0e4c 605 for (i = burst_len; i > 0 ; i -= 2)
56ca9040
PP		 606 MMC_BUFFER_ACCESS = *(host->data_ptr++);
607
608 stat = MMC_STATUS;
609
610 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
611 burst_len, stat);
612 }
613 }
614
615 *pstat = stat;
616
617 return trans_done;
618}
619
7d12e780 620static void imxmci_dma_irq(int dma, void *devid)
56ca9040
PP		 621{
622 struct imxmci_host *host = devid;
623 uint32_t stat = MMC_STATUS;
624
625 atomic_set(&host->stuck_timeout, 0);
626 host->status_reg = stat;
627 set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
628 tasklet_schedule(&host->tasklet);
629}
630
7d12e780 631static irqreturn_t imxmci_irq(int irq, void *devid)
56ca9040
PP		 632{
633 struct imxmci_host *host = devid;
634 uint32_t stat = MMC_STATUS;
635 int handled = 1;
636
637 MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT;
638
639 atomic_set(&host->stuck_timeout, 0);
640 host->status_reg = stat;
641 set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
81d38428 642 set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
56ca9040
PP		 643 tasklet_schedule(&host->tasklet);
644
645 return IRQ_RETVAL(handled);;
646}
647
648static void imxmci_tasklet_fnc(unsigned long data)
649{
650 struct imxmci_host *host = (struct imxmci_host *)data;
651 u32 stat;
652 unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
653 int timeout = 0;
654
4b7c0e4c 655 if (atomic_read(&host->stuck_timeout) > 4) {
56ca9040
PP		 656 char *what;
657 timeout = 1;
658 stat = MMC_STATUS;
659 host->status_reg = stat;
660 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
661 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
662 what = "RESP+DMA";
663 else
664 what = "RESP";
665 else
666 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
4b7c0e4c 667 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
56ca9040
PP		 668 what = "DATA";
669 else
670 what = "DMA";
671 else
672 what = "???";
673
674 dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
4b7c0e4c 675 what, stat, MMC_INT_MASK);
56ca9040 676 dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
4b7c0e4c 677 MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
148f93d5 678 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
4b7c0e4c 679 host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1 << host->actual_bus_width, host->dma_size);
56ca9040
PP		 680 }
681
4b7c0e4c 682 if (!host->present || timeout)
56ca9040 683 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
4b7c0e4c 684 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
56ca9040 685
4b7c0e4c 686 if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
56ca9040
PP		 687 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
688
689 stat = MMC_STATUS;
690 /*
691 * This is not required in theory, but there is chance to miss some flag
692 * which clears automatically by mask write, FreeScale original code keeps
693 * stat from IRQ time so do I
694 */
695 stat |= host->status_reg;
696
4b7c0e4c 697 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
2cb3320b
PP		 698 stat &= ~STATUS_CRC_READ_ERR;
699
4b7c0e4c 700 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
56ca9040 701 imxmci_busy_wait_for_status(host, &stat,
4b7c0e4c
MKB		 702 STATUS_END_CMD_RESP | STATUS_ERR_MASK,
703 20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
56ca9040
PP		 704 }
705
4b7c0e4c
MKB		 706 if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
707 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
56ca9040 708 imxmci_cmd_done(host, stat);
4b7c0e4c 709 if (host->data && (stat & STATUS_ERR_MASK))
56ca9040
PP		 710 imxmci_data_done(host, stat);
711 }
712
4b7c0e4c 713 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
56ca9040 714 stat |= MMC_STATUS;
4b7c0e4c
MKB		 715 if (imxmci_cpu_driven_data(host, &stat)) {
716 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
56ca9040
PP		 717 imxmci_cmd_done(host, stat);
718 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
4b7c0e4c 719 &host->pending_events);
56ca9040
PP		 720 imxmci_data_done(host, stat);
721 }
722 }
723 }
724
4b7c0e4c
MKB		 725 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
726 !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
56ca9040
PP		 727
728 stat = MMC_STATUS;
729 /* Same as above */
730 stat |= host->status_reg;
731
4b7c0e4c 732 if (host->dma_dir == DMA_TO_DEVICE)
56ca9040 733 data_dir_mask = STATUS_WRITE_OP_DONE;
4b7c0e4c 734 else
56ca9040 735 data_dir_mask = STATUS_DATA_TRANS_DONE;
56ca9040 736
4b7c0e4c 737 if (stat & data_dir_mask) {
56ca9040
PP		 738 clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
739 imxmci_data_done(host, stat);
740 }
741 }
742
4b7c0e4c 743 if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
56ca9040 744
4b7c0e4c 745 if (host->cmd)
56ca9040
PP		 746 imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
747
4b7c0e4c 748 if (host->data)
56ca9040
PP		 749 imxmci_data_done(host, STATUS_TIME_OUT_READ |
750 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
751
4b7c0e4c 752 if (host->req)
56ca9040
PP		 753 imxmci_finish_request(host, host->req);
754
755 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
756
757 }
758}
759
760static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
761{
762 struct imxmci_host *host = mmc_priv(mmc);
763 unsigned int cmdat;
764
765 WARN_ON(host->req != NULL);
766
767 host->req = req;
768
769 cmdat = 0;
770
771 if (req->data) {
772 imxmci_setup_data(host, req->data);
773
774 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
775
776 if (req->data->flags & MMC_DATA_WRITE)
777 cmdat |= CMD_DAT_CONT_WRITE;
778
4b7c0e4c 779 if (req->data->flags & MMC_DATA_STREAM)
56ca9040 780 cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
56ca9040
PP		 781 }
782
783 imxmci_start_cmd(host, req->cmd, cmdat);
784}
785
786#define CLK_RATE 19200000
787
788static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
789{
790 struct imxmci_host *host = mmc_priv(mmc);
791 int prescaler;
792
4b7c0e4c 793 if (ios->bus_width == MMC_BUS_WIDTH_4) {
56ca9040
PP		 794 host->actual_bus_width = MMC_BUS_WIDTH_4;
795 imx_gpio_mode(PB11_PF_SD_DAT3);
4b7c0e4c 796 } else {
56ca9040
PP		 797 host->actual_bus_width = MMC_BUS_WIDTH_1;
798 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
799 }
800
4b7c0e4c 801 if (host->power_mode != ios->power_mode) {
56ca9040
PP		 802 switch (ios->power_mode) {
803 case MMC_POWER_OFF:
4b7c0e4c 804 break;
56ca9040
PP		 805 case MMC_POWER_UP:
806 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
4b7c0e4c 807 break;
56ca9040 808 case MMC_POWER_ON:
4b7c0e4c 809 break;
56ca9040
PP		 810 }
811 host->power_mode = ios->power_mode;
812 }
813
4b7c0e4c 814 if (ios->clock) {
56ca9040
PP		 815 unsigned int clk;
816
817 /* The prescaler is 5 for PERCLK2 equal to 96MHz
818 * then 96MHz / 5 = 19.2 MHz
819 */
38a41fdf 820 clk = clk_get_rate(host->clk);
4b7c0e4c
MKB		 821 prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE;
822 switch (prescaler) {
56ca9040
PP		 823 case 0:
824 case 1: prescaler = 0;
825 break;
826 case 2: prescaler = 1;
827 break;
828 case 3: prescaler = 2;
829 break;
830 case 4: prescaler = 4;
831 break;
832 default:
833 case 5: prescaler = 5;
834 break;
835 }
836
837 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
838 clk, prescaler);
839
4b7c0e4c 840 for (clk = 0; clk < 8; clk++) {
56ca9040 841 int x;
4b7c0e4c
MKB		 842 x = CLK_RATE / (1 << clk);
843 if (x <= ios->clock)
56ca9040
PP		 844 break;
845 }
846
847 MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */
848
849 imxmci_stop_clock(host);
4b7c0e4c 850 MMC_CLK_RATE = (prescaler << 3) | clk;
2c171bf1
PP		 851 /*
852 * Under my understanding, clock should not be started there, because it would
853 * initiate SDHC sequencer and send last or random command into card
854 */
4b7c0e4c 855 /* imxmci_start_clock(host); */
56ca9040
PP		 856
857 dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
858 } else {
859 imxmci_stop_clock(host);
860 }
861}
862
faf39ede
PP		 863static int imxmci_get_ro(struct mmc_host *mmc)
864{
865 struct imxmci_host *host = mmc_priv(mmc);
866
867 if (host->pdata && host->pdata->get_ro)
08f80bb5
AV		 868 return !!host->pdata->get_ro(mmc_dev(mmc));
869 /*
870 * Board doesn't support read only detection; let the mmc core
871 * decide what to do.
872 */
873 return -ENOSYS;
faf39ede
PP		 874}
875
876
ab7aefd0 877static const struct mmc_host_ops imxmci_ops = {
56ca9040
PP		 878 .request = imxmci_request,
879 .set_ios = imxmci_set_ios,
faf39ede 880 .get_ro = imxmci_get_ro,
56ca9040
PP		 881};
882
56ca9040
PP		 883static void imxmci_check_status(unsigned long data)
884{
885 struct imxmci_host *host = (struct imxmci_host *)data;
886
c5d5e9c4
PZ		 887 if (host->pdata && host->pdata->card_present &&
888 host->pdata->card_present(mmc_dev(host->mmc)) != host->present) {
56ca9040
PP		 889 host->present ^= 1;
890 dev_info(mmc_dev(host->mmc), "card %s\n",
891 host->present ? "inserted" : "removed");
892
893 set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events);
894 tasklet_schedule(&host->tasklet);
895 }
896
4b7c0e4c
MKB		 897 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
898 test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
56ca9040 899 atomic_inc(&host->stuck_timeout);
4b7c0e4c 900 if (atomic_read(&host->stuck_timeout) > 4)
56ca9040
PP		 901 tasklet_schedule(&host->tasklet);
902 } else {
903 atomic_set(&host->stuck_timeout, 0);
904
905 }
906
907 mod_timer(&host->timer, jiffies + (HZ>>1));
908}
909
910static int imxmci_probe(struct platform_device *pdev)
911{
912 struct mmc_host *mmc;
913 struct imxmci_host *host = NULL;
914 struct resource *r;
915 int ret = 0, irq;
916
917 printk(KERN_INFO "i.MX mmc driver\n");
918
5fc63dfb
PZ		 919 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
920 irq = platform_get_irq(pdev, 0);
921 if (!r || irq < 0)
56ca9040
PP		 922 return -ENXIO;
923
5fc63dfb 924 if (!request_mem_region(r->start, 0x100, pdev->name))
56ca9040
PP		 925 return -EBUSY;
926
927 mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
928 if (!mmc) {
929 ret = -ENOMEM;
930 goto out;
931 }
932
933 mmc->ops = &imxmci_ops;
934 mmc->f_min = 150000;
935 mmc->f_max = CLK_RATE/2;
936 mmc->ocr_avail = MMC_VDD_32_33;
255d01af 937 mmc->caps = MMC_CAP_4_BIT_DATA;
56ca9040
PP		 938
939 /* MMC core transfer sizes tunable parameters */
940 mmc->max_hw_segs = 64;
941 mmc->max_phys_segs = 64;
56ca9040 942 mmc->max_seg_size = 64*512; /* default PAGE_CACHE_SIZE */
55db890a 943 mmc->max_req_size = 64*512; /* default PAGE_CACHE_SIZE */
fe4a3c7a 944 mmc->max_blk_size = 2048;
55db890a 945 mmc->max_blk_count = 65535;
56ca9040
PP		 946
947 host = mmc_priv(mmc);
948 host->mmc = mmc;
949 host->dma_allocated = 0;
950 host->pdata = pdev->dev.platform_data;
c5d5e9c4
PZ		 951 if (!host->pdata)
952 dev_warn(&pdev->dev, "No platform data provided!\n");
56ca9040
PP		 953
954 spin_lock_init(&host->lock);
955 host->res = r;
956 host->irq = irq;
957
38a41fdf
SH		 958 host->clk = clk_get(&pdev->dev, "perclk2");
959 if (IS_ERR(host->clk)) {
960 ret = PTR_ERR(host->clk);
961 goto out;
962 }
963 clk_enable(host->clk);
964
56ca9040
PP		 965 imx_gpio_mode(PB8_PF_SD_DAT0);
966 imx_gpio_mode(PB9_PF_SD_DAT1);
967 imx_gpio_mode(PB10_PF_SD_DAT2);
968 /* Configured as GPIO with pull-up to ensure right MCC card mode */
969 /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
970 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
971 /* imx_gpio_mode(PB11_PF_SD_DAT3); */
972 imx_gpio_mode(PB12_PF_SD_CLK);
973 imx_gpio_mode(PB13_PF_SD_CMD);
974
975 imxmci_softreset();
976
4b7c0e4c 977 if (MMC_REV_NO != 0x390) {
56ca9040 978 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
4b7c0e4c 979 MMC_REV_NO);
56ca9040
PP		 980 goto out;
981 }
982
983 MMC_READ_TO = 0x2db4; /* recommended in data sheet */
984
985 host->imask = IMXMCI_INT_MASK_DEFAULT;
986 MMC_INT_MASK = host->imask;
987
f7def13e
PZ		 988 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
989 if(host->dma < 0) {
56ca9040
PP		 990 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
991 ret = -EBUSY;
992 goto out;
993 }
4b7c0e4c 994 host->dma_allocated = 1;
56ca9040
PP		 995 imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
996
997 tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
998 host->status_reg=0;
999 host->pending_events=0;
1000
1001 ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host);
1002 if (ret)
1003 goto out;
1004
c5d5e9c4
PZ		 1005 if (host->pdata && host->pdata->card_present)
1006 host->present = host->pdata->card_present(mmc_dev(mmc));
1007 else /* if there is no way to detect assume that card is present */
1008 host->present = 1;
1009
56ca9040
PP		 1010 init_timer(&host->timer);
1011 host->timer.data = (unsigned long)host;
1012 host->timer.function = imxmci_check_status;
1013 add_timer(&host->timer);
4b7c0e4c 1014 mod_timer(&host->timer, jiffies + (HZ >> 1));
56ca9040
PP		 1015
1016 platform_set_drvdata(pdev, mmc);
1017
1018 mmc_add_host(mmc);
1019
1020 return 0;
1021
1022out:
1023 if (host) {
4b7c0e4c 1024 if (host->dma_allocated) {
56ca9040 1025 imx_dma_free(host->dma);
4b7c0e4c 1026 host->dma_allocated = 0;
56ca9040 1027 }
38a41fdf
SH		 1028 if (host->clk) {
1029 clk_disable(host->clk);
1030 clk_put(host->clk);
1031 }
56ca9040
PP		 1032 }
1033 if (mmc)
1034 mmc_free_host(mmc);
5fc63dfb 1035 release_mem_region(r->start, 0x100);
56ca9040
PP		 1036 return ret;
1037}
1038
1039static int imxmci_remove(struct platform_device *pdev)
1040{
1041 struct mmc_host *mmc = platform_get_drvdata(pdev);
1042
1043 platform_set_drvdata(pdev, NULL);
1044
1045 if (mmc) {
1046 struct imxmci_host *host = mmc_priv(mmc);
1047
1048 tasklet_disable(&host->tasklet);
1049
1050 del_timer_sync(&host->timer);
1051 mmc_remove_host(mmc);
1052
1053 free_irq(host->irq, host);
4b7c0e4c 1054 if (host->dma_allocated) {
56ca9040 1055 imx_dma_free(host->dma);
4b7c0e4c 1056 host->dma_allocated = 0;
56ca9040
PP		 1057 }
1058
1059 tasklet_kill(&host->tasklet);
1060
38a41fdf
SH		 1061 clk_disable(host->clk);
1062 clk_put(host->clk);
1063
5fc63dfb 1064 release_mem_region(host->res->start, 0x100);
56ca9040
PP		 1065
1066 mmc_free_host(mmc);
1067 }
1068 return 0;
1069}
1070
1071#ifdef CONFIG_PM
1072static int imxmci_suspend(struct platform_device *dev, pm_message_t state)
1073{
1074 struct mmc_host *mmc = platform_get_drvdata(dev);
1075 int ret = 0;
1076
1077 if (mmc)
1078 ret = mmc_suspend_host(mmc, state);
1079
1080 return ret;
1081}
1082
1083static int imxmci_resume(struct platform_device *dev)
1084{
1085 struct mmc_host *mmc = platform_get_drvdata(dev);
1086 struct imxmci_host *host;
1087 int ret = 0;
1088
1089 if (mmc) {
1090 host = mmc_priv(mmc);
4b7c0e4c 1091 if (host)
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PP		 1092 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
1093 ret = mmc_resume_host(mmc);
1094 }
1095
1096 return ret;
1097}
1098#else
1099#define imxmci_suspend NULL
1100#define imxmci_resume NULL
1101#endif /* CONFIG_PM */
1102
1103static struct platform_driver imxmci_driver = {
1104 .probe = imxmci_probe,
1105 .remove = imxmci_remove,
1106 .suspend = imxmci_suspend,
1107 .resume = imxmci_resume,
1108 .driver = {
1109 .name = DRIVER_NAME,
bc65c724 1110 .owner = THIS_MODULE,
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PP		 1111 }
1112};
1113
1114static int __init imxmci_init(void)
1115{
1116 return platform_driver_register(&imxmci_driver);
1117}
1118
1119static void __exit imxmci_exit(void)
1120{
1121 platform_driver_unregister(&imxmci_driver);
1122}
1123
1124module_init(imxmci_init);
1125module_exit(imxmci_exit);
1126
1127MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1128MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1129MODULE_LICENSE("GPL");
bc65c724 1130MODULE_ALIAS("platform:imx-mmc");
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