]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/misc/sgi-gru/grufile.c
gru: support contexts with zero dsrs or cbrs
[net-next-2.6.git] / drivers / misc / sgi-gru / grufile.c
CommitLineData
78cf1de4
JS
1/*
2 * SN Platform GRU Driver
3 *
4 * FILE OPERATIONS & DRIVER INITIALIZATION
5 *
6 * This file supports the user system call for file open, close, mmap, etc.
7 * This also incudes the driver initialization code.
8 *
9 * Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26#include <linux/module.h>
27#include <linux/kernel.h>
28#include <linux/errno.h>
29#include <linux/slab.h>
30#include <linux/mm.h>
31#include <linux/io.h>
32#include <linux/smp_lock.h>
33#include <linux/spinlock.h>
34#include <linux/device.h>
35#include <linux/miscdevice.h>
36#include <linux/interrupt.h>
37#include <linux/proc_fs.h>
38#include <linux/uaccess.h>
1c004004 39#include <asm/uv/uv.h>
78cf1de4
JS
40#include "gru.h"
41#include "grulib.h"
42#include "grutables.h"
43
78cf1de4
JS
44#include <asm/uv/uv_hub.h>
45#include <asm/uv/uv_mmrs.h>
46
47struct gru_blade_state *gru_base[GRU_MAX_BLADES] __read_mostly;
fe5bb6b0
JS
48unsigned long gru_start_paddr __read_mostly;
49unsigned long gru_end_paddr __read_mostly;
e1c3219d 50unsigned int gru_max_gids __read_mostly;
78cf1de4
JS
51struct gru_stats_s gru_stats;
52
53/* Guaranteed user available resources on each node */
54static int max_user_cbrs, max_user_dsr_bytes;
55
56static struct file_operations gru_fops;
57static struct miscdevice gru_miscdev;
58
59
60/*
61 * gru_vma_close
62 *
63 * Called when unmapping a device mapping. Frees all gru resources
64 * and tables belonging to the vma.
65 */
66static void gru_vma_close(struct vm_area_struct *vma)
67{
68 struct gru_vma_data *vdata;
69 struct gru_thread_state *gts;
70 struct list_head *entry, *next;
71
72 if (!vma->vm_private_data)
73 return;
74
75 vdata = vma->vm_private_data;
76 vma->vm_private_data = NULL;
77 gru_dbg(grudev, "vma %p, file %p, vdata %p\n", vma, vma->vm_file,
78 vdata);
79 list_for_each_safe(entry, next, &vdata->vd_head) {
80 gts =
81 list_entry(entry, struct gru_thread_state, ts_next);
82 list_del(&gts->ts_next);
83 mutex_lock(&gts->ts_ctxlock);
84 if (gts->ts_gru)
85 gru_unload_context(gts, 0);
86 mutex_unlock(&gts->ts_ctxlock);
87 gts_drop(gts);
88 }
89 kfree(vdata);
90 STAT(vdata_free);
91}
92
93/*
94 * gru_file_mmap
95 *
96 * Called when mmaping the device. Initializes the vma with a fault handler
97 * and private data structure necessary to allocate, track, and free the
98 * underlying pages.
99 */
100static int gru_file_mmap(struct file *file, struct vm_area_struct *vma)
101{
102 if ((vma->vm_flags & (VM_SHARED | VM_WRITE)) != (VM_SHARED | VM_WRITE))
103 return -EPERM;
104
9ca8e40c 105 if (vma->vm_start & (GRU_GSEG_PAGESIZE - 1) ||
fe5bb6b0 106 vma->vm_end & (GRU_GSEG_PAGESIZE - 1))
9ca8e40c
JS
107 return -EINVAL;
108
78cf1de4
JS
109 vma->vm_flags |=
110 (VM_IO | VM_DONTCOPY | VM_LOCKED | VM_DONTEXPAND | VM_PFNMAP |
111 VM_RESERVED);
112 vma->vm_page_prot = PAGE_SHARED;
113 vma->vm_ops = &gru_vm_ops;
114
115 vma->vm_private_data = gru_alloc_vma_data(vma, 0);
116 if (!vma->vm_private_data)
117 return -ENOMEM;
118
119 gru_dbg(grudev, "file %p, vaddr 0x%lx, vma %p, vdata %p\n",
120 file, vma->vm_start, vma, vma->vm_private_data);
121 return 0;
122}
123
124/*
125 * Create a new GRU context
126 */
127static int gru_create_new_context(unsigned long arg)
128{
129 struct gru_create_context_req req;
130 struct vm_area_struct *vma;
131 struct gru_vma_data *vdata;
132 int ret = -EINVAL;
133
134
135 if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
136 return -EFAULT;
137
3eac2e95 138 if (req.data_segment_bytes > max_user_dsr_bytes)
78cf1de4 139 return -EINVAL;
3eac2e95 140 if (req.control_blocks > max_user_cbrs || !req.maximum_thread_count)
78cf1de4
JS
141 return -EINVAL;
142
143 if (!(req.options & GRU_OPT_MISS_MASK))
144 req.options |= GRU_OPT_MISS_FMM_INTR;
145
146 down_write(&current->mm->mmap_sem);
147 vma = gru_find_vma(req.gseg);
148 if (vma) {
149 vdata = vma->vm_private_data;
150 vdata->vd_user_options = req.options;
151 vdata->vd_dsr_au_count =
152 GRU_DS_BYTES_TO_AU(req.data_segment_bytes);
153 vdata->vd_cbr_au_count = GRU_CB_COUNT_TO_AU(req.control_blocks);
154 ret = 0;
155 }
156 up_write(&current->mm->mmap_sem);
157
158 return ret;
159}
160
161/*
162 * Get GRU configuration info (temp - for emulator testing)
163 */
164static long gru_get_config_info(unsigned long arg)
165{
166 struct gru_config_info info;
167 int nodesperblade;
168
169 if (num_online_nodes() > 1 &&
170 (uv_node_to_blade_id(1) == uv_node_to_blade_id(0)))
171 nodesperblade = 2;
172 else
173 nodesperblade = 1;
174 info.cpus = num_online_cpus();
175 info.nodes = num_online_nodes();
176 info.blades = info.nodes / nodesperblade;
177 info.chiplets = GRU_CHIPLETS_PER_BLADE * info.blades;
178
179 if (copy_to_user((void __user *)arg, &info, sizeof(info)))
180 return -EFAULT;
181 return 0;
182}
183
184/*
185 * Get GRU chiplet status
186 */
187static long gru_get_chiplet_status(unsigned long arg)
188{
189 struct gru_state *gru;
190 struct gru_chiplet_info info;
191
192 if (copy_from_user(&info, (void __user *)arg, sizeof(info)))
193 return -EFAULT;
194
195 if (info.node == -1)
196 info.node = numa_node_id();
197 if (info.node >= num_possible_nodes() ||
198 info.chiplet >= GRU_CHIPLETS_PER_HUB ||
199 info.node < 0 || info.chiplet < 0)
200 return -EINVAL;
201
202 info.blade = uv_node_to_blade_id(info.node);
203 gru = get_gru(info.blade, info.chiplet);
204
205 info.total_dsr_bytes = GRU_NUM_DSR_BYTES;
206 info.total_cbr = GRU_NUM_CB;
207 info.total_user_dsr_bytes = GRU_NUM_DSR_BYTES -
208 gru->gs_reserved_dsr_bytes;
209 info.total_user_cbr = GRU_NUM_CB - gru->gs_reserved_cbrs;
210 info.free_user_dsr_bytes = hweight64(gru->gs_dsr_map) *
211 GRU_DSR_AU_BYTES;
212 info.free_user_cbr = hweight64(gru->gs_cbr_map) * GRU_CBR_AU_SIZE;
213
214 if (copy_to_user((void __user *)arg, &info, sizeof(info)))
215 return -EFAULT;
216 return 0;
217}
218
219/*
220 * gru_file_unlocked_ioctl
221 *
222 * Called to update file attributes via IOCTL calls.
223 */
224static long gru_file_unlocked_ioctl(struct file *file, unsigned int req,
225 unsigned long arg)
226{
227 int err = -EBADRQC;
228
229 gru_dbg(grudev, "file %p\n", file);
230
231 switch (req) {
232 case GRU_CREATE_CONTEXT:
233 err = gru_create_new_context(arg);
234 break;
235 case GRU_SET_TASK_SLICE:
236 err = gru_set_task_slice(arg);
237 break;
238 case GRU_USER_GET_EXCEPTION_DETAIL:
239 err = gru_get_exception_detail(arg);
240 break;
241 case GRU_USER_UNLOAD_CONTEXT:
242 err = gru_user_unload_context(arg);
243 break;
244 case GRU_GET_CHIPLET_STATUS:
245 err = gru_get_chiplet_status(arg);
246 break;
247 case GRU_USER_FLUSH_TLB:
248 err = gru_user_flush_tlb(arg);
249 break;
250 case GRU_USER_CALL_OS:
251 err = gru_handle_user_call_os(arg);
252 break;
253 case GRU_GET_CONFIG_INFO:
254 err = gru_get_config_info(arg);
255 break;
9cc9b056
JS
256 case GRU_DUMP_CHIPLET_STATE:
257 err = gru_dump_chiplet_request(arg);
258 break;
78cf1de4
JS
259 }
260 return err;
261}
262
263/*
264 * Called at init time to build tables for all GRUs that are present in the
265 * system.
266 */
267static void gru_init_chiplet(struct gru_state *gru, unsigned long paddr,
268 void *vaddr, int nid, int bid, int grunum)
269{
270 spin_lock_init(&gru->gs_lock);
271 spin_lock_init(&gru->gs_asid_lock);
272 gru->gs_gru_base_paddr = paddr;
273 gru->gs_gru_base_vaddr = vaddr;
274 gru->gs_gid = bid * GRU_CHIPLETS_PER_BLADE + grunum;
275 gru->gs_blade = gru_base[bid];
276 gru->gs_blade_id = bid;
277 gru->gs_cbr_map = (GRU_CBR_AU == 64) ? ~0 : (1UL << GRU_CBR_AU) - 1;
278 gru->gs_dsr_map = (1UL << GRU_DSR_AU) - 1;
87419412 279 gru->gs_asid_limit = MAX_ASID;
78cf1de4 280 gru_tgh_flush_init(gru);
e1c3219d
JS
281 if (gru->gs_gid >= gru_max_gids)
282 gru_max_gids = gru->gs_gid + 1;
43884604 283 gru_dbg(grudev, "bid %d, nid %d, gid %d, vaddr %p (0x%lx)\n",
78cf1de4
JS
284 bid, nid, gru->gs_gid, gru->gs_gru_base_vaddr,
285 gru->gs_gru_base_paddr);
286 gru_kservices_init(gru);
287}
288
289static int gru_init_tables(unsigned long gru_base_paddr, void *gru_base_vaddr)
290{
291 int pnode, nid, bid, chip;
292 int cbrs, dsrbytes, n;
293 int order = get_order(sizeof(struct gru_blade_state));
294 struct page *page;
295 struct gru_state *gru;
296 unsigned long paddr;
297 void *vaddr;
298
299 max_user_cbrs = GRU_NUM_CB;
300 max_user_dsr_bytes = GRU_NUM_DSR_BYTES;
301 for_each_online_node(nid) {
302 bid = uv_node_to_blade_id(nid);
303 pnode = uv_node_to_pnode(nid);
fe5bb6b0 304 if (bid < 0 || gru_base[bid])
78cf1de4 305 continue;
6484eb3e 306 page = alloc_pages_exact_node(nid, GFP_KERNEL, order);
78cf1de4
JS
307 if (!page)
308 goto fail;
309 gru_base[bid] = page_address(page);
310 memset(gru_base[bid], 0, sizeof(struct gru_blade_state));
311 gru_base[bid]->bs_lru_gru = &gru_base[bid]->bs_grus[0];
312 spin_lock_init(&gru_base[bid]->bs_lock);
313
314 dsrbytes = 0;
315 cbrs = 0;
316 for (gru = gru_base[bid]->bs_grus, chip = 0;
fe5bb6b0 317 chip < GRU_CHIPLETS_PER_BLADE;
78cf1de4
JS
318 chip++, gru++) {
319 paddr = gru_chiplet_paddr(gru_base_paddr, pnode, chip);
320 vaddr = gru_chiplet_vaddr(gru_base_vaddr, pnode, chip);
fe5bb6b0 321 gru_init_chiplet(gru, paddr, vaddr, nid, bid, chip);
78cf1de4
JS
322 n = hweight64(gru->gs_cbr_map) * GRU_CBR_AU_SIZE;
323 cbrs = max(cbrs, n);
324 n = hweight64(gru->gs_dsr_map) * GRU_DSR_AU_BYTES;
325 dsrbytes = max(dsrbytes, n);
326 }
327 max_user_cbrs = min(max_user_cbrs, cbrs);
328 max_user_dsr_bytes = min(max_user_dsr_bytes, dsrbytes);
329 }
330
331 return 0;
332
333fail:
334 for (nid--; nid >= 0; nid--)
335 free_pages((unsigned long)gru_base[nid], order);
336 return -ENOMEM;
337}
338
339#ifdef CONFIG_IA64
340
341static int get_base_irq(void)
342{
343 return IRQ_GRU;
344}
345
346#elif defined CONFIG_X86_64
347
348static void noop(unsigned int irq)
349{
350}
351
352static struct irq_chip gru_chip = {
353 .name = "gru",
354 .mask = noop,
355 .unmask = noop,
356 .ack = noop,
357};
358
359static int get_base_irq(void)
360{
361 set_irq_chip(IRQ_GRU, &gru_chip);
362 set_irq_chip(IRQ_GRU + 1, &gru_chip);
363 return IRQ_GRU;
364}
365#endif
366
367/*
368 * gru_init
369 *
370 * Called at boot or module load time to initialize the GRUs.
371 */
372static int __init gru_init(void)
373{
374 int ret, irq, chip;
375 char id[10];
376 void *gru_start_vaddr;
377
1c004004 378 if (!is_uv_system())
e873cff0 379 return 0;
78cf1de4
JS
380
381#if defined CONFIG_IA64
382 gru_start_paddr = 0xd000000000UL; /* ZZZZZZZZZZZZZZZZZZZ fixme */
383#else
384 gru_start_paddr = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR) &
385 0x7fffffffffffUL;
78cf1de4
JS
386#endif
387 gru_start_vaddr = __va(gru_start_paddr);
fe5bb6b0 388 gru_end_paddr = gru_start_paddr + GRU_MAX_BLADES * GRU_SIZE;
78cf1de4
JS
389 printk(KERN_INFO "GRU space: 0x%lx - 0x%lx\n",
390 gru_start_paddr, gru_end_paddr);
391 irq = get_base_irq();
392 for (chip = 0; chip < GRU_CHIPLETS_PER_BLADE; chip++) {
393 ret = request_irq(irq + chip, gru_intr, 0, id, NULL);
fe5bb6b0 394 /* TODO: fix irq handling on x86. For now ignore failure because
923f7f69
JS
395 * interrupts are not required & not yet fully supported */
396 if (ret) {
fe5bb6b0
JS
397 printk(KERN_WARNING
398 "!!!WARNING: GRU ignoring request failure!!!\n");
923f7f69
JS
399 ret = 0;
400 }
78cf1de4
JS
401 if (ret) {
402 printk(KERN_ERR "%s: request_irq failed\n",
403 GRU_DRIVER_ID_STR);
404 goto exit1;
405 }
406 }
407
408 ret = misc_register(&gru_miscdev);
409 if (ret) {
410 printk(KERN_ERR "%s: misc_register failed\n",
411 GRU_DRIVER_ID_STR);
412 goto exit1;
413 }
414
415 ret = gru_proc_init();
416 if (ret) {
417 printk(KERN_ERR "%s: proc init failed\n", GRU_DRIVER_ID_STR);
418 goto exit2;
419 }
420
421 ret = gru_init_tables(gru_start_paddr, gru_start_vaddr);
422 if (ret) {
423 printk(KERN_ERR "%s: init tables failed\n", GRU_DRIVER_ID_STR);
424 goto exit3;
425 }
426
427 printk(KERN_INFO "%s: v%s\n", GRU_DRIVER_ID_STR,
428 GRU_DRIVER_VERSION_STR);
429 return 0;
430
431exit3:
432 gru_proc_exit();
433exit2:
434 misc_deregister(&gru_miscdev);
435exit1:
436 for (--chip; chip >= 0; chip--)
437 free_irq(irq + chip, NULL);
438 return ret;
439
440}
441
442static void __exit gru_exit(void)
443{
27ca8a7b 444 int i, bid, gid;
78cf1de4
JS
445 int order = get_order(sizeof(struct gru_state) *
446 GRU_CHIPLETS_PER_BLADE);
447
1c004004 448 if (!is_uv_system())
8275d102
RH
449 return;
450
78cf1de4
JS
451 for (i = 0; i < GRU_CHIPLETS_PER_BLADE; i++)
452 free_irq(IRQ_GRU + i, NULL);
453
27ca8a7b
JS
454 foreach_gid(gid)
455 gru_kservices_exit(GID_TO_GRU(gid));
456
78cf1de4
JS
457 for (bid = 0; bid < GRU_MAX_BLADES; bid++)
458 free_pages((unsigned long)gru_base[bid], order);
459
460 misc_deregister(&gru_miscdev);
461 gru_proc_exit();
462}
463
464static struct file_operations gru_fops = {
465 .owner = THIS_MODULE,
466 .unlocked_ioctl = gru_file_unlocked_ioctl,
467 .mmap = gru_file_mmap,
468};
469
470static struct miscdevice gru_miscdev = {
471 .minor = MISC_DYNAMIC_MINOR,
472 .name = "gru",
473 .fops = &gru_fops,
474};
475
476struct vm_operations_struct gru_vm_ops = {
477 .close = gru_vma_close,
478 .fault = gru_fault,
479};
480
fe5bb6b0 481#ifndef MODULE
026bde12 482fs_initcall(gru_init);
fe5bb6b0
JS
483#else
484module_init(gru_init);
485#endif
78cf1de4
JS
486module_exit(gru_exit);
487
9ca8e40c
JS
488module_param(gru_options, ulong, 0644);
489MODULE_PARM_DESC(gru_options, "Various debug options");
78cf1de4
JS
490
491MODULE_AUTHOR("Silicon Graphics, Inc.");
492MODULE_LICENSE("GPL");
493MODULE_DESCRIPTION(GRU_DRIVER_ID_STR GRU_DRIVER_VERSION_STR);
494MODULE_VERSION(GRU_DRIVER_VERSION_STR);
495