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[net-next-2.6.git] / drivers / mfd / mc13xxx-core.c
CommitLineData
8e005935
UKK		 1/*
2 * Copyright 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * loosely based on an earlier driver that has
6 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 *
8 * This program is free software; you can redistribute it and/or modify it under
9 * the terms of the GNU General Public License version 2 as published by the
10 * Free Software Foundation.
11 */
8e005935
UKK		 12
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/mutex.h>
17#include <linux/interrupt.h>
18#include <linux/spi/spi.h>
19#include <linux/mfd/core.h>
20#include <linux/mfd/mc13xxx.h>
21
22struct mc13xxx {
23 struct spi_device *spidev;
24 struct mutex lock;
25 int irq;
26
27 irq_handler_t irqhandler[MC13XXX_NUM_IRQ];
28 void *irqdata[MC13XXX_NUM_IRQ];
29};
30
31struct mc13783 {
32 struct mc13xxx mc13xxx;
33
34 int adcflags;
35};
36
37struct mc13xxx *mc13783_to_mc13xxx(struct mc13783 *mc13783)
38{
39 return &mc13783->mc13xxx;
40}
41EXPORT_SYMBOL(mc13783_to_mc13xxx);
42
43#define MC13XXX_IRQSTAT0 0
44#define MC13XXX_IRQSTAT0_ADCDONEI (1 << 0)
45#define MC13XXX_IRQSTAT0_ADCBISDONEI (1 << 1)
46#define MC13XXX_IRQSTAT0_TSI (1 << 2)
47#define MC13783_IRQSTAT0_WHIGHI (1 << 3)
48#define MC13783_IRQSTAT0_WLOWI (1 << 4)
49#define MC13XXX_IRQSTAT0_CHGDETI (1 << 6)
50#define MC13783_IRQSTAT0_CHGOVI (1 << 7)
51#define MC13XXX_IRQSTAT0_CHGREVI (1 << 8)
52#define MC13XXX_IRQSTAT0_CHGSHORTI (1 << 9)
53#define MC13XXX_IRQSTAT0_CCCVI (1 << 10)
54#define MC13XXX_IRQSTAT0_CHGCURRI (1 << 11)
55#define MC13XXX_IRQSTAT0_BPONI (1 << 12)
56#define MC13XXX_IRQSTAT0_LOBATLI (1 << 13)
57#define MC13XXX_IRQSTAT0_LOBATHI (1 << 14)
58#define MC13783_IRQSTAT0_UDPI (1 << 15)
59#define MC13783_IRQSTAT0_USBI (1 << 16)
60#define MC13783_IRQSTAT0_IDI (1 << 19)
61#define MC13783_IRQSTAT0_SE1I (1 << 21)
62#define MC13783_IRQSTAT0_CKDETI (1 << 22)
63#define MC13783_IRQSTAT0_UDMI (1 << 23)
64
65#define MC13XXX_IRQMASK0 1
66#define MC13XXX_IRQMASK0_ADCDONEM MC13XXX_IRQSTAT0_ADCDONEI
67#define MC13XXX_IRQMASK0_ADCBISDONEM MC13XXX_IRQSTAT0_ADCBISDONEI
68#define MC13XXX_IRQMASK0_TSM MC13XXX_IRQSTAT0_TSI
69#define MC13783_IRQMASK0_WHIGHM MC13783_IRQSTAT0_WHIGHI
70#define MC13783_IRQMASK0_WLOWM MC13783_IRQSTAT0_WLOWI
71#define MC13XXX_IRQMASK0_CHGDETM MC13XXX_IRQSTAT0_CHGDETI
72#define MC13783_IRQMASK0_CHGOVM MC13783_IRQSTAT0_CHGOVI
73#define MC13XXX_IRQMASK0_CHGREVM MC13XXX_IRQSTAT0_CHGREVI
74#define MC13XXX_IRQMASK0_CHGSHORTM MC13XXX_IRQSTAT0_CHGSHORTI
75#define MC13XXX_IRQMASK0_CCCVM MC13XXX_IRQSTAT0_CCCVI
76#define MC13XXX_IRQMASK0_CHGCURRM MC13XXX_IRQSTAT0_CHGCURRI
77#define MC13XXX_IRQMASK0_BPONM MC13XXX_IRQSTAT0_BPONI
78#define MC13XXX_IRQMASK0_LOBATLM MC13XXX_IRQSTAT0_LOBATLI
79#define MC13XXX_IRQMASK0_LOBATHM MC13XXX_IRQSTAT0_LOBATHI
80#define MC13783_IRQMASK0_UDPM MC13783_IRQSTAT0_UDPI
81#define MC13783_IRQMASK0_USBM MC13783_IRQSTAT0_USBI
82#define MC13783_IRQMASK0_IDM MC13783_IRQSTAT0_IDI
83#define MC13783_IRQMASK0_SE1M MC13783_IRQSTAT0_SE1I
84#define MC13783_IRQMASK0_CKDETM MC13783_IRQSTAT0_CKDETI
85#define MC13783_IRQMASK0_UDMM MC13783_IRQSTAT0_UDMI
86
87#define MC13XXX_IRQSTAT1 3
88#define MC13XXX_IRQSTAT1_1HZI (1 << 0)
89#define MC13XXX_IRQSTAT1_TODAI (1 << 1)
90#define MC13783_IRQSTAT1_ONOFD1I (1 << 3)
91#define MC13783_IRQSTAT1_ONOFD2I (1 << 4)
92#define MC13783_IRQSTAT1_ONOFD3I (1 << 5)
93#define MC13XXX_IRQSTAT1_SYSRSTI (1 << 6)
94#define MC13XXX_IRQSTAT1_RTCRSTI (1 << 7)
95#define MC13XXX_IRQSTAT1_PCI (1 << 8)
96#define MC13XXX_IRQSTAT1_WARMI (1 << 9)
97#define MC13XXX_IRQSTAT1_MEMHLDI (1 << 10)
98#define MC13783_IRQSTAT1_PWRRDYI (1 << 11)
99#define MC13XXX_IRQSTAT1_THWARNLI (1 << 12)
100#define MC13XXX_IRQSTAT1_THWARNHI (1 << 13)
101#define MC13XXX_IRQSTAT1_CLKI (1 << 14)
102#define MC13783_IRQSTAT1_SEMAFI (1 << 15)
103#define MC13783_IRQSTAT1_MC2BI (1 << 17)
104#define MC13783_IRQSTAT1_HSDETI (1 << 18)
105#define MC13783_IRQSTAT1_HSLI (1 << 19)
106#define MC13783_IRQSTAT1_ALSPTHI (1 << 20)
107#define MC13783_IRQSTAT1_AHSSHORTI (1 << 21)
108
109#define MC13XXX_IRQMASK1 4
110#define MC13XXX_IRQMASK1_1HZM MC13XXX_IRQSTAT1_1HZI
111#define MC13XXX_IRQMASK1_TODAM MC13XXX_IRQSTAT1_TODAI
112#define MC13783_IRQMASK1_ONOFD1M MC13783_IRQSTAT1_ONOFD1I
113#define MC13783_IRQMASK1_ONOFD2M MC13783_IRQSTAT1_ONOFD2I
114#define MC13783_IRQMASK1_ONOFD3M MC13783_IRQSTAT1_ONOFD3I
115#define MC13XXX_IRQMASK1_SYSRSTM MC13XXX_IRQSTAT1_SYSRSTI
116#define MC13XXX_IRQMASK1_RTCRSTM MC13XXX_IRQSTAT1_RTCRSTI
117#define MC13XXX_IRQMASK1_PCM MC13XXX_IRQSTAT1_PCI
118#define MC13XXX_IRQMASK1_WARMM MC13XXX_IRQSTAT1_WARMI
119#define MC13XXX_IRQMASK1_MEMHLDM MC13XXX_IRQSTAT1_MEMHLDI
120#define MC13783_IRQMASK1_PWRRDYM MC13783_IRQSTAT1_PWRRDYI
121#define MC13XXX_IRQMASK1_THWARNLM MC13XXX_IRQSTAT1_THWARNLI
122#define MC13XXX_IRQMASK1_THWARNHM MC13XXX_IRQSTAT1_THWARNHI
123#define MC13XXX_IRQMASK1_CLKM MC13XXX_IRQSTAT1_CLKI
124#define MC13783_IRQMASK1_SEMAFM MC13783_IRQSTAT1_SEMAFI
125#define MC13783_IRQMASK1_MC2BM MC13783_IRQSTAT1_MC2BI
126#define MC13783_IRQMASK1_HSDETM MC13783_IRQSTAT1_HSDETI
127#define MC13783_IRQMASK1_HSLM MC13783_IRQSTAT1_HSLI
128#define MC13783_IRQMASK1_ALSPTHM MC13783_IRQSTAT1_ALSPTHI
129#define MC13783_IRQMASK1_AHSSHORTM MC13783_IRQSTAT1_AHSSHORTI
130
131#define MC13XXX_REVISION 7
132#define MC13XXX_REVISION_REVMETAL (0x07 << 0)
133#define MC13XXX_REVISION_REVFULL (0x03 << 3)
134#define MC13XXX_REVISION_ICID (0x07 << 6)
135#define MC13XXX_REVISION_FIN (0x03 << 9)
136#define MC13XXX_REVISION_FAB (0x03 << 11)
137#define MC13XXX_REVISION_ICIDCODE (0x3f << 13)
138
139#define MC13783_ADC1 44
140#define MC13783_ADC1_ADEN (1 << 0)
141#define MC13783_ADC1_RAND (1 << 1)
142#define MC13783_ADC1_ADSEL (1 << 3)
143#define MC13783_ADC1_ASC (1 << 20)
144#define MC13783_ADC1_ADTRIGIGN (1 << 21)
145
146#define MC13783_ADC2 45
147
148#define MC13XXX_NUMREGS 0x3f
149
150void mc13xxx_lock(struct mc13xxx *mc13xxx)
151{
152 if (!mutex_trylock(&mc13xxx->lock)) {
153 dev_dbg(&mc13xxx->spidev->dev, "wait for %s from %pf\n",
154 __func__, __builtin_return_address(0));
155
156 mutex_lock(&mc13xxx->lock);
157 }
158 dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
159 __func__, __builtin_return_address(0));
160}
161EXPORT_SYMBOL(mc13xxx_lock);
162
163void mc13xxx_unlock(struct mc13xxx *mc13xxx)
164{
165 dev_dbg(&mc13xxx->spidev->dev, "%s from %pf\n",
166 __func__, __builtin_return_address(0));
167 mutex_unlock(&mc13xxx->lock);
168}
169EXPORT_SYMBOL(mc13xxx_unlock);
170
171#define MC13XXX_REGOFFSET_SHIFT 25
172int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
173{
174 struct spi_transfer t;
175 struct spi_message m;
176 int ret;
177
178 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
179
180 if (offset > MC13XXX_NUMREGS)
181 return -EINVAL;
182
183 *val = offset << MC13XXX_REGOFFSET_SHIFT;
184
185 memset(&t, 0, sizeof(t));
186
187 t.tx_buf = val;
188 t.rx_buf = val;
189 t.len = sizeof(u32);
190
191 spi_message_init(&m);
192 spi_message_add_tail(&t, &m);
193
194 ret = spi_sync(mc13xxx->spidev, &m);
195
196 /* error in message.status implies error return from spi_sync */
197 BUG_ON(!ret && m.status);
198
199 if (ret)
200 return ret;
201
202 *val &= 0xffffff;
203
204 dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
205
206 return 0;
207}
208EXPORT_SYMBOL(mc13xxx_reg_read);
209
210int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
211{
212 u32 buf;
213 struct spi_transfer t;
214 struct spi_message m;
215 int ret;
216
217 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
218
219 dev_vdbg(&mc13xxx->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
220
221 if (offset > MC13XXX_NUMREGS || val > 0xffffff)
222 return -EINVAL;
223
224 buf = 1 << 31 | offset << MC13XXX_REGOFFSET_SHIFT | val;
225
226 memset(&t, 0, sizeof(t));
227
228 t.tx_buf = &buf;
229 t.rx_buf = &buf;
230 t.len = sizeof(u32);
231
232 spi_message_init(&m);
233 spi_message_add_tail(&t, &m);
234
235 ret = spi_sync(mc13xxx->spidev, &m);
236
237 BUG_ON(!ret && m.status);
238
239 if (ret)
240 return ret;
241
242 return 0;
243}
244EXPORT_SYMBOL(mc13xxx_reg_write);
245
246int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
247 u32 mask, u32 val)
248{
249 int ret;
250 u32 valread;
251
252 BUG_ON(val & ~mask);
253
254 ret = mc13xxx_reg_read(mc13xxx, offset, &valread);
255 if (ret)
256 return ret;
257
258 valread = (valread & ~mask) | val;
259
260 return mc13xxx_reg_write(mc13xxx, offset, valread);
261}
262EXPORT_SYMBOL(mc13xxx_reg_rmw);
263
264int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
265{
266 int ret;
267 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
268 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
269 u32 mask;
270
271 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
272 return -EINVAL;
273
274 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
275 if (ret)
276 return ret;
277
278 if (mask & irqbit)
279 /* already masked */
280 return 0;
281
282 return mc13xxx_reg_write(mc13xxx, offmask, mask | irqbit);
283}
284EXPORT_SYMBOL(mc13xxx_irq_mask);
285
286int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
287{
288 int ret;
289 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
290 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
291 u32 mask;
292
293 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
294 return -EINVAL;
295
296 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
297 if (ret)
298 return ret;
299
300 if (!(mask & irqbit))
301 /* already unmasked */
302 return 0;
303
304 return mc13xxx_reg_write(mc13xxx, offmask, mask & ~irqbit);
305}
306EXPORT_SYMBOL(mc13xxx_irq_unmask);
307
308int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
309 int *enabled, int *pending)
310{
311 int ret;
312 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
313 unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
314 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
315
316 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
317 return -EINVAL;
318
319 if (enabled) {
320 u32 mask;
321
322 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
323 if (ret)
324 return ret;
325
326 *enabled = mask & irqbit;
327 }
328
329 if (pending) {
330 u32 stat;
331
332 ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
333 if (ret)
334 return ret;
335
336 *pending = stat & irqbit;
337 }
338
339 return 0;
340}
341EXPORT_SYMBOL(mc13xxx_irq_status);
342
343int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq)
344{
345 unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
346 unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
347
348 BUG_ON(irq < 0 || irq >= MC13XXX_NUM_IRQ);
349
350 return mc13xxx_reg_write(mc13xxx, offstat, val);
351}
352EXPORT_SYMBOL(mc13xxx_irq_ack);
353
354int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
355 irq_handler_t handler, const char *name, void *dev)
356{
357 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
358 BUG_ON(!handler);
359
360 if (irq < 0 || irq >= MC13XXX_NUM_IRQ)
361 return -EINVAL;
362
363 if (mc13xxx->irqhandler[irq])
364 return -EBUSY;
365
366 mc13xxx->irqhandler[irq] = handler;
367 mc13xxx->irqdata[irq] = dev;
368
369 return 0;
370}
371EXPORT_SYMBOL(mc13xxx_irq_request_nounmask);
372
373int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
374 irq_handler_t handler, const char *name, void *dev)
375{
376 int ret;
377
378 ret = mc13xxx_irq_request_nounmask(mc13xxx, irq, handler, name, dev);
379 if (ret)
380 return ret;
381
382 ret = mc13xxx_irq_unmask(mc13xxx, irq);
383 if (ret) {
384 mc13xxx->irqhandler[irq] = NULL;
385 mc13xxx->irqdata[irq] = NULL;
386 return ret;
387 }
388
389 return 0;
390}
391EXPORT_SYMBOL(mc13xxx_irq_request);
392
393int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
394{
395 int ret;
396 BUG_ON(!mutex_is_locked(&mc13xxx->lock));
397
398 if (irq < 0 || irq >= MC13XXX_NUM_IRQ || !mc13xxx->irqhandler[irq] ||
399 mc13xxx->irqdata[irq] != dev)
400 return -EINVAL;
401
402 ret = mc13xxx_irq_mask(mc13xxx, irq);
403 if (ret)
404 return ret;
405
406 mc13xxx->irqhandler[irq] = NULL;
407 mc13xxx->irqdata[irq] = NULL;
408
409 return 0;
410}
411EXPORT_SYMBOL(mc13xxx_irq_free);
412
413static inline irqreturn_t mc13xxx_irqhandler(struct mc13xxx *mc13xxx, int irq)
414{
415 return mc13xxx->irqhandler[irq](irq, mc13xxx->irqdata[irq]);
416}
417
418/*
419 * returns: number of handled irqs or negative error
420 * locking: holds mc13xxx->lock
421 */
422static int mc13xxx_irq_handle(struct mc13xxx *mc13xxx,
423 unsigned int offstat, unsigned int offmask, int baseirq)
424{
425 u32 stat, mask;
426 int ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
427 int num_handled = 0;
428
429 if (ret)
430 return ret;
431
432 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
433 if (ret)
434 return ret;
435
436 while (stat & ~mask) {
437 int irq = __ffs(stat & ~mask);
438
439 stat &= ~(1 << irq);
440
441 if (likely(mc13xxx->irqhandler[baseirq + irq])) {
442 irqreturn_t handled;
443
444 handled = mc13xxx_irqhandler(mc13xxx, baseirq + irq);
445 if (handled == IRQ_HANDLED)
446 num_handled++;
447 } else {
448 dev_err(&mc13xxx->spidev->dev,
449 "BUG: irq %u but no handler\n",
450 baseirq + irq);
451
452 mask |= 1 << irq;
453
454 ret = mc13xxx_reg_write(mc13xxx, offmask, mask);
455 }
456 }
457
458 return num_handled;
459}
460
461static irqreturn_t mc13xxx_irq_thread(int irq, void *data)
462{
463 struct mc13xxx *mc13xxx = data;
464 irqreturn_t ret;
465 int handled = 0;
466
467 mc13xxx_lock(mc13xxx);
468
469 ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT0,
470 MC13XXX_IRQMASK0, 0);
471 if (ret > 0)
472 handled = 1;
473
474 ret = mc13xxx_irq_handle(mc13xxx, MC13XXX_IRQSTAT1,
475 MC13XXX_IRQMASK1, 24);
476 if (ret > 0)
477 handled = 1;
478
479 mc13xxx_unlock(mc13xxx);
480
481 return IRQ_RETVAL(handled);
482}
483
484enum mc13xxx_id {
485 MC13XXX_ID_MC13783,
486 MC13XXX_ID_MC13892,
487 MC13XXX_ID_INVALID,
488};
489
490const char *mc13xxx_chipname[] = {
491 [MC13XXX_ID_MC13783] = "mc13783",
492 [MC13XXX_ID_MC13892] = "mc13892",
493};
494
495#define maskval(reg, mask) (((reg) & (mask)) >> __ffs(mask))
496static int mc13xxx_identify(struct mc13xxx *mc13xxx, enum mc13xxx_id *id)
497{
498 u32 icid;
499 u32 revision;
500 const char *name;
501 int ret;
502
503 ret = mc13xxx_reg_read(mc13xxx, 46, &icid);
504 if (ret)
505 return ret;
506
507 icid = (icid >> 6) & 0x7;
508
509 switch (icid) {
510 case 2:
511 *id = MC13XXX_ID_MC13783;
512 name = "mc13783";
513 break;
514 case 7:
515 *id = MC13XXX_ID_MC13892;
516 name = "mc13892";
517 break;
518 default:
519 *id = MC13XXX_ID_INVALID;
520 break;
521 }
522
523 if (*id == MC13XXX_ID_MC13783 || *id == MC13XXX_ID_MC13892) {
524 ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
525 if (ret)
526 return ret;
527
528 dev_info(&mc13xxx->spidev->dev, "%s: rev: %d.%d, "
529 "fin: %d, fab: %d, icid: %d/%d\n",
530 mc13xxx_chipname[*id],
531 maskval(revision, MC13XXX_REVISION_REVFULL),
532 maskval(revision, MC13XXX_REVISION_REVMETAL),
533 maskval(revision, MC13XXX_REVISION_FIN),
534 maskval(revision, MC13XXX_REVISION_FAB),
535 maskval(revision, MC13XXX_REVISION_ICID),
536 maskval(revision, MC13XXX_REVISION_ICIDCODE));
537 }
538
539 if (*id != MC13XXX_ID_INVALID) {
540 const struct spi_device_id *devid =
541 spi_get_device_id(mc13xxx->spidev);
542 if (!devid || devid->driver_data != *id)
543 dev_warn(&mc13xxx->spidev->dev, "device id doesn't "
544 "match auto detection!\n");
545 }
546
547 return 0;
548}
549
550static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
551{
552 const struct spi_device_id *devid =
553 spi_get_device_id(mc13xxx->spidev);
554
555 if (!devid)
556 return NULL;
557
558 return mc13xxx_chipname[devid->driver_data];
559}
560
561#include <linux/mfd/mc13783.h>
562
563int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
564{
565 struct mc13xxx_platform_data *pdata =
566 dev_get_platdata(&mc13xxx->spidev->dev);
567
568 return pdata->flags;
569}
570EXPORT_SYMBOL(mc13xxx_get_flags);
571
572#define MC13783_ADC1_CHAN0_SHIFT 5
573#define MC13783_ADC1_CHAN1_SHIFT 8
574
575struct mc13xxx_adcdone_data {
576 struct mc13xxx *mc13xxx;
577 struct completion done;
578};
579
580static irqreturn_t mc13783_handler_adcdone(int irq, void *data)
581{
582 struct mc13xxx_adcdone_data *adcdone_data = data;
583
584 mc13xxx_irq_ack(adcdone_data->mc13xxx, irq);
585
586 complete_all(&adcdone_data->done);
587
588 return IRQ_HANDLED;
589}
590
591#define MC13783_ADC_WORKING (1 << 0)
592
593int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
594 unsigned int channel, unsigned int *sample)
595{
596 struct mc13xxx *mc13xxx = &mc13783->mc13xxx;
597 u32 adc0, adc1, old_adc0;
598 int i, ret;
599 struct mc13xxx_adcdone_data adcdone_data = {
600 .mc13xxx = mc13xxx,
601 };
602 init_completion(&adcdone_data.done);
603
604 dev_dbg(&mc13xxx->spidev->dev, "%s\n", __func__);
605
606 mc13xxx_lock(mc13xxx);
607
608 if (mc13783->adcflags & MC13783_ADC_WORKING) {
609 ret = -EBUSY;
610 goto out;
611 }
612
613 mc13783->adcflags |= MC13783_ADC_WORKING;
614
615 mc13xxx_reg_read(mc13xxx, MC13783_ADC0, &old_adc0);
616
617 adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
618 adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN | MC13783_ADC1_ASC;
619
620 if (channel > 7)
621 adc1 |= MC13783_ADC1_ADSEL;
622
623 switch (mode) {
624 case MC13783_ADC_MODE_TS:
625 adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_TSMOD0 |
626 MC13783_ADC0_TSMOD1;
627 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
628 break;
629
630 case MC13783_ADC_MODE_SINGLE_CHAN:
631 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
632 adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
633 adc1 |= MC13783_ADC1_RAND;
634 break;
635
636 case MC13783_ADC_MODE_MULT_CHAN:
637 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
638 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
639 break;
640
641 default:
642 mc13783_unlock(mc13783);
643 return -EINVAL;
644 }
645
646 dev_dbg(&mc13783->mc13xxx.spidev->dev, "%s: request irq\n", __func__);
647 mc13xxx_irq_request(mc13xxx, MC13783_IRQ_ADCDONE,
648 mc13783_handler_adcdone, __func__, &adcdone_data);
649 mc13xxx_irq_ack(mc13xxx, MC13783_IRQ_ADCDONE);
650
651 mc13xxx_reg_write(mc13xxx, MC13783_ADC0, adc0);
652 mc13xxx_reg_write(mc13xxx, MC13783_ADC1, adc1);
653
654 mc13xxx_unlock(mc13xxx);
655
656 ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
657
658 if (!ret)
659 ret = -ETIMEDOUT;
660
661 mc13xxx_lock(mc13xxx);
662
663 mc13xxx_irq_free(mc13xxx, MC13783_IRQ_ADCDONE, &adcdone_data);
664
665 if (ret > 0)
666 for (i = 0; i < 4; ++i) {
667 ret = mc13xxx_reg_read(mc13xxx,
668 MC13783_ADC2, &sample[i]);
669 if (ret)
670 break;
671 }
672
673 if (mode == MC13783_ADC_MODE_TS)
674 /* restore TSMOD */
675 mc13xxx_reg_write(mc13xxx, MC13783_ADC0, old_adc0);
676
677 mc13783->adcflags &= ~MC13783_ADC_WORKING;
678out:
679 mc13xxx_unlock(mc13xxx);
680
681 return ret;
682}
683EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
684
685static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
686 const char *format, void *pdata, size_t pdata_size)
687{
688 char buf[30];
689 const char *name = mc13xxx_get_chipname(mc13xxx);
690
691 struct mfd_cell cell = {
692 .platform_data = pdata,
693 .data_size = pdata_size,
694 };
695
696 /* there is no asnprintf in the kernel :-( */
697 if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
698 return -E2BIG;
699
700 cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
701 if (!cell.name)
702 return -ENOMEM;
703
704 return mfd_add_devices(&mc13xxx->spidev->dev, -1, &cell, 1, NULL, 0);
705}
706
707static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
708{
709 return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
710}
711
712static int mc13xxx_probe(struct spi_device *spi)
713{
714 struct mc13xxx *mc13xxx;
715 struct mc13xxx_platform_data *pdata = dev_get_platdata(&spi->dev);
716 enum mc13xxx_id id;
717 int ret;
718
719 mc13xxx = kzalloc(sizeof(*mc13xxx), GFP_KERNEL);
720 if (!mc13xxx)
721 return -ENOMEM;
722
723 dev_set_drvdata(&spi->dev, mc13xxx);
724 spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
725 spi->bits_per_word = 32;
726 spi_setup(spi);
727
728 mc13xxx->spidev = spi;
729
730 mutex_init(&mc13xxx->lock);
731 mc13xxx_lock(mc13xxx);
732
733 ret = mc13xxx_identify(mc13xxx, &id);
734 if (ret || id == MC13XXX_ID_INVALID)
735 goto err_revision;
736
737 /* mask all irqs */
738 ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK0, 0x00ffffff);
739 if (ret)
740 goto err_mask;
741
742 ret = mc13xxx_reg_write(mc13xxx, MC13XXX_IRQMASK1, 0x00ffffff);
743 if (ret)
744 goto err_mask;
745
746 ret = request_threaded_irq(spi->irq, NULL, mc13xxx_irq_thread,
747 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13xxx", mc13xxx);
748
749 if (ret) {
750err_mask:
751err_revision:
752 mutex_unlock(&mc13xxx->lock);
753 dev_set_drvdata(&spi->dev, NULL);
754 kfree(mc13xxx);
755 return ret;
756 }
757
758 mc13xxx_unlock(mc13xxx);
759
760 if (pdata->flags & MC13XXX_USE_ADC)
761 mc13xxx_add_subdevice(mc13xxx, "%s-adc");
762
763 if (pdata->flags & MC13XXX_USE_CODEC)
764 mc13xxx_add_subdevice(mc13xxx, "%s-codec");
765
766 if (pdata->flags & MC13XXX_USE_REGULATOR) {
767 struct mc13xxx_regulator_platform_data regulator_pdata = {
768 .num_regulators = pdata->num_regulators,
769 .regulators = pdata->regulators,
770 };
771
772 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
773 &regulator_pdata, sizeof(regulator_pdata));
774 }
775
776 if (pdata->flags & MC13XXX_USE_RTC)
777 mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
778
779 if (pdata->flags & MC13XXX_USE_TOUCHSCREEN)
780 mc13xxx_add_subdevice(mc13xxx, "%s-ts");
781
782 if (pdata->flags & MC13XXX_USE_LED) {
783 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
784 pdata->leds, sizeof(*pdata->leds));
785 }
786
787 return 0;
788}
789
790static int __devexit mc13xxx_remove(struct spi_device *spi)
791{
792 struct mc13xxx *mc13xxx = dev_get_drvdata(&spi->dev);
793
794 free_irq(mc13xxx->spidev->irq, mc13xxx);
795
796 mfd_remove_devices(&spi->dev);
797
cef92fe6
AL		 798 kfree(mc13xxx);
799
8e005935
UKK		 800 return 0;
801}
802
803static const struct spi_device_id mc13xxx_device_id[] = {
804 {
805 .name = "mc13783",
806 .driver_data = MC13XXX_ID_MC13783,
807 }, {
808 .name = "mc13892",
809 .driver_data = MC13XXX_ID_MC13892,
810 }, {
811 /* sentinel */
812 }
813};
814
815static struct spi_driver mc13xxx_driver = {
816 .id_table = mc13xxx_device_id,
817 .driver = {
818 .name = "mc13xxx",
819 .bus = &spi_bus_type,
820 .owner = THIS_MODULE,
821 },
822 .probe = mc13xxx_probe,
823 .remove = __devexit_p(mc13xxx_remove),
824};
825
826static int __init mc13xxx_init(void)
827{
828 return spi_register_driver(&mc13xxx_driver);
829}
830subsys_initcall(mc13xxx_init);
831
832static void __exit mc13xxx_exit(void)
833{
834 spi_unregister_driver(&mc13xxx_driver);
835}
836module_exit(mc13xxx_exit);
837
838MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
839MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
840MODULE_LICENSE("GPL v2");
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