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[net-next-2.6.git] / drivers / mfd / mc13783-core.c
CommitLineData
8238addc 1/*
9e272677
UKK		 2 * Copyright 2009 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
8238addc 4 *
9e272677
UKK		 5 * loosely based on an earlier driver that has
6 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
8238addc 7 *
9e272677
UKK		 8 * This program is free software; you can redistribute it and/or modify it under
9 * the terms of the GNU General Public License version 2 as published by the
10 * Free Software Foundation.
8238addc 11 */
5a0e3ad6 12#include <linux/slab.h>
8238addc 13#include <linux/module.h>
9e272677
UKK		 14#include <linux/spi/spi.h>
15#include <linux/mfd/core.h>
16#include <linux/mfd/mc13783-private.h>
17
18#define MC13783_IRQSTAT0 0
19#define MC13783_IRQSTAT0_ADCDONEI (1 << 0)
20#define MC13783_IRQSTAT0_ADCBISDONEI (1 << 1)
21#define MC13783_IRQSTAT0_TSI (1 << 2)
22#define MC13783_IRQSTAT0_WHIGHI (1 << 3)
23#define MC13783_IRQSTAT0_WLOWI (1 << 4)
24#define MC13783_IRQSTAT0_CHGDETI (1 << 6)
25#define MC13783_IRQSTAT0_CHGOVI (1 << 7)
26#define MC13783_IRQSTAT0_CHGREVI (1 << 8)
27#define MC13783_IRQSTAT0_CHGSHORTI (1 << 9)
28#define MC13783_IRQSTAT0_CCCVI (1 << 10)
29#define MC13783_IRQSTAT0_CHGCURRI (1 << 11)
30#define MC13783_IRQSTAT0_BPONI (1 << 12)
31#define MC13783_IRQSTAT0_LOBATLI (1 << 13)
32#define MC13783_IRQSTAT0_LOBATHI (1 << 14)
33#define MC13783_IRQSTAT0_UDPI (1 << 15)
34#define MC13783_IRQSTAT0_USBI (1 << 16)
35#define MC13783_IRQSTAT0_IDI (1 << 19)
36#define MC13783_IRQSTAT0_SE1I (1 << 21)
37#define MC13783_IRQSTAT0_CKDETI (1 << 22)
38#define MC13783_IRQSTAT0_UDMI (1 << 23)
39
40#define MC13783_IRQMASK0 1
41#define MC13783_IRQMASK0_ADCDONEM MC13783_IRQSTAT0_ADCDONEI
42#define MC13783_IRQMASK0_ADCBISDONEM MC13783_IRQSTAT0_ADCBISDONEI
43#define MC13783_IRQMASK0_TSM MC13783_IRQSTAT0_TSI
44#define MC13783_IRQMASK0_WHIGHM MC13783_IRQSTAT0_WHIGHI
45#define MC13783_IRQMASK0_WLOWM MC13783_IRQSTAT0_WLOWI
46#define MC13783_IRQMASK0_CHGDETM MC13783_IRQSTAT0_CHGDETI
47#define MC13783_IRQMASK0_CHGOVM MC13783_IRQSTAT0_CHGOVI
48#define MC13783_IRQMASK0_CHGREVM MC13783_IRQSTAT0_CHGREVI
49#define MC13783_IRQMASK0_CHGSHORTM MC13783_IRQSTAT0_CHGSHORTI
50#define MC13783_IRQMASK0_CCCVM MC13783_IRQSTAT0_CCCVI
51#define MC13783_IRQMASK0_CHGCURRM MC13783_IRQSTAT0_CHGCURRI
52#define MC13783_IRQMASK0_BPONM MC13783_IRQSTAT0_BPONI
53#define MC13783_IRQMASK0_LOBATLM MC13783_IRQSTAT0_LOBATLI
54#define MC13783_IRQMASK0_LOBATHM MC13783_IRQSTAT0_LOBATHI
55#define MC13783_IRQMASK0_UDPM MC13783_IRQSTAT0_UDPI
56#define MC13783_IRQMASK0_USBM MC13783_IRQSTAT0_USBI
57#define MC13783_IRQMASK0_IDM MC13783_IRQSTAT0_IDI
58#define MC13783_IRQMASK0_SE1M MC13783_IRQSTAT0_SE1I
59#define MC13783_IRQMASK0_CKDETM MC13783_IRQSTAT0_CKDETI
60#define MC13783_IRQMASK0_UDMM MC13783_IRQSTAT0_UDMI
61
62#define MC13783_IRQSTAT1 3
63#define MC13783_IRQSTAT1_1HZI (1 << 0)
64#define MC13783_IRQSTAT1_TODAI (1 << 1)
65#define MC13783_IRQSTAT1_ONOFD1I (1 << 3)
66#define MC13783_IRQSTAT1_ONOFD2I (1 << 4)
67#define MC13783_IRQSTAT1_ONOFD3I (1 << 5)
68#define MC13783_IRQSTAT1_SYSRSTI (1 << 6)
69#define MC13783_IRQSTAT1_RTCRSTI (1 << 7)
70#define MC13783_IRQSTAT1_PCI (1 << 8)
71#define MC13783_IRQSTAT1_WARMI (1 << 9)
72#define MC13783_IRQSTAT1_MEMHLDI (1 << 10)
73#define MC13783_IRQSTAT1_PWRRDYI (1 << 11)
74#define MC13783_IRQSTAT1_THWARNLI (1 << 12)
75#define MC13783_IRQSTAT1_THWARNHI (1 << 13)
76#define MC13783_IRQSTAT1_CLKI (1 << 14)
77#define MC13783_IRQSTAT1_SEMAFI (1 << 15)
78#define MC13783_IRQSTAT1_MC2BI (1 << 17)
79#define MC13783_IRQSTAT1_HSDETI (1 << 18)
80#define MC13783_IRQSTAT1_HSLI (1 << 19)
81#define MC13783_IRQSTAT1_ALSPTHI (1 << 20)
82#define MC13783_IRQSTAT1_AHSSHORTI (1 << 21)
83
84#define MC13783_IRQMASK1 4
85#define MC13783_IRQMASK1_1HZM MC13783_IRQSTAT1_1HZI
86#define MC13783_IRQMASK1_TODAM MC13783_IRQSTAT1_TODAI
87#define MC13783_IRQMASK1_ONOFD1M MC13783_IRQSTAT1_ONOFD1I
88#define MC13783_IRQMASK1_ONOFD2M MC13783_IRQSTAT1_ONOFD2I
89#define MC13783_IRQMASK1_ONOFD3M MC13783_IRQSTAT1_ONOFD3I
90#define MC13783_IRQMASK1_SYSRSTM MC13783_IRQSTAT1_SYSRSTI
91#define MC13783_IRQMASK1_RTCRSTM MC13783_IRQSTAT1_RTCRSTI
92#define MC13783_IRQMASK1_PCM MC13783_IRQSTAT1_PCI
93#define MC13783_IRQMASK1_WARMM MC13783_IRQSTAT1_WARMI
94#define MC13783_IRQMASK1_MEMHLDM MC13783_IRQSTAT1_MEMHLDI
95#define MC13783_IRQMASK1_PWRRDYM MC13783_IRQSTAT1_PWRRDYI
96#define MC13783_IRQMASK1_THWARNLM MC13783_IRQSTAT1_THWARNLI
97#define MC13783_IRQMASK1_THWARNHM MC13783_IRQSTAT1_THWARNHI
98#define MC13783_IRQMASK1_CLKM MC13783_IRQSTAT1_CLKI
99#define MC13783_IRQMASK1_SEMAFM MC13783_IRQSTAT1_SEMAFI
100#define MC13783_IRQMASK1_MC2BM MC13783_IRQSTAT1_MC2BI
101#define MC13783_IRQMASK1_HSDETM MC13783_IRQSTAT1_HSDETI
102#define MC13783_IRQMASK1_HSLM MC13783_IRQSTAT1_HSLI
103#define MC13783_IRQMASK1_ALSPTHM MC13783_IRQSTAT1_ALSPTHI
104#define MC13783_IRQMASK1_AHSSHORTM MC13783_IRQSTAT1_AHSSHORTI
105
106#define MC13783_ADC1 44
107#define MC13783_ADC1_ADEN (1 << 0)
108#define MC13783_ADC1_RAND (1 << 1)
109#define MC13783_ADC1_ADSEL (1 << 3)
110#define MC13783_ADC1_ASC (1 << 20)
111#define MC13783_ADC1_ADTRIGIGN (1 << 21)
112
113#define MC13783_NUMREGS 0x3f
114
115void mc13783_lock(struct mc13783 *mc13783)
116{
117 if (!mutex_trylock(&mc13783->lock)) {
118 dev_dbg(&mc13783->spidev->dev, "wait for %s from %pf\n",
119 __func__, __builtin_return_address(0));
120
121 mutex_lock(&mc13783->lock);
122 }
123 dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
124 __func__, __builtin_return_address(0));
125}
126EXPORT_SYMBOL(mc13783_lock);
8238addc 127
9e272677
UKK		 128void mc13783_unlock(struct mc13783 *mc13783)
129{
130 dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
131 __func__, __builtin_return_address(0));
132 mutex_unlock(&mc13783->lock);
133}
134EXPORT_SYMBOL(mc13783_unlock);
8238addc 135
9e272677
UKK		 136#define MC13783_REGOFFSET_SHIFT 25
137int mc13783_reg_read(struct mc13783 *mc13783, unsigned int offset, u32 *val)
8238addc 138{
9e272677 139 struct spi_transfer t;
8238addc 140 struct spi_message m;
9e272677
UKK		 141 int ret;
142
143 BUG_ON(!mutex_is_locked(&mc13783->lock));
144
145 if (offset > MC13783_NUMREGS)
146 return -EINVAL;
147
148 *val = offset << MC13783_REGOFFSET_SHIFT;
149
150 memset(&t, 0, sizeof(t));
151
152 t.tx_buf = val;
153 t.rx_buf = val;
154 t.len = sizeof(u32);
8238addc
SH		 155
156 spi_message_init(&m);
157 spi_message_add_tail(&t, &m);
8238addc 158
9e272677 159 ret = spi_sync(mc13783->spidev, &m);
8238addc 160
9e272677
UKK		 161 /* error in message.status implies error return from spi_sync */
162 BUG_ON(!ret && m.status);
8238addc 163
9e272677
UKK		 164 if (ret)
165 return ret;
8238addc 166
9e272677 167 *val &= 0xffffff;
8238addc 168
9e272677 169 dev_vdbg(&mc13783->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
8238addc 170
9e272677 171 return 0;
8238addc 172}
9e272677 173EXPORT_SYMBOL(mc13783_reg_read);
8238addc 174
9e272677 175int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val)
8238addc 176{
9e272677
UKK		 177 u32 buf;
178 struct spi_transfer t;
179 struct spi_message m;
180 int ret;
181
182 BUG_ON(!mutex_is_locked(&mc13783->lock));
8238addc 183
9e272677
UKK		 184 dev_vdbg(&mc13783->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
185
186 if (offset > MC13783_NUMREGS || val > 0xffffff)
8238addc
SH		 187 return -EINVAL;
188
9e272677
UKK		 189 buf = 1 << 31 | offset << MC13783_REGOFFSET_SHIFT | val;
190
191 memset(&t, 0, sizeof(t));
8238addc 192
9e272677
UKK		 193 t.tx_buf = &buf;
194 t.rx_buf = &buf;
195 t.len = sizeof(u32);
196
197 spi_message_init(&m);
198 spi_message_add_tail(&t, &m);
199
200 ret = spi_sync(mc13783->spidev, &m);
201
202 BUG_ON(!ret && m.status);
203
204 if (ret)
205 return ret;
206
207 return 0;
8238addc 208}
9e272677 209EXPORT_SYMBOL(mc13783_reg_write);
8238addc 210
9e272677
UKK		 211int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
212 u32 mask, u32 val)
8238addc
SH		 213{
214 int ret;
9e272677 215 u32 valread;
8238addc 216
9e272677 217 BUG_ON(val & ~mask);
8238addc 218
9e272677
UKK		 219 ret = mc13783_reg_read(mc13783, offset, &valread);
220 if (ret)
221 return ret;
222
223 valread = (valread & ~mask) | val;
224
225 return mc13783_reg_write(mc13783, offset, valread);
8238addc 226}
9e272677 227EXPORT_SYMBOL(mc13783_reg_rmw);
8238addc 228
57205026 229int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
8238addc
SH		 230{
231 int ret;
9e272677
UKK		 232 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
233 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
234 u32 mask;
8238addc 235
9e272677
UKK		 236 if (irq < 0 || irq >= MC13783_NUM_IRQ)
237 return -EINVAL;
8238addc 238
9e272677
UKK		 239 ret = mc13783_reg_read(mc13783, offmask, &mask);
240 if (ret)
241 return ret;
242
243 if (mask & irqbit)
244 /* already masked */
245 return 0;
246
247 return mc13783_reg_write(mc13783, offmask, mask | irqbit);
8238addc 248}
57205026 249EXPORT_SYMBOL(mc13783_irq_mask);
8238addc 250
57205026 251int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
8238addc 252{
8238addc 253 int ret;
9e272677
UKK		 254 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
255 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
256 u32 mask;
8238addc 257
9e272677
UKK		 258 if (irq < 0 || irq >= MC13783_NUM_IRQ)
259 return -EINVAL;
8238addc 260
9e272677
UKK		 261 ret = mc13783_reg_read(mc13783, offmask, &mask);
262 if (ret)
263 return ret;
8238addc 264
9e272677
UKK		 265 if (!(mask & irqbit))
266 /* already unmasked */
267 return 0;
8238addc 268
9e272677 269 return mc13783_reg_write(mc13783, offmask, mask & ~irqbit);
8238addc 270}
57205026
UKK		 271EXPORT_SYMBOL(mc13783_irq_unmask);
272
86c34008
UKK		 273int mc13783_irq_status(struct mc13783 *mc13783, int irq,
274 int *enabled, int *pending)
275{
276 int ret;
277 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
278 unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
279 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
280
281 if (irq < 0 || irq >= MC13783_NUM_IRQ)
282 return -EINVAL;
283
284 if (enabled) {
285 u32 mask;
286
287 ret = mc13783_reg_read(mc13783, offmask, &mask);
288 if (ret)
289 return ret;
290
291 *enabled = mask & irqbit;
292 }
293
294 if (pending) {
295 u32 stat;
296
297 ret = mc13783_reg_read(mc13783, offstat, &stat);
298 if (ret)
299 return ret;
300
301 *pending = stat & irqbit;
302 }
303
304 return 0;
305}
306EXPORT_SYMBOL(mc13783_irq_status);
307
57205026
UKK		 308int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
309{
310 unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
311 unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
312
313 BUG_ON(irq < 0 || irq >= MC13783_NUM_IRQ);
314
315 return mc13783_reg_write(mc13783, offstat, val);
316}
317EXPORT_SYMBOL(mc13783_irq_ack);
8238addc 318
9e272677
UKK		 319int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
320 irq_handler_t handler, const char *name, void *dev)
8238addc 321{
9e272677
UKK		 322 BUG_ON(!mutex_is_locked(&mc13783->lock));
323 BUG_ON(!handler);
324
325 if (irq < 0 || irq >= MC13783_NUM_IRQ)
8238addc
SH		 326 return -EINVAL;
327
9e272677 328 if (mc13783->irqhandler[irq])
8238addc
SH		 329 return -EBUSY;
330
9e272677
UKK		 331 mc13783->irqhandler[irq] = handler;
332 mc13783->irqdata[irq] = dev;
8238addc
SH		 333
334 return 0;
335}
9e272677 336EXPORT_SYMBOL(mc13783_irq_request_nounmask);
8238addc 337
9e272677
UKK		 338int mc13783_irq_request(struct mc13783 *mc13783, int irq,
339 irq_handler_t handler, const char *name, void *dev)
8238addc 340{
9e272677
UKK		 341 int ret;
342
343 ret = mc13783_irq_request_nounmask(mc13783, irq, handler, name, dev);
344 if (ret)
345 return ret;
346
57205026 347 ret = mc13783_irq_unmask(mc13783, irq);
9e272677
UKK		 348 if (ret) {
349 mc13783->irqhandler[irq] = NULL;
350 mc13783->irqdata[irq] = NULL;
351 return ret;
352 }
353
354 return 0;
355}
356EXPORT_SYMBOL(mc13783_irq_request);
357
358int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
359{
360 int ret;
361 BUG_ON(!mutex_is_locked(&mc13783->lock));
362
363 if (irq < 0 || irq >= MC13783_NUM_IRQ || !mc13783->irqhandler[irq] ||
364 mc13783->irqdata[irq] != dev)
8238addc
SH		 365 return -EINVAL;
366
57205026 367 ret = mc13783_irq_mask(mc13783, irq);
9e272677
UKK		 368 if (ret)
369 return ret;
370
371 mc13783->irqhandler[irq] = NULL;
372 mc13783->irqdata[irq] = NULL;
8238addc
SH		 373
374 return 0;
375}
9e272677 376EXPORT_SYMBOL(mc13783_irq_free);
8238addc 377
9e272677 378static inline irqreturn_t mc13783_irqhandler(struct mc13783 *mc13783, int irq)
8238addc 379{
9e272677 380 return mc13783->irqhandler[irq](irq, mc13783->irqdata[irq]);
8238addc
SH		 381}
382
9e272677
UKK		 383/*
384 * returns: number of handled irqs or negative error
385 * locking: holds mc13783->lock
386 */
387static int mc13783_irq_handle(struct mc13783 *mc13783,
388 unsigned int offstat, unsigned int offmask, int baseirq)
8238addc 389{
9e272677
UKK		 390 u32 stat, mask;
391 int ret = mc13783_reg_read(mc13783, offstat, &stat);
392 int num_handled = 0;
393
394 if (ret)
395 return ret;
396
397 ret = mc13783_reg_read(mc13783, offmask, &mask);
398 if (ret)
399 return ret;
400
401 while (stat & ~mask) {
402 int irq = __ffs(stat & ~mask);
403
404 stat &= ~(1 << irq);
405
406 if (likely(mc13783->irqhandler[baseirq + irq])) {
407 irqreturn_t handled;
8238addc 408
9e272677
UKK		 409 handled = mc13783_irqhandler(mc13783, baseirq + irq);
410 if (handled == IRQ_HANDLED)
411 num_handled++;
412 } else {
413 dev_err(&mc13783->spidev->dev,
414 "BUG: irq %u but no handler\n",
415 baseirq + irq);
8238addc 416
9e272677
UKK		 417 mask |= 1 << irq;
418
419 ret = mc13783_reg_write(mc13783, offmask, mask);
420 }
421 }
422
423 return num_handled;
8238addc
SH		 424}
425
9e272677
UKK		 426static irqreturn_t mc13783_irq_thread(int irq, void *data)
427{
428 struct mc13783 *mc13783 = data;
429 irqreturn_t ret;
430 int handled = 0;
431
432 mc13783_lock(mc13783);
433
434 ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT0,
435 MC13783_IRQMASK0, MC13783_IRQ_ADCDONE);
436 if (ret > 0)
437 handled = 1;
438
439 ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT1,
440 MC13783_IRQMASK1, MC13783_IRQ_1HZ);
441 if (ret > 0)
442 handled = 1;
443
444 mc13783_unlock(mc13783);
445
446 return IRQ_RETVAL(handled);
447}
448
449#define MC13783_ADC1_CHAN0_SHIFT 5
450#define MC13783_ADC1_CHAN1_SHIFT 8
451
452struct mc13783_adcdone_data {
453 struct mc13783 *mc13783;
454 struct completion done;
455};
456
457static irqreturn_t mc13783_handler_adcdone(int irq, void *data)
458{
459 struct mc13783_adcdone_data *adcdone_data = data;
460
57205026 461 mc13783_irq_ack(adcdone_data->mc13783, irq);
9e272677
UKK		 462
463 complete_all(&adcdone_data->done);
464
465 return IRQ_HANDLED;
466}
467
468#define MC13783_ADC_WORKING (1 << 16)
469
8238addc
SH		 470int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
471 unsigned int channel, unsigned int *sample)
472{
9e272677
UKK		 473 u32 adc0, adc1, old_adc0;
474 int i, ret;
475 struct mc13783_adcdone_data adcdone_data = {
476 .mc13783 = mc13783,
477 };
478 init_completion(&adcdone_data.done);
479
480 dev_dbg(&mc13783->spidev->dev, "%s\n", __func__);
481
482 mc13783_lock(mc13783);
483
484 if (mc13783->flags & MC13783_ADC_WORKING) {
485 ret = -EBUSY;
486 goto out;
487 }
488
489 mc13783->flags |= MC13783_ADC_WORKING;
8238addc 490
9e272677 491 mc13783_reg_read(mc13783, MC13783_ADC0, &old_adc0);
8238addc 492
9e272677
UKK		 493 adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
494 adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN | MC13783_ADC1_ASC;
8238addc 495
8238addc 496 if (channel > 7)
9e272677 497 adc1 |= MC13783_ADC1_ADSEL;
8238addc
SH		 498
499 switch (mode) {
500 case MC13783_ADC_MODE_TS:
be26d664
UKK		 501 adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_TSMOD0 |
502 MC13783_ADC0_TSMOD1;
9e272677 503 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
8238addc 504 break;
9e272677 505
8238addc 506 case MC13783_ADC_MODE_SINGLE_CHAN:
9e272677
UKK		 507 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
508 adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
509 adc1 |= MC13783_ADC1_RAND;
8238addc 510 break;
9e272677 511
8238addc 512 case MC13783_ADC_MODE_MULT_CHAN:
9e272677
UKK		 513 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
514 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
8238addc 515 break;
9e272677 516
8238addc 517 default:
9e272677 518 mc13783_unlock(mc13783);
8238addc
SH		 519 return -EINVAL;
520 }
521
9e272677
UKK		 522 dev_dbg(&mc13783->spidev->dev, "%s: request irq\n", __func__);
523 mc13783_irq_request(mc13783, MC13783_IRQ_ADCDONE,
524 mc13783_handler_adcdone, __func__, &adcdone_data);
57205026 525 mc13783_irq_ack(mc13783, MC13783_IRQ_ADCDONE);
8238addc 526
9e272677
UKK		 527 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, adc0);
528 mc13783_reg_write(mc13783, MC13783_REG_ADC_1, adc1);
8238addc 529
9e272677 530 mc13783_unlock(mc13783);
8238addc 531
9e272677 532 ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
8238addc 533
9e272677
UKK		 534 if (!ret)
535 ret = -ETIMEDOUT;
8238addc 536
9e272677
UKK		 537 mc13783_lock(mc13783);
538
539 mc13783_irq_free(mc13783, MC13783_IRQ_ADCDONE, &adcdone_data);
540
541 if (ret > 0)
542 for (i = 0; i < 4; ++i) {
543 ret = mc13783_reg_read(mc13783,
544 MC13783_REG_ADC_2, &sample[i]);
545 if (ret)
546 break;
547 }
548
549 if (mode == MC13783_ADC_MODE_TS)
550 /* restore TSMOD */
551 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, old_adc0);
552
553 mc13783->flags &= ~MC13783_ADC_WORKING;
554out:
555 mc13783_unlock(mc13783);
556
557 return ret;
8238addc
SH		 558}
559EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
560
9e272677
UKK		 561static int mc13783_add_subdevice_pdata(struct mc13783 *mc13783,
562 const char *name, void *pdata, size_t pdata_size)
8238addc 563{
9e272677
UKK		 564 struct mfd_cell cell = {
565 .name = name,
566 .platform_data = pdata,
567 .data_size = pdata_size,
568 };
569
570 return mfd_add_devices(&mc13783->spidev->dev, -1, &cell, 1, NULL, 0);
571}
572
573static int mc13783_add_subdevice(struct mc13783 *mc13783, const char *name)
574{
575 return mc13783_add_subdevice_pdata(mc13783, name, NULL, 0);
8238addc 576}
8238addc
SH		 577
578static int mc13783_check_revision(struct mc13783 *mc13783)
579{
580 u32 rev_id, rev1, rev2, finid, icid;
581
9e272677 582 mc13783_reg_read(mc13783, MC13783_REG_REVISION, &rev_id);
8238addc
SH		 583
584 rev1 = (rev_id & 0x018) >> 3;
585 rev2 = (rev_id & 0x007);
586 icid = (rev_id & 0x01C0) >> 6;
587 finid = (rev_id & 0x01E00) >> 9;
588
589 /* Ver 0.2 is actually 3.2a. Report as 3.2 */
590 if ((rev1 == 0) && (rev2 == 2))
591 rev1 = 3;
592
593 if (rev1 == 0 || icid != 2) {
9e272677 594 dev_err(&mc13783->spidev->dev, "No MC13783 detected.\n");
8238addc
SH		 595 return -ENODEV;
596 }
597
9e272677
UKK		 598 dev_info(&mc13783->spidev->dev,
599 "MC13783 Rev %d.%d FinVer %x detected\n",
600 rev1, rev2, finid);
8238addc
SH		 601
602 return 0;
603}
604
9e272677 605static int mc13783_probe(struct spi_device *spi)
8238addc
SH		 606{
607 struct mc13783 *mc13783;
9e272677 608 struct mc13783_platform_data *pdata = dev_get_platdata(&spi->dev);
8238addc
SH		 609 int ret;
610
9e272677 611 mc13783 = kzalloc(sizeof(*mc13783), GFP_KERNEL);
8238addc
SH		 612 if (!mc13783)
613 return -ENOMEM;
614
615 dev_set_drvdata(&spi->dev, mc13783);
616 spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
617 spi->bits_per_word = 32;
618 spi_setup(spi);
619
9e272677
UKK		 620 mc13783->spidev = spi;
621
622 mutex_init(&mc13783->lock);
623 mc13783_lock(mc13783);
624
625 ret = mc13783_check_revision(mc13783);
626 if (ret)
627 goto err_revision;
628
629 /* mask all irqs */
630 ret = mc13783_reg_write(mc13783, MC13783_IRQMASK0, 0x00ffffff);
631 if (ret)
632 goto err_mask;
8238addc 633
9e272677
UKK		 634 ret = mc13783_reg_write(mc13783, MC13783_IRQMASK1, 0x00ffffff);
635 if (ret)
636 goto err_mask;
637
638 ret = request_threaded_irq(spi->irq, NULL, mc13783_irq_thread,
639 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13783", mc13783);
640
641 if (ret) {
642err_mask:
643err_revision:
644 mutex_unlock(&mc13783->lock);
645 dev_set_drvdata(&spi->dev, NULL);
646 kfree(mc13783);
647 return ret;
648 }
8238addc 649
9e272677 650 /* This should go away (BEGIN) */
8238addc
SH		 651 if (pdata) {
652 mc13783->flags = pdata->flags;
653 mc13783->regulators = pdata->regulators;
654 mc13783->num_regulators = pdata->num_regulators;
655 }
9e272677 656 /* This should go away (END) */
8238addc 657
1e02b2c3
AP		 658 mc13783_unlock(mc13783);
659
9e272677
UKK		 660 if (pdata->flags & MC13783_USE_ADC)
661 mc13783_add_subdevice(mc13783, "mc13783-adc");
662
663 if (pdata->flags & MC13783_USE_CODEC)
664 mc13783_add_subdevice(mc13783, "mc13783-codec");
665
666 if (pdata->flags & MC13783_USE_REGULATOR) {
667 struct mc13783_regulator_platform_data regulator_pdata = {
668 .num_regulators = pdata->num_regulators,
669 .regulators = pdata->regulators,
670 };
671
672 mc13783_add_subdevice_pdata(mc13783, "mc13783-regulator",
673 &regulator_pdata, sizeof(regulator_pdata));
8238addc
SH		 674 }
675
9e272677
UKK		 676 if (pdata->flags & MC13783_USE_RTC)
677 mc13783_add_subdevice(mc13783, "mc13783-rtc");
8238addc 678
9e272677
UKK		 679 if (pdata->flags & MC13783_USE_TOUCHSCREEN)
680 mc13783_add_subdevice(mc13783, "mc13783-ts");
8238addc 681
7fdcef8a
PR		 682 if (pdata->flags & MC13783_USE_LED)
683 mc13783_add_subdevice_pdata(mc13783, "mc13783-led",
684 pdata->leds, sizeof(*pdata->leds));
685
8238addc 686 return 0;
8238addc
SH		 687}
688
689static int __devexit mc13783_remove(struct spi_device *spi)
690{
9e272677 691 struct mc13783 *mc13783 = dev_get_drvdata(&spi->dev);
8238addc 692
9e272677 693 free_irq(mc13783->spidev->irq, mc13783);
8238addc
SH		 694
695 mfd_remove_devices(&spi->dev);
696
697 return 0;
698}
699
9e272677 700static struct spi_driver mc13783_driver = {
8238addc 701 .driver = {
9e272677
UKK		 702 .name = "mc13783",
703 .bus = &spi_bus_type,
704 .owner = THIS_MODULE,
8238addc
SH		 705 },
706 .probe = mc13783_probe,
707 .remove = __devexit_p(mc13783_remove),
708};
709
9e272677 710static int __init mc13783_init(void)
8238addc 711{
9e272677 712 return spi_register_driver(&mc13783_driver);
8238addc 713}
9e272677 714subsys_initcall(mc13783_init);
8238addc 715
9e272677 716static void __exit mc13783_exit(void)
8238addc 717{
9e272677 718 spi_unregister_driver(&mc13783_driver);
8238addc 719}
9e272677 720module_exit(mc13783_exit);
8238addc 721
9e272677
UKK		 722MODULE_DESCRIPTION("Core driver for Freescale MC13783 PMIC");
723MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
724MODULE_LICENSE("GPL v2");
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