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[net-next-2.6.git] / drivers / mfd / mc13783-core.c
CommitLineData
8238addc 1/*
9e272677
UKK		 2 * Copyright 2009 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
8238addc 4 *
9e272677
UKK		 5 * loosely based on an earlier driver that has
6 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
8238addc 7 *
9e272677
UKK		 8 * This program is free software; you can redistribute it and/or modify it under
9 * the terms of the GNU General Public License version 2 as published by the
10 * Free Software Foundation.
8238addc 11 */
5a0e3ad6 12#include <linux/slab.h>
8238addc 13#include <linux/module.h>
b6e6d54c
UKK		 14#include <linux/platform_device.h>
15#include <linux/mutex.h>
16#include <linux/interrupt.h>
9e272677
UKK		 17#include <linux/spi/spi.h>
18#include <linux/mfd/core.h>
b6e6d54c
UKK		 19#include <linux/mfd/mc13783.h>
20
21struct mc13783 {
22 struct spi_device *spidev;
23 struct mutex lock;
24 int irq;
25 int flags;
26
27 irq_handler_t irqhandler[MC13783_NUM_IRQ];
28 void *irqdata[MC13783_NUM_IRQ];
29
30 /* XXX these should go as platformdata to the regulator subdevice */
31 struct mc13783_regulator_init_data *regulators;
32 int num_regulators;
33};
34
35#define MC13783_REG_REVISION 7
36#define MC13783_REG_ADC_0 43
37#define MC13783_REG_ADC_1 44
38#define MC13783_REG_ADC_2 45
9e272677
UKK		 39
40#define MC13783_IRQSTAT0 0
41#define MC13783_IRQSTAT0_ADCDONEI (1 << 0)
42#define MC13783_IRQSTAT0_ADCBISDONEI (1 << 1)
43#define MC13783_IRQSTAT0_TSI (1 << 2)
44#define MC13783_IRQSTAT0_WHIGHI (1 << 3)
45#define MC13783_IRQSTAT0_WLOWI (1 << 4)
46#define MC13783_IRQSTAT0_CHGDETI (1 << 6)
47#define MC13783_IRQSTAT0_CHGOVI (1 << 7)
48#define MC13783_IRQSTAT0_CHGREVI (1 << 8)
49#define MC13783_IRQSTAT0_CHGSHORTI (1 << 9)
50#define MC13783_IRQSTAT0_CCCVI (1 << 10)
51#define MC13783_IRQSTAT0_CHGCURRI (1 << 11)
52#define MC13783_IRQSTAT0_BPONI (1 << 12)
53#define MC13783_IRQSTAT0_LOBATLI (1 << 13)
54#define MC13783_IRQSTAT0_LOBATHI (1 << 14)
55#define MC13783_IRQSTAT0_UDPI (1 << 15)
56#define MC13783_IRQSTAT0_USBI (1 << 16)
57#define MC13783_IRQSTAT0_IDI (1 << 19)
58#define MC13783_IRQSTAT0_SE1I (1 << 21)
59#define MC13783_IRQSTAT0_CKDETI (1 << 22)
60#define MC13783_IRQSTAT0_UDMI (1 << 23)
61
62#define MC13783_IRQMASK0 1
63#define MC13783_IRQMASK0_ADCDONEM MC13783_IRQSTAT0_ADCDONEI
64#define MC13783_IRQMASK0_ADCBISDONEM MC13783_IRQSTAT0_ADCBISDONEI
65#define MC13783_IRQMASK0_TSM MC13783_IRQSTAT0_TSI
66#define MC13783_IRQMASK0_WHIGHM MC13783_IRQSTAT0_WHIGHI
67#define MC13783_IRQMASK0_WLOWM MC13783_IRQSTAT0_WLOWI
68#define MC13783_IRQMASK0_CHGDETM MC13783_IRQSTAT0_CHGDETI
69#define MC13783_IRQMASK0_CHGOVM MC13783_IRQSTAT0_CHGOVI
70#define MC13783_IRQMASK0_CHGREVM MC13783_IRQSTAT0_CHGREVI
71#define MC13783_IRQMASK0_CHGSHORTM MC13783_IRQSTAT0_CHGSHORTI
72#define MC13783_IRQMASK0_CCCVM MC13783_IRQSTAT0_CCCVI
73#define MC13783_IRQMASK0_CHGCURRM MC13783_IRQSTAT0_CHGCURRI
74#define MC13783_IRQMASK0_BPONM MC13783_IRQSTAT0_BPONI
75#define MC13783_IRQMASK0_LOBATLM MC13783_IRQSTAT0_LOBATLI
76#define MC13783_IRQMASK0_LOBATHM MC13783_IRQSTAT0_LOBATHI
77#define MC13783_IRQMASK0_UDPM MC13783_IRQSTAT0_UDPI
78#define MC13783_IRQMASK0_USBM MC13783_IRQSTAT0_USBI
79#define MC13783_IRQMASK0_IDM MC13783_IRQSTAT0_IDI
80#define MC13783_IRQMASK0_SE1M MC13783_IRQSTAT0_SE1I
81#define MC13783_IRQMASK0_CKDETM MC13783_IRQSTAT0_CKDETI
82#define MC13783_IRQMASK0_UDMM MC13783_IRQSTAT0_UDMI
83
84#define MC13783_IRQSTAT1 3
85#define MC13783_IRQSTAT1_1HZI (1 << 0)
86#define MC13783_IRQSTAT1_TODAI (1 << 1)
87#define MC13783_IRQSTAT1_ONOFD1I (1 << 3)
88#define MC13783_IRQSTAT1_ONOFD2I (1 << 4)
89#define MC13783_IRQSTAT1_ONOFD3I (1 << 5)
90#define MC13783_IRQSTAT1_SYSRSTI (1 << 6)
91#define MC13783_IRQSTAT1_RTCRSTI (1 << 7)
92#define MC13783_IRQSTAT1_PCI (1 << 8)
93#define MC13783_IRQSTAT1_WARMI (1 << 9)
94#define MC13783_IRQSTAT1_MEMHLDI (1 << 10)
95#define MC13783_IRQSTAT1_PWRRDYI (1 << 11)
96#define MC13783_IRQSTAT1_THWARNLI (1 << 12)
97#define MC13783_IRQSTAT1_THWARNHI (1 << 13)
98#define MC13783_IRQSTAT1_CLKI (1 << 14)
99#define MC13783_IRQSTAT1_SEMAFI (1 << 15)
100#define MC13783_IRQSTAT1_MC2BI (1 << 17)
101#define MC13783_IRQSTAT1_HSDETI (1 << 18)
102#define MC13783_IRQSTAT1_HSLI (1 << 19)
103#define MC13783_IRQSTAT1_ALSPTHI (1 << 20)
104#define MC13783_IRQSTAT1_AHSSHORTI (1 << 21)
105
106#define MC13783_IRQMASK1 4
107#define MC13783_IRQMASK1_1HZM MC13783_IRQSTAT1_1HZI
108#define MC13783_IRQMASK1_TODAM MC13783_IRQSTAT1_TODAI
109#define MC13783_IRQMASK1_ONOFD1M MC13783_IRQSTAT1_ONOFD1I
110#define MC13783_IRQMASK1_ONOFD2M MC13783_IRQSTAT1_ONOFD2I
111#define MC13783_IRQMASK1_ONOFD3M MC13783_IRQSTAT1_ONOFD3I
112#define MC13783_IRQMASK1_SYSRSTM MC13783_IRQSTAT1_SYSRSTI
113#define MC13783_IRQMASK1_RTCRSTM MC13783_IRQSTAT1_RTCRSTI
114#define MC13783_IRQMASK1_PCM MC13783_IRQSTAT1_PCI
115#define MC13783_IRQMASK1_WARMM MC13783_IRQSTAT1_WARMI
116#define MC13783_IRQMASK1_MEMHLDM MC13783_IRQSTAT1_MEMHLDI
117#define MC13783_IRQMASK1_PWRRDYM MC13783_IRQSTAT1_PWRRDYI
118#define MC13783_IRQMASK1_THWARNLM MC13783_IRQSTAT1_THWARNLI
119#define MC13783_IRQMASK1_THWARNHM MC13783_IRQSTAT1_THWARNHI
120#define MC13783_IRQMASK1_CLKM MC13783_IRQSTAT1_CLKI
121#define MC13783_IRQMASK1_SEMAFM MC13783_IRQSTAT1_SEMAFI
122#define MC13783_IRQMASK1_MC2BM MC13783_IRQSTAT1_MC2BI
123#define MC13783_IRQMASK1_HSDETM MC13783_IRQSTAT1_HSDETI
124#define MC13783_IRQMASK1_HSLM MC13783_IRQSTAT1_HSLI
125#define MC13783_IRQMASK1_ALSPTHM MC13783_IRQSTAT1_ALSPTHI
126#define MC13783_IRQMASK1_AHSSHORTM MC13783_IRQSTAT1_AHSSHORTI
127
128#define MC13783_ADC1 44
129#define MC13783_ADC1_ADEN (1 << 0)
130#define MC13783_ADC1_RAND (1 << 1)
131#define MC13783_ADC1_ADSEL (1 << 3)
132#define MC13783_ADC1_ASC (1 << 20)
133#define MC13783_ADC1_ADTRIGIGN (1 << 21)
134
135#define MC13783_NUMREGS 0x3f
136
137void mc13783_lock(struct mc13783 *mc13783)
138{
139 if (!mutex_trylock(&mc13783->lock)) {
140 dev_dbg(&mc13783->spidev->dev, "wait for %s from %pf\n",
141 __func__, __builtin_return_address(0));
142
143 mutex_lock(&mc13783->lock);
144 }
145 dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
146 __func__, __builtin_return_address(0));
147}
148EXPORT_SYMBOL(mc13783_lock);
8238addc 149
9e272677
UKK		 150void mc13783_unlock(struct mc13783 *mc13783)
151{
152 dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
153 __func__, __builtin_return_address(0));
154 mutex_unlock(&mc13783->lock);
155}
156EXPORT_SYMBOL(mc13783_unlock);
8238addc 157
9e272677
UKK		 158#define MC13783_REGOFFSET_SHIFT 25
159int mc13783_reg_read(struct mc13783 *mc13783, unsigned int offset, u32 *val)
8238addc 160{
9e272677 161 struct spi_transfer t;
8238addc 162 struct spi_message m;
9e272677
UKK		 163 int ret;
164
165 BUG_ON(!mutex_is_locked(&mc13783->lock));
166
167 if (offset > MC13783_NUMREGS)
168 return -EINVAL;
169
170 *val = offset << MC13783_REGOFFSET_SHIFT;
171
172 memset(&t, 0, sizeof(t));
173
174 t.tx_buf = val;
175 t.rx_buf = val;
176 t.len = sizeof(u32);
8238addc
SH		 177
178 spi_message_init(&m);
179 spi_message_add_tail(&t, &m);
8238addc 180
9e272677 181 ret = spi_sync(mc13783->spidev, &m);
8238addc 182
9e272677
UKK		 183 /* error in message.status implies error return from spi_sync */
184 BUG_ON(!ret && m.status);
8238addc 185
9e272677
UKK		 186 if (ret)
187 return ret;
8238addc 188
9e272677 189 *val &= 0xffffff;
8238addc 190
9e272677 191 dev_vdbg(&mc13783->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
8238addc 192
9e272677 193 return 0;
8238addc 194}
9e272677 195EXPORT_SYMBOL(mc13783_reg_read);
8238addc 196
9e272677 197int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val)
8238addc 198{
9e272677
UKK		 199 u32 buf;
200 struct spi_transfer t;
201 struct spi_message m;
202 int ret;
203
204 BUG_ON(!mutex_is_locked(&mc13783->lock));
8238addc 205
9e272677
UKK		 206 dev_vdbg(&mc13783->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
207
208 if (offset > MC13783_NUMREGS || val > 0xffffff)
8238addc
SH		 209 return -EINVAL;
210
9e272677
UKK		 211 buf = 1 << 31 | offset << MC13783_REGOFFSET_SHIFT | val;
212
213 memset(&t, 0, sizeof(t));
8238addc 214
9e272677
UKK		 215 t.tx_buf = &buf;
216 t.rx_buf = &buf;
217 t.len = sizeof(u32);
218
219 spi_message_init(&m);
220 spi_message_add_tail(&t, &m);
221
222 ret = spi_sync(mc13783->spidev, &m);
223
224 BUG_ON(!ret && m.status);
225
226 if (ret)
227 return ret;
228
229 return 0;
8238addc 230}
9e272677 231EXPORT_SYMBOL(mc13783_reg_write);
8238addc 232
9e272677
UKK		 233int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
234 u32 mask, u32 val)
8238addc
SH		 235{
236 int ret;
9e272677 237 u32 valread;
8238addc 238
9e272677 239 BUG_ON(val & ~mask);
8238addc 240
9e272677
UKK		 241 ret = mc13783_reg_read(mc13783, offset, &valread);
242 if (ret)
243 return ret;
244
245 valread = (valread & ~mask) | val;
246
247 return mc13783_reg_write(mc13783, offset, valread);
8238addc 248}
9e272677 249EXPORT_SYMBOL(mc13783_reg_rmw);
8238addc 250
3b16bb53
UKK		 251int mc13783_get_flags(struct mc13783 *mc13783)
252{
253 return mc13783->flags;
254}
255EXPORT_SYMBOL(mc13783_get_flags);
256
57205026 257int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
8238addc
SH		 258{
259 int ret;
9e272677
UKK		 260 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
261 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
262 u32 mask;
8238addc 263
9e272677
UKK		 264 if (irq < 0 || irq >= MC13783_NUM_IRQ)
265 return -EINVAL;
8238addc 266
9e272677
UKK		 267 ret = mc13783_reg_read(mc13783, offmask, &mask);
268 if (ret)
269 return ret;
270
271 if (mask & irqbit)
272 /* already masked */
273 return 0;
274
275 return mc13783_reg_write(mc13783, offmask, mask | irqbit);
8238addc 276}
57205026 277EXPORT_SYMBOL(mc13783_irq_mask);
8238addc 278
57205026 279int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
8238addc 280{
8238addc 281 int ret;
9e272677
UKK		 282 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
283 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
284 u32 mask;
8238addc 285
9e272677
UKK		 286 if (irq < 0 || irq >= MC13783_NUM_IRQ)
287 return -EINVAL;
8238addc 288
9e272677
UKK		 289 ret = mc13783_reg_read(mc13783, offmask, &mask);
290 if (ret)
291 return ret;
8238addc 292
9e272677
UKK		 293 if (!(mask & irqbit))
294 /* already unmasked */
295 return 0;
8238addc 296
9e272677 297 return mc13783_reg_write(mc13783, offmask, mask & ~irqbit);
8238addc 298}
57205026
UKK		 299EXPORT_SYMBOL(mc13783_irq_unmask);
300
86c34008
UKK		 301int mc13783_irq_status(struct mc13783 *mc13783, int irq,
302 int *enabled, int *pending)
303{
304 int ret;
305 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
306 unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
307 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
308
309 if (irq < 0 || irq >= MC13783_NUM_IRQ)
310 return -EINVAL;
311
312 if (enabled) {
313 u32 mask;
314
315 ret = mc13783_reg_read(mc13783, offmask, &mask);
316 if (ret)
317 return ret;
318
319 *enabled = mask & irqbit;
320 }
321
322 if (pending) {
323 u32 stat;
324
325 ret = mc13783_reg_read(mc13783, offstat, &stat);
326 if (ret)
327 return ret;
328
329 *pending = stat & irqbit;
330 }
331
332 return 0;
333}
334EXPORT_SYMBOL(mc13783_irq_status);
335
57205026
UKK		 336int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
337{
338 unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
339 unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
340
341 BUG_ON(irq < 0 || irq >= MC13783_NUM_IRQ);
342
343 return mc13783_reg_write(mc13783, offstat, val);
344}
345EXPORT_SYMBOL(mc13783_irq_ack);
8238addc 346
9e272677
UKK		 347int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
348 irq_handler_t handler, const char *name, void *dev)
8238addc 349{
9e272677
UKK		 350 BUG_ON(!mutex_is_locked(&mc13783->lock));
351 BUG_ON(!handler);
352
353 if (irq < 0 || irq >= MC13783_NUM_IRQ)
8238addc
SH		 354 return -EINVAL;
355
9e272677 356 if (mc13783->irqhandler[irq])
8238addc
SH		 357 return -EBUSY;
358
9e272677
UKK		 359 mc13783->irqhandler[irq] = handler;
360 mc13783->irqdata[irq] = dev;
8238addc
SH		 361
362 return 0;
363}
9e272677 364EXPORT_SYMBOL(mc13783_irq_request_nounmask);
8238addc 365
9e272677
UKK		 366int mc13783_irq_request(struct mc13783 *mc13783, int irq,
367 irq_handler_t handler, const char *name, void *dev)
8238addc 368{
9e272677
UKK		 369 int ret;
370
371 ret = mc13783_irq_request_nounmask(mc13783, irq, handler, name, dev);
372 if (ret)
373 return ret;
374
57205026 375 ret = mc13783_irq_unmask(mc13783, irq);
9e272677
UKK		 376 if (ret) {
377 mc13783->irqhandler[irq] = NULL;
378 mc13783->irqdata[irq] = NULL;
379 return ret;
380 }
381
382 return 0;
383}
384EXPORT_SYMBOL(mc13783_irq_request);
385
386int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
387{
388 int ret;
389 BUG_ON(!mutex_is_locked(&mc13783->lock));
390
391 if (irq < 0 || irq >= MC13783_NUM_IRQ || !mc13783->irqhandler[irq] ||
392 mc13783->irqdata[irq] != dev)
8238addc
SH		 393 return -EINVAL;
394
57205026 395 ret = mc13783_irq_mask(mc13783, irq);
9e272677
UKK		 396 if (ret)
397 return ret;
398
399 mc13783->irqhandler[irq] = NULL;
400 mc13783->irqdata[irq] = NULL;
8238addc
SH		 401
402 return 0;
403}
9e272677 404EXPORT_SYMBOL(mc13783_irq_free);
8238addc 405
9e272677 406static inline irqreturn_t mc13783_irqhandler(struct mc13783 *mc13783, int irq)
8238addc 407{
9e272677 408 return mc13783->irqhandler[irq](irq, mc13783->irqdata[irq]);
8238addc
SH		 409}
410
9e272677
UKK		 411/*
412 * returns: number of handled irqs or negative error
413 * locking: holds mc13783->lock
414 */
415static int mc13783_irq_handle(struct mc13783 *mc13783,
416 unsigned int offstat, unsigned int offmask, int baseirq)
8238addc 417{
9e272677
UKK		 418 u32 stat, mask;
419 int ret = mc13783_reg_read(mc13783, offstat, &stat);
420 int num_handled = 0;
421
422 if (ret)
423 return ret;
424
425 ret = mc13783_reg_read(mc13783, offmask, &mask);
426 if (ret)
427 return ret;
428
429 while (stat & ~mask) {
430 int irq = __ffs(stat & ~mask);
431
432 stat &= ~(1 << irq);
433
434 if (likely(mc13783->irqhandler[baseirq + irq])) {
435 irqreturn_t handled;
8238addc 436
9e272677
UKK		 437 handled = mc13783_irqhandler(mc13783, baseirq + irq);
438 if (handled == IRQ_HANDLED)
439 num_handled++;
440 } else {
441 dev_err(&mc13783->spidev->dev,
442 "BUG: irq %u but no handler\n",
443 baseirq + irq);
8238addc 444
9e272677
UKK		 445 mask |= 1 << irq;
446
447 ret = mc13783_reg_write(mc13783, offmask, mask);
448 }
449 }
450
451 return num_handled;
8238addc
SH		 452}
453
9e272677
UKK		 454static irqreturn_t mc13783_irq_thread(int irq, void *data)
455{
456 struct mc13783 *mc13783 = data;
457 irqreturn_t ret;
458 int handled = 0;
459
460 mc13783_lock(mc13783);
461
462 ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT0,
463 MC13783_IRQMASK0, MC13783_IRQ_ADCDONE);
464 if (ret > 0)
465 handled = 1;
466
467 ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT1,
468 MC13783_IRQMASK1, MC13783_IRQ_1HZ);
469 if (ret > 0)
470 handled = 1;
471
472 mc13783_unlock(mc13783);
473
474 return IRQ_RETVAL(handled);
475}
476
477#define MC13783_ADC1_CHAN0_SHIFT 5
478#define MC13783_ADC1_CHAN1_SHIFT 8
479
480struct mc13783_adcdone_data {
481 struct mc13783 *mc13783;
482 struct completion done;
483};
484
485static irqreturn_t mc13783_handler_adcdone(int irq, void *data)
486{
487 struct mc13783_adcdone_data *adcdone_data = data;
488
57205026 489 mc13783_irq_ack(adcdone_data->mc13783, irq);
9e272677
UKK		 490
491 complete_all(&adcdone_data->done);
492
493 return IRQ_HANDLED;
494}
495
496#define MC13783_ADC_WORKING (1 << 16)
497
8238addc
SH		 498int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
499 unsigned int channel, unsigned int *sample)
500{
9e272677
UKK		 501 u32 adc0, adc1, old_adc0;
502 int i, ret;
503 struct mc13783_adcdone_data adcdone_data = {
504 .mc13783 = mc13783,
505 };
506 init_completion(&adcdone_data.done);
507
508 dev_dbg(&mc13783->spidev->dev, "%s\n", __func__);
509
510 mc13783_lock(mc13783);
511
512 if (mc13783->flags & MC13783_ADC_WORKING) {
513 ret = -EBUSY;
514 goto out;
515 }
516
517 mc13783->flags |= MC13783_ADC_WORKING;
8238addc 518
9e272677 519 mc13783_reg_read(mc13783, MC13783_ADC0, &old_adc0);
8238addc 520
9e272677
UKK		 521 adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
522 adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN | MC13783_ADC1_ASC;
8238addc 523
8238addc 524 if (channel > 7)
9e272677 525 adc1 |= MC13783_ADC1_ADSEL;
8238addc
SH		 526
527 switch (mode) {
528 case MC13783_ADC_MODE_TS:
be26d664
UKK		 529 adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_TSMOD0 |
530 MC13783_ADC0_TSMOD1;
9e272677 531 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
8238addc 532 break;
9e272677 533
8238addc 534 case MC13783_ADC_MODE_SINGLE_CHAN:
9e272677
UKK		 535 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
536 adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
537 adc1 |= MC13783_ADC1_RAND;
8238addc 538 break;
9e272677 539
8238addc 540 case MC13783_ADC_MODE_MULT_CHAN:
9e272677
UKK		 541 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
542 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
8238addc 543 break;
9e272677 544
8238addc 545 default:
9e272677 546 mc13783_unlock(mc13783);
8238addc
SH		 547 return -EINVAL;
548 }
549
9e272677
UKK		 550 dev_dbg(&mc13783->spidev->dev, "%s: request irq\n", __func__);
551 mc13783_irq_request(mc13783, MC13783_IRQ_ADCDONE,
552 mc13783_handler_adcdone, __func__, &adcdone_data);
57205026 553 mc13783_irq_ack(mc13783, MC13783_IRQ_ADCDONE);
8238addc 554
9e272677
UKK		 555 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, adc0);
556 mc13783_reg_write(mc13783, MC13783_REG_ADC_1, adc1);
8238addc 557
9e272677 558 mc13783_unlock(mc13783);
8238addc 559
9e272677 560 ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
8238addc 561
9e272677
UKK		 562 if (!ret)
563 ret = -ETIMEDOUT;
8238addc 564
9e272677
UKK		 565 mc13783_lock(mc13783);
566
567 mc13783_irq_free(mc13783, MC13783_IRQ_ADCDONE, &adcdone_data);
568
569 if (ret > 0)
570 for (i = 0; i < 4; ++i) {
571 ret = mc13783_reg_read(mc13783,
572 MC13783_REG_ADC_2, &sample[i]);
573 if (ret)
574 break;
575 }
576
577 if (mode == MC13783_ADC_MODE_TS)
578 /* restore TSMOD */
579 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, old_adc0);
580
581 mc13783->flags &= ~MC13783_ADC_WORKING;
582out:
583 mc13783_unlock(mc13783);
584
585 return ret;
8238addc
SH		 586}
587EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
588
9e272677
UKK		 589static int mc13783_add_subdevice_pdata(struct mc13783 *mc13783,
590 const char *name, void *pdata, size_t pdata_size)
8238addc 591{
9e272677
UKK		 592 struct mfd_cell cell = {
593 .name = name,
594 .platform_data = pdata,
595 .data_size = pdata_size,
596 };
597
598 return mfd_add_devices(&mc13783->spidev->dev, -1, &cell, 1, NULL, 0);
599}
600
601static int mc13783_add_subdevice(struct mc13783 *mc13783, const char *name)
602{
603 return mc13783_add_subdevice_pdata(mc13783, name, NULL, 0);
8238addc 604}
8238addc
SH		 605
606static int mc13783_check_revision(struct mc13783 *mc13783)
607{
608 u32 rev_id, rev1, rev2, finid, icid;
609
9e272677 610 mc13783_reg_read(mc13783, MC13783_REG_REVISION, &rev_id);
8238addc
SH		 611
612 rev1 = (rev_id & 0x018) >> 3;
613 rev2 = (rev_id & 0x007);
614 icid = (rev_id & 0x01C0) >> 6;
615 finid = (rev_id & 0x01E00) >> 9;
616
617 /* Ver 0.2 is actually 3.2a. Report as 3.2 */
618 if ((rev1 == 0) && (rev2 == 2))
619 rev1 = 3;
620
621 if (rev1 == 0 || icid != 2) {
9e272677 622 dev_err(&mc13783->spidev->dev, "No MC13783 detected.\n");
8238addc
SH		 623 return -ENODEV;
624 }
625
9e272677
UKK		 626 dev_info(&mc13783->spidev->dev,
627 "MC13783 Rev %d.%d FinVer %x detected\n",
628 rev1, rev2, finid);
8238addc
SH		 629
630 return 0;
631}
632
9e272677 633static int mc13783_probe(struct spi_device *spi)
8238addc
SH		 634{
635 struct mc13783 *mc13783;
9e272677 636 struct mc13783_platform_data *pdata = dev_get_platdata(&spi->dev);
8238addc
SH		 637 int ret;
638
9e272677 639 mc13783 = kzalloc(sizeof(*mc13783), GFP_KERNEL);
8238addc
SH		 640 if (!mc13783)
641 return -ENOMEM;
642
643 dev_set_drvdata(&spi->dev, mc13783);
644 spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
645 spi->bits_per_word = 32;
646 spi_setup(spi);
647
9e272677
UKK		 648 mc13783->spidev = spi;
649
650 mutex_init(&mc13783->lock);
651 mc13783_lock(mc13783);
652
653 ret = mc13783_check_revision(mc13783);
654 if (ret)
655 goto err_revision;
656
657 /* mask all irqs */
658 ret = mc13783_reg_write(mc13783, MC13783_IRQMASK0, 0x00ffffff);
659 if (ret)
660 goto err_mask;
8238addc 661
9e272677
UKK		 662 ret = mc13783_reg_write(mc13783, MC13783_IRQMASK1, 0x00ffffff);
663 if (ret)
664 goto err_mask;
665
666 ret = request_threaded_irq(spi->irq, NULL, mc13783_irq_thread,
667 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13783", mc13783);
668
669 if (ret) {
670err_mask:
671err_revision:
672 mutex_unlock(&mc13783->lock);
673 dev_set_drvdata(&spi->dev, NULL);
674 kfree(mc13783);
675 return ret;
676 }
8238addc 677
9e272677 678 /* This should go away (BEGIN) */
8238addc
SH		 679 if (pdata) {
680 mc13783->flags = pdata->flags;
681 mc13783->regulators = pdata->regulators;
682 mc13783->num_regulators = pdata->num_regulators;
683 }
9e272677 684 /* This should go away (END) */
8238addc 685
1e02b2c3
AP		 686 mc13783_unlock(mc13783);
687
9e272677
UKK		 688 if (pdata->flags & MC13783_USE_ADC)
689 mc13783_add_subdevice(mc13783, "mc13783-adc");
690
691 if (pdata->flags & MC13783_USE_CODEC)
692 mc13783_add_subdevice(mc13783, "mc13783-codec");
693
694 if (pdata->flags & MC13783_USE_REGULATOR) {
695 struct mc13783_regulator_platform_data regulator_pdata = {
696 .num_regulators = pdata->num_regulators,
697 .regulators = pdata->regulators,
698 };
699
700 mc13783_add_subdevice_pdata(mc13783, "mc13783-regulator",
701 &regulator_pdata, sizeof(regulator_pdata));
8238addc
SH		 702 }
703
9e272677
UKK		 704 if (pdata->flags & MC13783_USE_RTC)
705 mc13783_add_subdevice(mc13783, "mc13783-rtc");
8238addc 706
9e272677
UKK		 707 if (pdata->flags & MC13783_USE_TOUCHSCREEN)
708 mc13783_add_subdevice(mc13783, "mc13783-ts");
8238addc 709
7fdcef8a
PR		 710 if (pdata->flags & MC13783_USE_LED)
711 mc13783_add_subdevice_pdata(mc13783, "mc13783-led",
712 pdata->leds, sizeof(*pdata->leds));
713
8238addc 714 return 0;
8238addc
SH		 715}
716
717static int __devexit mc13783_remove(struct spi_device *spi)
718{
9e272677 719 struct mc13783 *mc13783 = dev_get_drvdata(&spi->dev);
8238addc 720
9e272677 721 free_irq(mc13783->spidev->irq, mc13783);
8238addc
SH		 722
723 mfd_remove_devices(&spi->dev);
724
725 return 0;
726}
727
9e272677 728static struct spi_driver mc13783_driver = {
8238addc 729 .driver = {
9e272677
UKK		 730 .name = "mc13783",
731 .bus = &spi_bus_type,
732 .owner = THIS_MODULE,
8238addc
SH		 733 },
734 .probe = mc13783_probe,
735 .remove = __devexit_p(mc13783_remove),
736};
737
9e272677 738static int __init mc13783_init(void)
8238addc 739{
9e272677 740 return spi_register_driver(&mc13783_driver);
8238addc 741}
9e272677 742subsys_initcall(mc13783_init);
8238addc 743
9e272677 744static void __exit mc13783_exit(void)
8238addc 745{
9e272677 746 spi_unregister_driver(&mc13783_driver);
8238addc 747}
9e272677 748module_exit(mc13783_exit);
8238addc 749
9e272677
UKK		 750MODULE_DESCRIPTION("Core driver for Freescale MC13783 PMIC");
751MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
752MODULE_LICENSE("GPL v2");
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