[net-next-2.6.git] / drivers / mfd / asic3.c

/*
 * driver/mfd/asic3.c
 *
 * Compaq ASIC3 support.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Copyright 2001 Compaq Computer Corporation.
 * Copyright 2004-2005 Phil Blundell
 * Copyright 2007-2008 OpenedHand Ltd.
 *
 * Authors: Phil Blundell <pb@handhelds.org>,
 *	    Samuel Ortiz <sameo@openedhand.com>
 *
 */

#include <linux/kernel.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>

#include <linux/mfd/asic3.h>

struct asic3 {
	void __iomem *mapping;
	unsigned int bus_shift;
	unsigned int irq_nr;
	unsigned int irq_base;
	spinlock_t lock;
	u16 irq_bothedge[4];
	struct gpio_chip gpio;
	struct device *dev;
};

static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);

static inline void asic3_write_register(struct asic3 *asic,
				 unsigned int reg, u32 value)
{
	iowrite16(value, asic->mapping +
		  (reg >> asic->bus_shift));
}

static inline u32 asic3_read_register(struct asic3 *asic,
			       unsigned int reg)
{
	return ioread16(asic->mapping +
			(reg >> asic->bus_shift));
}

void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
{
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&asic->lock, flags);
	val = asic3_read_register(asic, reg);
	if (set)
		val |= bits;
	else
		val &= ~bits;
	asic3_write_register(asic, reg, val);
	spin_unlock_irqrestore(&asic->lock, flags);
}

/* IRQs */
#define MAX_ASIC_ISR_LOOPS    20
#define ASIC3_GPIO_BASE_INCR \
	(ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)

static void asic3_irq_flip_edge(struct asic3 *asic,
				u32 base, int bit)
{
	u16 edge;
	unsigned long flags;

	spin_lock_irqsave(&asic->lock, flags);
	edge = asic3_read_register(asic,
				   base + ASIC3_GPIO_EDGE_TRIGGER);
	edge ^= bit;
	asic3_write_register(asic,
			     base + ASIC3_GPIO_EDGE_TRIGGER, edge);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
{
	int iter, i;
	unsigned long flags;
	struct asic3 *asic;

	desc->chip->ack(irq);

	asic = desc->handler_data;

	for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
		u32 status;
		int bank;

		spin_lock_irqsave(&asic->lock, flags);
		status = asic3_read_register(asic,
					     ASIC3_OFFSET(INTR, P_INT_STAT));
		spin_unlock_irqrestore(&asic->lock, flags);

		/* Check all ten register bits */
		if ((status & 0x3ff) == 0)
			break;

		/* Handle GPIO IRQs */
		for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
			if (status & (1 << bank)) {
				unsigned long base, istat;

				base = ASIC3_GPIO_A_BASE
				       + bank * ASIC3_GPIO_BASE_INCR;

				spin_lock_irqsave(&asic->lock, flags);
				istat = asic3_read_register(asic,
							    base +
							    ASIC3_GPIO_INT_STATUS);
				/* Clearing IntStatus */
				asic3_write_register(asic,
						     base +
						     ASIC3_GPIO_INT_STATUS, 0);
				spin_unlock_irqrestore(&asic->lock, flags);

				for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
					int bit = (1 << i);
					unsigned int irqnr;

					if (!(istat & bit))
						continue;

					irqnr = asic->irq_base +
						(ASIC3_GPIOS_PER_BANK * bank)
						+ i;
					desc = irq_to_desc(irqnr);
					desc->handle_irq(irqnr, desc);
					if (asic->irq_bothedge[bank] & bit)
						asic3_irq_flip_edge(asic, base,
								    bit);
				}
			}
		}

		/* Handle remaining IRQs in the status register */
		for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
			/* They start at bit 4 and go up */
			if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
				desc = irq_to_desc(asic->irq_base + i);
				desc->handle_irq(asic->irq_base + i,
						 desc);
			}
		}
	}

	if (iter >= MAX_ASIC_ISR_LOOPS)
		dev_err(asic->dev, "interrupt processing overrun\n");
}

static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
{
	int n;

	n = (irq - asic->irq_base) >> 4;

	return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
}

static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
{
	return (irq - asic->irq_base) & 0xf;
}

static void asic3_mask_gpio_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	u32 val, bank, index;
	unsigned long flags;

	bank = asic3_irq_to_bank(asic, irq);
	index = asic3_irq_to_index(asic, irq);

	spin_lock_irqsave(&asic->lock, flags);
	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
	val |= 1 << index;
	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_mask_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	int regval;
	unsigned long flags;

	spin_lock_irqsave(&asic->lock, flags);
	regval = asic3_read_register(asic,
				     ASIC3_INTR_BASE +
				     ASIC3_INTR_INT_MASK);

	regval &= ~(ASIC3_INTMASK_MASK0 <<
		    (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));

	asic3_write_register(asic,
			     ASIC3_INTR_BASE +
			     ASIC3_INTR_INT_MASK,
			     regval);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_unmask_gpio_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	u32 val, bank, index;
	unsigned long flags;

	bank = asic3_irq_to_bank(asic, irq);
	index = asic3_irq_to_index(asic, irq);

	spin_lock_irqsave(&asic->lock, flags);
	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
	val &= ~(1 << index);
	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static void asic3_unmask_irq(unsigned int irq)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	int regval;
	unsigned long flags;

	spin_lock_irqsave(&asic->lock, flags);
	regval = asic3_read_register(asic,
				     ASIC3_INTR_BASE +
				     ASIC3_INTR_INT_MASK);

	regval |= (ASIC3_INTMASK_MASK0 <<
		   (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));

	asic3_write_register(asic,
			     ASIC3_INTR_BASE +
			     ASIC3_INTR_INT_MASK,
			     regval);
	spin_unlock_irqrestore(&asic->lock, flags);
}

static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
{
	struct asic3 *asic = get_irq_chip_data(irq);
	u32 bank, index;
	u16 trigger, level, edge, bit;
	unsigned long flags;

	bank = asic3_irq_to_bank(asic, irq);
	index = asic3_irq_to_index(asic, irq);
	bit = 1<<index;

	spin_lock_irqsave(&asic->lock, flags);
	level = asic3_read_register(asic,
				    bank + ASIC3_GPIO_LEVEL_TRIGGER);
	edge = asic3_read_register(asic,
				   bank + ASIC3_GPIO_EDGE_TRIGGER);
	trigger = asic3_read_register(asic,
				      bank + ASIC3_GPIO_TRIGGER_TYPE);
	asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;

	if (type == IRQ_TYPE_EDGE_RISING) {
		trigger |= bit;
		edge |= bit;
	} else if (type == IRQ_TYPE_EDGE_FALLING) {
		trigger |= bit;
		edge &= ~bit;
	} else if (type == IRQ_TYPE_EDGE_BOTH) {
		trigger |= bit;
		if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
			edge &= ~bit;
		else
			edge |= bit;
		asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
	} else if (type == IRQ_TYPE_LEVEL_LOW) {
		trigger &= ~bit;
		level &= ~bit;
	} else if (type == IRQ_TYPE_LEVEL_HIGH) {
		trigger &= ~bit;
		level |= bit;
	} else {
		/*
		 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
		 * be careful to not unmask them if mask was also called.
		 * Probably need internal state for mask.
		 */
		dev_notice(asic->dev, "irq type not changed\n");
	}
	asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
			     level);
	asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
			     edge);
	asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
			     trigger);
	spin_unlock_irqrestore(&asic->lock, flags);
	return 0;
}

static struct irq_chip asic3_gpio_irq_chip = {
	.name		= "ASIC3-GPIO",
	.ack		= asic3_mask_gpio_irq,
	.mask		= asic3_mask_gpio_irq,
	.unmask		= asic3_unmask_gpio_irq,
	.set_type	= asic3_gpio_irq_type,
};

static struct irq_chip asic3_irq_chip = {
	.name		= "ASIC3",
	.ack		= asic3_mask_irq,
	.mask		= asic3_mask_irq,
	.unmask		= asic3_unmask_irq,
};

static int __init asic3_irq_probe(struct platform_device *pdev)
{
	struct asic3 *asic = platform_get_drvdata(pdev);
	unsigned long clksel = 0;
	unsigned int irq, irq_base;
	int ret;

	ret = platform_get_irq(pdev, 0);
	if (ret < 0)
		return ret;
	asic->irq_nr = ret;

	/* turn on clock to IRQ controller */
	clksel |= CLOCK_SEL_CX;
	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
			     clksel);

	irq_base = asic->irq_base;

	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
		if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
			set_irq_chip(irq, &asic3_gpio_irq_chip);
		else
			set_irq_chip(irq, &asic3_irq_chip);

		set_irq_chip_data(irq, asic);
		set_irq_handler(irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
			     ASIC3_INTMASK_GINTMASK);

	set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
	set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
	set_irq_data(asic->irq_nr, asic);

	return 0;
}

static void asic3_irq_remove(struct platform_device *pdev)
{
	struct asic3 *asic = platform_get_drvdata(pdev);
	unsigned int irq, irq_base;

	irq_base = asic->irq_base;

	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
		set_irq_flags(irq, 0);
		set_irq_handler(irq, NULL);
		set_irq_chip(irq, NULL);
		set_irq_chip_data(irq, NULL);
	}
	set_irq_chained_handler(asic->irq_nr, NULL);
}

/* GPIOs */
static int asic3_gpio_direction(struct gpio_chip *chip,
				unsigned offset, int out)
{
	u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
	unsigned int gpio_base;
	unsigned long flags;
	struct asic3 *asic;

	asic = container_of(chip, struct asic3, gpio);
	gpio_base = ASIC3_GPIO_TO_BASE(offset);

	if (gpio_base > ASIC3_GPIO_D_BASE) {
		dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
			gpio_base, offset);
		return -EINVAL;
	}

	spin_lock_irqsave(&asic->lock, flags);

	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);

	/* Input is 0, Output is 1 */
	if (out)
		out_reg |= mask;
	else
		out_reg &= ~mask;

	asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);

	spin_unlock_irqrestore(&asic->lock, flags);

	return 0;

}

static int asic3_gpio_direction_input(struct gpio_chip *chip,
				      unsigned offset)
{
	return asic3_gpio_direction(chip, offset, 0);
}

static int asic3_gpio_direction_output(struct gpio_chip *chip,
				       unsigned offset, int value)
{
	return asic3_gpio_direction(chip, offset, 1);
}

static int asic3_gpio_get(struct gpio_chip *chip,
			  unsigned offset)
{
	unsigned int gpio_base;
	u32 mask = ASIC3_GPIO_TO_MASK(offset);
	struct asic3 *asic;

	asic = container_of(chip, struct asic3, gpio);
	gpio_base = ASIC3_GPIO_TO_BASE(offset);

	if (gpio_base > ASIC3_GPIO_D_BASE) {
		dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
			gpio_base, offset);
		return -EINVAL;
	}

	return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
}

static void asic3_gpio_set(struct gpio_chip *chip,
			   unsigned offset, int value)
{
	u32 mask, out_reg;
	unsigned int gpio_base;
	unsigned long flags;
	struct asic3 *asic;

	asic = container_of(chip, struct asic3, gpio);
	gpio_base = ASIC3_GPIO_TO_BASE(offset);

	if (gpio_base > ASIC3_GPIO_D_BASE) {
		dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
			gpio_base, offset);
		return;
	}

	mask = ASIC3_GPIO_TO_MASK(offset);

	spin_lock_irqsave(&asic->lock, flags);

	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);

	if (value)
		out_reg |= mask;
	else
		out_reg &= ~mask;

	asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);

	spin_unlock_irqrestore(&asic->lock, flags);

	return;
}

static __init int asic3_gpio_probe(struct platform_device *pdev,
				   u16 *gpio_config, int num)
{
	struct asic3 *asic = platform_get_drvdata(pdev);
	u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
	u16 out_reg[ASIC3_NUM_GPIO_BANKS];
	u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
	int i;

	memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
	memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
	memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));

	/* Enable all GPIOs */
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
	asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);

	for (i = 0; i < num; i++) {
		u8 alt, pin, dir, init, bank_num, bit_num;
		u16 config = gpio_config[i];

		pin = ASIC3_CONFIG_GPIO_PIN(config);
		alt = ASIC3_CONFIG_GPIO_ALT(config);
		dir = ASIC3_CONFIG_GPIO_DIR(config);
		init = ASIC3_CONFIG_GPIO_INIT(config);

		bank_num = ASIC3_GPIO_TO_BANK(pin);
		bit_num = ASIC3_GPIO_TO_BIT(pin);

		alt_reg[bank_num] |= (alt << bit_num);
		out_reg[bank_num] |= (init << bit_num);
		dir_reg[bank_num] |= (dir << bit_num);
	}

	for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
		asic3_write_register(asic,
				     ASIC3_BANK_TO_BASE(i) +
				     ASIC3_GPIO_DIRECTION,
				     dir_reg[i]);
		asic3_write_register(asic,
				     ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
				     out_reg[i]);
		asic3_write_register(asic,
				     ASIC3_BANK_TO_BASE(i) +
				     ASIC3_GPIO_ALT_FUNCTION,
				     alt_reg[i]);
	}

	return gpiochip_add(&asic->gpio);
}

static int asic3_gpio_remove(struct platform_device *pdev)
{
	struct asic3 *asic = platform_get_drvdata(pdev);

	return gpiochip_remove(&asic->gpio);
}


/* Core */
static int __init asic3_probe(struct platform_device *pdev)
{
	struct asic3_platform_data *pdata = pdev->dev.platform_data;
	struct asic3 *asic;
	struct resource *mem;
	unsigned long clksel;
	int map_size;
	int ret = 0;

	asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
	if (asic == NULL) {
		printk(KERN_ERR "kzalloc failed\n");
		return -ENOMEM;
	}

	spin_lock_init(&asic->lock);
	platform_set_drvdata(pdev, asic);
	asic->dev = &pdev->dev;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		ret = -ENOMEM;
		dev_err(asic->dev, "no MEM resource\n");
		goto out_free;
	}

	map_size = mem->end - mem->start + 1;
	asic->mapping = ioremap(mem->start, map_size);
	if (!asic->mapping) {
		ret = -ENOMEM;
		dev_err(asic->dev, "Couldn't ioremap\n");
		goto out_free;
	}

	asic->irq_base = pdata->irq_base;

	/* calculate bus shift from mem resource */
	asic->bus_shift = 2 - (map_size >> 12);

	clksel = 0;
	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);

	ret = asic3_irq_probe(pdev);
	if (ret < 0) {
		dev_err(asic->dev, "Couldn't probe IRQs\n");
		goto out_unmap;
	}

	asic->gpio.base = pdata->gpio_base;
	asic->gpio.ngpio = ASIC3_NUM_GPIOS;
	asic->gpio.get = asic3_gpio_get;
	asic->gpio.set = asic3_gpio_set;
	asic->gpio.direction_input = asic3_gpio_direction_input;
	asic->gpio.direction_output = asic3_gpio_direction_output;

	ret = asic3_gpio_probe(pdev,
			       pdata->gpio_config,
			       pdata->gpio_config_num);
	if (ret < 0) {
		dev_err(asic->dev, "GPIO probe failed\n");
		goto out_irq;
	}

	dev_info(asic->dev, "ASIC3 Core driver\n");

	return 0;

 out_irq:
	asic3_irq_remove(pdev);

 out_unmap:
	iounmap(asic->mapping);

 out_free:
	kfree(asic);

	return ret;
}

static int asic3_remove(struct platform_device *pdev)
{
	int ret;
	struct asic3 *asic = platform_get_drvdata(pdev);

	ret = asic3_gpio_remove(pdev);
	if (ret < 0)
		return ret;
	asic3_irq_remove(pdev);

	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);

	iounmap(asic->mapping);

	kfree(asic);

	return 0;
}

static void asic3_shutdown(struct platform_device *pdev)
{
}

static struct platform_driver asic3_device_driver = {
	.driver		= {
		.name	= "asic3",
	},
	.remove		= __devexit_p(asic3_remove),
	.shutdown	= asic3_shutdown,
};

static int __init asic3_init(void)
{
	int retval = 0;
	retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
	return retval;
}

subsys_initcall(asic3_init);
Commit	Line	Data
fa9ff4b1 SO	1	/*
	2	* driver/mfd/asic3.c
	3	*
	4	* Compaq ASIC3 support.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Copyright 2001 Compaq Computer Corporation.
	11	* Copyright 2004-2005 Phil Blundell
6f2384c4	12	* Copyright 2007-2008 OpenedHand Ltd.
fa9ff4b1 SO	13	*
	14	* Authors: Phil Blundell <pb@handhelds.org>,
	15	* Samuel Ortiz <sameo@openedhand.com>
	16	*
	17	*/
	18
fa9ff4b1 SO	19	#include <linux/kernel.h>
fa9ff4b1 SO	20	#include <linux/irq.h>
6f2384c4	21	#include <linux/gpio.h>
fa9ff4b1 SO	22	#include <linux/io.h>
	23	#include <linux/spinlock.h>
	24	#include <linux/platform_device.h>
	25
	26	#include <linux/mfd/asic3.h>
	27
6f2384c4 SO	28	struct asic3 {
	29	void __iomem *mapping;
	30	unsigned int bus_shift;
	31	unsigned int irq_nr;
	32	unsigned int irq_base;
	33	spinlock_t lock;
	34	u16 irq_bothedge[4];
	35	struct gpio_chip gpio;
	36	struct device *dev;
	37	};
	38
	39	static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
	40
fa9ff4b1 SO	41	static inline void asic3_write_register(struct asic3 *asic,
	42	unsigned int reg, u32 value)
	43	{
b32661e0	44	iowrite16(value, asic->mapping +
fa9ff4b1 SO	45	(reg >> asic->bus_shift));
	46	}
	47
	48	static inline u32 asic3_read_register(struct asic3 *asic,
	49	unsigned int reg)
	50	{
b32661e0	51	return ioread16(asic->mapping +
fa9ff4b1 SO	52	(reg >> asic->bus_shift));
	53	}
	54
6483c1b5 PZ	55	void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
	56	{
	57	unsigned long flags;
	58	u32 val;
	59
	60	spin_lock_irqsave(&asic->lock, flags);
	61	val = asic3_read_register(asic, reg);
	62	if (set)
	63	val \|= bits;
	64	else
	65	val &= ~bits;
	66	asic3_write_register(asic, reg, val);
	67	spin_unlock_irqrestore(&asic->lock, flags);
	68	}
	69
fa9ff4b1 SO	70	/* IRQs */
fa9ff4b1 SO	71	#define MAX_ASIC_ISR_LOOPS 20
3b8139f8 SO	72	#define ASIC3_GPIO_BASE_INCR \
3b8139f8 SO	73	(ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
fa9ff4b1 SO	74
	75	static void asic3_irq_flip_edge(struct asic3 *asic,
	76	u32 base, int bit)
	77	{
	78	u16 edge;
	79	unsigned long flags;
	80
	81	spin_lock_irqsave(&asic->lock, flags);
	82	edge = asic3_read_register(asic,
3b8139f8	83	base + ASIC3_GPIO_EDGE_TRIGGER);
fa9ff4b1 SO	84	edge ^= bit;
fa9ff4b1 SO	85	asic3_write_register(asic,
3b8139f8	86	base + ASIC3_GPIO_EDGE_TRIGGER, edge);
fa9ff4b1 SO	87	spin_unlock_irqrestore(&asic->lock, flags);
	88	}
	89
	90	static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
	91	{
	92	int iter, i;
	93	unsigned long flags;
	94	struct asic3 *asic;
	95
	96	desc->chip->ack(irq);
	97
	98	asic = desc->handler_data;
	99
	100	for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
	101	u32 status;
	102	int bank;
	103
	104	spin_lock_irqsave(&asic->lock, flags);
	105	status = asic3_read_register(asic,
3b8139f8	106	ASIC3_OFFSET(INTR, P_INT_STAT));
fa9ff4b1 SO	107	spin_unlock_irqrestore(&asic->lock, flags);
	108
	109	/* Check all ten register bits */
	110	if ((status & 0x3ff) == 0)
	111	break;
	112
	113	/* Handle GPIO IRQs */
	114	for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
	115	if (status & (1 << bank)) {
	116	unsigned long base, istat;
	117
3b8139f8 SO	118	base = ASIC3_GPIO_A_BASE
3b8139f8 SO	119	+ bank * ASIC3_GPIO_BASE_INCR;
fa9ff4b1 SO	120
	121	spin_lock_irqsave(&asic->lock, flags);
	122	istat = asic3_read_register(asic,
	123	base +
3b8139f8	124	ASIC3_GPIO_INT_STATUS);
fa9ff4b1 SO	125	/* Clearing IntStatus */
	126	asic3_write_register(asic,
	127	base +
3b8139f8	128	ASIC3_GPIO_INT_STATUS, 0);
fa9ff4b1 SO	129	spin_unlock_irqrestore(&asic->lock, flags);
	130
	131	for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
	132	int bit = (1 << i);
	133	unsigned int irqnr;
	134
	135	if (!(istat & bit))
	136	continue;
	137
	138	irqnr = asic->irq_base +
	139	(ASIC3_GPIOS_PER_BANK * bank)
	140	+ i;
08678b08	141	desc = irq_to_desc(irqnr);
fa9ff4b1 SO	142	desc->handle_irq(irqnr, desc);
	143	if (asic->irq_bothedge[bank] & bit)
	144	asic3_irq_flip_edge(asic, base,
	145	bit);
	146	}
	147	}
	148	}
	149
	150	/* Handle remaining IRQs in the status register */
	151	for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
	152	/* They start at bit 4 and go up */
	153	if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
08678b08	154	desc = irq_to_desc(asic->irq_base + i);
fa9ff4b1 SO	155	desc->handle_irq(asic->irq_base + i,
	156	desc);
	157	}
	158	}
	159	}
	160
	161	if (iter >= MAX_ASIC_ISR_LOOPS)
24f4f2ee	162	dev_err(asic->dev, "interrupt processing overrun\n");
fa9ff4b1 SO	163	}
	164
	165	static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
	166	{
	167	int n;
	168
	169	n = (irq - asic->irq_base) >> 4;
	170
3b8139f8	171	return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
fa9ff4b1 SO	172	}
	173
	174	static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
	175	{
	176	return (irq - asic->irq_base) & 0xf;
	177	}
	178
	179	static void asic3_mask_gpio_irq(unsigned int irq)
	180	{
	181	struct asic3 *asic = get_irq_chip_data(irq);
	182	u32 val, bank, index;
	183	unsigned long flags;
	184
	185	bank = asic3_irq_to_bank(asic, irq);
	186	index = asic3_irq_to_index(asic, irq);
	187
	188	spin_lock_irqsave(&asic->lock, flags);
3b8139f8	189	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
fa9ff4b1	190	val \|= 1 << index;
3b8139f8	191	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
fa9ff4b1 SO	192	spin_unlock_irqrestore(&asic->lock, flags);
	193	}
	194
	195	static void asic3_mask_irq(unsigned int irq)
	196	{
	197	struct asic3 *asic = get_irq_chip_data(irq);
	198	int regval;
	199	unsigned long flags;
	200
	201	spin_lock_irqsave(&asic->lock, flags);
	202	regval = asic3_read_register(asic,
3b8139f8 SO	203	ASIC3_INTR_BASE +
3b8139f8 SO	204	ASIC3_INTR_INT_MASK);
fa9ff4b1 SO	205
	206	regval &= ~(ASIC3_INTMASK_MASK0 <<
	207	(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
	208
	209	asic3_write_register(asic,
3b8139f8 SO	210	ASIC3_INTR_BASE +
3b8139f8 SO	211	ASIC3_INTR_INT_MASK,
fa9ff4b1 SO	212	regval);
	213	spin_unlock_irqrestore(&asic->lock, flags);
	214	}
	215
	216	static void asic3_unmask_gpio_irq(unsigned int irq)
	217	{
	218	struct asic3 *asic = get_irq_chip_data(irq);
	219	u32 val, bank, index;
	220	unsigned long flags;
	221
	222	bank = asic3_irq_to_bank(asic, irq);
	223	index = asic3_irq_to_index(asic, irq);
	224
	225	spin_lock_irqsave(&asic->lock, flags);
3b8139f8	226	val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
fa9ff4b1	227	val &= ~(1 << index);
3b8139f8	228	asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
fa9ff4b1 SO	229	spin_unlock_irqrestore(&asic->lock, flags);
	230	}
	231
	232	static void asic3_unmask_irq(unsigned int irq)
	233	{
	234	struct asic3 *asic = get_irq_chip_data(irq);
	235	int regval;
	236	unsigned long flags;
	237
	238	spin_lock_irqsave(&asic->lock, flags);
	239	regval = asic3_read_register(asic,
3b8139f8 SO	240	ASIC3_INTR_BASE +
3b8139f8 SO	241	ASIC3_INTR_INT_MASK);
fa9ff4b1 SO	242
	243	regval \|= (ASIC3_INTMASK_MASK0 <<
	244	(irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
	245
	246	asic3_write_register(asic,
3b8139f8 SO	247	ASIC3_INTR_BASE +
3b8139f8 SO	248	ASIC3_INTR_INT_MASK,
fa9ff4b1 SO	249	regval);
	250	spin_unlock_irqrestore(&asic->lock, flags);
	251	}
	252
	253	static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
	254	{
	255	struct asic3 *asic = get_irq_chip_data(irq);
	256	u32 bank, index;
	257	u16 trigger, level, edge, bit;
	258	unsigned long flags;
	259
	260	bank = asic3_irq_to_bank(asic, irq);
	261	index = asic3_irq_to_index(asic, irq);
	262	bit = 1<<index;
	263
	264	spin_lock_irqsave(&asic->lock, flags);
	265	level = asic3_read_register(asic,
3b8139f8	266	bank + ASIC3_GPIO_LEVEL_TRIGGER);
fa9ff4b1	267	edge = asic3_read_register(asic,
3b8139f8	268	bank + ASIC3_GPIO_EDGE_TRIGGER);
fa9ff4b1	269	trigger = asic3_read_register(asic,
3b8139f8	270	bank + ASIC3_GPIO_TRIGGER_TYPE);
fa9ff4b1 SO	271	asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
fa9ff4b1 SO	272
6cab4860	273	if (type == IRQ_TYPE_EDGE_RISING) {
fa9ff4b1 SO	274	trigger \|= bit;
fa9ff4b1 SO	275	edge \|= bit;
6cab4860	276	} else if (type == IRQ_TYPE_EDGE_FALLING) {
fa9ff4b1 SO	277	trigger \|= bit;
fa9ff4b1 SO	278	edge &= ~bit;
6cab4860	279	} else if (type == IRQ_TYPE_EDGE_BOTH) {
fa9ff4b1	280	trigger \|= bit;
6f2384c4	281	if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
fa9ff4b1 SO	282	edge &= ~bit;
	283	else
	284	edge \|= bit;
	285	asic->irq_bothedge[(irq - asic->irq_base) >> 4] \|= bit;
6cab4860	286	} else if (type == IRQ_TYPE_LEVEL_LOW) {
fa9ff4b1 SO	287	trigger &= ~bit;
fa9ff4b1 SO	288	level &= ~bit;
6cab4860	289	} else if (type == IRQ_TYPE_LEVEL_HIGH) {
fa9ff4b1 SO	290	trigger &= ~bit;
	291	level \|= bit;
	292	} else {
	293	/*
6cab4860	294	* if type == IRQ_TYPE_NONE, we should mask interrupts, but
fa9ff4b1 SO	295	* be careful to not unmask them if mask was also called.
	296	* Probably need internal state for mask.
	297	*/
24f4f2ee	298	dev_notice(asic->dev, "irq type not changed\n");
fa9ff4b1	299	}
3b8139f8	300	asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
fa9ff4b1	301	level);
3b8139f8	302	asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
fa9ff4b1	303	edge);
3b8139f8	304	asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
fa9ff4b1 SO	305	trigger);
	306	spin_unlock_irqrestore(&asic->lock, flags);
	307	return 0;
	308	}
	309
	310	static struct irq_chip asic3_gpio_irq_chip = {
	311	.name = "ASIC3-GPIO",
	312	.ack = asic3_mask_gpio_irq,
	313	.mask = asic3_mask_gpio_irq,
	314	.unmask = asic3_unmask_gpio_irq,
	315	.set_type = asic3_gpio_irq_type,
	316	};
	317
	318	static struct irq_chip asic3_irq_chip = {
	319	.name = "ASIC3",
	320	.ack = asic3_mask_irq,
	321	.mask = asic3_mask_irq,
	322	.unmask = asic3_unmask_irq,
	323	};
	324
065032f6	325	static int __init asic3_irq_probe(struct platform_device *pdev)
fa9ff4b1 SO	326	{
	327	struct asic3 *asic = platform_get_drvdata(pdev);
	328	unsigned long clksel = 0;
	329	unsigned int irq, irq_base;
c491b2ff	330	int ret;
fa9ff4b1	331
c491b2ff RK	332	ret = platform_get_irq(pdev, 0);
	333	if (ret < 0)
	334	return ret;
	335	asic->irq_nr = ret;
fa9ff4b1 SO	336
	337	/* turn on clock to IRQ controller */
	338	clksel \|= CLOCK_SEL_CX;
	339	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
	340	clksel);
	341
	342	irq_base = asic->irq_base;
	343
	344	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
	345	if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
	346	set_irq_chip(irq, &asic3_gpio_irq_chip);
	347	else
	348	set_irq_chip(irq, &asic3_irq_chip);
	349
	350	set_irq_chip_data(irq, asic);
	351	set_irq_handler(irq, handle_level_irq);
	352	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	353	}
	354
3b8139f8	355	asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
fa9ff4b1 SO	356	ASIC3_INTMASK_GINTMASK);
	357
	358	set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
6cab4860	359	set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
fa9ff4b1 SO	360	set_irq_data(asic->irq_nr, asic);
	361
	362	return 0;
	363	}
	364
	365	static void asic3_irq_remove(struct platform_device *pdev)
	366	{
	367	struct asic3 *asic = platform_get_drvdata(pdev);
	368	unsigned int irq, irq_base;
	369
	370	irq_base = asic->irq_base;
	371
	372	for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
	373	set_irq_flags(irq, 0);
	374	set_irq_handler(irq, NULL);
	375	set_irq_chip(irq, NULL);
	376	set_irq_chip_data(irq, NULL);
	377	}
	378	set_irq_chained_handler(asic->irq_nr, NULL);
	379	}
	380
	381	/* GPIOs */
6f2384c4 SO	382	static int asic3_gpio_direction(struct gpio_chip *chip,
	383	unsigned offset, int out)
	384	{
	385	u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
	386	unsigned int gpio_base;
	387	unsigned long flags;
	388	struct asic3 *asic;
	389
	390	asic = container_of(chip, struct asic3, gpio);
	391	gpio_base = ASIC3_GPIO_TO_BASE(offset);
	392
3b8139f8	393	if (gpio_base > ASIC3_GPIO_D_BASE) {
24f4f2ee SO	394	dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
24f4f2ee SO	395	gpio_base, offset);
6f2384c4 SO	396	return -EINVAL;
	397	}
	398
	399	spin_lock_irqsave(&asic->lock, flags);
	400
3b8139f8	401	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
6f2384c4 SO	402
	403	/* Input is 0, Output is 1 */
	404	if (out)
	405	out_reg \|= mask;
	406	else
	407	out_reg &= ~mask;
	408
3b8139f8	409	asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
6f2384c4 SO	410
	411	spin_unlock_irqrestore(&asic->lock, flags);
	412
	413	return 0;
	414
	415	}
	416
	417	static int asic3_gpio_direction_input(struct gpio_chip *chip,
	418	unsigned offset)
	419	{
	420	return asic3_gpio_direction(chip, offset, 0);
	421	}
	422
	423	static int asic3_gpio_direction_output(struct gpio_chip *chip,
	424	unsigned offset, int value)
	425	{
	426	return asic3_gpio_direction(chip, offset, 1);
	427	}
	428
	429	static int asic3_gpio_get(struct gpio_chip *chip,
	430	unsigned offset)
	431	{
	432	unsigned int gpio_base;
	433	u32 mask = ASIC3_GPIO_TO_MASK(offset);
	434	struct asic3 *asic;
	435
	436	asic = container_of(chip, struct asic3, gpio);
	437	gpio_base = ASIC3_GPIO_TO_BASE(offset);
	438
3b8139f8	439	if (gpio_base > ASIC3_GPIO_D_BASE) {
24f4f2ee SO	440	dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
24f4f2ee SO	441	gpio_base, offset);
6f2384c4 SO	442	return -EINVAL;
	443	}
	444
3b8139f8	445	return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
6f2384c4 SO	446	}
	447
	448	static void asic3_gpio_set(struct gpio_chip *chip,
	449	unsigned offset, int value)
	450	{
	451	u32 mask, out_reg;
	452	unsigned int gpio_base;
	453	unsigned long flags;
	454	struct asic3 *asic;
	455
	456	asic = container_of(chip, struct asic3, gpio);
	457	gpio_base = ASIC3_GPIO_TO_BASE(offset);
	458
3b8139f8	459	if (gpio_base > ASIC3_GPIO_D_BASE) {
24f4f2ee SO	460	dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
24f4f2ee SO	461	gpio_base, offset);
6f2384c4 SO	462	return;
	463	}
	464
	465	mask = ASIC3_GPIO_TO_MASK(offset);
	466
	467	spin_lock_irqsave(&asic->lock, flags);
	468
3b8139f8	469	out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
6f2384c4 SO	470
	471	if (value)
	472	out_reg \|= mask;
	473	else
	474	out_reg &= ~mask;
	475
3b8139f8	476	asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
6f2384c4 SO	477
	478	spin_unlock_irqrestore(&asic->lock, flags);
	479
	480	return;
	481	}
	482
065032f6 PZ	483	static __init int asic3_gpio_probe(struct platform_device *pdev,
065032f6 PZ	484	u16 *gpio_config, int num)
fa9ff4b1	485	{
fa9ff4b1	486	struct asic3 *asic = platform_get_drvdata(pdev);
3b26bf17 SO	487	u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
	488	u16 out_reg[ASIC3_NUM_GPIO_BANKS];
	489	u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
	490	int i;
fa9ff4b1	491
59f0cb0f RK	492	memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
	493	memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
	494	memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
3b26bf17 SO	495
3b26bf17 SO	496	/* Enable all GPIOs */
3b8139f8 SO	497	asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
	498	asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
	499	asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
	500	asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
fa9ff4b1	501
3b26bf17 SO	502	for (i = 0; i < num; i++) {
	503	u8 alt, pin, dir, init, bank_num, bit_num;
	504	u16 config = gpio_config[i];
	505
	506	pin = ASIC3_CONFIG_GPIO_PIN(config);
	507	alt = ASIC3_CONFIG_GPIO_ALT(config);
	508	dir = ASIC3_CONFIG_GPIO_DIR(config);
	509	init = ASIC3_CONFIG_GPIO_INIT(config);
	510
	511	bank_num = ASIC3_GPIO_TO_BANK(pin);
	512	bit_num = ASIC3_GPIO_TO_BIT(pin);
	513
	514	alt_reg[bank_num] \|= (alt << bit_num);
	515	out_reg[bank_num] \|= (init << bit_num);
	516	dir_reg[bank_num] \|= (dir << bit_num);
	517	}
	518
	519	for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
	520	asic3_write_register(asic,
	521	ASIC3_BANK_TO_BASE(i) +
3b8139f8	522	ASIC3_GPIO_DIRECTION,
3b26bf17 SO	523	dir_reg[i]);
3b26bf17 SO	524	asic3_write_register(asic,
3b8139f8	525	ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
3b26bf17 SO	526	out_reg[i]);
	527	asic3_write_register(asic,
	528	ASIC3_BANK_TO_BASE(i) +
3b8139f8	529	ASIC3_GPIO_ALT_FUNCTION,
3b26bf17	530	alt_reg[i]);
fa9ff4b1 SO	531	}
fa9ff4b1 SO	532
6f2384c4	533	return gpiochip_add(&asic->gpio);
fa9ff4b1 SO	534	}
fa9ff4b1 SO	535
6f2384c4	536	static int asic3_gpio_remove(struct platform_device *pdev)
fa9ff4b1	537	{
6f2384c4 SO	538	struct asic3 *asic = platform_get_drvdata(pdev);
	539
	540	return gpiochip_remove(&asic->gpio);
fa9ff4b1 SO	541	}
	542
	543
	544	/* Core */
065032f6	545	static int __init asic3_probe(struct platform_device *pdev)
fa9ff4b1 SO	546	{
	547	struct asic3_platform_data *pdata = pdev->dev.platform_data;
	548	struct asic3 *asic;
	549	struct resource *mem;
	550	unsigned long clksel;
6cac6e84	551	int map_size;
6f2384c4	552	int ret = 0;
fa9ff4b1 SO	553
fa9ff4b1 SO	554	asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
6f2384c4 SO	555	if (asic == NULL) {
6f2384c4 SO	556	printk(KERN_ERR "kzalloc failed\n");
fa9ff4b1	557	return -ENOMEM;
6f2384c4	558	}
fa9ff4b1 SO	559
	560	spin_lock_init(&asic->lock);
	561	platform_set_drvdata(pdev, asic);
	562	asic->dev = &pdev->dev;
	563
	564	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	565	if (!mem) {
	566	ret = -ENOMEM;
24f4f2ee	567	dev_err(asic->dev, "no MEM resource\n");
6f2384c4	568	goto out_free;
fa9ff4b1 SO	569	}
fa9ff4b1 SO	570
99cdb0c8 PZ	571	map_size = mem->end - mem->start + 1;
99cdb0c8 PZ	572	asic->mapping = ioremap(mem->start, map_size);
fa9ff4b1 SO	573	if (!asic->mapping) {
fa9ff4b1 SO	574	ret = -ENOMEM;
24f4f2ee	575	dev_err(asic->dev, "Couldn't ioremap\n");
6f2384c4	576	goto out_free;
fa9ff4b1 SO	577	}
	578
	579	asic->irq_base = pdata->irq_base;
	580
99cdb0c8 PZ	581	/* calculate bus shift from mem resource */
99cdb0c8 PZ	582	asic->bus_shift = 2 - (map_size >> 12);
fa9ff4b1 SO	583
	584	clksel = 0;
	585	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
	586
	587	ret = asic3_irq_probe(pdev);
	588	if (ret < 0) {
24f4f2ee	589	dev_err(asic->dev, "Couldn't probe IRQs\n");
6f2384c4 SO	590	goto out_unmap;
	591	}
	592
	593	asic->gpio.base = pdata->gpio_base;
	594	asic->gpio.ngpio = ASIC3_NUM_GPIOS;
	595	asic->gpio.get = asic3_gpio_get;
	596	asic->gpio.set = asic3_gpio_set;
	597	asic->gpio.direction_input = asic3_gpio_direction_input;
	598	asic->gpio.direction_output = asic3_gpio_direction_output;
	599
3b26bf17 SO	600	ret = asic3_gpio_probe(pdev,
	601	pdata->gpio_config,
	602	pdata->gpio_config_num);
6f2384c4	603	if (ret < 0) {
24f4f2ee	604	dev_err(asic->dev, "GPIO probe failed\n");
6f2384c4	605	goto out_irq;
fa9ff4b1	606	}
fa9ff4b1	607
24f4f2ee	608	dev_info(asic->dev, "ASIC3 Core driver\n");
fa9ff4b1 SO	609
	610	return 0;
	611
6f2384c4 SO	612	out_irq:
	613	asic3_irq_remove(pdev);
	614
	615	out_unmap:
fa9ff4b1	616	iounmap(asic->mapping);
6f2384c4 SO	617
6f2384c4 SO	618	out_free:
fa9ff4b1 SO	619	kfree(asic);
	620
	621	return ret;
	622	}
	623
	624	static int asic3_remove(struct platform_device *pdev)
	625	{
6f2384c4	626	int ret;
fa9ff4b1 SO	627	struct asic3 *asic = platform_get_drvdata(pdev);
fa9ff4b1 SO	628
6f2384c4 SO	629	ret = asic3_gpio_remove(pdev);
	630	if (ret < 0)
	631	return ret;
fa9ff4b1 SO	632	asic3_irq_remove(pdev);
	633
	634	asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
	635
	636	iounmap(asic->mapping);
	637
	638	kfree(asic);
	639
	640	return 0;
	641	}
	642
	643	static void asic3_shutdown(struct platform_device *pdev)
	644	{
	645	}
	646
	647	static struct platform_driver asic3_device_driver = {
	648	.driver = {
	649	.name = "asic3",
	650	},
fa9ff4b1 SO	651	.remove = __devexit_p(asic3_remove),
	652	.shutdown = asic3_shutdown,
	653	};
	654
	655	static int __init asic3_init(void)
	656	{
	657	int retval = 0;
065032f6	658	retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
fa9ff4b1 SO	659	return retval;
	660	}
	661
	662	subsys_initcall(asic3_init);