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Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6
[net-next-2.6.git] / drivers / media / video / tvaudio.c
CommitLineData
1da177e4 1/*
b4ab114c 2 * Driver for simple i2c audio chips.
1da177e4
LT		 3 *
4 * Copyright (c) 2000 Gerd Knorr
5 * based on code by:
6 * Eric Sandeen (eric_sandeen@bigfoot.com)
7 * Steve VanDeBogart (vandebo@uclink.berkeley.edu)
8 * Greg Alexander (galexand@acm.org)
9 *
b4ab114c
MCC		 10 * Copyright(c) 2005-2008 Mauro Carvalho Chehab
11 * - Some cleanups, code fixes, etc
12 * - Convert it to V4L2 API
13 *
1da177e4
LT		 14 * This code is placed under the terms of the GNU General Public License
15 *
16 * OPTIONS:
17 * debug - set to 1 if you'd like to see debug messages
18 *
19 */
20
1da177e4 21#include <linux/module.h>
1da177e4
LT		 22#include <linux/kernel.h>
23#include <linux/sched.h>
24#include <linux/string.h>
25#include <linux/timer.h>
26#include <linux/delay.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
7f6adeaf 29#include <linux/videodev2.h>
1da177e4 30#include <linux/i2c.h>
1da177e4 31#include <linux/init.h>
bc282879 32#include <linux/kthread.h>
7dfb7103 33#include <linux/freezer.h>
1da177e4 34
8bf2f8e7 35#include <media/tvaudio.h>
64f70e7e 36#include <media/v4l2-device.h>
74cab31c 37#include <media/v4l2-chip-ident.h>
1da177e4 38
7c9b5048 39#include <media/i2c-addr.h>
1da177e4
LT		 40
41/* ---------------------------------------------------------------------- */
42/* insmod args */
43
ff699e6b 44static int debug; /* insmod parameter */
1da177e4
LT		 45module_param(debug, int, 0644);
46
47MODULE_DESCRIPTION("device driver for various i2c TV sound decoder / audiomux chips");
48MODULE_AUTHOR("Eric Sandeen, Steve VanDeBogart, Greg Alexander, Gerd Knorr");
49MODULE_LICENSE("GPL");
50
51#define UNSET (-1U)
18fc59e2 52
1da177e4
LT		 53/* ---------------------------------------------------------------------- */
54/* our structs */
55
4c6c390e 56#define MAXREGS 256
1da177e4
LT		 57
58struct CHIPSTATE;
59typedef int (*getvalue)(int);
60typedef int (*checkit)(struct CHIPSTATE*);
61typedef int (*initialize)(struct CHIPSTATE*);
62typedef int (*getmode)(struct CHIPSTATE*);
63typedef void (*setmode)(struct CHIPSTATE*, int mode);
1da177e4
LT		 64
65/* i2c command */
66typedef struct AUDIOCMD {
67 int count; /* # of bytes to send */
68 unsigned char bytes[MAXREGS+1]; /* addr, data, data, ... */
69} audiocmd;
70
71/* chip description */
72struct CHIPDESC {
73 char *name; /* chip name */
1da177e4
LT		 74 int addr_lo, addr_hi; /* i2c address range */
75 int registers; /* # of registers */
76
77 int *insmodopt;
78 checkit checkit;
79 initialize initialize;
80 int flags;
81#define CHIP_HAS_VOLUME 1
82#define CHIP_HAS_BASSTREBLE 2
83#define CHIP_HAS_INPUTSEL 4
dd03e970 84#define CHIP_NEED_CHECKMODE 8
1da177e4
LT		 85
86 /* various i2c command sequences */
87 audiocmd init;
88
89 /* which register has which value */
90 int leftreg,rightreg,treblereg,bassreg;
91
92 /* initialize with (defaults to 65535/65535/32768/32768 */
93 int leftinit,rightinit,trebleinit,bassinit;
94
95 /* functions to convert the values (v4l -> chip) */
96 getvalue volfunc,treblefunc,bassfunc;
97
98 /* get/set mode */
99 getmode getmode;
100 setmode setmode;
101
1da177e4
LT		 102 /* input switch register + values for v4l inputs */
103 int inputreg;
8bf2f8e7 104 int inputmap[4];
1da177e4
LT		 105 int inputmute;
106 int inputmask;
107};
1da177e4
LT		 108
109/* current state of the chip */
110struct CHIPSTATE {
64f70e7e 111 struct v4l2_subdev sd;
1da177e4 112
81cb5c4f
MCC		 113 /* chip-specific description - should point to
114 an entry at CHIPDESC table */
115 struct CHIPDESC *desc;
1da177e4
LT		 116
117 /* shadow register set */
118 audiocmd shadow;
119
120 /* current settings */
8bf2f8e7 121 __u16 left,right,treble,bass,muted,mode;
1da177e4 122 int prevmode;
8a854284 123 int radio;
8bf2f8e7 124 int input;
1da177e4
LT		 125
126 /* thread */
bc282879 127 struct task_struct *thread;
1da177e4 128 struct timer_list wt;
1da177e4 129 int watch_stereo;
8a4b275f 130 int audmode;
1da177e4
LT		 131};
132
64f70e7e
HV		 133static inline struct CHIPSTATE *to_state(struct v4l2_subdev *sd)
134{
135 return container_of(sd, struct CHIPSTATE, sd);
136}
137
1da177e4 138
1da177e4
LT		 139/* ---------------------------------------------------------------------- */
140/* i2c I/O functions */
141
142static int chip_write(struct CHIPSTATE *chip, int subaddr, int val)
143{
64f70e7e
HV		 144 struct v4l2_subdev *sd = &chip->sd;
145 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 146 unsigned char buffer[2];
147
49426437 148 if (subaddr < 0) {
64f70e7e 149 v4l2_dbg(1, debug, sd, "chip_write: 0x%x\n", val);
1da177e4
LT		 150 chip->shadow.bytes[1] = val;
151 buffer[0] = val;
64f70e7e
HV		 152 if (1 != i2c_master_send(c, buffer, 1)) {
153 v4l2_warn(sd, "I/O error (write 0x%x)\n", val);
1da177e4
LT		 154 return -1;
155 }
156 } else {
49426437 157 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 158 v4l2_info(sd,
49426437
MCC		 159 "Tried to access a non-existent register: %d\n",
160 subaddr);
161 return -EINVAL;
162 }
163
64f70e7e
HV		 164 v4l2_dbg(1, debug, sd, "chip_write: reg%d=0x%x\n",
165 subaddr, val);
1da177e4
LT		 166 chip->shadow.bytes[subaddr+1] = val;
167 buffer[0] = subaddr;
168 buffer[1] = val;
64f70e7e
HV		 169 if (2 != i2c_master_send(c, buffer, 2)) {
170 v4l2_warn(sd, "I/O error (write reg%d=0x%x)\n",
171 subaddr, val);
1da177e4
LT		 172 return -1;
173 }
174 }
175 return 0;
176}
177
49426437
MCC		 178static int chip_write_masked(struct CHIPSTATE *chip,
179 int subaddr, int val, int mask)
1da177e4 180{
64f70e7e
HV		 181 struct v4l2_subdev *sd = &chip->sd;
182
1da177e4 183 if (mask != 0) {
49426437 184 if (subaddr < 0) {
1da177e4
LT		 185 val = (chip->shadow.bytes[1] & ~mask) | (val & mask);
186 } else {
49426437 187 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 188 v4l2_info(sd,
49426437
MCC		 189 "Tried to access a non-existent register: %d\n",
190 subaddr);
191 return -EINVAL;
192 }
193
1da177e4
LT		 194 val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask);
195 }
196 }
197 return chip_write(chip, subaddr, val);
198}
199
200static int chip_read(struct CHIPSTATE *chip)
201{
64f70e7e
HV		 202 struct v4l2_subdev *sd = &chip->sd;
203 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 204 unsigned char buffer;
205
64f70e7e
HV		 206 if (1 != i2c_master_recv(c, &buffer, 1)) {
207 v4l2_warn(sd, "I/O error (read)\n");
1da177e4
LT		 208 return -1;
209 }
64f70e7e 210 v4l2_dbg(1, debug, sd, "chip_read: 0x%x\n", buffer);
1da177e4
LT		 211 return buffer;
212}
213
214static int chip_read2(struct CHIPSTATE *chip, int subaddr)
215{
64f70e7e
HV		 216 struct v4l2_subdev *sd = &chip->sd;
217 struct i2c_client *c = v4l2_get_subdevdata(sd);
18fc59e2
MCC		 218 unsigned char write[1];
219 unsigned char read[1];
220 struct i2c_msg msgs[2] = {
64f70e7e
HV		 221 { c->addr, 0, 1, write },
222 { c->addr, I2C_M_RD, 1, read }
18fc59e2 223 };
64f70e7e 224
18fc59e2 225 write[0] = subaddr;
1da177e4 226
64f70e7e
HV		 227 if (2 != i2c_transfer(c->adapter, msgs, 2)) {
228 v4l2_warn(sd, "I/O error (read2)\n");
1da177e4
LT		 229 return -1;
230 }
64f70e7e
HV		 231 v4l2_dbg(1, debug, sd, "chip_read2: reg%d=0x%x\n",
232 subaddr, read[0]);
1da177e4
LT		 233 return read[0];
234}
235
236static int chip_cmd(struct CHIPSTATE *chip, char *name, audiocmd *cmd)
237{
64f70e7e
HV		 238 struct v4l2_subdev *sd = &chip->sd;
239 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 240 int i;
241
242 if (0 == cmd->count)
243 return 0;
244
49426437 245 if (cmd->count + cmd->bytes[0] - 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 246 v4l2_info(sd,
49426437
MCC		 247 "Tried to access a non-existent register range: %d to %d\n",
248 cmd->bytes[0] + 1, cmd->bytes[0] + cmd->count - 1);
249 return -EINVAL;
250 }
251
252 /* FIXME: it seems that the shadow bytes are wrong bellow !*/
253
1da177e4 254 /* update our shadow register set; print bytes if (debug > 0) */
64f70e7e
HV		 255 v4l2_dbg(1, debug, sd, "chip_cmd(%s): reg=%d, data:",
256 name, cmd->bytes[0]);
1da177e4 257 for (i = 1; i < cmd->count; i++) {
18fc59e2 258 if (debug)
64f70e7e 259 printk(KERN_CONT " 0x%x", cmd->bytes[i]);
1da177e4
LT		 260 chip->shadow.bytes[i+cmd->bytes[0]] = cmd->bytes[i];
261 }
18fc59e2 262 if (debug)
64f70e7e 263 printk(KERN_CONT "\n");
1da177e4
LT		 264
265 /* send data to the chip */
64f70e7e
HV		 266 if (cmd->count != i2c_master_send(c, cmd->bytes, cmd->count)) {
267 v4l2_warn(sd, "I/O error (%s)\n", name);
1da177e4
LT		 268 return -1;
269 }
270 return 0;
271}
272
273/* ---------------------------------------------------------------------- */
274/* kernel thread for doing i2c stuff asyncronly
275 * right now it is used only to check the audio mode (mono/stereo/whatever)
276 * some time after switching to another TV channel, then turn on stereo
277 * if available, ...
278 */
279
280static void chip_thread_wake(unsigned long data)
281{
18fc59e2 282 struct CHIPSTATE *chip = (struct CHIPSTATE*)data;
bc282879 283 wake_up_process(chip->thread);
1da177e4
LT		 284}
285
286static int chip_thread(void *data)
287{
18fc59e2 288 struct CHIPSTATE *chip = data;
81cb5c4f 289 struct CHIPDESC *desc = chip->desc;
64f70e7e 290 struct v4l2_subdev *sd = &chip->sd;
dd03e970 291 int mode;
1da177e4 292
64f70e7e 293 v4l2_dbg(1, debug, sd, "thread started\n");
83144186 294 set_freezable();
1da177e4 295 for (;;) {
bc282879
CLG		 296 set_current_state(TASK_INTERRUPTIBLE);
297 if (!kthread_should_stop())
1da177e4 298 schedule();
bc282879 299 set_current_state(TASK_RUNNING);
5e50e7a9 300 try_to_freeze();
bc282879 301 if (kthread_should_stop())
1da177e4 302 break;
64f70e7e 303 v4l2_dbg(1, debug, sd, "thread wakeup\n");
1da177e4
LT		 304
305 /* don't do anything for radio or if mode != auto */
8a854284 306 if (chip->radio || chip->mode != 0)
1da177e4
LT		 307 continue;
308
309 /* have a look what's going on */
dd03e970
MCC		 310 mode = desc->getmode(chip);
311 if (mode == chip->prevmode)
312 continue;
313
314 /* chip detected a new audio mode - set it */
64f70e7e 315 v4l2_dbg(1, debug, sd, "thread checkmode\n");
dd03e970
MCC		 316
317 chip->prevmode = mode;
318
319 if (mode & V4L2_TUNER_MODE_STEREO)
320 desc->setmode(chip, V4L2_TUNER_MODE_STEREO);
321 if (mode & V4L2_TUNER_MODE_LANG1_LANG2)
322 desc->setmode(chip, V4L2_TUNER_MODE_STEREO);
323 else if (mode & V4L2_TUNER_MODE_LANG1)
324 desc->setmode(chip, V4L2_TUNER_MODE_LANG1);
325 else if (mode & V4L2_TUNER_MODE_LANG2)
326 desc->setmode(chip, V4L2_TUNER_MODE_LANG2);
327 else
328 desc->setmode(chip, V4L2_TUNER_MODE_MONO);
1da177e4
LT		 329
330 /* schedule next check */
09df5cbe 331 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
1da177e4
LT		 332 }
333
64f70e7e 334 v4l2_dbg(1, debug, sd, "thread exiting\n");
1da177e4
LT		 335 return 0;
336}
337
1da177e4
LT		 338/* ---------------------------------------------------------------------- */
339/* audio chip descriptions - defines+functions for tda9840 */
340
341#define TDA9840_SW 0x00
342#define TDA9840_LVADJ 0x02
343#define TDA9840_STADJ 0x03
344#define TDA9840_TEST 0x04
345
346#define TDA9840_MONO 0x10
347#define TDA9840_STEREO 0x2a
348#define TDA9840_DUALA 0x12
349#define TDA9840_DUALB 0x1e
350#define TDA9840_DUALAB 0x1a
351#define TDA9840_DUALBA 0x16
352#define TDA9840_EXTERNAL 0x7a
353
354#define TDA9840_DS_DUAL 0x20 /* Dual sound identified */
355#define TDA9840_ST_STEREO 0x40 /* Stereo sound identified */
356#define TDA9840_PONRES 0x80 /* Power-on reset detected if = 1 */
357
358#define TDA9840_TEST_INT1SN 0x1 /* Integration time 0.5s when set */
359#define TDA9840_TEST_INTFU 0x02 /* Disables integrator function */
360
361static int tda9840_getmode(struct CHIPSTATE *chip)
362{
64f70e7e 363 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 364 int val, mode;
365
366 val = chip_read(chip);
dc3d75da 367 mode = V4L2_TUNER_MODE_MONO;
1da177e4 368 if (val & TDA9840_DS_DUAL)
dc3d75da 369 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4 370 if (val & TDA9840_ST_STEREO)
dc3d75da 371 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 372
64f70e7e 373 v4l2_dbg(1, debug, sd, "tda9840_getmode(): raw chip read: %d, return: %d\n",
18fc59e2 374 val, mode);
1da177e4
LT		 375 return mode;
376}
377
378static void tda9840_setmode(struct CHIPSTATE *chip, int mode)
379{
380 int update = 1;
381 int t = chip->shadow.bytes[TDA9840_SW + 1] & ~0x7e;
382
383 switch (mode) {
dc3d75da 384 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 385 t |= TDA9840_MONO;
386 break;
dc3d75da 387 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 388 t |= TDA9840_STEREO;
389 break;
dc3d75da 390 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 391 t |= TDA9840_DUALA;
392 break;
dc3d75da 393 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 394 t |= TDA9840_DUALB;
395 break;
396 default:
397 update = 0;
398 }
399
400 if (update)
401 chip_write(chip, TDA9840_SW, t);
402}
403
94f9e56e
HV		 404static int tda9840_checkit(struct CHIPSTATE *chip)
405{
406 int rc;
407 rc = chip_read(chip);
408 /* lower 5 bits should be 0 */
409 return ((rc & 0x1f) == 0) ? 1 : 0;
410}
411
1da177e4
LT		 412/* ---------------------------------------------------------------------- */
413/* audio chip descriptions - defines+functions for tda985x */
414
415/* subaddresses for TDA9855 */
416#define TDA9855_VR 0x00 /* Volume, right */
417#define TDA9855_VL 0x01 /* Volume, left */
418#define TDA9855_BA 0x02 /* Bass */
419#define TDA9855_TR 0x03 /* Treble */
420#define TDA9855_SW 0x04 /* Subwoofer - not connected on DTV2000 */
421
422/* subaddresses for TDA9850 */
423#define TDA9850_C4 0x04 /* Control 1 for TDA9850 */
424
425/* subaddesses for both chips */
426#define TDA985x_C5 0x05 /* Control 2 for TDA9850, Control 1 for TDA9855 */
427#define TDA985x_C6 0x06 /* Control 3 for TDA9850, Control 2 for TDA9855 */
428#define TDA985x_C7 0x07 /* Control 4 for TDA9850, Control 3 for TDA9855 */
429#define TDA985x_A1 0x08 /* Alignment 1 for both chips */
430#define TDA985x_A2 0x09 /* Alignment 2 for both chips */
431#define TDA985x_A3 0x0a /* Alignment 3 for both chips */
432
433/* Masks for bits in TDA9855 subaddresses */
434/* 0x00 - VR in TDA9855 */
435/* 0x01 - VL in TDA9855 */
436/* lower 7 bits control gain from -71dB (0x28) to 16dB (0x7f)
437 * in 1dB steps - mute is 0x27 */
438
439
440/* 0x02 - BA in TDA9855 */
441/* lower 5 bits control bass gain from -12dB (0x06) to 16.5dB (0x19)
442 * in .5dB steps - 0 is 0x0E */
443
444
445/* 0x03 - TR in TDA9855 */
446/* 4 bits << 1 control treble gain from -12dB (0x3) to 12dB (0xb)
447 * in 3dB steps - 0 is 0x7 */
448
449/* Masks for bits in both chips' subaddresses */
450/* 0x04 - SW in TDA9855, C4/Control 1 in TDA9850 */
451/* Unique to TDA9855: */
452/* 4 bits << 2 control subwoofer/surround gain from -14db (0x1) to 14db (0xf)
453 * in 3dB steps - mute is 0x0 */
454
455/* Unique to TDA9850: */
456/* lower 4 bits control stereo noise threshold, over which stereo turns off
457 * set to values of 0x00 through 0x0f for Ster1 through Ster16 */
458
459
460/* 0x05 - C5 - Control 1 in TDA9855 , Control 2 in TDA9850*/
461/* Unique to TDA9855: */
462#define TDA9855_MUTE 1<<7 /* GMU, Mute at outputs */
463#define TDA9855_AVL 1<<6 /* AVL, Automatic Volume Level */
464#define TDA9855_LOUD 1<<5 /* Loudness, 1==off */
465#define TDA9855_SUR 1<<3 /* Surround / Subwoofer 1==.5(L-R) 0==.5(L+R) */
466 /* Bits 0 to 3 select various combinations
4ac97914
MCC		 467 * of line in and line out, only the
468 * interesting ones are defined */
1da177e4
LT		 469#define TDA9855_EXT 1<<2 /* Selects inputs LIR and LIL. Pins 41 & 12 */
470#define TDA9855_INT 0 /* Selects inputs LOR and LOL. (internal) */
471
472/* Unique to TDA9850: */
473/* lower 4 bits contol SAP noise threshold, over which SAP turns off
474 * set to values of 0x00 through 0x0f for SAP1 through SAP16 */
475
476
477/* 0x06 - C6 - Control 2 in TDA9855, Control 3 in TDA9850 */
478/* Common to TDA9855 and TDA9850: */
479#define TDA985x_SAP 3<<6 /* Selects SAP output, mute if not received */
480#define TDA985x_STEREO 1<<6 /* Selects Stereo ouput, mono if not received */
481#define TDA985x_MONO 0 /* Forces Mono output */
482#define TDA985x_LMU 1<<3 /* Mute (LOR/LOL for 9855, OUTL/OUTR for 9850) */
483
484/* Unique to TDA9855: */
485#define TDA9855_TZCM 1<<5 /* If set, don't mute till zero crossing */
486#define TDA9855_VZCM 1<<4 /* If set, don't change volume till zero crossing*/
487#define TDA9855_LINEAR 0 /* Linear Stereo */
488#define TDA9855_PSEUDO 1 /* Pseudo Stereo */
489#define TDA9855_SPAT_30 2 /* Spatial Stereo, 30% anti-phase crosstalk */
490#define TDA9855_SPAT_50 3 /* Spatial Stereo, 52% anti-phase crosstalk */
491#define TDA9855_E_MONO 7 /* Forced mono - mono select elseware, so useless*/
492
493/* 0x07 - C7 - Control 3 in TDA9855, Control 4 in TDA9850 */
494/* Common to both TDA9855 and TDA9850: */
495/* lower 4 bits control input gain from -3.5dB (0x0) to 4dB (0xF)
496 * in .5dB steps - 0dB is 0x7 */
497
498/* 0x08, 0x09 - A1 and A2 (read/write) */
499/* Common to both TDA9855 and TDA9850: */
500/* lower 5 bites are wideband and spectral expander alignment
501 * from 0x00 to 0x1f - nominal at 0x0f and 0x10 (read/write) */
502#define TDA985x_STP 1<<5 /* Stereo Pilot/detect (read-only) */
503#define TDA985x_SAPP 1<<6 /* SAP Pilot/detect (read-only) */
504#define TDA985x_STS 1<<7 /* Stereo trigger 1= <35mV 0= <30mV (write-only)*/
505
506/* 0x0a - A3 */
507/* Common to both TDA9855 and TDA9850: */
508/* lower 3 bits control timing current for alignment: -30% (0x0), -20% (0x1),
509 * -10% (0x2), nominal (0x3), +10% (0x6), +20% (0x5), +30% (0x4) */
510#define TDA985x_ADJ 1<<7 /* Stereo adjust on/off (wideband and spectral */
511
512static int tda9855_volume(int val) { return val/0x2e8+0x27; }
513static int tda9855_bass(int val) { return val/0xccc+0x06; }
514static int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; }
515
516static int tda985x_getmode(struct CHIPSTATE *chip)
517{
518 int mode;
519
520 mode = ((TDA985x_STP | TDA985x_SAPP) &
521 chip_read(chip)) >> 4;
522 /* Add mono mode regardless of SAP and stereo */
523 /* Allows forced mono */
dc3d75da 524 return mode | V4L2_TUNER_MODE_MONO;
1da177e4
LT		 525}
526
527static void tda985x_setmode(struct CHIPSTATE *chip, int mode)
528{
529 int update = 1;
530 int c6 = chip->shadow.bytes[TDA985x_C6+1] & 0x3f;
531
532 switch (mode) {
dc3d75da 533 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 534 c6 |= TDA985x_MONO;
535 break;
dc3d75da 536 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 537 c6 |= TDA985x_STEREO;
538 break;
dc3d75da 539 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 540 c6 |= TDA985x_SAP;
541 break;
542 default:
543 update = 0;
544 }
545 if (update)
546 chip_write(chip,TDA985x_C6,c6);
547}
548
549
550/* ---------------------------------------------------------------------- */
551/* audio chip descriptions - defines+functions for tda9873h */
552
553/* Subaddresses for TDA9873H */
554
555#define TDA9873_SW 0x00 /* Switching */
556#define TDA9873_AD 0x01 /* Adjust */
557#define TDA9873_PT 0x02 /* Port */
558
559/* Subaddress 0x00: Switching Data
560 * B7..B0:
561 *
562 * B1, B0: Input source selection
563 * 0, 0 internal
564 * 1, 0 external stereo
565 * 0, 1 external mono
566 */
567#define TDA9873_INP_MASK 3
568#define TDA9873_INTERNAL 0
569#define TDA9873_EXT_STEREO 2
570#define TDA9873_EXT_MONO 1
571
572/* B3, B2: output signal select
573 * B4 : transmission mode
574 * 0, 0, 1 Mono
575 * 1, 0, 0 Stereo
576 * 1, 1, 1 Stereo (reversed channel)
577 * 0, 0, 0 Dual AB
578 * 0, 0, 1 Dual AA
579 * 0, 1, 0 Dual BB
580 * 0, 1, 1 Dual BA
581 */
582
583#define TDA9873_TR_MASK (7 << 2)
584#define TDA9873_TR_MONO 4
585#define TDA9873_TR_STEREO 1 << 4
586#define TDA9873_TR_REVERSE (1 << 3) & (1 << 2)
587#define TDA9873_TR_DUALA 1 << 2
588#define TDA9873_TR_DUALB 1 << 3
589
590/* output level controls
591 * B5: output level switch (0 = reduced gain, 1 = normal gain)
592 * B6: mute (1 = muted)
593 * B7: auto-mute (1 = auto-mute enabled)
594 */
595
596#define TDA9873_GAIN_NORMAL 1 << 5
597#define TDA9873_MUTE 1 << 6
598#define TDA9873_AUTOMUTE 1 << 7
599
600/* Subaddress 0x01: Adjust/standard */
601
602/* Lower 4 bits (C3..C0) control stereo adjustment on R channel (-0.6 - +0.7 dB)
603 * Recommended value is +0 dB
604 */
605
606#define TDA9873_STEREO_ADJ 0x06 /* 0dB gain */
607
608/* Bits C6..C4 control FM stantard
609 * C6, C5, C4
610 * 0, 0, 0 B/G (PAL FM)
611 * 0, 0, 1 M
612 * 0, 1, 0 D/K(1)
613 * 0, 1, 1 D/K(2)
614 * 1, 0, 0 D/K(3)
615 * 1, 0, 1 I
616 */
617#define TDA9873_BG 0
618#define TDA9873_M 1
619#define TDA9873_DK1 2
620#define TDA9873_DK2 3
621#define TDA9873_DK3 4
622#define TDA9873_I 5
623
624/* C7 controls identification response time (1=fast/0=normal)
625 */
626#define TDA9873_IDR_NORM 0
627#define TDA9873_IDR_FAST 1 << 7
628
629
630/* Subaddress 0x02: Port data */
631
632/* E1, E0 free programmable ports P1/P2
633 0, 0 both ports low
634 0, 1 P1 high
635 1, 0 P2 high
636 1, 1 both ports high
637*/
638
639#define TDA9873_PORTS 3
640
641/* E2: test port */
642#define TDA9873_TST_PORT 1 << 2
643
644/* E5..E3 control mono output channel (together with transmission mode bit B4)
645 *
646 * E5 E4 E3 B4 OUTM
647 * 0 0 0 0 mono
648 * 0 0 1 0 DUAL B
649 * 0 1 0 1 mono (from stereo decoder)
650 */
651#define TDA9873_MOUT_MONO 0
652#define TDA9873_MOUT_FMONO 0
653#define TDA9873_MOUT_DUALA 0
654#define TDA9873_MOUT_DUALB 1 << 3
655#define TDA9873_MOUT_ST 1 << 4
656#define TDA9873_MOUT_EXTM (1 << 4 ) & (1 << 3)
657#define TDA9873_MOUT_EXTL 1 << 5
658#define TDA9873_MOUT_EXTR (1 << 5 ) & (1 << 3)
659#define TDA9873_MOUT_EXTLR (1 << 5 ) & (1 << 4)
660#define TDA9873_MOUT_MUTE (1 << 5 ) & (1 << 4) & (1 << 3)
661
662/* Status bits: (chip read) */
663#define TDA9873_PONR 0 /* Power-on reset detected if = 1 */
664#define TDA9873_STEREO 2 /* Stereo sound is identified */
665#define TDA9873_DUAL 4 /* Dual sound is identified */
666
667static int tda9873_getmode(struct CHIPSTATE *chip)
668{
64f70e7e 669 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 670 int val,mode;
671
672 val = chip_read(chip);
dc3d75da 673 mode = V4L2_TUNER_MODE_MONO;
1da177e4 674 if (val & TDA9873_STEREO)
dc3d75da 675 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 676 if (val & TDA9873_DUAL)
dc3d75da 677 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
64f70e7e 678 v4l2_dbg(1, debug, sd, "tda9873_getmode(): raw chip read: %d, return: %d\n",
18fc59e2 679 val, mode);
1da177e4
LT		 680 return mode;
681}
682
683static void tda9873_setmode(struct CHIPSTATE *chip, int mode)
684{
64f70e7e 685 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 686 int sw_data = chip->shadow.bytes[TDA9873_SW+1] & ~ TDA9873_TR_MASK;
687 /* int adj_data = chip->shadow.bytes[TDA9873_AD+1] ; */
688
689 if ((sw_data & TDA9873_INP_MASK) != TDA9873_INTERNAL) {
64f70e7e 690 v4l2_dbg(1, debug, sd, "tda9873_setmode(): external input\n");
1da177e4
LT		 691 return;
692 }
693
64f70e7e
HV		 694 v4l2_dbg(1, debug, sd, "tda9873_setmode(): chip->shadow.bytes[%d] = %d\n", TDA9873_SW+1, chip->shadow.bytes[TDA9873_SW+1]);
695 v4l2_dbg(1, debug, sd, "tda9873_setmode(): sw_data = %d\n", sw_data);
1da177e4
LT		 696
697 switch (mode) {
dc3d75da 698 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 699 sw_data |= TDA9873_TR_MONO;
700 break;
dc3d75da 701 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 702 sw_data |= TDA9873_TR_STEREO;
703 break;
dc3d75da 704 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 705 sw_data |= TDA9873_TR_DUALA;
706 break;
dc3d75da 707 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 708 sw_data |= TDA9873_TR_DUALB;
709 break;
710 default:
711 chip->mode = 0;
712 return;
713 }
714
715 chip_write(chip, TDA9873_SW, sw_data);
64f70e7e 716 v4l2_dbg(1, debug, sd, "tda9873_setmode(): req. mode %d; chip_write: %d\n",
1da177e4
LT		 717 mode, sw_data);
718}
719
720static int tda9873_checkit(struct CHIPSTATE *chip)
721{
722 int rc;
723
724 if (-1 == (rc = chip_read2(chip,254)))
725 return 0;
726 return (rc & ~0x1f) == 0x80;
727}
728
729
730/* ---------------------------------------------------------------------- */
731/* audio chip description - defines+functions for tda9874h and tda9874a */
732/* Dariusz Kowalewski <darekk@automex.pl> */
733
734/* Subaddresses for TDA9874H and TDA9874A (slave rx) */
735#define TDA9874A_AGCGR 0x00 /* AGC gain */
736#define TDA9874A_GCONR 0x01 /* general config */
737#define TDA9874A_MSR 0x02 /* monitor select */
738#define TDA9874A_C1FRA 0x03 /* carrier 1 freq. */
739#define TDA9874A_C1FRB 0x04 /* carrier 1 freq. */
740#define TDA9874A_C1FRC 0x05 /* carrier 1 freq. */
741#define TDA9874A_C2FRA 0x06 /* carrier 2 freq. */
742#define TDA9874A_C2FRB 0x07 /* carrier 2 freq. */
743#define TDA9874A_C2FRC 0x08 /* carrier 2 freq. */
744#define TDA9874A_DCR 0x09 /* demodulator config */
745#define TDA9874A_FMER 0x0a /* FM de-emphasis */
746#define TDA9874A_FMMR 0x0b /* FM dematrix */
747#define TDA9874A_C1OLAR 0x0c /* ch.1 output level adj. */
748#define TDA9874A_C2OLAR 0x0d /* ch.2 output level adj. */
749#define TDA9874A_NCONR 0x0e /* NICAM config */
750#define TDA9874A_NOLAR 0x0f /* NICAM output level adj. */
751#define TDA9874A_NLELR 0x10 /* NICAM lower error limit */
752#define TDA9874A_NUELR 0x11 /* NICAM upper error limit */
753#define TDA9874A_AMCONR 0x12 /* audio mute control */
754#define TDA9874A_SDACOSR 0x13 /* stereo DAC output select */
755#define TDA9874A_AOSR 0x14 /* analog output select */
756#define TDA9874A_DAICONR 0x15 /* digital audio interface config */
757#define TDA9874A_I2SOSR 0x16 /* I2S-bus output select */
758#define TDA9874A_I2SOLAR 0x17 /* I2S-bus output level adj. */
759#define TDA9874A_MDACOSR 0x18 /* mono DAC output select (tda9874a) */
760#define TDA9874A_ESP 0xFF /* easy standard progr. (tda9874a) */
761
762/* Subaddresses for TDA9874H and TDA9874A (slave tx) */
763#define TDA9874A_DSR 0x00 /* device status */
764#define TDA9874A_NSR 0x01 /* NICAM status */
765#define TDA9874A_NECR 0x02 /* NICAM error count */
766#define TDA9874A_DR1 0x03 /* add. data LSB */
767#define TDA9874A_DR2 0x04 /* add. data MSB */
768#define TDA9874A_LLRA 0x05 /* monitor level read-out LSB */
769#define TDA9874A_LLRB 0x06 /* monitor level read-out MSB */
770#define TDA9874A_SIFLR 0x07 /* SIF level */
771#define TDA9874A_TR2 252 /* test reg. 2 */
772#define TDA9874A_TR1 253 /* test reg. 1 */
773#define TDA9874A_DIC 254 /* device id. code */
774#define TDA9874A_SIC 255 /* software id. code */
775
776
777static int tda9874a_mode = 1; /* 0: A2, 1: NICAM */
778static int tda9874a_GCONR = 0xc0; /* default config. input pin: SIFSEL=0 */
779static int tda9874a_NCONR = 0x01; /* default NICAM config.: AMSEL=0,AMUTE=1 */
780static int tda9874a_ESP = 0x07; /* default standard: NICAM D/K */
781static int tda9874a_dic = -1; /* device id. code */
782
783/* insmod options for tda9874a */
784static unsigned int tda9874a_SIF = UNSET;
785static unsigned int tda9874a_AMSEL = UNSET;
786static unsigned int tda9874a_STD = UNSET;
787module_param(tda9874a_SIF, int, 0444);
788module_param(tda9874a_AMSEL, int, 0444);
789module_param(tda9874a_STD, int, 0444);
790
791/*
792 * initialization table for tda9874 decoder:
793 * - carrier 1 freq. registers (3 bytes)
794 * - carrier 2 freq. registers (3 bytes)
795 * - demudulator config register
796 * - FM de-emphasis register (slow identification mode)
797 * Note: frequency registers must be written in single i2c transfer.
798 */
799static struct tda9874a_MODES {
800 char *name;
801 audiocmd cmd;
802} tda9874a_modelist[9] = {
04e6f990 803 { "A2, B/G", /* default */
1da177e4
LT		 804 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x77,0xA0,0x00, 0x00,0x00 }} },
805 { "A2, M (Korea)",
806 { 9, { TDA9874A_C1FRA, 0x5D,0xC0,0x00, 0x62,0x6A,0xAA, 0x20,0x22 }} },
807 { "A2, D/K (1)",
808 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x82,0x60,0x00, 0x00,0x00 }} },
809 { "A2, D/K (2)",
810 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x8C,0x75,0x55, 0x00,0x00 }} },
811 { "A2, D/K (3)",
812 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x77,0xA0,0x00, 0x00,0x00 }} },
813 { "NICAM, I",
814 { 9, { TDA9874A_C1FRA, 0x7D,0x00,0x00, 0x88,0x8A,0xAA, 0x08,0x33 }} },
815 { "NICAM, B/G",
816 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x79,0xEA,0xAA, 0x08,0x33 }} },
04e6f990 817 { "NICAM, D/K",
1da177e4
LT		 818 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x08,0x33 }} },
819 { "NICAM, L",
820 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x09,0x33 }} }
821};
822
823static int tda9874a_setup(struct CHIPSTATE *chip)
824{
64f70e7e
HV		 825 struct v4l2_subdev *sd = &chip->sd;
826
1da177e4
LT		 827 chip_write(chip, TDA9874A_AGCGR, 0x00); /* 0 dB */
828 chip_write(chip, TDA9874A_GCONR, tda9874a_GCONR);
829 chip_write(chip, TDA9874A_MSR, (tda9874a_mode) ? 0x03:0x02);
830 if(tda9874a_dic == 0x11) {
831 chip_write(chip, TDA9874A_FMMR, 0x80);
832 } else { /* dic == 0x07 */
833 chip_cmd(chip,"tda9874_modelist",&tda9874a_modelist[tda9874a_STD].cmd);
834 chip_write(chip, TDA9874A_FMMR, 0x00);
835 }
836 chip_write(chip, TDA9874A_C1OLAR, 0x00); /* 0 dB */
837 chip_write(chip, TDA9874A_C2OLAR, 0x00); /* 0 dB */
838 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
839 chip_write(chip, TDA9874A_NOLAR, 0x00); /* 0 dB */
840 /* Note: If signal quality is poor you may want to change NICAM */
841 /* error limit registers (NLELR and NUELR) to some greater values. */
842 /* Then the sound would remain stereo, but won't be so clear. */
843 chip_write(chip, TDA9874A_NLELR, 0x14); /* default */
844 chip_write(chip, TDA9874A_NUELR, 0x50); /* default */
845
846 if(tda9874a_dic == 0x11) {
847 chip_write(chip, TDA9874A_AMCONR, 0xf9);
848 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
849 chip_write(chip, TDA9874A_AOSR, 0x80);
850 chip_write(chip, TDA9874A_MDACOSR, (tda9874a_mode) ? 0x82:0x80);
851 chip_write(chip, TDA9874A_ESP, tda9874a_ESP);
852 } else { /* dic == 0x07 */
853 chip_write(chip, TDA9874A_AMCONR, 0xfb);
854 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
18fc59e2 855 chip_write(chip, TDA9874A_AOSR, 0x00); /* or 0x10 */
1da177e4 856 }
64f70e7e 857 v4l2_dbg(1, debug, sd, "tda9874a_setup(): %s [0x%02X].\n",
1da177e4
LT		 858 tda9874a_modelist[tda9874a_STD].name,tda9874a_STD);
859 return 1;
860}
861
862static int tda9874a_getmode(struct CHIPSTATE *chip)
863{
64f70e7e 864 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 865 int dsr,nsr,mode;
866 int necr; /* just for debugging */
867
dc3d75da 868 mode = V4L2_TUNER_MODE_MONO;
1da177e4
LT		 869
870 if(-1 == (dsr = chip_read2(chip,TDA9874A_DSR)))
871 return mode;
872 if(-1 == (nsr = chip_read2(chip,TDA9874A_NSR)))
873 return mode;
874 if(-1 == (necr = chip_read2(chip,TDA9874A_NECR)))
875 return mode;
876
877 /* need to store dsr/nsr somewhere */
878 chip->shadow.bytes[MAXREGS-2] = dsr;
879 chip->shadow.bytes[MAXREGS-1] = nsr;
880
881 if(tda9874a_mode) {
882 /* Note: DSR.RSSF and DSR.AMSTAT bits are also checked.
883 * If NICAM auto-muting is enabled, DSR.AMSTAT=1 indicates
884 * that sound has (temporarily) switched from NICAM to
885 * mono FM (or AM) on 1st sound carrier due to high NICAM bit
886 * error count. So in fact there is no stereo in this case :-(
dc3d75da 887 * But changing the mode to V4L2_TUNER_MODE_MONO would switch
1da177e4
LT		 888 * external 4052 multiplexer in audio_hook().
889 */
1da177e4 890 if(nsr & 0x02) /* NSR.S/MB=1 */
dc3d75da 891 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 892 if(nsr & 0x01) /* NSR.D/SB=1 */
dc3d75da 893 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4
LT		 894 } else {
895 if(dsr & 0x02) /* DSR.IDSTE=1 */
dc3d75da 896 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 897 if(dsr & 0x04) /* DSR.IDDUA=1 */
dc3d75da 898 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4
LT		 899 }
900
64f70e7e 901 v4l2_dbg(1, debug, sd, "tda9874a_getmode(): DSR=0x%X, NSR=0x%X, NECR=0x%X, return: %d.\n",
1da177e4
LT		 902 dsr, nsr, necr, mode);
903 return mode;
904}
905
906static void tda9874a_setmode(struct CHIPSTATE *chip, int mode)
907{
64f70e7e
HV		 908 struct v4l2_subdev *sd = &chip->sd;
909
1da177e4
LT		 910 /* Disable/enable NICAM auto-muting (based on DSR.RSSF status bit). */
911 /* If auto-muting is disabled, we can hear a signal of degrading quality. */
64f70e7e 912 if (tda9874a_mode) {
1da177e4
LT		 913 if(chip->shadow.bytes[MAXREGS-2] & 0x20) /* DSR.RSSF=1 */
914 tda9874a_NCONR &= 0xfe; /* enable */
915 else
916 tda9874a_NCONR |= 0x01; /* disable */
917 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
918 }
919
920 /* Note: TDA9874A supports automatic FM dematrixing (FMMR register)
921 * and has auto-select function for audio output (AOSR register).
922 * Old TDA9874H doesn't support these features.
923 * TDA9874A also has additional mono output pin (OUTM), which
924 * on same (all?) tv-cards is not used, anyway (as well as MONOIN).
925 */
926 if(tda9874a_dic == 0x11) {
927 int aosr = 0x80;
928 int mdacosr = (tda9874a_mode) ? 0x82:0x80;
929
930 switch(mode) {
dc3d75da
MCC		 931 case V4L2_TUNER_MODE_MONO:
932 case V4L2_TUNER_MODE_STEREO:
1da177e4 933 break;
dc3d75da 934 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 935 aosr = 0x80; /* auto-select, dual A/A */
936 mdacosr = (tda9874a_mode) ? 0x82:0x80;
937 break;
dc3d75da 938 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 939 aosr = 0xa0; /* auto-select, dual B/B */
940 mdacosr = (tda9874a_mode) ? 0x83:0x81;
941 break;
942 default:
943 chip->mode = 0;
944 return;
945 }
946 chip_write(chip, TDA9874A_AOSR, aosr);
947 chip_write(chip, TDA9874A_MDACOSR, mdacosr);
948
64f70e7e 949 v4l2_dbg(1, debug, sd, "tda9874a_setmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\n",
1da177e4
LT		 950 mode, aosr, mdacosr);
951
952 } else { /* dic == 0x07 */
953 int fmmr,aosr;
954
955 switch(mode) {
dc3d75da 956 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 957 fmmr = 0x00; /* mono */
958 aosr = 0x10; /* A/A */
959 break;
dc3d75da 960 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 961 if(tda9874a_mode) {
962 fmmr = 0x00;
963 aosr = 0x00; /* handled by NICAM auto-mute */
964 } else {
965 fmmr = (tda9874a_ESP == 1) ? 0x05 : 0x04; /* stereo */
966 aosr = 0x00;
967 }
968 break;
dc3d75da 969 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 970 fmmr = 0x02; /* dual */
971 aosr = 0x10; /* dual A/A */
972 break;
dc3d75da 973 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 974 fmmr = 0x02; /* dual */
975 aosr = 0x20; /* dual B/B */
976 break;
977 default:
978 chip->mode = 0;
979 return;
980 }
981 chip_write(chip, TDA9874A_FMMR, fmmr);
982 chip_write(chip, TDA9874A_AOSR, aosr);
983
64f70e7e 984 v4l2_dbg(1, debug, sd, "tda9874a_setmode(): req. mode %d; FMMR=0x%X, AOSR=0x%X.\n",
1da177e4
LT		 985 mode, fmmr, aosr);
986 }
987}
988
989static int tda9874a_checkit(struct CHIPSTATE *chip)
990{
64f70e7e 991 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 992 int dic,sic; /* device id. and software id. codes */
993
994 if(-1 == (dic = chip_read2(chip,TDA9874A_DIC)))
995 return 0;
996 if(-1 == (sic = chip_read2(chip,TDA9874A_SIC)))
997 return 0;
998
64f70e7e 999 v4l2_dbg(1, debug, sd, "tda9874a_checkit(): DIC=0x%X, SIC=0x%X.\n", dic, sic);
1da177e4
LT		 1000
1001 if((dic == 0x11)||(dic == 0x07)) {
64f70e7e 1002 v4l2_info(sd, "found tda9874%s.\n", (dic == 0x11) ? "a" : "h");
1da177e4
LT		 1003 tda9874a_dic = dic; /* remember device id. */
1004 return 1;
1005 }
1006 return 0; /* not found */
1007}
1008
1009static int tda9874a_initialize(struct CHIPSTATE *chip)
1010{
1011 if (tda9874a_SIF > 2)
1012 tda9874a_SIF = 1;
04e6f990 1013 if (tda9874a_STD >= ARRAY_SIZE(tda9874a_modelist))
1da177e4
LT		 1014 tda9874a_STD = 0;
1015 if(tda9874a_AMSEL > 1)
1016 tda9874a_AMSEL = 0;
1017
1018 if(tda9874a_SIF == 1)
1019 tda9874a_GCONR = 0xc0; /* sound IF input 1 */
1020 else
1021 tda9874a_GCONR = 0xc1; /* sound IF input 2 */
1022
1023 tda9874a_ESP = tda9874a_STD;
1024 tda9874a_mode = (tda9874a_STD < 5) ? 0 : 1;
1025
1026 if(tda9874a_AMSEL == 0)
1027 tda9874a_NCONR = 0x01; /* auto-mute: analog mono input */
1028 else
1029 tda9874a_NCONR = 0x05; /* auto-mute: 1st carrier FM or AM */
1030
1031 tda9874a_setup(chip);
1032 return 0;
1033}
1034
411674fd
HV		 1035/* ---------------------------------------------------------------------- */
1036/* audio chip description - defines+functions for tda9875 */
1037/* The TDA9875 is made by Philips Semiconductor
1038 * http://www.semiconductors.philips.com
1039 * TDA9875: I2C-bus controlled DSP audio processor, FM demodulator
1040 *
1041 */
1042
1043/* subaddresses for TDA9875 */
1044#define TDA9875_MUT 0x12 /*General mute (value --> 0b11001100*/
1045#define TDA9875_CFG 0x01 /* Config register (value --> 0b00000000 */
1046#define TDA9875_DACOS 0x13 /*DAC i/o select (ADC) 0b0000100*/
1047#define TDA9875_LOSR 0x16 /*Line output select regirter 0b0100 0001*/
1048
1049#define TDA9875_CH1V 0x0c /*Channel 1 volume (mute)*/
1050#define TDA9875_CH2V 0x0d /*Channel 2 volume (mute)*/
1051#define TDA9875_SC1 0x14 /*SCART 1 in (mono)*/
1052#define TDA9875_SC2 0x15 /*SCART 2 in (mono)*/
1053
1054#define TDA9875_ADCIS 0x17 /*ADC input select (mono) 0b0110 000*/
1055#define TDA9875_AER 0x19 /*Audio effect (AVL+Pseudo) 0b0000 0110*/
1056#define TDA9875_MCS 0x18 /*Main channel select (DAC) 0b0000100*/
1057#define TDA9875_MVL 0x1a /* Main volume gauche */
1058#define TDA9875_MVR 0x1b /* Main volume droite */
1059#define TDA9875_MBA 0x1d /* Main Basse */
1060#define TDA9875_MTR 0x1e /* Main treble */
1061#define TDA9875_ACS 0x1f /* Auxilary channel select (FM) 0b0000000*/
1062#define TDA9875_AVL 0x20 /* Auxilary volume gauche */
1063#define TDA9875_AVR 0x21 /* Auxilary volume droite */
1064#define TDA9875_ABA 0x22 /* Auxilary Basse */
1065#define TDA9875_ATR 0x23 /* Auxilary treble */
1066
1067#define TDA9875_MSR 0x02 /* Monitor select register */
1068#define TDA9875_C1MSB 0x03 /* Carrier 1 (FM) frequency register MSB */
1069#define TDA9875_C1MIB 0x04 /* Carrier 1 (FM) frequency register (16-8]b */
1070#define TDA9875_C1LSB 0x05 /* Carrier 1 (FM) frequency register LSB */
1071#define TDA9875_C2MSB 0x06 /* Carrier 2 (nicam) frequency register MSB */
1072#define TDA9875_C2MIB 0x07 /* Carrier 2 (nicam) frequency register (16-8]b */
1073#define TDA9875_C2LSB 0x08 /* Carrier 2 (nicam) frequency register LSB */
1074#define TDA9875_DCR 0x09 /* Demodulateur configuration regirter*/
1075#define TDA9875_DEEM 0x0a /* FM de-emphasis regirter*/
1076#define TDA9875_FMAT 0x0b /* FM Matrix regirter*/
1077
1078/* values */
1079#define TDA9875_MUTE_ON 0xff /* general mute */
1080#define TDA9875_MUTE_OFF 0xcc /* general no mute */
1081
1082static int tda9875_initialize(struct CHIPSTATE *chip)
1083{
1084 chip_write(chip, TDA9875_CFG, 0xd0); /*reg de config 0 (reset)*/
1085 chip_write(chip, TDA9875_MSR, 0x03); /* Monitor 0b00000XXX*/
1086 chip_write(chip, TDA9875_C1MSB, 0x00); /*Car1(FM) MSB XMHz*/
1087 chip_write(chip, TDA9875_C1MIB, 0x00); /*Car1(FM) MIB XMHz*/
1088 chip_write(chip, TDA9875_C1LSB, 0x00); /*Car1(FM) LSB XMHz*/
1089 chip_write(chip, TDA9875_C2MSB, 0x00); /*Car2(NICAM) MSB XMHz*/
1090 chip_write(chip, TDA9875_C2MIB, 0x00); /*Car2(NICAM) MIB XMHz*/
1091 chip_write(chip, TDA9875_C2LSB, 0x00); /*Car2(NICAM) LSB XMHz*/
1092 chip_write(chip, TDA9875_DCR, 0x00); /*Demod config 0x00*/
1093 chip_write(chip, TDA9875_DEEM, 0x44); /*DE-Emph 0b0100 0100*/
1094 chip_write(chip, TDA9875_FMAT, 0x00); /*FM Matrix reg 0x00*/
1095 chip_write(chip, TDA9875_SC1, 0x00); /* SCART 1 (SC1)*/
1096 chip_write(chip, TDA9875_SC2, 0x01); /* SCART 2 (sc2)*/
1097
1098 chip_write(chip, TDA9875_CH1V, 0x10); /* Channel volume 1 mute*/
1099 chip_write(chip, TDA9875_CH2V, 0x10); /* Channel volume 2 mute */
1100 chip_write(chip, TDA9875_DACOS, 0x02); /* sig DAC i/o(in:nicam)*/
1101 chip_write(chip, TDA9875_ADCIS, 0x6f); /* sig ADC input(in:mono)*/
1102 chip_write(chip, TDA9875_LOSR, 0x00); /* line out (in:mono)*/
1103 chip_write(chip, TDA9875_AER, 0x00); /*06 Effect (AVL+PSEUDO) */
1104 chip_write(chip, TDA9875_MCS, 0x44); /* Main ch select (DAC) */
1105 chip_write(chip, TDA9875_MVL, 0x03); /* Vol Main left 10dB */
1106 chip_write(chip, TDA9875_MVR, 0x03); /* Vol Main right 10dB*/
1107 chip_write(chip, TDA9875_MBA, 0x00); /* Main Bass Main 0dB*/
1108 chip_write(chip, TDA9875_MTR, 0x00); /* Main Treble Main 0dB*/
1109 chip_write(chip, TDA9875_ACS, 0x44); /* Aux chan select (dac)*/
1110 chip_write(chip, TDA9875_AVL, 0x00); /* Vol Aux left 0dB*/
1111 chip_write(chip, TDA9875_AVR, 0x00); /* Vol Aux right 0dB*/
1112 chip_write(chip, TDA9875_ABA, 0x00); /* Aux Bass Main 0dB*/
1113 chip_write(chip, TDA9875_ATR, 0x00); /* Aux Aigus Main 0dB*/
1114
1115 chip_write(chip, TDA9875_MUT, 0xcc); /* General mute */
1116 return 0;
1117}
1118
1119static int tda9875_volume(int val) { return (unsigned char)(val / 602 - 84); }
1120static int tda9875_bass(int val) { return (unsigned char)(max(-12, val / 2115 - 15)); }
1121static int tda9875_treble(int val) { return (unsigned char)(val / 2622 - 12); }
1122
1123/* ----------------------------------------------------------------------- */
1124
1125
1126/* *********************** *
1127 * i2c interface functions *
1128 * *********************** */
1129
1130static int tda9875_checkit(struct CHIPSTATE *chip)
1131{
1132 struct v4l2_subdev *sd = &chip->sd;
1133 int dic, rev;
1134
1135 dic = chip_read2(chip, 254);
1136 rev = chip_read2(chip, 255);
1137
1138 if (dic == 0 || dic == 2) { /* tda9875 and tda9875A */
1139 v4l2_info(sd, "found tda9875%s rev. %d.\n",
1140 dic == 0 ? "" : "A", rev);
1141 return 1;
1142 }
1143 return 0;
1144}
1da177e4
LT		 1145
1146/* ---------------------------------------------------------------------- */
1147/* audio chip descriptions - defines+functions for tea6420 */
1148
1149#define TEA6300_VL 0x00 /* volume left */
1150#define TEA6300_VR 0x01 /* volume right */
1151#define TEA6300_BA 0x02 /* bass */
1152#define TEA6300_TR 0x03 /* treble */
1153#define TEA6300_FA 0x04 /* fader control */
1154#define TEA6300_S 0x05 /* switch register */
f2421ca3 1155 /* values for those registers: */
1da177e4
LT		 1156#define TEA6300_S_SA 0x01 /* stereo A input */
1157#define TEA6300_S_SB 0x02 /* stereo B */
1158#define TEA6300_S_SC 0x04 /* stereo C */
1159#define TEA6300_S_GMU 0x80 /* general mute */
1160
1161#define TEA6320_V 0x00 /* volume (0-5)/loudness off (6)/zero crossing mute(7) */
1162#define TEA6320_FFR 0x01 /* fader front right (0-5) */
1163#define TEA6320_FFL 0x02 /* fader front left (0-5) */
1164#define TEA6320_FRR 0x03 /* fader rear right (0-5) */
1165#define TEA6320_FRL 0x04 /* fader rear left (0-5) */
1166#define TEA6320_BA 0x05 /* bass (0-4) */
1167#define TEA6320_TR 0x06 /* treble (0-4) */
1168#define TEA6320_S 0x07 /* switch register */
f2421ca3 1169 /* values for those registers: */
1da177e4
LT		 1170#define TEA6320_S_SA 0x07 /* stereo A input */
1171#define TEA6320_S_SB 0x06 /* stereo B */
1172#define TEA6320_S_SC 0x05 /* stereo C */
1173#define TEA6320_S_SD 0x04 /* stereo D */
1174#define TEA6320_S_GMU 0x80 /* general mute */
1175
1176#define TEA6420_S_SA 0x00 /* stereo A input */
1177#define TEA6420_S_SB 0x01 /* stereo B */
1178#define TEA6420_S_SC 0x02 /* stereo C */
1179#define TEA6420_S_SD 0x03 /* stereo D */
1180#define TEA6420_S_SE 0x04 /* stereo E */
1181#define TEA6420_S_GMU 0x05 /* general mute */
1182
1183static int tea6300_shift10(int val) { return val >> 10; }
1184static int tea6300_shift12(int val) { return val >> 12; }
1185
1186/* Assumes 16bit input (values 0x3f to 0x0c are unique, values less than */
1187/* 0x0c mirror those immediately higher) */
1188static int tea6320_volume(int val) { return (val / (65535/(63-12)) + 12) & 0x3f; }
1189static int tea6320_shift11(int val) { return val >> 11; }
1190static int tea6320_initialize(struct CHIPSTATE * chip)
1191{
1192 chip_write(chip, TEA6320_FFR, 0x3f);
1193 chip_write(chip, TEA6320_FFL, 0x3f);
1194 chip_write(chip, TEA6320_FRR, 0x3f);
1195 chip_write(chip, TEA6320_FRL, 0x3f);
1196
1197 return 0;
1198}
1199
1200
1201/* ---------------------------------------------------------------------- */
1202/* audio chip descriptions - defines+functions for tda8425 */
1203
1204#define TDA8425_VL 0x00 /* volume left */
1205#define TDA8425_VR 0x01 /* volume right */
1206#define TDA8425_BA 0x02 /* bass */
1207#define TDA8425_TR 0x03 /* treble */
1208#define TDA8425_S1 0x08 /* switch functions */
f2421ca3 1209 /* values for those registers: */
1da177e4
LT		 1210#define TDA8425_S1_OFF 0xEE /* audio off (mute on) */
1211#define TDA8425_S1_CH1 0xCE /* audio channel 1 (mute off) - "linear stereo" mode */
1212#define TDA8425_S1_CH2 0xCF /* audio channel 2 (mute off) - "linear stereo" mode */
1213#define TDA8425_S1_MU 0x20 /* mute bit */
1214#define TDA8425_S1_STEREO 0x18 /* stereo bits */
1215#define TDA8425_S1_STEREO_SPATIAL 0x18 /* spatial stereo */
1216#define TDA8425_S1_STEREO_LINEAR 0x08 /* linear stereo */
1217#define TDA8425_S1_STEREO_PSEUDO 0x10 /* pseudo stereo */
1218#define TDA8425_S1_STEREO_MONO 0x00 /* forced mono */
1219#define TDA8425_S1_ML 0x06 /* language selector */
1220#define TDA8425_S1_ML_SOUND_A 0x02 /* sound a */
1221#define TDA8425_S1_ML_SOUND_B 0x04 /* sound b */
1222#define TDA8425_S1_ML_STEREO 0x06 /* stereo */
1223#define TDA8425_S1_IS 0x01 /* channel selector */
1224
1225
1226static int tda8425_shift10(int val) { return (val >> 10) | 0xc0; }
1227static int tda8425_shift12(int val) { return (val >> 12) | 0xf0; }
1228
1da177e4
LT		 1229static void tda8425_setmode(struct CHIPSTATE *chip, int mode)
1230{
1231 int s1 = chip->shadow.bytes[TDA8425_S1+1] & 0xe1;
1232
dc3d75da 1233 if (mode & V4L2_TUNER_MODE_LANG1) {
1da177e4
LT		 1234 s1 |= TDA8425_S1_ML_SOUND_A;
1235 s1 |= TDA8425_S1_STEREO_PSEUDO;
1236
dc3d75da 1237 } else if (mode & V4L2_TUNER_MODE_LANG2) {
1da177e4
LT		 1238 s1 |= TDA8425_S1_ML_SOUND_B;
1239 s1 |= TDA8425_S1_STEREO_PSEUDO;
1240
1241 } else {
1242 s1 |= TDA8425_S1_ML_STEREO;
1243
dc3d75da 1244 if (mode & V4L2_TUNER_MODE_MONO)
1da177e4 1245 s1 |= TDA8425_S1_STEREO_MONO;
dc3d75da 1246 if (mode & V4L2_TUNER_MODE_STEREO)
1da177e4
LT		 1247 s1 |= TDA8425_S1_STEREO_SPATIAL;
1248 }
1249 chip_write(chip,TDA8425_S1,s1);
1250}
1251
1252
1253/* ---------------------------------------------------------------------- */
1254/* audio chip descriptions - defines+functions for pic16c54 (PV951) */
1255
1256/* the registers of 16C54, I2C sub address. */
1257#define PIC16C54_REG_KEY_CODE 0x01 /* Not use. */
1258#define PIC16C54_REG_MISC 0x02
1259
1260/* bit definition of the RESET register, I2C data. */
1261#define PIC16C54_MISC_RESET_REMOTE_CTL 0x01 /* bit 0, Reset to receive the key */
f2421ca3 1262 /* code of remote controller */
1da177e4
LT		 1263#define PIC16C54_MISC_MTS_MAIN 0x02 /* bit 1 */
1264#define PIC16C54_MISC_MTS_SAP 0x04 /* bit 2 */
1265#define PIC16C54_MISC_MTS_BOTH 0x08 /* bit 3 */
1266#define PIC16C54_MISC_SND_MUTE 0x10 /* bit 4, Mute Audio(Line-in and Tuner) */
1267#define PIC16C54_MISC_SND_NOTMUTE 0x20 /* bit 5 */
1268#define PIC16C54_MISC_SWITCH_TUNER 0x40 /* bit 6 , Switch to Line-in */
1269#define PIC16C54_MISC_SWITCH_LINE 0x80 /* bit 7 , Switch to Tuner */
1270
1271/* ---------------------------------------------------------------------- */
1272/* audio chip descriptions - defines+functions for TA8874Z */
1273
18fc59e2 1274/* write 1st byte */
1da177e4
LT		 1275#define TA8874Z_LED_STE 0x80
1276#define TA8874Z_LED_BIL 0x40
1277#define TA8874Z_LED_EXT 0x20
1278#define TA8874Z_MONO_SET 0x10
1279#define TA8874Z_MUTE 0x08
1280#define TA8874Z_F_MONO 0x04
1281#define TA8874Z_MODE_SUB 0x02
1282#define TA8874Z_MODE_MAIN 0x01
1283
18fc59e2
MCC		 1284/* write 2nd byte */
1285/*#define TA8874Z_TI 0x80 */ /* test mode */
1da177e4
LT		 1286#define TA8874Z_SEPARATION 0x3f
1287#define TA8874Z_SEPARATION_DEFAULT 0x10
1288
18fc59e2 1289/* read */
1da177e4
LT		 1290#define TA8874Z_B1 0x80
1291#define TA8874Z_B0 0x40
1292#define TA8874Z_CHAG_FLAG 0x20
1293
18fc59e2
MCC		 1294/*
1295 * B1 B0
1296 * mono L H
1297 * stereo L L
1298 * BIL H L
1299 */
1da177e4
LT		 1300static int ta8874z_getmode(struct CHIPSTATE *chip)
1301{
1302 int val, mode;
1303
1304 val = chip_read(chip);
dc3d75da 1305 mode = V4L2_TUNER_MODE_MONO;
1da177e4 1306 if (val & TA8874Z_B1){
dc3d75da 1307 mode |= V4L2_TUNER_MODE_LANG1 | V4L2_TUNER_MODE_LANG2;
1da177e4 1308 }else if (!(val & TA8874Z_B0)){
dc3d75da 1309 mode |= V4L2_TUNER_MODE_STEREO;
1da177e4 1310 }
08e14054 1311 /* v4l_dbg(1, debug, chip->c, "ta8874z_getmode(): raw chip read: 0x%02x, return: 0x%02x\n", val, mode); */
1da177e4
LT		 1312 return mode;
1313}
1314
1315static audiocmd ta8874z_stereo = { 2, {0, TA8874Z_SEPARATION_DEFAULT}};
1316static audiocmd ta8874z_mono = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}};
1317static audiocmd ta8874z_main = {2, { 0, TA8874Z_SEPARATION_DEFAULT}};
1318static audiocmd ta8874z_sub = {2, { TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
1319
1320static void ta8874z_setmode(struct CHIPSTATE *chip, int mode)
1321{
64f70e7e 1322 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 1323 int update = 1;
1324 audiocmd *t = NULL;
64f70e7e
HV		 1325
1326 v4l2_dbg(1, debug, sd, "ta8874z_setmode(): mode: 0x%02x\n", mode);
1da177e4
LT		 1327
1328 switch(mode){
dc3d75da 1329 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 1330 t = &ta8874z_mono;
1331 break;
dc3d75da 1332 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 1333 t = &ta8874z_stereo;
1334 break;
dc3d75da 1335 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 1336 t = &ta8874z_main;
1337 break;
dc3d75da 1338 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1339 t = &ta8874z_sub;
1340 break;
1341 default:
1342 update = 0;
1343 }
1344
1345 if(update)
1346 chip_cmd(chip, "TA8874Z", t);
1347}
1348
1349static int ta8874z_checkit(struct CHIPSTATE *chip)
1350{
1351 int rc;
1352 rc = chip_read(chip);
1353 return ((rc & 0x1f) == 0x1f) ? 1 : 0;
1354}
1355
1356/* ---------------------------------------------------------------------- */
1357/* audio chip descriptions - struct CHIPDESC */
1358
1359/* insmod options to enable/disable individual audio chips */
52c1da39
AB		 1360static int tda8425 = 1;
1361static int tda9840 = 1;
1362static int tda9850 = 1;
1363static int tda9855 = 1;
1364static int tda9873 = 1;
1365static int tda9874a = 1;
411674fd 1366static int tda9875 = 1;
ff699e6b
DSL		 1367static int tea6300; /* default 0 - address clash with msp34xx */
1368static int tea6320; /* default 0 - address clash with msp34xx */
52c1da39
AB		 1369static int tea6420 = 1;
1370static int pic16c54 = 1;
ff699e6b 1371static int ta8874z; /* default 0 - address clash with tda9840 */
1da177e4
LT		 1372
1373module_param(tda8425, int, 0444);
1374module_param(tda9840, int, 0444);
1375module_param(tda9850, int, 0444);
1376module_param(tda9855, int, 0444);
1377module_param(tda9873, int, 0444);
1378module_param(tda9874a, int, 0444);
411674fd 1379module_param(tda9875, int, 0444);
1da177e4
LT		 1380module_param(tea6300, int, 0444);
1381module_param(tea6320, int, 0444);
1382module_param(tea6420, int, 0444);
1383module_param(pic16c54, int, 0444);
1384module_param(ta8874z, int, 0444);
1385
1386static struct CHIPDESC chiplist[] = {
1387 {
1388 .name = "tda9840",
1da177e4 1389 .insmodopt = &tda9840,
09df1c16
MCC		 1390 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1391 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4 1392 .registers = 5,
dd03e970 1393 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1394
af1a9951 1395 /* callbacks */
94f9e56e 1396 .checkit = tda9840_checkit,
1da177e4
LT		 1397 .getmode = tda9840_getmode,
1398 .setmode = tda9840_setmode,
1da177e4 1399
4ac97914 1400 .init = { 2, { TDA9840_TEST, TDA9840_TEST_INT1SN
1da177e4
LT		 1401 /* ,TDA9840_SW, TDA9840_MONO */} }
1402 },
1403 {
1404 .name = "tda9873h",
1da177e4 1405 .insmodopt = &tda9873,
09df1c16
MCC		 1406 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1407 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4 1408 .registers = 3,
dd03e970 1409 .flags = CHIP_HAS_INPUTSEL | CHIP_NEED_CHECKMODE,
1da177e4 1410
af1a9951
MCC		 1411 /* callbacks */
1412 .checkit = tda9873_checkit,
1da177e4
LT		 1413 .getmode = tda9873_getmode,
1414 .setmode = tda9873_setmode,
1da177e4
LT		 1415
1416 .init = { 4, { TDA9873_SW, 0xa4, 0x06, 0x03 } },
1417 .inputreg = TDA9873_SW,
1418 .inputmute = TDA9873_MUTE | TDA9873_AUTOMUTE,
8bf2f8e7 1419 .inputmap = {0xa0, 0xa2, 0xa0, 0xa0},
1da177e4
LT		 1420 .inputmask = TDA9873_INP_MASK|TDA9873_MUTE|TDA9873_AUTOMUTE,
1421
1422 },
1423 {
1424 .name = "tda9874h/a",
1da177e4 1425 .insmodopt = &tda9874a,
09df1c16
MCC		 1426 .addr_lo = I2C_ADDR_TDA9874 >> 1,
1427 .addr_hi = I2C_ADDR_TDA9874 >> 1,
dd03e970 1428 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1429
af1a9951
MCC		 1430 /* callbacks */
1431 .initialize = tda9874a_initialize,
1432 .checkit = tda9874a_checkit,
1da177e4
LT		 1433 .getmode = tda9874a_getmode,
1434 .setmode = tda9874a_setmode,
1da177e4 1435 },
411674fd
HV		 1436 {
1437 .name = "tda9875",
1438 .insmodopt = &tda9875,
1439 .addr_lo = I2C_ADDR_TDA9875 >> 1,
1440 .addr_hi = I2C_ADDR_TDA9875 >> 1,
1441 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1442
1443 /* callbacks */
1444 .initialize = tda9875_initialize,
1445 .checkit = tda9875_checkit,
1446 .volfunc = tda9875_volume,
1447 .bassfunc = tda9875_bass,
1448 .treblefunc = tda9875_treble,
1449 .leftreg = TDA9875_MVL,
1450 .rightreg = TDA9875_MVR,
1451 .bassreg = TDA9875_MBA,
1452 .treblereg = TDA9875_MTR,
1453 .leftinit = 58880,
1454 .rightinit = 58880,
1455 },
1da177e4
LT		 1456 {
1457 .name = "tda9850",
1da177e4 1458 .insmodopt = &tda9850,
09df1c16
MCC		 1459 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1460 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1461 .registers = 11,
1462
1463 .getmode = tda985x_getmode,
1464 .setmode = tda985x_setmode,
1465
1466 .init = { 8, { TDA9850_C4, 0x08, 0x08, TDA985x_STEREO, 0x07, 0x10, 0x10, 0x03 } }
1467 },
1468 {
1469 .name = "tda9855",
1da177e4 1470 .insmodopt = &tda9855,
09df1c16
MCC		 1471 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1472 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1473 .registers = 11,
1474 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1475
1476 .leftreg = TDA9855_VL,
1477 .rightreg = TDA9855_VR,
1478 .bassreg = TDA9855_BA,
1479 .treblereg = TDA9855_TR,
af1a9951
MCC		 1480
1481 /* callbacks */
1da177e4
LT		 1482 .volfunc = tda9855_volume,
1483 .bassfunc = tda9855_bass,
1484 .treblefunc = tda9855_treble,
1da177e4
LT		 1485 .getmode = tda985x_getmode,
1486 .setmode = tda985x_setmode,
1487
1488 .init = { 12, { 0, 0x6f, 0x6f, 0x0e, 0x07<<1, 0x8<<2,
1489 TDA9855_MUTE | TDA9855_AVL | TDA9855_LOUD | TDA9855_INT,
1490 TDA985x_STEREO | TDA9855_LINEAR | TDA9855_TZCM | TDA9855_VZCM,
1491 0x07, 0x10, 0x10, 0x03 }}
1492 },
1493 {
1494 .name = "tea6300",
1da177e4 1495 .insmodopt = &tea6300,
09df1c16
MCC		 1496 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1497 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1498 .registers = 6,
1499 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1500
1501 .leftreg = TEA6300_VR,
1502 .rightreg = TEA6300_VL,
1503 .bassreg = TEA6300_BA,
1504 .treblereg = TEA6300_TR,
af1a9951
MCC		 1505
1506 /* callbacks */
1da177e4
LT		 1507 .volfunc = tea6300_shift10,
1508 .bassfunc = tea6300_shift12,
1509 .treblefunc = tea6300_shift12,
1510
1511 .inputreg = TEA6300_S,
1512 .inputmap = { TEA6300_S_SA, TEA6300_S_SB, TEA6300_S_SC },
1513 .inputmute = TEA6300_S_GMU,
1514 },
1515 {
1516 .name = "tea6320",
1da177e4 1517 .insmodopt = &tea6320,
09df1c16
MCC		 1518 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1519 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1520 .registers = 8,
1521 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1522
1523 .leftreg = TEA6320_V,
1524 .rightreg = TEA6320_V,
1525 .bassreg = TEA6320_BA,
1526 .treblereg = TEA6320_TR,
af1a9951
MCC		 1527
1528 /* callbacks */
1529 .initialize = tea6320_initialize,
1da177e4
LT		 1530 .volfunc = tea6320_volume,
1531 .bassfunc = tea6320_shift11,
1532 .treblefunc = tea6320_shift11,
1533
1534 .inputreg = TEA6320_S,
1535 .inputmap = { TEA6320_S_SA, TEA6420_S_SB, TEA6300_S_SC, TEA6320_S_SD },
1536 .inputmute = TEA6300_S_GMU,
1537 },
1538 {
1539 .name = "tea6420",
1da177e4 1540 .insmodopt = &tea6420,
09df1c16
MCC		 1541 .addr_lo = I2C_ADDR_TEA6420 >> 1,
1542 .addr_hi = I2C_ADDR_TEA6420 >> 1,
1da177e4
LT		 1543 .registers = 1,
1544 .flags = CHIP_HAS_INPUTSEL,
1545
1546 .inputreg = -1,
1547 .inputmap = { TEA6420_S_SA, TEA6420_S_SB, TEA6420_S_SC },
1548 .inputmute = TEA6300_S_GMU,
1549 },
1550 {
1551 .name = "tda8425",
1da177e4 1552 .insmodopt = &tda8425,
09df1c16
MCC		 1553 .addr_lo = I2C_ADDR_TDA8425 >> 1,
1554 .addr_hi = I2C_ADDR_TDA8425 >> 1,
1da177e4
LT		 1555 .registers = 9,
1556 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1557
1558 .leftreg = TDA8425_VL,
1559 .rightreg = TDA8425_VR,
1560 .bassreg = TDA8425_BA,
1561 .treblereg = TDA8425_TR,
af1a9951
MCC		 1562
1563 /* callbacks */
1da177e4
LT		 1564 .volfunc = tda8425_shift10,
1565 .bassfunc = tda8425_shift12,
1566 .treblefunc = tda8425_shift12,
af1a9951 1567 .setmode = tda8425_setmode,
1da177e4
LT		 1568
1569 .inputreg = TDA8425_S1,
1570 .inputmap = { TDA8425_S1_CH1, TDA8425_S1_CH1, TDA8425_S1_CH1 },
1571 .inputmute = TDA8425_S1_OFF,
1572
1da177e4
LT		 1573 },
1574 {
1575 .name = "pic16c54 (PV951)",
1da177e4 1576 .insmodopt = &pic16c54,
09df1c16
MCC		 1577 .addr_lo = I2C_ADDR_PIC16C54 >> 1,
1578 .addr_hi = I2C_ADDR_PIC16C54>> 1,
1da177e4
LT		 1579 .registers = 2,
1580 .flags = CHIP_HAS_INPUTSEL,
1581
1582 .inputreg = PIC16C54_REG_MISC,
1583 .inputmap = {PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_TUNER,
1584 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
1585 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
8bf2f8e7 1586 PIC16C54_MISC_SND_MUTE},
1da177e4
LT		 1587 .inputmute = PIC16C54_MISC_SND_MUTE,
1588 },
1589 {
1590 .name = "ta8874z",
1da177e4
LT		 1591 .checkit = ta8874z_checkit,
1592 .insmodopt = &ta8874z,
09df1c16
MCC		 1593 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1594 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4 1595 .registers = 2,
dd03e970 1596 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1597
af1a9951 1598 /* callbacks */
1da177e4
LT		 1599 .getmode = ta8874z_getmode,
1600 .setmode = ta8874z_setmode,
1da177e4 1601
4ac97914 1602 .init = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}},
1da177e4
LT		 1603 },
1604 { .name = NULL } /* EOF */
1605};
1606
1607
1608/* ---------------------------------------------------------------------- */
1da177e4 1609
64f70e7e 1610static int tvaudio_g_ctrl(struct v4l2_subdev *sd,
dc3d75da
MCC		 1611 struct v4l2_control *ctrl)
1612{
64f70e7e 1613 struct CHIPSTATE *chip = to_state(sd);
81cb5c4f 1614 struct CHIPDESC *desc = chip->desc;
dc3d75da
MCC		 1615
1616 switch (ctrl->id) {
1617 case V4L2_CID_AUDIO_MUTE:
5fa7b9f3
HV		 1618 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1619 break;
dc3d75da
MCC		 1620 ctrl->value=chip->muted;
1621 return 0;
1622 case V4L2_CID_AUDIO_VOLUME:
18c0ecf1 1623 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1624 break;
1625 ctrl->value = max(chip->left,chip->right);
1626 return 0;
1627 case V4L2_CID_AUDIO_BALANCE:
1628 {
1629 int volume;
18c0ecf1 1630 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1631 break;
1632 volume = max(chip->left,chip->right);
1633 if (volume)
1634 ctrl->value=(32768*min(chip->left,chip->right))/volume;
1635 else
1636 ctrl->value=32768;
1637 return 0;
1638 }
1639 case V4L2_CID_AUDIO_BASS:
01a1a3cc 1640 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
dc3d75da
MCC		 1641 break;
1642 ctrl->value = chip->bass;
1643 return 0;
1644 case V4L2_CID_AUDIO_TREBLE:
01a1a3cc
MCC		 1645 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
1646 break;
dc3d75da
MCC		 1647 ctrl->value = chip->treble;
1648 return 0;
1649 }
1650 return -EINVAL;
1651}
1652
64f70e7e 1653static int tvaudio_s_ctrl(struct v4l2_subdev *sd,
dc3d75da 1654 struct v4l2_control *ctrl)
8bf2f8e7 1655{
64f70e7e 1656 struct CHIPSTATE *chip = to_state(sd);
81cb5c4f 1657 struct CHIPDESC *desc = chip->desc;
8bf2f8e7
HV		 1658
1659 switch (ctrl->id) {
1660 case V4L2_CID_AUDIO_MUTE:
5fa7b9f3
HV		 1661 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1662 break;
1663
8bf2f8e7
HV		 1664 if (ctrl->value < 0 || ctrl->value >= 2)
1665 return -ERANGE;
1666 chip->muted = ctrl->value;
1667 if (chip->muted)
1668 chip_write_masked(chip,desc->inputreg,desc->inputmute,desc->inputmask);
1669 else
1670 chip_write_masked(chip,desc->inputreg,
1671 desc->inputmap[chip->input],desc->inputmask);
dc3d75da
MCC		 1672 return 0;
1673 case V4L2_CID_AUDIO_VOLUME:
1674 {
1675 int volume,balance;
1676
18c0ecf1 1677 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1678 break;
1679
1680 volume = max(chip->left,chip->right);
1681 if (volume)
1682 balance=(32768*min(chip->left,chip->right))/volume;
1683 else
1684 balance=32768;
1685
1686 volume=ctrl->value;
1687 chip->left = (min(65536 - balance,32768) * volume) / 32768;
1688 chip->right = (min(balance,volume *(__u16)32768)) / 32768;
1689
1690 chip_write(chip,desc->leftreg,desc->volfunc(chip->left));
1691 chip_write(chip,desc->rightreg,desc->volfunc(chip->right));
1692
1693 return 0;
8bf2f8e7 1694 }
dc3d75da
MCC		 1695 case V4L2_CID_AUDIO_BALANCE:
1696 {
1697 int volume, balance;
18c0ecf1 1698 if (!(desc->flags & CHIP_HAS_VOLUME))
dc3d75da
MCC		 1699 break;
1700
1701 volume = max(chip->left,chip->right);
1702 balance = ctrl->value;
1703
1704 chip_write(chip,desc->leftreg,desc->volfunc(chip->left));
1705 chip_write(chip,desc->rightreg,desc->volfunc(chip->right));
1706
1707 return 0;
1708 }
1709 case V4L2_CID_AUDIO_BASS:
01a1a3cc 1710 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
dc3d75da
MCC		 1711 break;
1712 chip->bass = ctrl->value;
1713 chip_write(chip,desc->bassreg,desc->bassfunc(chip->bass));
1714
1715 return 0;
1716 case V4L2_CID_AUDIO_TREBLE:
01a1a3cc
MCC		 1717 if (!(desc->flags & CHIP_HAS_BASSTREBLE))
1718 break;
dc3d75da
MCC		 1719 chip->treble = ctrl->value;
1720 chip_write(chip,desc->treblereg,desc->treblefunc(chip->treble));
1721
1722 return 0;
1723 }
1724 return -EINVAL;
8bf2f8e7
HV		 1725}
1726
1727
1da177e4
LT		 1728/* ---------------------------------------------------------------------- */
1729/* video4linux interface */
1730
64f70e7e 1731static int tvaudio_s_radio(struct v4l2_subdev *sd)
1da177e4 1732{
64f70e7e 1733 struct CHIPSTATE *chip = to_state(sd);
1da177e4 1734
64f70e7e
HV		 1735 chip->radio = 1;
1736 chip->watch_stereo = 0;
1737 /* del_timer(&chip->wt); */
1738 return 0;
1739}
1740
1741static int tvaudio_queryctrl(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc)
1742{
1743 struct CHIPSTATE *chip = to_state(sd);
1744 struct CHIPDESC *desc = chip->desc;
1745
1746 switch (qc->id) {
1747 case V4L2_CID_AUDIO_MUTE:
5fa7b9f3
HV		 1748 if (desc->flags & CHIP_HAS_INPUTSEL)
1749 return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0);
1750 break;
64f70e7e 1751 case V4L2_CID_AUDIO_VOLUME:
10afbef1
HV		 1752 if (desc->flags & CHIP_HAS_VOLUME)
1753 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 58880);
1754 break;
64f70e7e 1755 case V4L2_CID_AUDIO_BALANCE:
10afbef1
HV		 1756 if (desc->flags & CHIP_HAS_VOLUME)
1757 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
64f70e7e
HV		 1758 break;
1759 case V4L2_CID_AUDIO_BASS:
1760 case V4L2_CID_AUDIO_TREBLE:
10afbef1
HV		 1761 if (desc->flags & CHIP_HAS_BASSTREBLE)
1762 return v4l2_ctrl_query_fill(qc, 0, 65535, 65535 / 100, 32768);
64f70e7e
HV		 1763 break;
1764 default:
10afbef1 1765 break;
c6241b6c 1766 }
10afbef1 1767 return -EINVAL;
64f70e7e
HV		 1768}
1769
5325b427
HV		 1770static int tvaudio_s_routing(struct v4l2_subdev *sd,
1771 u32 input, u32 output, u32 config)
64f70e7e
HV		 1772{
1773 struct CHIPSTATE *chip = to_state(sd);
1774 struct CHIPDESC *desc = chip->desc;
1da177e4 1775
5fa7b9f3
HV		 1776 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1777 return 0;
5325b427 1778 if (input >= 4)
64f70e7e
HV		 1779 return -EINVAL;
1780 /* There are four inputs: tuner, radio, extern and intern. */
5325b427 1781 chip->input = input;
64f70e7e
HV		 1782 if (chip->muted)
1783 return 0;
1784 chip_write_masked(chip, desc->inputreg,
1785 desc->inputmap[chip->input], desc->inputmask);
1786 return 0;
1787}
1788
1789static int tvaudio_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1790{
1791 struct CHIPSTATE *chip = to_state(sd);
1792 struct CHIPDESC *desc = chip->desc;
1793 int mode = 0;
1794
5fa7b9f3
HV		 1795 if (!desc->setmode)
1796 return 0;
64f70e7e
HV		 1797 if (chip->radio)
1798 return 0;
5fa7b9f3 1799
64f70e7e
HV		 1800 switch (vt->audmode) {
1801 case V4L2_TUNER_MODE_MONO:
1802 case V4L2_TUNER_MODE_STEREO:
1803 case V4L2_TUNER_MODE_LANG1:
1804 case V4L2_TUNER_MODE_LANG2:
1805 mode = vt->audmode;
1806 break;
1807 case V4L2_TUNER_MODE_LANG1_LANG2:
1808 mode = V4L2_TUNER_MODE_STEREO;
1809 break;
1810 default:
1811 return -EINVAL;
1812 }
1813 chip->audmode = vt->audmode;
1814
5fa7b9f3 1815 if (mode) {
1da177e4
LT		 1816 chip->watch_stereo = 0;
1817 /* del_timer(&chip->wt); */
64f70e7e
HV		 1818 chip->mode = mode;
1819 desc->setmode(chip, mode);
1da177e4 1820 }
64f70e7e
HV		 1821 return 0;
1822}
8bf2f8e7 1823
64f70e7e
HV		 1824static int tvaudio_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1825{
1826 struct CHIPSTATE *chip = to_state(sd);
1827 struct CHIPDESC *desc = chip->desc;
1828 int mode = V4L2_TUNER_MODE_MONO;
2474ed44 1829
5fa7b9f3
HV		 1830 if (!desc->getmode)
1831 return 0;
64f70e7e
HV		 1832 if (chip->radio)
1833 return 0;
5fa7b9f3 1834
64f70e7e
HV		 1835 vt->audmode = chip->audmode;
1836 vt->rxsubchans = 0;
1837 vt->capability = V4L2_TUNER_CAP_STEREO |
1838 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
1839
5fa7b9f3 1840 mode = desc->getmode(chip);
64f70e7e
HV		 1841
1842 if (mode & V4L2_TUNER_MODE_MONO)
1843 vt->rxsubchans |= V4L2_TUNER_SUB_MONO;
1844 if (mode & V4L2_TUNER_MODE_STEREO)
1845 vt->rxsubchans |= V4L2_TUNER_SUB_STEREO;
1846 /* Note: for SAP it should be mono/lang2 or stereo/lang2.
1847 When this module is converted fully to v4l2, then this
1848 should change for those chips that can detect SAP. */
1849 if (mode & V4L2_TUNER_MODE_LANG1)
1850 vt->rxsubchans = V4L2_TUNER_SUB_LANG1 |
1851 V4L2_TUNER_SUB_LANG2;
1852 return 0;
1853}
1854
1855static int tvaudio_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1856{
1857 struct CHIPSTATE *chip = to_state(sd);
1858
1859 chip->radio = 0;
1860 return 0;
1861}
1862
1863static int tvaudio_s_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *freq)
1864{
1865 struct CHIPSTATE *chip = to_state(sd);
1866 struct CHIPDESC *desc = chip->desc;
1867
1868 chip->mode = 0; /* automatic */
1869
1870 /* For chips that provide getmode and setmode, and doesn't
1871 automatically follows the stereo carrier, a kthread is
1872 created to set the audio standard. In this case, when then
1873 the video channel is changed, tvaudio starts on MONO mode.
1874 After waiting for 2 seconds, the kernel thread is called,
1875 to follow whatever audio standard is pointed by the
1876 audio carrier.
1877 */
1878 if (chip->thread) {
1879 desc->setmode(chip, V4L2_TUNER_MODE_MONO);
1880 if (chip->prevmode != V4L2_TUNER_MODE_MONO)
1881 chip->prevmode = -1; /* reset previous mode */
1882 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
2474ed44 1883 }
64f70e7e
HV		 1884 return 0;
1885}
2474ed44 1886
aecde8b5 1887static int tvaudio_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
64f70e7e
HV		 1888{
1889 struct i2c_client *client = v4l2_get_subdevdata(sd);
1890
1891 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_TVAUDIO, 0);
1892}
1893
64f70e7e
HV		 1894/* ----------------------------------------------------------------------- */
1895
1896static const struct v4l2_subdev_core_ops tvaudio_core_ops = {
1897 .g_chip_ident = tvaudio_g_chip_ident,
1898 .queryctrl = tvaudio_queryctrl,
1899 .g_ctrl = tvaudio_g_ctrl,
1900 .s_ctrl = tvaudio_s_ctrl,
f41737ec 1901 .s_std = tvaudio_s_std,
64f70e7e
HV		 1902};
1903
1904static const struct v4l2_subdev_tuner_ops tvaudio_tuner_ops = {
1905 .s_radio = tvaudio_s_radio,
1906 .s_frequency = tvaudio_s_frequency,
64f70e7e 1907 .s_tuner = tvaudio_s_tuner,
e6a1a08f 1908 .g_tuner = tvaudio_g_tuner,
64f70e7e
HV		 1909};
1910
1911static const struct v4l2_subdev_audio_ops tvaudio_audio_ops = {
1912 .s_routing = tvaudio_s_routing,
1913};
1914
1915static const struct v4l2_subdev_ops tvaudio_ops = {
1916 .core = &tvaudio_core_ops,
1917 .tuner = &tvaudio_tuner_ops,
1918 .audio = &tvaudio_audio_ops,
1919};
1920
1921/* ----------------------------------------------------------------------- */
1922
1923
1924/* i2c registration */
1925
1926static int tvaudio_probe(struct i2c_client *client, const struct i2c_device_id *id)
1927{
1928 struct CHIPSTATE *chip;
1929 struct CHIPDESC *desc;
1930 struct v4l2_subdev *sd;
1931
1932 if (debug) {
1933 printk(KERN_INFO "tvaudio: TV audio decoder + audio/video mux driver\n");
1934 printk(KERN_INFO "tvaudio: known chips: ");
1935 for (desc = chiplist; desc->name != NULL; desc++)
1936 printk("%s%s", (desc == chiplist) ? "" : ", ", desc->name);
1937 printk("\n");
2474ed44 1938 }
1da177e4 1939
64f70e7e
HV		 1940 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1941 if (!chip)
1942 return -ENOMEM;
1943 sd = &chip->sd;
1944 v4l2_i2c_subdev_init(sd, client, &tvaudio_ops);
8a854284 1945
64f70e7e
HV		 1946 /* find description for the chip */
1947 v4l2_dbg(1, debug, sd, "chip found @ 0x%x\n", client->addr<<1);
1948 for (desc = chiplist; desc->name != NULL; desc++) {
1949 if (0 == *(desc->insmodopt))
1950 continue;
1951 if (client->addr < desc->addr_lo ||
1952 client->addr > desc->addr_hi)
1953 continue;
1954 if (desc->checkit && !desc->checkit(chip))
1955 continue;
1da177e4
LT		 1956 break;
1957 }
64f70e7e
HV		 1958 if (desc->name == NULL) {
1959 v4l2_dbg(1, debug, sd, "no matching chip description found\n");
1960 kfree(chip);
1961 return -EIO;
1962 }
1963 v4l2_info(sd, "%s found @ 0x%x (%s)\n", desc->name, client->addr<<1, client->adapter->name);
1964 if (desc->flags) {
1965 v4l2_dbg(1, debug, sd, "matches:%s%s%s.\n",
1966 (desc->flags & CHIP_HAS_VOLUME) ? " volume" : "",
1967 (desc->flags & CHIP_HAS_BASSTREBLE) ? " bass/treble" : "",
1968 (desc->flags & CHIP_HAS_INPUTSEL) ? " audiomux" : "");
1969 }
8a854284 1970
64f70e7e
HV		 1971 /* fill required data structures */
1972 if (!id)
1973 strlcpy(client->name, desc->name, I2C_NAME_SIZE);
1974 chip->desc = desc;
1975 chip->shadow.count = desc->registers+1;
1976 chip->prevmode = -1;
1977 chip->audmode = V4L2_TUNER_MODE_LANG1;
8a854284 1978
64f70e7e
HV		 1979 /* initialization */
1980 if (desc->initialize != NULL)
1981 desc->initialize(chip);
1982 else
1983 chip_cmd(chip, "init", &desc->init);
8a854284 1984
64f70e7e
HV		 1985 if (desc->flags & CHIP_HAS_VOLUME) {
1986 if (!desc->volfunc) {
1987 /* This shouldn't be happen. Warn user, but keep working
1988 without volume controls
1989 */
1990 v4l2_info(sd, "volume callback undefined!\n");
1991 desc->flags &= ~CHIP_HAS_VOLUME;
1992 } else {
1993 chip->left = desc->leftinit ? desc->leftinit : 65535;
1994 chip->right = desc->rightinit ? desc->rightinit : 65535;
1995 chip_write(chip, desc->leftreg,
1996 desc->volfunc(chip->left));
1997 chip_write(chip, desc->rightreg,
1998 desc->volfunc(chip->right));
1999 }
8a854284 2000 }
64f70e7e
HV		 2001 if (desc->flags & CHIP_HAS_BASSTREBLE) {
2002 if (!desc->bassfunc || !desc->treblefunc) {
2003 /* This shouldn't be happen. Warn user, but keep working
2004 without bass/treble controls
2005 */
2006 v4l2_info(sd, "bass/treble callbacks undefined!\n");
2007 desc->flags &= ~CHIP_HAS_BASSTREBLE;
2008 } else {
2009 chip->treble = desc->trebleinit ?
2010 desc->trebleinit : 32768;
2011 chip->bass = desc->bassinit ?
2012 desc->bassinit : 32768;
2013 chip_write(chip, desc->bassreg,
2014 desc->bassfunc(chip->bass));
2015 chip_write(chip, desc->treblereg,
2016 desc->treblefunc(chip->treble));
1da177e4 2017 }
64f70e7e 2018 }
74cab31c 2019
64f70e7e 2020 chip->thread = NULL;
e4129a9c 2021 init_timer(&chip->wt);
64f70e7e
HV		 2022 if (desc->flags & CHIP_NEED_CHECKMODE) {
2023 if (!desc->getmode || !desc->setmode) {
2024 /* This shouldn't be happen. Warn user, but keep working
2025 without kthread
2026 */
2027 v4l2_info(sd, "set/get mode callbacks undefined!\n");
2028 return 0;
2029 }
2030 /* start async thread */
64f70e7e
HV		 2031 chip->wt.function = chip_thread_wake;
2032 chip->wt.data = (unsigned long)chip;
2033 chip->thread = kthread_run(chip_thread, chip, client->name);
2034 if (IS_ERR(chip->thread)) {
2035 v4l2_warn(sd, "failed to create kthread\n");
2036 chip->thread = NULL;
2037 }
1da177e4
LT		 2038 }
2039 return 0;
2040}
2041
64f70e7e
HV		 2042static int tvaudio_remove(struct i2c_client *client)
2043{
2044 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2045 struct CHIPSTATE *chip = to_state(sd);
2046
2047 del_timer_sync(&chip->wt);
2048 if (chip->thread) {
2049 /* shutdown async thread */
2050 kthread_stop(chip->thread);
2051 chip->thread = NULL;
2052 }
2053
2054 v4l2_device_unregister_subdev(sd);
2055 kfree(chip);
2056 return 0;
2057}
2058
ae429083
JD		 2059/* This driver supports many devices and the idea is to let the driver
2060 detect which device is present. So rather than listing all supported
2061 devices here, we pretend to support a single, fake device type. */
64f70e7e 2062static const struct i2c_device_id tvaudio_id[] = {
ae429083
JD		 2063 { "tvaudio", 0 },
2064 { }
2065};
64f70e7e 2066MODULE_DEVICE_TABLE(i2c, tvaudio_id);
ae429083 2067
7a004d13
HV		 2068static struct i2c_driver tvaudio_driver = {
2069 .driver = {
2070 .owner = THIS_MODULE,
2071 .name = "tvaudio",
2072 },
2073 .probe = tvaudio_probe,
2074 .remove = tvaudio_remove,
2075 .id_table = tvaudio_id,
08e14054 2076};
7a004d13
HV		 2077
2078static __init int init_tvaudio(void)
2079{
2080 return i2c_add_driver(&tvaudio_driver);
2081}
2082
2083static __exit void exit_tvaudio(void)
2084{
2085 i2c_del_driver(&tvaudio_driver);
2086}
2087
2088module_init(init_tvaudio);
2089module_exit(exit_tvaudio);
Clone of davem's net-next-2.6 tree