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Merge branch 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[net-next-2.6.git] / drivers / media / video / saa7115.c
CommitLineData
89f75ffc
MCC		 1/* saa711x - Philips SAA711x video decoder driver
2 * This driver can work with saa7111, saa7111a, saa7113, saa7114,
3 * saa7115 and saa7118.
e19b2fcc
HV		 4 *
5 * Based on saa7114 driver by Maxim Yevtyushkin, which is based on
6 * the saa7111 driver by Dave Perks.
7 *
8 * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
9 * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com>
10 *
11 * Slight changes for video timing and attachment output by
12 * Wolfgang Scherr <scherr@net4you.net>
13 *
14 * Moved over to the linux >= 2.4.x i2c protocol (1/1/2003)
15 * by Ronald Bultje <rbultje@ronald.bitfreak.net>
16 *
17 * Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com>
18 * (2/17/2003)
19 *
20 * VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl>
89f75ffc
MCC		 21 *
22 * Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
23 * SAA7111, SAA7113 and SAA7118 support
e19b2fcc
HV		 24 *
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
29 *
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
34 *
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
38 */
39
96ecfc4e 40#include "saa711x_regs.h"
e19b2fcc
HV		 41
42#include <linux/kernel.h>
43#include <linux/module.h>
44#include <linux/slab.h>
45#include <linux/i2c.h>
46#include <linux/videodev2.h>
9415f4b2 47#include <media/v4l2-device.h>
3434eb7e 48#include <media/v4l2-chip-ident.h>
ef6078e9 49#include <media/v4l2-i2c-drv.h>
1f8f5fa9 50#include <media/saa7115.h>
3578d3dd 51#include <asm/div64.h>
e19b2fcc 52
97d9e80e 53#define VRES_60HZ (480+16)
d9dce96f 54
89f75ffc 55MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver");
f5762e44
MCC		 56MODULE_AUTHOR( "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, "
57 "Hans Verkuil, Mauro Carvalho Chehab");
e19b2fcc
HV		 58MODULE_LICENSE("GPL");
59
ff699e6b 60static int debug;
fac9e899 61module_param(debug, bool, 0644);
e19b2fcc
HV		 62
63MODULE_PARM_DESC(debug, "Debug level (0-1)");
64
e19b2fcc 65
66ec1193 66struct saa711x_state {
9415f4b2 67 struct v4l2_subdev sd;
e19b2fcc
HV		 68 v4l2_std_id std;
69 int input;
4cbca185 70 int output;
e19b2fcc 71 int enable;
3faeeae4 72 int radio;
e19b2fcc
HV		 73 int bright;
74 int contrast;
75 int hue;
76 int sat;
87a6fe4a 77 int chroma_agc;
d9dce96f
MCC		 78 int width;
79 int height;
3434eb7e 80 u32 ident;
3578d3dd 81 u32 audclk_freq;
b7f8292c
HV		 82 u32 crystal_freq;
83 u8 ucgc;
84 u8 cgcdiv;
85 u8 apll;
e19b2fcc
HV		 86};
87
9415f4b2
HV		 88static inline struct saa711x_state *to_state(struct v4l2_subdev *sd)
89{
90 return container_of(sd, struct saa711x_state, sd);
91}
92
e19b2fcc
HV		 93/* ----------------------------------------------------------------------- */
94
9415f4b2 95static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value)
e19b2fcc 96{
9415f4b2
HV		 97 struct i2c_client *client = v4l2_get_subdevdata(sd);
98
e19b2fcc
HV		 99 return i2c_smbus_write_byte_data(client, reg, value);
100}
101
89f75ffc
MCC		 102/* Sanity routine to check if a register is present */
103static int saa711x_has_reg(const int id, const u8 reg)
104{
d9dce96f
MCC		 105 if (id == V4L2_IDENT_SAA7111)
106 return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
107 (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e;
340dde81
HV		 108 if (id == V4L2_IDENT_SAA7111A)
109 return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
110 reg != 0x14 && reg != 0x18 && reg != 0x19 &&
111 reg != 0x1d && reg != 0x1e;
d9dce96f
MCC		 112
113 /* common for saa7113/4/5/8 */
114 if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f ||
115 reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) ||
116 reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) ||
117 reg == 0x82 || (reg >= 0x89 && reg <= 0x8e)))
118 return 0;
119
89f75ffc 120 switch (id) {
89f75ffc 121 case V4L2_IDENT_SAA7113:
d9dce96f
MCC		 122 return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) &&
123 reg != 0x5d && reg < 0x63;
89f75ffc 124 case V4L2_IDENT_SAA7114:
d9dce96f
MCC		 125 return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) &&
126 (reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 &&
127 reg != 0x81 && reg < 0xf0;
89f75ffc 128 case V4L2_IDENT_SAA7115:
d9dce96f 129 return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe);
89f75ffc 130 case V4L2_IDENT_SAA7118:
d9dce96f
MCC		 131 return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) &&
132 (reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 &&
133 (reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0;
89f75ffc 134 }
89f75ffc
MCC		 135 return 1;
136}
137
9415f4b2 138static int saa711x_writeregs(struct v4l2_subdev *sd, const unsigned char *regs)
e19b2fcc 139{
9415f4b2 140 struct saa711x_state *state = to_state(sd);
e19b2fcc
HV		 141 unsigned char reg, data;
142
143 while (*regs != 0x00) {
144 reg = *(regs++);
145 data = *(regs++);
89f75ffc
MCC		 146
147 /* According with datasheets, reserved regs should be
148 filled with 0 - seems better not to touch on they */
9415f4b2
HV		 149 if (saa711x_has_reg(state->ident, reg)) {
150 if (saa711x_write(sd, reg, data) < 0)
89f75ffc 151 return -1;
d87edf26 152 } else {
9415f4b2 153 v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x\n", reg);
89f75ffc 154 }
e19b2fcc
HV		 155 }
156 return 0;
157}
158
9415f4b2 159static inline int saa711x_read(struct v4l2_subdev *sd, u8 reg)
e19b2fcc 160{
9415f4b2
HV		 161 struct i2c_client *client = v4l2_get_subdevdata(sd);
162
e19b2fcc
HV		 163 return i2c_smbus_read_byte_data(client, reg);
164}
165
166/* ----------------------------------------------------------------------- */
167
89f75ffc 168/* SAA7111 initialization table */
183d896a 169static const unsigned char saa7111_init[] = {
89f75ffc
MCC		 170 R_01_INC_DELAY, 0x00, /* reserved */
171
172 /*front end */
173 R_02_INPUT_CNTL_1, 0xd0, /* FUSE=3, GUDL=2, MODE=0 */
174 R_03_INPUT_CNTL_2, 0x23, /* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0,
175 * GAFIX=0, GAI1=256, GAI2=256 */
176 R_04_INPUT_CNTL_3, 0x00, /* GAI1=256 */
177 R_05_INPUT_CNTL_4, 0x00, /* GAI2=256 */
178
179 /* decoder */
180 R_06_H_SYNC_START, 0xf3, /* HSB at 13(50Hz) / 17(60Hz)
181 * pixels after end of last line */
182 R_07_H_SYNC_STOP, 0xe8, /* HSS seems to be needed to
183 * work with NTSC, too */
184 R_08_SYNC_CNTL, 0xc8, /* AUFD=1, FSEL=1, EXFIL=0,
185 * VTRC=1, HPLL=0, VNOI=0 */
186 R_09_LUMA_CNTL, 0x01, /* BYPS=0, PREF=0, BPSS=0,
187 * VBLB=0, UPTCV=0, APER=1 */
188 R_0A_LUMA_BRIGHT_CNTL, 0x80,
189 R_0B_LUMA_CONTRAST_CNTL, 0x47, /* 0b - CONT=1.109 */
190 R_0C_CHROMA_SAT_CNTL, 0x40,
191 R_0D_CHROMA_HUE_CNTL, 0x00,
192 R_0E_CHROMA_CNTL_1, 0x01, /* 0e - CDTO=0, CSTD=0, DCCF=0,
193 * FCTC=0, CHBW=1 */
194 R_0F_CHROMA_GAIN_CNTL, 0x00, /* reserved */
195 R_10_CHROMA_CNTL_2, 0x48, /* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */
196 R_11_MODE_DELAY_CNTL, 0x1c, /* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1,
197 * OEYC=1, OEHV=1, VIPB=0, COLO=0 */
198 R_12_RT_SIGNAL_CNTL, 0x00, /* 12 - output control 2 */
199 R_13_RT_X_PORT_OUT_CNTL, 0x00, /* 13 - output control 3 */
200 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
201 R_15_VGATE_START_FID_CHG, 0x00,
202 R_16_VGATE_STOP, 0x00,
203 R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
204
205 0x00, 0x00
206};
207
208/* SAA7113 init codes */
183d896a 209static const unsigned char saa7113_init[] = {
89f75ffc
MCC		 210 R_01_INC_DELAY, 0x08,
211 R_02_INPUT_CNTL_1, 0xc2,
212 R_03_INPUT_CNTL_2, 0x30,
213 R_04_INPUT_CNTL_3, 0x00,
214 R_05_INPUT_CNTL_4, 0x00,
215 R_06_H_SYNC_START, 0x89,
216 R_07_H_SYNC_STOP, 0x0d,
217 R_08_SYNC_CNTL, 0x88,
218 R_09_LUMA_CNTL, 0x01,
219 R_0A_LUMA_BRIGHT_CNTL, 0x80,
220 R_0B_LUMA_CONTRAST_CNTL, 0x47,
221 R_0C_CHROMA_SAT_CNTL, 0x40,
222 R_0D_CHROMA_HUE_CNTL, 0x00,
223 R_0E_CHROMA_CNTL_1, 0x01,
224 R_0F_CHROMA_GAIN_CNTL, 0x2a,
225 R_10_CHROMA_CNTL_2, 0x08,
226 R_11_MODE_DELAY_CNTL, 0x0c,
227 R_12_RT_SIGNAL_CNTL, 0x07,
228 R_13_RT_X_PORT_OUT_CNTL, 0x00,
229 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
230 R_15_VGATE_START_FID_CHG, 0x00,
231 R_16_VGATE_STOP, 0x00,
232 R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
233
234 0x00, 0x00
235};
236
e19b2fcc
HV		 237/* If a value differs from the Hauppauge driver values, then the comment starts with
238 'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the
239 Hauppauge driver sets. */
240
89f75ffc 241/* SAA7114 and SAA7115 initialization table */
e19b2fcc 242static const unsigned char saa7115_init_auto_input[] = {
f5762e44 243 /* Front-End Part */
96ecfc4e
MCC		 244 R_01_INC_DELAY, 0x48, /* white peak control disabled */
245 R_03_INPUT_CNTL_2, 0x20, /* was 0x30. 0x20: long vertical blanking */
246 R_04_INPUT_CNTL_3, 0x90, /* analog gain set to 0 */
247 R_05_INPUT_CNTL_4, 0x90, /* analog gain set to 0 */
f5762e44 248 /* Decoder Part */
96ecfc4e
MCC		 249 R_06_H_SYNC_START, 0xeb, /* horiz sync begin = -21 */
250 R_07_H_SYNC_STOP, 0xe0, /* horiz sync stop = -17 */
183d896a 251 R_09_LUMA_CNTL, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */
96ecfc4e
MCC		 252 R_0A_LUMA_BRIGHT_CNTL, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */
253 R_0B_LUMA_CONTRAST_CNTL, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */
254 R_0C_CHROMA_SAT_CNTL, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */
255 R_0D_CHROMA_HUE_CNTL, 0x00,
256 R_0F_CHROMA_GAIN_CNTL, 0x00, /* use automatic gain */
257 R_10_CHROMA_CNTL_2, 0x06, /* chroma: active adaptive combfilter */
258 R_11_MODE_DELAY_CNTL, 0x00,
259 R_12_RT_SIGNAL_CNTL, 0x9d, /* RTS0 output control: VGATE */
260 R_13_RT_X_PORT_OUT_CNTL, 0x80, /* ITU656 standard mode, RTCO output enable RTCE */
261 R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
262 R_18_RAW_DATA_GAIN_CNTL, 0x40, /* gain 0x00 = nominal */
263 R_19_RAW_DATA_OFF_CNTL, 0x80,
264 R_1A_COLOR_KILL_LVL_CNTL, 0x77, /* recommended value */
265 R_1B_MISC_TVVCRDET, 0x42, /* recommended value */
266 R_1C_ENHAN_COMB_CTRL1, 0xa9, /* recommended value */
267 R_1D_ENHAN_COMB_CTRL2, 0x01, /* recommended value */
f5762e44 268
d9dce96f
MCC		 269
270 R_80_GLOBAL_CNTL_1, 0x0, /* No tasks enabled at init */
271
f5762e44 272 /* Power Device Control */
96ecfc4e
MCC		 273 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset device */
274 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* set device programmed, all in operational mode */
e19b2fcc
HV		 275 0x00, 0x00
276};
277
89f75ffc 278/* Used to reset saa7113, saa7114 and saa7115 */
e19b2fcc 279static const unsigned char saa7115_cfg_reset_scaler[] = {
96ecfc4e
MCC		 280 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00, /* disable I-port output */
281 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
282 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
283 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* enable I-port output */
e19b2fcc
HV		 284 0x00, 0x00
285};
286
287/* ============== SAA7715 VIDEO templates ============= */
288
e19b2fcc 289static const unsigned char saa7115_cfg_60hz_video[] = {
96ecfc4e
MCC		 290 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
291 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
e19b2fcc 292
96ecfc4e
MCC		 293 R_15_VGATE_START_FID_CHG, 0x03,
294 R_16_VGATE_STOP, 0x11,
295 R_17_MISC_VGATE_CONF_AND_MSB, 0x9c,
e19b2fcc 296
96ecfc4e
MCC		 297 R_08_SYNC_CNTL, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */
298 R_0E_CHROMA_CNTL_1, 0x07, /* video autodetection is on */
e19b2fcc 299
96ecfc4e 300 R_5A_V_OFF_FOR_SLICER, 0x06, /* standard 60hz value for ITU656 line counting */
e19b2fcc
HV		 301
302 /* Task A */
96ecfc4e
MCC		 303 R_90_A_TASK_HANDLING_CNTL, 0x80,
304 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
305 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
306 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
307
308 /* hoffset low (input), 0x0002 is minimum */
309 R_94_A_HORIZ_INPUT_WINDOW_START, 0x01,
310 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
311
312 /* hsize low (input), 0x02d0 = 720 */
313 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
314 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
315
316 R_98_A_VERT_INPUT_WINDOW_START, 0x05,
317 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
318
319 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
320 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
321
322 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
323 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,
324
325 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
326 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
e19b2fcc
HV		 327
328 /* Task B */
96ecfc4e
MCC		 329 R_C0_B_TASK_HANDLING_CNTL, 0x00,
330 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
331 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
332 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
333
334 /* 0x0002 is minimum */
335 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02,
336 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
337
338 /* 0x02d0 = 720 */
339 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
340 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
341
342 /* vwindow start 0x12 = 18 */
343 R_C8_B_VERT_INPUT_WINDOW_START, 0x12,
344 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
345
346 /* vwindow length 0xf8 = 248 */
97d9e80e
MCC		 347 R_CA_B_VERT_INPUT_WINDOW_LENGTH, VRES_60HZ>>1,
348 R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, VRES_60HZ>>9,
96ecfc4e
MCC		 349
350 /* hwindow 0x02d0 = 720 */
351 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
352 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
353
354 R_F0_LFCO_PER_LINE, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
355 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0 */
356 R_F5_PULSGEN_LINE_LENGTH, 0xad,
357 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
358
e19b2fcc
HV		 359 0x00, 0x00
360};
361
e19b2fcc 362static const unsigned char saa7115_cfg_50hz_video[] = {
96ecfc4e
MCC		 363 R_80_GLOBAL_CNTL_1, 0x00,
364 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
e19b2fcc 365
96ecfc4e
MCC		 366 R_15_VGATE_START_FID_CHG, 0x37, /* VGATE start */
367 R_16_VGATE_STOP, 0x16,
368 R_17_MISC_VGATE_CONF_AND_MSB, 0x99,
e19b2fcc 369
96ecfc4e
MCC		 370 R_08_SYNC_CNTL, 0x28, /* 0x28 = PAL */
371 R_0E_CHROMA_CNTL_1, 0x07,
e19b2fcc 372
96ecfc4e 373 R_5A_V_OFF_FOR_SLICER, 0x03, /* standard 50hz value */
e19b2fcc
HV		 374
375 /* Task A */
96ecfc4e
MCC		 376 R_90_A_TASK_HANDLING_CNTL, 0x81,
377 R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
378 R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
379 R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
380
e19b2fcc
HV		 381 /* This is weird: the datasheet says that you should use 2 as the minimum value, */
382 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
96ecfc4e
MCC		 383 /* hoffset low (input), 0x0002 is minimum */
384 R_94_A_HORIZ_INPUT_WINDOW_START, 0x00,
385 R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
386
387 /* hsize low (input), 0x02d0 = 720 */
388 R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
389 R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
390
391 R_98_A_VERT_INPUT_WINDOW_START, 0x03,
392 R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
393
394 /* vsize 0x12 = 18 */
395 R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12,
396 R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
397
398 /* hsize 0x05a0 = 1440 */
399 R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
400 R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05, /* hsize hi (output) */
401 R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12, /* vsize low (output), 0x12 = 18 */
402 R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00, /* vsize hi (output) */
e19b2fcc
HV		 403
404 /* Task B */
96ecfc4e
MCC		 405 R_C0_B_TASK_HANDLING_CNTL, 0x00,
406 R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
407 R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
408 R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
409
410 /* This is weird: the datasheet says that you should use 2 as the minimum value, */
411 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
412 /* hoffset low (input), 0x0002 is minimum. See comment above. */
413 R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00,
414 R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
415
416 /* hsize 0x02d0 = 720 */
417 R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
418 R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
419
420 /* voffset 0x16 = 22 */
421 R_C8_B_VERT_INPUT_WINDOW_START, 0x16,
422 R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
423
424 /* vsize 0x0120 = 288 */
425 R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20,
426 R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,
427
428 /* hsize 0x02d0 = 720 */
429 R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
430 R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
431
96ecfc4e
MCC		 432 R_F0_LFCO_PER_LINE, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
433 R_F1_P_I_PARAM_SELECT, 0x05, /* low bit with 0xF0, (was 0x05) */
434 R_F5_PULSGEN_LINE_LENGTH, 0xb0,
435 R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
436
e19b2fcc
HV		 437 0x00, 0x00
438};
439
440/* ============== SAA7715 VIDEO templates (end) ======= */
441
442static const unsigned char saa7115_cfg_vbi_on[] = {
96ecfc4e
MCC		 443 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
444 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
445 R_80_GLOBAL_CNTL_1, 0x30, /* Activate both tasks */
446 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
447 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
448
e19b2fcc
HV		 449 0x00, 0x00
450};
451
452static const unsigned char saa7115_cfg_vbi_off[] = {
96ecfc4e
MCC		 453 R_80_GLOBAL_CNTL_1, 0x00, /* reset tasks */
454 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0, /* reset scaler */
455 R_80_GLOBAL_CNTL_1, 0x20, /* Activate only task "B" */
456 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0, /* activate scaler */
457 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01, /* Enable I-port output */
458
e19b2fcc
HV		 459 0x00, 0x00
460};
461
f5762e44 462
e19b2fcc 463static const unsigned char saa7115_init_misc[] = {
96ecfc4e 464 R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
96ecfc4e
MCC		 465 R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01,
466 R_84_I_PORT_SIGNAL_DEF, 0x20,
467 R_85_I_PORT_SIGNAL_POLAR, 0x21,
468 R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5,
469 R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,
e19b2fcc
HV		 470
471 /* Task A */
96ecfc4e
MCC		 472 R_A0_A_HORIZ_PRESCALING, 0x01,
473 R_A1_A_ACCUMULATION_LENGTH, 0x00,
474 R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
475
476 /* Configure controls at nominal value*/
477 R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80,
478 R_A5_A_LUMA_CONTRAST_CNTL, 0x40,
479 R_A6_A_CHROMA_SATURATION_CNTL, 0x40,
480
481 /* note: 2 x zoom ensures that VBI lines have same length as video lines. */
482 R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00,
483 R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,
484
485 R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00,
486
487 /* must be horiz lum scaling / 2 */
488 R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00,
489 R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,
490
491 /* must be offset luma / 2 */
492 R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00,
493
494 R_B0_A_VERT_LUMA_SCALING_INC, 0x00,
495 R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04,
496
497 R_B2_A_VERT_CHROMA_SCALING_INC, 0x00,
498 R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04,
499
500 R_B4_A_VERT_SCALING_MODE_CNTL, 0x01,
501
502 R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00,
503 R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00,
504 R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00,
505 R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00,
506
507 R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00,
508 R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00,
509 R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00,
510 R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00,
e19b2fcc
HV		 511
512 /* Task B */
96ecfc4e
MCC		 513 R_D0_B_HORIZ_PRESCALING, 0x01,
514 R_D1_B_ACCUMULATION_LENGTH, 0x00,
515 R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
516
517 /* Configure controls at nominal value*/
518 R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80,
519 R_D5_B_LUMA_CONTRAST_CNTL, 0x40,
520 R_D6_B_CHROMA_SATURATION_CNTL, 0x40,
521
522 /* hor lum scaling 0x0400 = 1 */
523 R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
524 R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
525
526 R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00,
527
528 /* must be hor lum scaling / 2 */
529 R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
530 R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
531
532 /* must be offset luma / 2 */
533 R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,
534
535 R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
536 R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
537
538 R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
539 R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
540
541 R_E4_B_VERT_SCALING_MODE_CNTL, 0x01,
542
543 R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00,
544 R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00,
545 R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00,
546 R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00,
547
548 R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00,
549 R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00,
550 R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00,
551 R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00,
552
553 R_F2_NOMINAL_PLL2_DTO, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */
554 R_F3_PLL_INCREMENT, 0x46,
555 R_F4_PLL2_STATUS, 0x00,
556 R_F7_PULSE_A_POS_MSB, 0x4b, /* not the recommended settings! */
557 R_F8_PULSE_B_POS, 0x00,
558 R_F9_PULSE_B_POS_MSB, 0x4b,
559 R_FA_PULSE_C_POS, 0x00,
560 R_FB_PULSE_C_POS_MSB, 0x4b,
561
562 /* PLL2 lock detection settings: 71 lines 50% phase error */
563 R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
e19b2fcc
HV		 564
565 /* Turn off VBI */
96ecfc4e
MCC		 566 R_40_SLICER_CNTL_1, 0x20, /* No framing code errors allowed. */
567 R_41_LCR_BASE, 0xff,
568 R_41_LCR_BASE+1, 0xff,
569 R_41_LCR_BASE+2, 0xff,
570 R_41_LCR_BASE+3, 0xff,
571 R_41_LCR_BASE+4, 0xff,
572 R_41_LCR_BASE+5, 0xff,
573 R_41_LCR_BASE+6, 0xff,
574 R_41_LCR_BASE+7, 0xff,
575 R_41_LCR_BASE+8, 0xff,
576 R_41_LCR_BASE+9, 0xff,
577 R_41_LCR_BASE+10, 0xff,
578 R_41_LCR_BASE+11, 0xff,
579 R_41_LCR_BASE+12, 0xff,
580 R_41_LCR_BASE+13, 0xff,
581 R_41_LCR_BASE+14, 0xff,
582 R_41_LCR_BASE+15, 0xff,
583 R_41_LCR_BASE+16, 0xff,
584 R_41_LCR_BASE+17, 0xff,
585 R_41_LCR_BASE+18, 0xff,
586 R_41_LCR_BASE+19, 0xff,
587 R_41_LCR_BASE+20, 0xff,
588 R_41_LCR_BASE+21, 0xff,
589 R_41_LCR_BASE+22, 0xff,
590 R_58_PROGRAM_FRAMING_CODE, 0x40,
591 R_59_H_OFF_FOR_SLICER, 0x47,
592 R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83,
593 R_5D_DID, 0xbd,
594 R_5E_SDID, 0x35,
595
fea551fa 596 R_02_INPUT_CNTL_1, 0xc4, /* input tuner -> input 4, amplifier active */
96ecfc4e
MCC		 597
598 R_80_GLOBAL_CNTL_1, 0x20, /* enable task B */
599 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,
600 R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,
e19b2fcc
HV		 601 0x00, 0x00
602};
603
66ec1193 604static int saa711x_odd_parity(u8 c)
e19b2fcc
HV		 605{
606 c ^= (c >> 4);
607 c ^= (c >> 2);
608 c ^= (c >> 1);
609
610 return c & 1;
611}
612
9415f4b2 613static int saa711x_decode_vps(u8 *dst, u8 *p)
e19b2fcc
HV		 614{
615 static const u8 biphase_tbl[] = {
616 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
617 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
618 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
619 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
620 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
621 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
622 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
623 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
624 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
625 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
626 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
627 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
628 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
629 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
630 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
631 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
632 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
633 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
634 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
635 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
636 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
637 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
638 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
639 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
640 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
641 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
642 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
643 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
644 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
645 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
646 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
647 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
648 };
649 int i;
650 u8 c, err = 0;
651
652 for (i = 0; i < 2 * 13; i += 2) {
653 err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
654 c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4);
655 dst[i / 2] = c;
656 }
657 return err & 0xf0;
658}
659
9415f4b2 660static int saa711x_decode_wss(u8 *p)
e19b2fcc
HV		 661{
662 static const int wss_bits[8] = {
663 0, 0, 0, 1, 0, 1, 1, 1
664 };
665 unsigned char parity;
666 int wss = 0;
667 int i;
668
669 for (i = 0; i < 16; i++) {
670 int b1 = wss_bits[p[i] & 7];
671 int b2 = wss_bits[(p[i] >> 3) & 7];
672
673 if (b1 == b2)
674 return -1;
675 wss |= b2 << i;
676 }
677 parity = wss & 15;
678 parity ^= parity >> 2;
679 parity ^= parity >> 1;
680
681 if (!(parity & 1))
682 return -1;
683
684 return wss;
685}
686
9415f4b2 687static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
e19b2fcc 688{
9415f4b2 689 struct saa711x_state *state = to_state(sd);
3578d3dd
HV		 690 u32 acpf;
691 u32 acni;
692 u32 hz;
693 u64 f;
b7f8292c 694 u8 acc = 0; /* reg 0x3a, audio clock control */
e19b2fcc 695
89f75ffc 696 /* Checks for chips that don't have audio clock (saa7111, saa7113) */
9415f4b2 697 if (!saa711x_has_reg(state->ident, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD))
89f75ffc
MCC		 698 return 0;
699
9415f4b2 700 v4l2_dbg(1, debug, sd, "set audio clock freq: %d\n", freq);
3578d3dd
HV		 701
702 /* sanity check */
703 if (freq < 32000 || freq > 48000)
704 return -EINVAL;
705
706 /* hz is the refresh rate times 100 */
707 hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000;
708 /* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */
709 acpf = (25600 * freq) / hz;
710 /* acni = (256 * freq * 2^23) / crystal_frequency =
711 (freq * 2^(8+23)) / crystal_frequency =
b7f8292c 712 (freq << 31) / crystal_frequency */
3578d3dd
HV		 713 f = freq;
714 f = f << 31;
b7f8292c 715 do_div(f, state->crystal_freq);
3578d3dd 716 acni = f;
b7f8292c
HV		 717 if (state->ucgc) {
718 acpf = acpf * state->cgcdiv / 16;
719 acni = acni * state->cgcdiv / 16;
720 acc = 0x80;
721 if (state->cgcdiv == 3)
722 acc |= 0x40;
723 }
724 if (state->apll)
725 acc |= 0x08;
3578d3dd 726
9415f4b2
HV		 727 saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
728 saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10);
729 saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
96ecfc4e 730
9415f4b2
HV		 731 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
732 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
96ecfc4e 733 (acpf >> 8) & 0xff);
9415f4b2 734 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
96ecfc4e
MCC		 735 (acpf >> 16) & 0x03);
736
9415f4b2
HV		 737 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
738 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
739 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
e19b2fcc
HV		 740 state->audclk_freq = freq;
741 return 0;
742}
743
9415f4b2 744static int saa711x_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
e19b2fcc 745{
9415f4b2 746 struct saa711x_state *state = to_state(sd);
87a6fe4a 747 u8 val;
e19b2fcc
HV		 748
749 switch (ctrl->id) {
750 case V4L2_CID_BRIGHTNESS:
751 if (ctrl->value < 0 || ctrl->value > 255) {
9415f4b2 752 v4l2_err(sd, "invalid brightness setting %d\n", ctrl->value);
e19b2fcc
HV		 753 return -ERANGE;
754 }
755
756 state->bright = ctrl->value;
9415f4b2 757 saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, state->bright);
e19b2fcc
HV		 758 break;
759
760 case V4L2_CID_CONTRAST:
761 if (ctrl->value < 0 || ctrl->value > 127) {
9415f4b2 762 v4l2_err(sd, "invalid contrast setting %d\n", ctrl->value);
e19b2fcc
HV		 763 return -ERANGE;
764 }
765
766 state->contrast = ctrl->value;
9415f4b2 767 saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, state->contrast);
e19b2fcc
HV		 768 break;
769
770 case V4L2_CID_SATURATION:
771 if (ctrl->value < 0 || ctrl->value > 127) {
9415f4b2 772 v4l2_err(sd, "invalid saturation setting %d\n", ctrl->value);
e19b2fcc
HV		 773 return -ERANGE;
774 }
775
776 state->sat = ctrl->value;
9415f4b2 777 saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, state->sat);
e19b2fcc
HV		 778 break;
779
780 case V4L2_CID_HUE:
de6476f5 781 if (ctrl->value < -128 || ctrl->value > 127) {
9415f4b2 782 v4l2_err(sd, "invalid hue setting %d\n", ctrl->value);
e19b2fcc
HV		 783 return -ERANGE;
784 }
785
786 state->hue = ctrl->value;
9415f4b2 787 saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, state->hue);
e19b2fcc 788 break;
87a6fe4a
DH		 789 case V4L2_CID_CHROMA_AGC:
790 val = saa711x_read(sd, R_0F_CHROMA_GAIN_CNTL);
791 state->chroma_agc = ctrl->value;
792 if (ctrl->value)
793 val &= 0x7f;
794 else
795 val |= 0x80;
796 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, val);
797 break;
798 case V4L2_CID_CHROMA_GAIN:
799 /* Chroma gain cannot be set when AGC is enabled */
800 if (state->chroma_agc == 1)
801 return -EINVAL;
802 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, ctrl->value | 0x80);
803 break;
3faeeae4
HV		 804 default:
805 return -EINVAL;
e19b2fcc
HV		 806 }
807
808 return 0;
809}
810
9415f4b2 811static int saa711x_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl)
e19b2fcc 812{
9415f4b2 813 struct saa711x_state *state = to_state(sd);
e19b2fcc
HV		 814
815 switch (ctrl->id) {
816 case V4L2_CID_BRIGHTNESS:
817 ctrl->value = state->bright;
818 break;
819 case V4L2_CID_CONTRAST:
820 ctrl->value = state->contrast;
821 break;
822 case V4L2_CID_SATURATION:
823 ctrl->value = state->sat;
824 break;
825 case V4L2_CID_HUE:
826 ctrl->value = state->hue;
827 break;
87a6fe4a
DH		 828 case V4L2_CID_CHROMA_AGC:
829 ctrl->value = state->chroma_agc;
830 break;
831 case V4L2_CID_CHROMA_GAIN:
832 ctrl->value = saa711x_read(sd, R_0F_CHROMA_GAIN_CNTL) & 0x7f;
833 break;
e19b2fcc
HV		 834 default:
835 return -EINVAL;
836 }
837
838 return 0;
839}
840
9415f4b2 841static int saa711x_set_size(struct v4l2_subdev *sd, int width, int height)
d9dce96f 842{
9415f4b2 843 struct saa711x_state *state = to_state(sd);
d9dce96f
MCC		 844 int HPSC, HFSC;
845 int VSCY;
846 int res;
847 int is_50hz = state->std & V4L2_STD_625_50;
848 int Vsrc = is_50hz ? 576 : 480;
849
9415f4b2 850 v4l2_dbg(1, debug, sd, "decoder set size to %ix%i\n", width, height);
d9dce96f
MCC		 851
852 /* FIXME need better bounds checking here */
853 if ((width < 1) || (width > 1440))
854 return -EINVAL;
855 if ((height < 1) || (height > Vsrc))
856 return -EINVAL;
857
9415f4b2 858 if (!saa711x_has_reg(state->ident, R_D0_B_HORIZ_PRESCALING)) {
d9dce96f
MCC		 859 /* Decoder only supports 720 columns and 480 or 576 lines */
860 if (width != 720)
861 return -EINVAL;
862 if (height != Vsrc)
863 return -EINVAL;
864 }
865
866 state->width = width;
867 state->height = height;
868
869 if (!saa711x_has_reg(state->ident, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH))
870 return 0;
871
872 /* probably have a valid size, let's set it */
873 /* Set output width/height */
874 /* width */
875
9415f4b2 876 saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
d9dce96f 877 (u8) (width & 0xff));
9415f4b2 878 saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
d9dce96f
MCC		 879 (u8) ((width >> 8) & 0xff));
880
881 /* Vertical Scaling uses height/2 */
9415f4b2 882 res = height / 2;
d9dce96f
MCC		 883
884 /* On 60Hz, it is using a higher Vertical Output Size */
885 if (!is_50hz)
d0d30c03 886 res += (VRES_60HZ - 480) >> 1;
d9dce96f
MCC		 887
888 /* height */
9415f4b2 889 saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
d9dce96f 890 (u8) (res & 0xff));
9415f4b2 891 saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
d9dce96f
MCC		 892 (u8) ((res >> 8) & 0xff));
893
894 /* Scaling settings */
895 /* Hprescaler is floor(inres/outres) */
896 HPSC = (int)(720 / width);
897 /* 0 is not allowed (div. by zero) */
898 HPSC = HPSC ? HPSC : 1;
899 HFSC = (int)((1024 * 720) / (HPSC * width));
900 /* FIXME hardcodes to "Task B"
901 * write H prescaler integer */
9415f4b2 902 saa711x_write(sd, R_D0_B_HORIZ_PRESCALING,
d9dce96f
MCC		 903 (u8) (HPSC & 0x3f));
904
9415f4b2 905 v4l2_dbg(1, debug, sd, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
d9dce96f 906 /* write H fine-scaling (luminance) */
9415f4b2 907 saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC,
d9dce96f 908 (u8) (HFSC & 0xff));
9415f4b2 909 saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
d9dce96f
MCC		 910 (u8) ((HFSC >> 8) & 0xff));
911 /* write H fine-scaling (chrominance)
912 * must be lum/2, so i'll just bitshift :) */
9415f4b2 913 saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING,
d9dce96f 914 (u8) ((HFSC >> 1) & 0xff));
9415f4b2 915 saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
d9dce96f
MCC		 916 (u8) ((HFSC >> 9) & 0xff));
917
918 VSCY = (int)((1024 * Vsrc) / height);
9415f4b2 919 v4l2_dbg(1, debug, sd, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
d9dce96f
MCC		 920
921 /* Correct Contrast and Luminance */
9415f4b2 922 saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL,
d9dce96f 923 (u8) (64 * 1024 / VSCY));
9415f4b2 924 saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL,
d9dce96f
MCC		 925 (u8) (64 * 1024 / VSCY));
926
927 /* write V fine-scaling (luminance) */
9415f4b2 928 saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC,
d9dce96f 929 (u8) (VSCY & 0xff));
9415f4b2 930 saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
d9dce96f
MCC		 931 (u8) ((VSCY >> 8) & 0xff));
932 /* write V fine-scaling (chrominance) */
9415f4b2 933 saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC,
d9dce96f 934 (u8) (VSCY & 0xff));
9415f4b2 935 saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
d9dce96f
MCC		 936 (u8) ((VSCY >> 8) & 0xff));
937
9415f4b2 938 saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
d9dce96f
MCC		 939
940 /* Activates task "B" */
9415f4b2
HV		 941 saa711x_write(sd, R_80_GLOBAL_CNTL_1,
942 saa711x_read(sd, R_80_GLOBAL_CNTL_1) | 0x20);
d9dce96f
MCC		 943
944 return 0;
945}
946
9415f4b2 947static void saa711x_set_v4lstd(struct v4l2_subdev *sd, v4l2_std_id std)
e19b2fcc 948{
9415f4b2 949 struct saa711x_state *state = to_state(sd);
e19b2fcc 950
30b54d50
HV		 951 /* Prevent unnecessary standard changes. During a standard
952 change the I-Port is temporarily disabled. Any devices
953 reading from that port can get confused.
bccfa449
HV		 954 Note that s_std is also used to switch from
955 radio to TV mode, so if a s_std is broadcast to
30b54d50
HV		 956 all I2C devices then you do not want to have an unwanted
957 side-effect here. */
958 if (std == state->std)
959 return;
960
d9dce96f
MCC		 961 state->std = std;
962
e19b2fcc
HV		 963 // This works for NTSC-M, SECAM-L and the 50Hz PAL variants.
964 if (std & V4L2_STD_525_60) {
9415f4b2
HV		 965 v4l2_dbg(1, debug, sd, "decoder set standard 60 Hz\n");
966 saa711x_writeregs(sd, saa7115_cfg_60hz_video);
967 saa711x_set_size(sd, 720, 480);
e19b2fcc 968 } else {
9415f4b2
HV		 969 v4l2_dbg(1, debug, sd, "decoder set standard 50 Hz\n");
970 saa711x_writeregs(sd, saa7115_cfg_50hz_video);
971 saa711x_set_size(sd, 720, 576);
e19b2fcc
HV		 972 }
973
f89982a9 974 /* Register 0E - Bits D6-D4 on NO-AUTO mode
89f75ffc 975 (SAA7111 and SAA7113 doesn't have auto mode)
f89982a9
MCC		 976 50 Hz / 625 lines 60 Hz / 525 lines
977 000 PAL BGDHI (4.43Mhz) NTSC M (3.58MHz)
978 001 NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz)
979 010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz)
980 011 NTSC N (3.58MHz) PAL M (3.58MHz)
981 100 reserved NTSC-Japan (3.58MHz)
982 */
340dde81 983 if (state->ident <= V4L2_IDENT_SAA7113) {
9415f4b2 984 u8 reg = saa711x_read(sd, R_0E_CHROMA_CNTL_1) & 0x8f;
f89982a9 985
02c17224 986 if (std == V4L2_STD_PAL_M) {
01342358 987 reg |= 0x30;
e0028027 988 } else if (std == V4L2_STD_PAL_Nc) {
01342358 989 reg |= 0x20;
02c17224 990 } else if (std == V4L2_STD_PAL_60) {
01342358 991 reg |= 0x10;
02c17224 992 } else if (std == V4L2_STD_NTSC_M_JP) {
01342358 993 reg |= 0x40;
a9aaec4e 994 } else if (std & V4L2_STD_SECAM) {