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V4L/DVB (3709): Improve line-in handling
[net-next-2.6.git] / drivers / media / video / saa7115.c
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f5762e44 1/* saa7115 - Philips SAA7113/SAA7114/SAA7115 video decoder driver
e19b2fcc
HV		 2 *
3 * Based on saa7114 driver by Maxim Yevtyushkin, which is based on
4 * the saa7111 driver by Dave Perks.
5 *
6 * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
7 * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com>
8 *
9 * Slight changes for video timing and attachment output by
10 * Wolfgang Scherr <scherr@net4you.net>
11 *
12 * Moved over to the linux >= 2.4.x i2c protocol (1/1/2003)
13 * by Ronald Bultje <rbultje@ronald.bitfreak.net>
14 *
15 * Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com>
16 * (2/17/2003)
17 *
18 * VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl>
f5762e44 19 * SAA7113 support by Mauro Carvalho Chehab <mchehab@infradead.org>
e19b2fcc
HV		 20 *
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License
23 * as published by the Free Software Foundation; either version 2
24 * of the License, or (at your option) any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
34 */
35
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/i2c.h>
41#include <linux/videodev2.h>
e19b2fcc 42#include <media/v4l2-common.h>
1f8f5fa9 43#include <media/saa7115.h>
3578d3dd 44#include <asm/div64.h>
e19b2fcc 45
f5762e44
MCC		 46MODULE_DESCRIPTION("Philips SAA7113/SAA7114/SAA7115 video decoder driver");
47MODULE_AUTHOR( "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, "
48 "Hans Verkuil, Mauro Carvalho Chehab");
e19b2fcc
HV		 49MODULE_LICENSE("GPL");
50
51static int debug = 0;
fac9e899 52module_param(debug, bool, 0644);
e19b2fcc
HV		 53
54MODULE_PARM_DESC(debug, "Debug level (0-1)");
55
f5762e44 56static unsigned short normal_i2c[] = {
01342358 57 0x4a >> 1, 0x48 >> 1, /* SAA7113 */
f5762e44
MCC		 58 0x42 >> 1, 0x40 >> 1, /* SAA7114 and SAA7115 */
59 I2C_CLIENT_END };
e19b2fcc
HV		 60
61
62I2C_CLIENT_INSMOD;
63
64struct saa7115_state {
65 v4l2_std_id std;
66 int input;
67 int enable;
3faeeae4 68 int radio;
e19b2fcc
HV		 69 int bright;
70 int contrast;
71 int hue;
72 int sat;
73 enum v4l2_chip_ident ident;
3578d3dd 74 u32 audclk_freq;
e19b2fcc
HV		 75};
76
77/* ----------------------------------------------------------------------- */
78
79static inline int saa7115_write(struct i2c_client *client, u8 reg, u8 value)
80{
81 return i2c_smbus_write_byte_data(client, reg, value);
82}
83
84static int saa7115_writeregs(struct i2c_client *client, const unsigned char *regs)
85{
86 unsigned char reg, data;
87
88 while (*regs != 0x00) {
89 reg = *(regs++);
90 data = *(regs++);
91 if (saa7115_write(client, reg, data) < 0)
92 return -1;
93 }
94 return 0;
95}
96
97static inline int saa7115_read(struct i2c_client *client, u8 reg)
98{
99 return i2c_smbus_read_byte_data(client, reg);
100}
101
102/* ----------------------------------------------------------------------- */
103
104/* If a value differs from the Hauppauge driver values, then the comment starts with
105 'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the
106 Hauppauge driver sets. */
107
108static const unsigned char saa7115_init_auto_input[] = {
f5762e44 109 /* Front-End Part */
e19b2fcc
HV		 110 0x01, 0x48, /* white peak control disabled */
111 0x03, 0x20, /* was 0x30. 0x20: long vertical blanking */
112 0x04, 0x90, /* analog gain set to 0 */
113 0x05, 0x90, /* analog gain set to 0 */
f5762e44 114 /* Decoder Part */
e19b2fcc
HV		 115 0x06, 0xeb, /* horiz sync begin = -21 */
116 0x07, 0xe0, /* horiz sync stop = -17 */
117 0x0a, 0x80, /* was 0x88. decoder brightness, 0x80 is itu standard */
118 0x0b, 0x44, /* was 0x48. decoder contrast, 0x44 is itu standard */
119 0x0c, 0x40, /* was 0x47. decoder saturation, 0x40 is itu standard */
120 0x0d, 0x00, /* chrominance hue control */
121 0x0f, 0x00, /* chrominance gain control: use automicatic mode */
122 0x10, 0x06, /* chrominance/luminance control: active adaptive combfilter */
123 0x11, 0x00, /* delay control */
124 0x12, 0x9d, /* RTS0 output control: VGATE */
125 0x13, 0x80, /* X-port output control: ITU656 standard mode, RTCO output enable RTCE */
126 0x14, 0x00, /* analog/ADC/auto compatibility control */
127 0x18, 0x40, /* raw data gain 0x00 = nominal */
128 0x19, 0x80, /* raw data offset 0x80 = 0 LSB */
129 0x1a, 0x77, /* color killer level control 0x77 = recommended */
130 0x1b, 0x42, /* misc chroma control 0x42 = recommended */
131 0x1c, 0xa9, /* combfilter control 0xA9 = recommended */
132 0x1d, 0x01, /* combfilter control 0x01 = recommended */
f5762e44
MCC		 133
134 /* Power Device Control */
e19b2fcc
HV		 135 0x88, 0xd0, /* reset device */
136 0x88, 0xf0, /* set device programmed, all in operational mode */
137 0x00, 0x00
138};
139
140static const unsigned char saa7115_cfg_reset_scaler[] = {
141 0x87, 0x00, /* disable I-port output */
142 0x88, 0xd0, /* reset scaler */
143 0x88, 0xf0, /* activate scaler */
144 0x87, 0x01, /* enable I-port output */
145 0x00, 0x00
146};
147
148/* ============== SAA7715 VIDEO templates ============= */
149
150static const unsigned char saa7115_cfg_60hz_fullres_x[] = {
151 0xcc, 0xd0, /* hsize low (output), hor. output window size = 0x2d0 = 720 */
152 0xcd, 0x02, /* hsize hi (output) */
153
154 /* Why not in 60hz-Land, too? */
155 0xd0, 0x01, /* downscale = 1 */
156 0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */
157 0xd9, 0x04,
158 0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */
159 0xdd, 0x02, /* H-scaling incr chroma */
160
161 0x00, 0x00
162};
163static const unsigned char saa7115_cfg_60hz_fullres_y[] = {
164 0xce, 0xf8, /* vsize low (output), ver. output window size = 248 (but 60hz is 240?) */
165 0xcf, 0x00, /* vsize hi (output) */
166
167 /* Why not in 60hz-Land, too? */
168 0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */
169 0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */
170
171 0xe0, 0x00, /* V-scaling incr luma low */
172 0xe1, 0x04, /* " hi */
173 0xe2, 0x00, /* V-scaling incr chroma low */
174 0xe3, 0x04, /* " hi */
175
176 0x00, 0x00
177};
178
179static const unsigned char saa7115_cfg_60hz_video[] = {
180 0x80, 0x00, /* reset tasks */
181 0x88, 0xd0, /* reset scaler */
182
183 0x15, 0x03, /* VGATE pulse start */
184 0x16, 0x11, /* VGATE pulse stop */
185 0x17, 0x9c, /* VGATE MSB and other values */
186
187 0x08, 0x68, /* 0xBO: auto detection, 0x68 = NTSC */
188 0x0e, 0x07, /* lots of different stuff... video autodetection is on */
189
190 0x5a, 0x06, /* Vertical offset, standard 60hz value for ITU656 line counting */
191
192 /* Task A */
193 0x90, 0x80, /* Task Handling Control */
194 0x91, 0x48, /* X-port formats/config */
195 0x92, 0x40, /* Input Ref. signal Def. */
196 0x93, 0x84, /* I-port config */
197 0x94, 0x01, /* hoffset low (input), 0x0002 is minimum */
198 0x95, 0x00, /* hoffset hi (input) */
199 0x96, 0xd0, /* hsize low (input), 0x02d0 = 720 */
200 0x97, 0x02, /* hsize hi (input) */
201 0x98, 0x05, /* voffset low (input) */
202 0x99, 0x00, /* voffset hi (input) */
203 0x9a, 0x0c, /* vsize low (input), 0x0c = 12 */
204 0x9b, 0x00, /* vsize hi (input) */
205 0x9c, 0xa0, /* hsize low (output), 0x05a0 = 1440 */
206 0x9d, 0x05, /* hsize hi (output) */
207 0x9e, 0x0c, /* vsize low (output), 0x0c = 12 */
208 0x9f, 0x00, /* vsize hi (output) */
209
210 /* Task B */
211 0xc0, 0x00, /* Task Handling Control */
212 0xc1, 0x08, /* X-port formats/config */
213 0xc2, 0x00, /* Input Ref. signal Def. */
214 0xc3, 0x80, /* I-port config */
215 0xc4, 0x02, /* hoffset low (input), 0x0002 is minimum */
216 0xc5, 0x00, /* hoffset hi (input) */
217 0xc6, 0xd0, /* hsize low (input), 0x02d0 = 720 */
218 0xc7, 0x02, /* hsize hi (input) */
219 0xc8, 0x12, /* voffset low (input), 0x12 = 18 */
220 0xc9, 0x00, /* voffset hi (input) */
221 0xca, 0xf8, /* vsize low (input), 0xf8 = 248 */
222 0xcb, 0x00, /* vsize hi (input) */
223 0xcc, 0xd0, /* hsize low (output), 0x02d0 = 720 */
224 0xcd, 0x02, /* hsize hi (output) */
225
226 0xf0, 0xad, /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
227 0xf1, 0x05, /* low bit with 0xF0 */
228 0xf5, 0xad, /* Set pulse generator register */
229 0xf6, 0x01,
230
231 0x87, 0x00, /* Disable I-port output */
232 0x88, 0xd0, /* reset scaler */
233 0x80, 0x20, /* Activate only task "B", continuous mode (was 0xA0) */
234 0x88, 0xf0, /* activate scaler */
235 0x87, 0x01, /* Enable I-port output */
236 0x00, 0x00
237};
238
239static const unsigned char saa7115_cfg_50hz_fullres_x[] = {
240 0xcc, 0xd0, /* hsize low (output), 720 same as 60hz */
241 0xcd, 0x02, /* hsize hi (output) */
242
243 0xd0, 0x01, /* down scale = 1 */
244 0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */
245 0xd9, 0x04,
246 0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */
247 0xdd, 0x02, /* H-scaling incr chroma */
248
249 0x00, 0x00
250};
251static const unsigned char saa7115_cfg_50hz_fullres_y[] = {
252 0xce, 0x20, /* vsize low (output), 0x0120 = 288 */
253 0xcf, 0x01, /* vsize hi (output) */
254
255 0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */
256 0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */
257
258 0xe0, 0x00, /* V-scaling incr luma low */
259 0xe1, 0x04, /* " hi */
260 0xe2, 0x00, /* V-scaling incr chroma low */
261 0xe3, 0x04, /* " hi */
262
263 0x00, 0x00
264};
265
266static const unsigned char saa7115_cfg_50hz_video[] = {
267 0x80, 0x00, /* reset tasks */
268 0x88, 0xd0, /* reset scaler */
269
270 0x15, 0x37, /* VGATE start */
271 0x16, 0x16, /* VGATE stop */
272 0x17, 0x99, /* VGATE MSB and other values */
273
274 0x08, 0x28, /* 0x28 = PAL */
275 0x0e, 0x07, /* chrominance control 1 */
276
277 0x5a, 0x03, /* Vertical offset, standard 50hz value */
278
279 /* Task A */
280 0x90, 0x81, /* Task Handling Control */
281 0x91, 0x48, /* X-port formats/config */
282 0x92, 0x40, /* Input Ref. signal Def. */
283 0x93, 0x84, /* I-port config */
284 /* This is weird: the datasheet says that you should use 2 as the minimum value, */
285 /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
286 0x94, 0x00, /* hoffset low (input), 0x0002 is minimum */
287 0x95, 0x00, /* hoffset hi (input) */
288 0x96, 0xd0, /* hsize low (input), 0x02d0 = 720 */
289 0x97, 0x02, /* hsize hi (input) */
290 0x98, 0x03, /* voffset low (input) */
291 0x99, 0x00, /* voffset hi (input) */
292 0x9a, 0x12, /* vsize low (input), 0x12 = 18 */
293 0x9b, 0x00, /* vsize hi (input) */
294 0x9c, 0xa0, /* hsize low (output), 0x05a0 = 1440 */
295 0x9d, 0x05, /* hsize hi (output) */
296 0x9e, 0x12, /* vsize low (output), 0x12 = 18 */
297 0x9f, 0x00, /* vsize hi (output) */
298
299 /* Task B */
300 0xc0, 0x00, /* Task Handling Control */
301 0xc1, 0x08, /* X-port formats/config */
302 0xc2, 0x00, /* Input Ref. signal Def. */
303 0xc3, 0x80, /* I-port config */
304 0xc4, 0x00, /* hoffset low (input), 0x0002 is minimum. See comment at 0x94 above. */
305 0xc5, 0x00, /* hoffset hi (input) */
306 0xc6, 0xd0, /* hsize low (input), 0x02d0 = 720 */
307 0xc7, 0x02, /* hsize hi (input) */
308 0xc8, 0x16, /* voffset low (input), 0x16 = 22 */
309 0xc9, 0x00, /* voffset hi (input) */
310 0xca, 0x20, /* vsize low (input), 0x0120 = 288 */
311 0xcb, 0x01, /* vsize hi (input) */
312 0xcc, 0xd0, /* hsize low (output), 0x02d0 = 720 */
313 0xcd, 0x02, /* hsize hi (output) */
314 0xce, 0x20, /* vsize low (output), 0x0120 = 288 */
315 0xcf, 0x01, /* vsize hi (output) */
316
317 0xf0, 0xb0, /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
318 0xf1, 0x05, /* low bit with 0xF0, (was 0x05) */
319 0xf5, 0xb0, /* Set pulse generator register */
320 0xf6, 0x01,
321
322 0x87, 0x00, /* Disable I-port output */
323 0x88, 0xd0, /* reset scaler (was 0xD0) */
324 0x80, 0x20, /* Activate only task "B" */
325 0x88, 0xf0, /* activate scaler */
326 0x87, 0x01, /* Enable I-port output */
327 0x00, 0x00
328};
329
330/* ============== SAA7715 VIDEO templates (end) ======= */
331
332static const unsigned char saa7115_cfg_vbi_on[] = {
333 0x80, 0x00, /* reset tasks */
334 0x88, 0xd0, /* reset scaler */
335 0x80, 0x30, /* Activate both tasks */
336 0x88, 0xf0, /* activate scaler */
337 0x87, 0x01, /* Enable I-port output */
338 0x00, 0x00
339};
340
341static const unsigned char saa7115_cfg_vbi_off[] = {
342 0x80, 0x00, /* reset tasks */
343 0x88, 0xd0, /* reset scaler */
344 0x80, 0x20, /* Activate only task "B" */
345 0x88, 0xf0, /* activate scaler */
346 0x87, 0x01, /* Enable I-port output */
347 0x00, 0x00
348};
349
f5762e44
MCC		 350static const unsigned char saa7113_init_auto_input[] = {
351 0x01, 0x08, /* PH7113_INCREMENT_DELAY - (1) (1) (1) (1) IDEL3 IDEL2 IDELL1 IDEL0 */
352 0x02, 0xc2, /* PH7113_ANALOG_INPUT_CONTR_1 - FUSE1 FUSE0 GUDL1 GUDL0 MODE3 MODE2 MODE1 MODE0 */
353 0x03, 0x30, /* PH7113_ANALOG_INPUT_CONTR_2 - (1) HLNRS VBSL WPOFF HOLDG GAFIX GAI28 GAI18 */
354 0x04, 0x00, /* PH7113_ANALOG_INPUT_CONTR_3 - GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 */
355 0x05, 0x00, /* PH7113_ANALOG_INPUT_CONTR_4 - GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20 */
356 0x06, 0x89, /* PH7113_HORIZONTAL_SYNC_START - HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 */
357 0x07, 0x0d, /* PH7113_HORIZONTAL_SYNC_STOP - HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 */
358 0x08, 0x88, /* PH7113_SYNC_CONTROL - AUFD FSEL FOET HTC1 HTC0 HPLL VNOI1 VNOI0 */
359 0x09, 0x01, /* PH7113_LUMINANCE_CONTROL - BYPS PREF BPSS1 BPSS0 VBLB UPTCV APER1 APER0 */
360 0x0a, 0x80, /* PH7113_LUMINANCE_BRIGHTNESS - BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 */
361 0x0b, 0x47, /* PH7113_LUMINANCE_CONTRAST - CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 */
362 0x0c, 0x40, /* PH7113_CHROMA_SATURATION - SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 */
363 0x0d, 0x00, /* PH7113_CHROMA_HUE_CONTROL - HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 */
364 0x0e, 0x01, /* PH7113_CHROMA_CONTROL - CDTO CSTD2 CSTD1 CSTD0 DCCF FCTC CHBW1 CHBW0 */
365 0x0f, 0x2a, /* PH7113_CHROMA_GAIN_CONTROL - ACGC CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0 */
366 0x10, 0x08, /* PH7113_FORMAT_DELAY_CONTROL - OFTS1 OFTS0 HDEL1 HDEL0 VRLN YDEL2 YDEL1 YDEL0 */
367 0x11, 0x0c, /* PH7113_OUTPUT_CONTROL_1 - GPSW1 CM99 GPSW0 HLSEL OEYC OERT VIPB COLO */
368 0x12, 0x07, /* PH7113_OUTPUT_CONTROL_2 - RTSE13 RTSE12 RTSE11 RTSE10 RTSE03 RTSE02 RTSE01 RTSE00 */
369 0x13, 0x00, /* PH7113_OUTPUT_CONTROL_3 - ADLSB (1) (1) OLDSB FIDP (1) AOSL1 AOSL0 */
370 0x14, 0x00, /* RESERVED 14 - (1) (1) (1) (1) (1) (1) (1) (1) */
371 0x15, 0x00, /* PH7113_V_GATE1_START - VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 */
372 0x16, 0x00, /* PH7113_V_GATE1_STOP - VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0 */
373 0x17, 0x00, /* PH7113_V_GATE1_MSB - (1) (1) (1) (1) (1) (1) VSTO8 VSTA8 */
374 0x00, 0x00
375};
376
e19b2fcc
HV		 377static const unsigned char saa7115_init_misc[] = {
378 0x38, 0x03, /* audio stuff */
379 0x39, 0x10,
380 0x3a, 0x08,
381
382 0x81, 0x01, /* reg 0x15,0x16 define blanking window */
383 0x82, 0x00,
384 0x83, 0x01, /* I port settings */
385 0x84, 0x20,
386 0x85, 0x21,
387 0x86, 0xc5,
388 0x87, 0x01,
389
390 /* Task A */
391 0xa0, 0x01, /* down scale = 1 */
392 0xa1, 0x00, /* prescale accumulation length = 1 */
393 0xa2, 0x00, /* dc gain and fir prefilter control */
394 0xa4, 0x80, /* Lum Brightness, nominal value = 0x80 */
395 0xa5, 0x40, /* Lum contrast, nominal value = 0x40 */
396 0xa6, 0x40, /* Chroma satur. nominal value = 0x80 */
397 0xa8, 0x00, /* hor lum scaling 0x0200 = 2 zoom */
398 0xa9, 0x02, /* note: 2 x zoom ensures that VBI lines have same length as video lines. */
399 0xaa, 0x00, /* H-phase offset Luma = 0 */
400 0xac, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */
401 0xad, 0x01, /* H-scaling incr chroma */
402 0xae, 0x00, /* H-phase offset chroma. must be offset luma / 2 */
403
404 0xb0, 0x00, /* V-scaling incr luma low */
405 0xb1, 0x04, /* " hi */
406 0xb2, 0x00, /* V-scaling incr chroma low */
407 0xb3, 0x04, /* " hi */
408 0xb4, 0x01, /* V-scaling mode control */
409 0xb8, 0x00, /* V-phase offset chroma 00 */
410 0xb9, 0x00, /* V-phase offset chroma 01 */
411 0xba, 0x00, /* V-phase offset chroma 10 */
412 0xbb, 0x00, /* V-phase offset chroma 11 */
413 0xbc, 0x00, /* V-phase offset luma 00 */
414 0xbd, 0x00, /* V-phase offset luma 01 */
415 0xbe, 0x00, /* V-phase offset luma 10 */
416 0xbf, 0x00, /* V-phase offset luma 11 */
417
418 /* Task B */
419 0xd0, 0x01, /* down scale = 1 */
420 0xd1, 0x00, /* prescale accumulation length = 1 */
421 0xd2, 0x00, /* dc gain and fir prefilter control */
422 0xd4, 0x80, /* Lum Brightness, nominal value = 0x80 */
423 0xd5, 0x40, /* Lum contrast, nominal value = 0x40 */
424 0xd6, 0x40, /* Chroma satur. nominal value = 0x80 */
425 0xd8, 0x00, /* hor lum scaling 0x0400 = 1 */
426 0xd9, 0x04,
427 0xda, 0x00, /* H-phase offset Luma = 0 */
428 0xdc, 0x00, /* hor chrom scaling 0x0200. must be hor lum scaling / 2 */
429 0xdd, 0x02, /* H-scaling incr chroma */
430 0xde, 0x00, /* H-phase offset chroma. must be offset luma / 2 */
431
432 0xe0, 0x00, /* V-scaling incr luma low */
433 0xe1, 0x04, /* " hi */
434 0xe2, 0x00, /* V-scaling incr chroma low */
435 0xe3, 0x04, /* " hi */
436 0xe4, 0x01, /* V-scaling mode control */
437 0xe8, 0x00, /* V-phase offset chroma 00 */
438 0xe9, 0x00, /* V-phase offset chroma 01 */
439 0xea, 0x00, /* V-phase offset chroma 10 */
440 0xeb, 0x00, /* V-phase offset chroma 11 */
441 0xec, 0x00, /* V-phase offset luma 00 */
442 0xed, 0x00, /* V-phase offset luma 01 */
443 0xee, 0x00, /* V-phase offset luma 10 */
444 0xef, 0x00, /* V-phase offset luma 11 */
445
446 0xf2, 0x50, /* crystal clock = 24.576 MHz, target = 27MHz */
447 0xf3, 0x46,
448 0xf4, 0x00,
449 0xf7, 0x4b, /* not the recommended settings! */
450 0xf8, 0x00,
451 0xf9, 0x4b,
452 0xfa, 0x00,
453 0xfb, 0x4b,
454 0xff, 0x88, /* PLL2 lock detection settings: 71 lines 50% phase error */
455
456 /* Turn off VBI */
457 0x40, 0x20, /* No framing code errors allowed. */
458 0x41, 0xff,
459 0x42, 0xff,
460 0x43, 0xff,
461 0x44, 0xff,
462 0x45, 0xff,
463 0x46, 0xff,
464 0x47, 0xff,
465 0x48, 0xff,
466 0x49, 0xff,
467 0x4a, 0xff,
468 0x4b, 0xff,
469 0x4c, 0xff,
470 0x4d, 0xff,
471 0x4e, 0xff,
472 0x4f, 0xff,
473 0x50, 0xff,
474 0x51, 0xff,
475 0x52, 0xff,
476 0x53, 0xff,
477 0x54, 0xff,
478 0x55, 0xff,
479 0x56, 0xff,
480 0x57, 0xff,
481 0x58, 0x40,
482 0x59, 0x47,
483 0x5b, 0x83,
484 0x5d, 0xbd,
485 0x5e, 0x35,
486
487 0x02, 0x84, /* input tuner -> input 4, amplifier active */
488 0x09, 0x53, /* 0x53, was 0x56 for 60hz. luminance control */
489
490 0x80, 0x20, /* enable task B */
491 0x88, 0xd0,
492 0x88, 0xf0,
493 0x00, 0x00
494};
495
e19b2fcc
HV		 496static int saa7115_odd_parity(u8 c)
497{
498 c ^= (c >> 4);
499 c ^= (c >> 2);
500 c ^= (c >> 1);
501
502 return c & 1;
503}
504
505static int saa7115_decode_vps(u8 * dst, u8 * p)
506{
507 static const u8 biphase_tbl[] = {
508 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
509 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
510 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
511 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
512 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
513 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
514 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
515 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
516 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
517 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
518 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
519 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
520 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
521 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
522 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
523 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
524 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
525 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
526 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
527 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
528 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
529 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
530 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
531 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
532 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
533 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
534 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
535 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
536 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
537 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
538 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
539 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
540 };
541 int i;
542 u8 c, err = 0;
543
544 for (i = 0; i < 2 * 13; i += 2) {
545 err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
546 c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4);
547 dst[i / 2] = c;
548 }
549 return err & 0xf0;
550}
551
552static int saa7115_decode_wss(u8 * p)
553{
554 static const int wss_bits[8] = {
555 0, 0, 0, 1, 0, 1, 1, 1
556 };
557 unsigned char parity;
558 int wss = 0;
559 int i;
560
561 for (i = 0; i < 16; i++) {
562 int b1 = wss_bits[p[i] & 7];
563 int b2 = wss_bits[(p[i] >> 3) & 7];
564
565 if (b1 == b2)
566 return -1;
567 wss |= b2 << i;
568 }
569 parity = wss & 15;
570 parity ^= parity >> 2;
571 parity ^= parity >> 1;
572
573 if (!(parity & 1))
574 return -1;
575
576 return wss;
577}
578
579
3578d3dd 580static int saa7115_set_audio_clock_freq(struct i2c_client *client, u32 freq)
e19b2fcc
HV		 581{
582 struct saa7115_state *state = i2c_get_clientdata(client);
3578d3dd
HV		 583 u32 acpf;
584 u32 acni;
585 u32 hz;
586 u64 f;
e19b2fcc 587
f167cb4e 588 v4l_dbg(1, debug, client, "set audio clock freq: %d\n", freq);
3578d3dd
HV		 589
590 /* sanity check */
591 if (freq < 32000 || freq > 48000)
592 return -EINVAL;
593
594 /* hz is the refresh rate times 100 */
595 hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000;
596 /* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */
597 acpf = (25600 * freq) / hz;
598 /* acni = (256 * freq * 2^23) / crystal_frequency =
599 (freq * 2^(8+23)) / crystal_frequency =
600 (freq << 31) / 32.11 MHz */
601 f = freq;
602 f = f << 31;
603 do_div(f, 32110000);
604 acni = f;
605
606 saa7115_write(client, 0x30, acpf & 0xff);
607 saa7115_write(client, 0x31, (acpf >> 8) & 0xff);
608 saa7115_write(client, 0x32, (acpf >> 16) & 0x03);
609 saa7115_write(client, 0x34, acni & 0xff);
610 saa7115_write(client, 0x35, (acni >> 8) & 0xff);
611 saa7115_write(client, 0x36, (acni >> 16) & 0x3f);
e19b2fcc
HV		 612 state->audclk_freq = freq;
613 return 0;
614}
615
616static int saa7115_set_v4lctrl(struct i2c_client *client, struct v4l2_control *ctrl)
617{
618 struct saa7115_state *state = i2c_get_clientdata(client);
619
620 switch (ctrl->id) {
621 case V4L2_CID_BRIGHTNESS:
622 if (ctrl->value < 0 || ctrl->value > 255) {
fac9e899 623 v4l_err(client, "invalid brightness setting %d\n", ctrl->value);
e19b2fcc
HV		 624 return -ERANGE;
625 }
626
627 state->bright = ctrl->value;
628 saa7115_write(client, 0x0a, state->bright);
629 break;
630
631 case V4L2_CID_CONTRAST:
632 if (ctrl->value < 0 || ctrl->value > 127) {
fac9e899 633 v4l_err(client, "invalid contrast setting %d\n", ctrl->value);
e19b2fcc
HV		 634 return -ERANGE;
635 }
636
637 state->contrast = ctrl->value;
638 saa7115_write(client, 0x0b, state->contrast);
639 break;
640
641 case V4L2_CID_SATURATION:
642 if (ctrl->value < 0 || ctrl->value > 127) {
fac9e899 643 v4l_err(client, "invalid saturation setting %d\n", ctrl->value);
e19b2fcc
HV		 644 return -ERANGE;
645 }
646
647 state->sat = ctrl->value;
648 saa7115_write(client, 0x0c, state->sat);
649 break;
650
651 case V4L2_CID_HUE:
652 if (ctrl->value < -127 || ctrl->value > 127) {
fac9e899 653 v4l_err(client, "invalid hue setting %d\n", ctrl->value);
e19b2fcc
HV		 654 return -ERANGE;
655 }
656
657 state->hue = ctrl->value;
658 saa7115_write(client, 0x0d, state->hue);
659 break;
3faeeae4
HV		 660
661 default:
662 return -EINVAL;
e19b2fcc
HV		 663 }
664
665 return 0;
666}
667
668static int saa7115_get_v4lctrl(struct i2c_client *client, struct v4l2_control *ctrl)
669{
670 struct saa7115_state *state = i2c_get_clientdata(client);
671
672 switch (ctrl->id) {
673 case V4L2_CID_BRIGHTNESS:
674 ctrl->value = state->bright;
675 break;
676 case V4L2_CID_CONTRAST:
677 ctrl->value = state->contrast;
678 break;
679 case V4L2_CID_SATURATION:
680 ctrl->value = state->sat;
681 break;
682 case V4L2_CID_HUE:
683 ctrl->value = state->hue;
684 break;
685 default:
686 return -EINVAL;
687 }
688
689 return 0;
690}
691
692static void saa7115_set_v4lstd(struct i2c_client *client, v4l2_std_id std)
693{
694 struct saa7115_state *state = i2c_get_clientdata(client);
695 int taskb = saa7115_read(client, 0x80) & 0x10;
696
30b54d50
HV		 697 /* Prevent unnecessary standard changes. During a standard
698 change the I-Port is temporarily disabled. Any devices
699 reading from that port can get confused.
700 Note that VIDIOC_S_STD is also used to switch from
701 radio to TV mode, so if a VIDIOC_S_STD is broadcast to
702 all I2C devices then you do not want to have an unwanted
703 side-effect here. */
704 if (std == state->std)
705 return;
706
e19b2fcc
HV		 707 // This works for NTSC-M, SECAM-L and the 50Hz PAL variants.
708 if (std & V4L2_STD_525_60) {
f167cb4e 709 v4l_dbg(1, debug, client, "decoder set standard 60 Hz\n");
e19b2fcc
HV		 710 saa7115_writeregs(client, saa7115_cfg_60hz_video);
711 } else {
f167cb4e 712 v4l_dbg(1, debug, client, "decoder set standard 50 Hz\n");
e19b2fcc
HV		 713 saa7115_writeregs(client, saa7115_cfg_50hz_video);
714 }
715
f89982a9
MCC		 716 /* Register 0E - Bits D6-D4 on NO-AUTO mode
717 (SAA7113 doesn't have auto mode)
718 50 Hz / 625 lines 60 Hz / 525 lines
719 000 PAL BGDHI (4.43Mhz) NTSC M (3.58MHz)
720 001 NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz)
721 010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz)
722 011 NTSC N (3.58MHz) PAL M (3.58MHz)
723 100 reserved NTSC-Japan (3.58MHz)
724 */
725 if (state->ident == V4L2_IDENT_SAA7113) {
01342358 726 u8 reg = saa7115_read(client, 0x0e) & 0x8f;
f89982a9 727
02c17224 728 if (std == V4L2_STD_PAL_M) {
01342358 729 reg |= 0x30;
02c17224 730 } else if (std == V4L2_STD_PAL_N) {
01342358 731 reg |= 0x20;
02c17224 732 } else if (std == V4L2_STD_PAL_60) {
01342358 733 reg |= 0x10;
02c17224 734 } else if (std == V4L2_STD_NTSC_M_JP) {
01342358 735 reg |= 0x40;
f89982a9
MCC		 736 }
737 saa7115_write(client, 0x0e, reg);
738 }
739
740
e19b2fcc
HV		 741 state->std = std;
742
743 /* restart task B if needed */
f5762e44 744 if (taskb && state->ident != V4L2_IDENT_SAA7115) {
e19b2fcc
HV		 745 saa7115_writeregs(client, saa7115_cfg_vbi_on);
746 }
747
748 /* switch audio mode too! */
749 saa7115_set_audio_clock_freq(client, state->audclk_freq);
750}
751
752static v4l2_std_id saa7115_get_v4lstd(struct i2c_client *client)
753{
754 struct saa7115_state *state = i2c_get_clientdata(client);
755
756 return state->std;
757}
758
759static void saa7115_log_status(struct i2c_client *client)
760{
e19b2fcc
HV		 761 struct saa7115_state *state = i2c_get_clientdata(client);
762 int reg1e, reg1f;
763 int signalOk;
764 int vcr;
765
fac9e899 766 v4l_info(client, "Audio frequency: %d Hz\n", state->audclk_freq);
f5762e44 767 if (state->ident != V4L2_IDENT_SAA7115) {
e19b2fcc
HV		 768 /* status for the saa7114 */
769 reg1f = saa7115_read(client, 0x1f);
770 signalOk = (reg1f & 0xc1) == 0x81;
fac9e899
HV		 771 v4l_info(client, "Video signal: %s\n", signalOk ? "ok" : "bad");
772 v4l_info(client, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
e19b2fcc
HV		 773 return;
774 }
775
776 /* status for the saa7115 */
777 reg1e = saa7115_read(client, 0x1e);
778 reg1f = saa7115_read(client, 0x1f);
779
780 signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80;
781 vcr = !(reg1f & 0x10);
782
21fa715e 783 if (state->input >= 6) {
fac9e899 784 v4l_info(client, "Input: S-Video %d\n", state->input - 6);
21fa715e 785 } else {
fac9e899 786 v4l_info(client, "Input: Composite %d\n", state->input);
21fa715e 787 }
fac9e899
HV		 788 v4l_info(client, "Video signal: %s\n", signalOk ? (vcr ? "VCR" : "broadcast/DVD") : "bad");
789 v4l_info(client, "Frequency: %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
e19b2fcc
HV		 790
791 switch (reg1e & 0x03) {
792 case 1:
fac9e899 793 v4l_info(client, "Detected format: NTSC\n");
e19b2fcc
HV		 794 break;
795 case 2:
fac9e899 796 v4l_info(client, "Detected format: PAL\n");
e19b2fcc
HV		 797 break;
798 case 3:
fac9e899 799 v4l_info(client, "Detected format: SECAM\n");
e19b2fcc
HV		 800 break;
801 default:
fac9e899 802 v4l_info(client, "Detected format: BW/No color\n");
e19b2fcc
HV		 803 break;
804 }
805}
806
807/* setup the sliced VBI lcr registers according to the sliced VBI format */
808static void saa7115_set_lcr(struct i2c_client *client, struct v4l2_sliced_vbi_format *fmt)
809{
810 struct saa7115_state *state = i2c_get_clientdata(client);
811 int is_50hz = (state->std & V4L2_STD_625_50);
812 u8 lcr[24];
813 int i, x;
814
01342358 815 /* saa7113/7114 doesn't yet support VBI */
f5762e44 816 if (state->ident != V4L2_IDENT_SAA7115)
e19b2fcc
HV		 817 return;
818
819 for (i = 0; i <= 23; i++)
820 lcr[i] = 0xff;
821
822 if (fmt->service_set == 0) {
823 /* raw VBI */
824 if (is_50hz)
825 for (i = 6; i <= 23; i++)
826 lcr[i] = 0xdd;
827 else
828 for (i = 10; i <= 21; i++)
829 lcr[i] = 0xdd;
830 } else {
831 /* sliced VBI */
832 /* first clear lines that cannot be captured */
833 if (is_50hz) {
834 for (i = 0; i <= 5; i++)
835 fmt->service_lines[0][i] =
836 fmt->service_lines[1][i] = 0;
837 }
838 else {
839 for (i = 0; i <= 9; i++)
840 fmt->service_lines[0][i] =
841 fmt->service_lines[1][i] = 0;
842 for (i = 22; i <= 23; i++)
843 fmt->service_lines[0][i] =
844 fmt->service_lines[1][i] = 0;
845 }
846
847 /* Now set the lcr values according to the specified service */
848 for (i = 6; i <= 23; i++) {
849 lcr[i] = 0;
850 for (x = 0; x <= 1; x++) {
851 switch (fmt->service_lines[1-x][i]) {
852 case 0:
853 lcr[i] |= 0xf << (4 * x);
854 break;
9bc7400a 855 case V4L2_SLICED_TELETEXT_B:
e19b2fcc
HV		 856 lcr[i] |= 1 << (4 * x);
857 break;
858 case V4L2_SLICED_CAPTION_525:
859 lcr[i] |= 4 << (4 * x);
860 break;
861 case V4L2_SLICED_WSS_625:
862 lcr[i] |= 5 << (4 * x);
863 break;
864 case V4L2_SLICED_VPS:
865 lcr[i] |= 7 << (4 * x);
866 break;
867 }
868 }
869 }
870 }
871
872 /* write the lcr registers */
873 for (i = 2; i <= 23; i++) {
874 saa7115_write(client, i - 2 + 0x41, lcr[i]);
875 }
876
877 /* enable/disable raw VBI capturing */
878 saa7115_writeregs(client, fmt->service_set == 0 ? saa7115_cfg_vbi_on : saa7115_cfg_vbi_off);
879}
880
881static int saa7115_get_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt)
882{
883 static u16 lcr2vbi[] = {
9bc7400a 884 0, V4L2_SLICED_TELETEXT_B, 0, /* 1 */
e19b2fcc
HV		 885 0, V4L2_SLICED_CAPTION_525, /* 4 */
886 V4L2_SLICED_WSS_625, 0, /* 5 */
887 V4L2_SLICED_VPS, 0, 0, 0, 0, /* 7 */
888 0, 0, 0, 0
889 };
890 struct v4l2_sliced_vbi_format *sliced = &fmt->fmt.sliced;
891 int i;
892
893 if (fmt->type != V4L2_BUF_TYPE_SLICED_VBI_CAPTURE)
894 return -EINVAL;
895 memset(sliced, 0, sizeof(*sliced));
896 /* done if using raw VBI */
897 if (saa7115_read(client, 0x80) & 0x10)
898 return 0;
899 for (i = 2; i <= 23; i++) {
900 u8 v = saa7115_read(client, i - 2 + 0x41);
901
902 sliced->service_lines[0][i] = lcr2vbi[v >> 4];
903 sliced->service_lines[1][i] = lcr2vbi[v & 0xf];
904 sliced->service_set |=
905 sliced->service_lines[0][i] | sliced->service_lines[1][i];
906 }
907 return 0;
908}
909
910static int saa7115_set_v4lfmt(struct i2c_client *client, struct v4l2_format *fmt)
911{
912 struct saa7115_state *state = i2c_get_clientdata(client);
913 struct v4l2_pix_format *pix;
914 int HPSC, HFSC;
915 int VSCY, Vsrc;
916 int is_50hz = state->std & V4L2_STD_625_50;
917
918 if (fmt->type == V4L2_BUF_TYPE_SLICED_VBI_CAPTURE) {
919 saa7115_set_lcr(client, &fmt->fmt.sliced);
920 return 0;
921 }
922 if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
923 return -EINVAL;
924
925 pix = &(fmt->fmt.pix);
926
f167cb4e 927 v4l_dbg(1, debug, client, "decoder set size\n");
e19b2fcc
HV		 928
929 /* FIXME need better bounds checking here */
930 if ((pix->width < 1) || (pix->width > 1440))
931 return -EINVAL;
932 if ((pix->height < 1) || (pix->height > 960))
933 return -EINVAL;
934
935 /* probably have a valid size, let's set it */
936 /* Set output width/height */
937 /* width */
938 saa7115_write(client, 0xcc, (u8) (pix->width & 0xff));
939 saa7115_write(client, 0xcd, (u8) ((pix->width >> 8) & 0xff));
940 /* height */
941 saa7115_write(client, 0xce, (u8) (pix->height & 0xff));
942 saa7115_write(client, 0xcf, (u8) ((pix->height >> 8) & 0xff));
943
944 /* Scaling settings */
945 /* Hprescaler is floor(inres/outres) */
946 /* FIXME hardcoding input res */
947 if (pix->width != 720) {
948 HPSC = (int)(720 / pix->width);
949 /* 0 is not allowed (div. by zero) */
950 HPSC = HPSC ? HPSC : 1;
951 HFSC = (int)((1024 * 720) / (HPSC * pix->width));
952
f167cb4e 953 v4l_dbg(1, debug, client, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
e19b2fcc
HV		 954 /* FIXME hardcodes to "Task B"
955 * write H prescaler integer */
956 saa7115_write(client, 0xd0, (u8) (HPSC & 0x3f));
957
958 /* write H fine-scaling (luminance) */
959 saa7115_write(client, 0xd8, (u8) (HFSC & 0xff));
960 saa7115_write(client, 0xd9, (u8) ((HFSC >> 8) & 0xff));
961 /* write H fine-scaling (chrominance)
962 * must be lum/2, so i'll just bitshift :) */
963 saa7115_write(client, 0xDC, (u8) ((HFSC >> 1) & 0xff));
964 saa7115_write(client, 0xDD, (u8) ((HFSC >> 9) & 0xff));
965 } else {
966 if (is_50hz) {
f167cb4e 967 v4l_dbg(1, debug, client, "Setting full 50hz width\n");
e19b2fcc
HV		 968 saa7115_writeregs(client, saa7115_cfg_50hz_fullres_x);
969 } else {
f167cb4e 970 v4l_dbg(1, debug, client, "Setting full 60hz width\n");
e19b2fcc
HV		 971 saa7115_writeregs(client, saa7115_cfg_60hz_fullres_x);
972 }
973 }
974
975 Vsrc = is_50hz ? 576 : 480;
976
977 if (pix->height != Vsrc) {
978 VSCY = (int)((1024 * Vsrc) / pix->height);
f167cb4e 979 v4l_dbg(1, debug, client, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
e19b2fcc
HV		 980
981 /* Correct Contrast and Luminance */
982 saa7115_write(client, 0xd5, (u8) (64 * 1024 / VSCY));
983 saa7115_write(client, 0xd6, (u8) (64 * 1024 / VSCY));
984
985 /* write V fine-scaling (luminance) */
986 saa7115_write(client, 0xe0, (u8) (VSCY & 0xff));
987 saa7115_write(client, 0xe1, (u8) ((VSCY >> 8) & 0xff));
988 /* write V fine-scaling (chrominance) */
989 saa7115_write(client, 0xe2, (u8) (VSCY & 0xff));
990 saa7115_write(client, 0xe3, (u8) ((VSCY >> 8) & 0xff));
991 } else {
992 if (is_50hz) {
f167cb4e 993 v4l_dbg(1, debug, client, "Setting full 50Hz height\n");
e19b2fcc
HV		 994 saa7115_writeregs(client, saa7115_cfg_50hz_fullres_y);
995 } else {
f167cb4e 996 v4l_dbg(1, debug, client, "Setting full 60hz height\n");
e19b2fcc
HV		 997 saa7115_writeregs(client, saa7115_cfg_60hz_fullres_y);
998 }
999 }
1000
1001 saa7115_writeregs(client, saa7115_cfg_reset_scaler);
1002 return 0;
1003}
1004
1005/* Decode the sliced VBI data stream as created by the saa7115.
1006 The format is described in the saa7115 datasheet in Tables 25 and 26
1007 and in Figure 33.
1008 The current implementation uses SAV/EAV codes and not the ancillary data
1009 headers. The vbi->p pointer points to the SDID byte right after the SAV
1010 code. */
1011static void saa7115_decode_vbi_line(struct i2c_client *client,
1012 struct v4l2_decode_vbi_line *vbi)
1013{
1014 static const char vbi_no_data_pattern[] = {
1015 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0
1016 };
1017 struct saa7115_state *state = i2c_get_clientdata(client);
1018 u8 *p = vbi->p;
1019 u32 wss;
1020 int id1, id2; /* the ID1 and ID2 bytes from the internal header */
1021
1022 vbi->type = 0; /* mark result as a failure */
1023 id1 = p[2];
1024 id2 = p[3];
1025 /* Note: the field bit is inverted for 60 Hz video */
1026 if (state->std & V4L2_STD_525_60)
1027 id1 ^= 0x40;
1028
1029 /* Skip internal header, p now points to the start of the payload */
1030 p += 4;
1031 vbi->p = p;
1032
1033 /* calculate field and line number of the VBI packet (1-23) */
1034 vbi->is_second_field = ((id1 & 0x40) != 0);
1035 vbi->line = (id1 & 0x3f) << 3;
1036 vbi->line |= (id2 & 0x70) >> 4;
1037
1038 /* Obtain data type */
1039 id2 &= 0xf;
1040
1041 /* If the VBI slicer does not detect any signal it will fill up
1042 the payload buffer with 0xa0 bytes. */
1043 if (!memcmp(p, vbi_no_data_pattern, sizeof(vbi_no_data_pattern)))
1044 return;
1045
1046 /* decode payloads */
1047 switch (id2) {
1048 case 1:
9bc7400a 1049 vbi->type = V4L2_SLICED_TELETEXT_B;
e19b2fcc
HV		 1050 break;
1051 case 4:
1052 if (!saa7115_odd_parity(p[0]) || !saa7115_odd_parity(p[1]))
1053 return;
1054 vbi->type = V4L2_SLICED_CAPTION_525;
1055 break;
1056 case 5:
1057 wss = saa7115_decode_wss(p);
1058 if (wss == -1)
1059 return;
1060 p[0] = wss & 0xff;
1061 p[1] = wss >> 8;
1062 vbi->type = V4L2_SLICED_WSS_625;
1063 break;
1064 case 7:
1065 if (saa7115_decode_vps(p, p) != 0)
1066 return;
1067 vbi->type = V4L2_SLICED_VPS;
1068 break;
1069 default:
1070 return;
1071 }
1072}
1073
1074/* ============ SAA7115 AUDIO settings (end) ============= */
1075
da4ae5a7
HV		 1076static struct v4l2_queryctrl saa7115_qctrl[] = {
1077 {
1078 .id = V4L2_CID_BRIGHTNESS,
1079 .type = V4L2_CTRL_TYPE_INTEGER,
1080 .name = "Brightness",
1081 .minimum = 0,
1082 .maximum = 255,
1083 .step = 1,
1084 .default_value = 128,
1085 .flags = 0,
1086 }, {
1087 .id = V4L2_CID_CONTRAST,
1088 .type = V4L2_CTRL_TYPE_INTEGER,
1089 .name = "Contrast",
1090 .minimum = 0,
ecc0b947 1091 .maximum = 127,
da4ae5a7
HV		 1092 .step = 1,
1093 .default_value = 64,
1094 .flags = 0,
1095 }, {
1096 .id = V4L2_CID_SATURATION,
1097 .type = V4L2_CTRL_TYPE_INTEGER,
1098 .name = "Saturation",
1099 .minimum = 0,
ecc0b947 1100 .maximum = 127,
da4ae5a7
HV		 1101 .step = 1,
1102 .default_value = 64,
1103 .flags = 0,
1104 }, {
1105 .id = V4L2_CID_HUE,
1106 .type = V4L2_CTRL_TYPE_INTEGER,
1107 .name = "Hue",
1108 .minimum = -128,
1109 .maximum = 127,
1110 .step = 1,
1111 .default_value = 0,
1112 .flags = 0,
1113 },
1114};
1115
1116/* ----------------------------------------------------------------------- */
1117
e19b2fcc
HV		 1118static int saa7115_command(struct i2c_client *client, unsigned int cmd, void *arg)
1119{
1120 struct saa7115_state *state = i2c_get_clientdata(client);
1121 int *iarg = arg;
1122
1123 /* ioctls to allow direct access to the saa7115 registers for testing */
1124 switch (cmd) {
1125 case VIDIOC_S_FMT:
1126 return saa7115_set_v4lfmt(client, (struct v4l2_format *)arg);
1127
1128 case VIDIOC_G_FMT:
1129 return saa7115_get_v4lfmt(client, (struct v4l2_format *)arg);
1130
1131 case VIDIOC_INT_AUDIO_CLOCK_FREQ:
3578d3dd 1132 return saa7115_set_audio_clock_freq(client, *(u32 *)arg);
e19b2fcc
HV		 1133
1134 case VIDIOC_G_TUNER:
1135 {
1136 struct v4l2_tuner *vt = arg;
1137 int status;
1138
3faeeae4
HV		 1139 if (state->radio)
1140 break;
e19b2fcc
HV		 1141 status = saa7115_read(client, 0x1f);
1142
f167cb4e 1143 v4l_dbg(1, debug, client, "status: 0x%02x\n", status);
e19b2fcc
HV		 1144 vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0;
1145 break;
1146 }
1147
1148 case VIDIOC_LOG_STATUS:
1149 saa7115_log_status(client);
1150 break;
1151
1152 case VIDIOC_G_CTRL:
1153 return saa7115_get_v4lctrl(client, (struct v4l2_control *)arg);
1154
1155 case VIDIOC_S_CTRL:
1156 return saa7115_set_v4lctrl(client, (struct v4l2_control *)arg);
1157
da4ae5a7
HV		 1158 case VIDIOC_QUERYCTRL:
1159 {
1160 struct v4l2_queryctrl *qc = arg;
1161 int i;
1162
1163 for (i = 0; i < ARRAY_SIZE(saa7115_qctrl); i++)
1164 if (qc->id && qc->id == saa7115_qctrl[i].id) {
1165 memcpy(qc, &saa7115_qctrl[i], sizeof(*qc));
1166 return 0;
1167 }
1168 return -EINVAL;
1169 }
1170
e19b2fcc
HV		 1171 case VIDIOC_G_STD:
1172 *(v4l2_std_id *)arg = saa7115_get_v4lstd(client);
1173 break;
1174
1175 case VIDIOC_S_STD:
3faeeae4 1176 state->radio = 0;
e19b2fcc
HV		 1177 saa7115_set_v4lstd(client, *(v4l2_std_id *)arg);
1178 break;
1179
3faeeae4
HV		 1180 case AUDC_SET_RADIO:
1181 state->radio = 1;
1182 break;
1183
1f8f5fa9
HV		 1184 case VIDIOC_INT_G_VIDEO_ROUTING:
1185 {
1186 struct v4l2_routing *route = arg;
1187
1188 route->input = state->input;
1189 route->output = 0;
1190 break;
1191 }
1192
1193 case VIDIOC_INT_S_VIDEO_ROUTING:
1194 {
1195 struct v4l2_routing *route = arg;
1196
1197 v4l_dbg(1, debug, client, "decoder set input %d\n", route->input);
1198 /* saa7113 does not have these inputs */
1199 if (state->ident == V4L2_IDENT_SAA7113 &&
1200 (route->input == SAA7115_COMPOSITE4 ||
1201 route->input == SAA7115_COMPOSITE5)) {
1202 return -EINVAL;
1203 }
1204 if (route->input > SAA7115_SVIDEO3)
1205 return -EINVAL;
1206 if (state->input == route->input)
1207 break;
1208 v4l_dbg(1, debug, client, "now setting %s input\n",
1209 (route->input >= SAA7115_SVIDEO0) ? "S-Video" : "Composite");
1210 state->input = route->input;
1211
1212 /* select mode */
1213 saa7115_write(client, 0x02,
1214 (saa7115_read(client, 0x02) & 0xf0) |
1215 state->input);
1216
1217 /* bypass chrominance trap for S-Video modes */
1218 saa7115_write(client, 0x09,
1219 (saa7115_read(client, 0x09) & 0x7f) |
1220 (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0));
1221 break;
1222 }
1223
e19b2fcc
HV		 1224 case VIDIOC_G_INPUT:
1225 *(int *)arg = state->input;
1226 break;
1227
1228 case VIDIOC_S_INPUT:
f167cb4e 1229 v4l_dbg(1, debug, client, "decoder set input %d\n", *iarg);
e19b2fcc
HV		 1230 /* inputs from 0-9 are available */
1231 if (*iarg < 0 || *iarg > 9) {
1232 return -EINVAL;
1233 }
1234
1235 if (state->input == *iarg)
1236 break;
f167cb4e 1237 v4l_dbg(1, debug, client, "now setting %s input\n",
e19b2fcc
HV		 1238 *iarg >= 6 ? "S-Video" : "Composite");
1239 state->input = *iarg;
1240
1241 /* select mode */
1242 saa7115_write(client, 0x02,
1243 (saa7115_read(client, 0x02) & 0xf0) |
1244 state->input);
1245
1246 /* bypass chrominance trap for modes 6..9 */
1247 saa7115_write(client, 0x09,
1248 (saa7115_read(client, 0x09) & 0x7f) |
1249 (state->input < 6 ? 0x0 : 0x80));
1250 break;
1251
1252 case VIDIOC_STREAMON:
1253 case VIDIOC_STREAMOFF:
f167cb4e 1254 v4l_dbg(1, debug, client, "%s output\n",
e19b2fcc
HV		 1255 (cmd == VIDIOC_STREAMON) ? "enable" : "disable");
1256
1257 if (state->enable != (cmd == VIDIOC_STREAMON)) {
1258 state->enable = (cmd == VIDIOC_STREAMON);
1259 saa7115_write(client, 0x87, state->enable);
1260 }
1261 break;
1262
1263 case VIDIOC_INT_DECODE_VBI_LINE:
1264 saa7115_decode_vbi_line(client, arg);
1265 break;
1266
1267 case VIDIOC_INT_RESET:
f167cb4e 1268 v4l_dbg(1, debug, client, "decoder RESET\n");
e19b2fcc
HV		 1269 saa7115_writeregs(client, saa7115_cfg_reset_scaler);
1270 break;
1271
1272 case VIDIOC_INT_G_VBI_DATA:
1273 {
1274 struct v4l2_sliced_vbi_data *data = arg;
1275
1276 switch (data->id) {
1277 case V4L2_SLICED_WSS_625:
1278 if (saa7115_read(client, 0x6b) & 0xc0)
1279 return -EIO;
1280 data->data[0] = saa7115_read(client, 0x6c);
1281 data->data[1] = saa7115_read(client, 0x6d);
1282 return 0;
1283 case V4L2_SLICED_CAPTION_525:
1284 if (data->field == 0) {
1285 /* CC */
1286 if (saa7115_read(client, 0x66) & 0xc0)
1287 return -EIO;
1288 data->data[0] = saa7115_read(client, 0x67);
1289 data->data[1] = saa7115_read(client, 0x68);
1290 return 0;
1291 }
1292 /* XDS */
1293 if (saa7115_read(client, 0x66) & 0x30)
1294 return -EIO;
1295 data->data[0] = saa7115_read(client, 0x69);
1296 data->data[1] = saa7115_read(client, 0x6a);
1297 return 0;
1298 default:
1299 return -EINVAL;
1300 }
1301 break;
1302 }
1303
1304#ifdef CONFIG_VIDEO_ADV_DEBUG
1305 case VIDIOC_INT_G_REGISTER:
1306 {
1307 struct v4l2_register *reg = arg;
1308
1309 if (reg->i2c_id != I2C_DRIVERID_SAA711X)
1310 return -EINVAL;
1311 reg->val = saa7115_read(client, reg->reg & 0xff);
1312 break;
1313 }
1314
1315 case VIDIOC_INT_S_REGISTER:
1316 {
1317 struct v4l2_register *reg = arg;
1318
1319 if (reg->i2c_id != I2C_DRIVERID_SAA711X)
1320 return -EINVAL;
1321 if (!capable(CAP_SYS_ADMIN))
1322 return -EPERM;
1323 saa7115_write(client, reg->reg & 0xff, reg->val & 0xff);
1324 break;
1325 }
1326#endif
1327
1328 case VIDIOC_INT_G_CHIP_IDENT:
1329 *iarg = state->ident;
1330 break;
1331
1332 default:
1333 return -EINVAL;
1334 }
1335
1336 return 0;
1337}
1338
1339/* ----------------------------------------------------------------------- */
1340
1341static struct i2c_driver i2c_driver_saa7115;
1342
1343static int saa7115_attach(struct i2c_adapter *adapter, int address, int kind)
1344{
1345 struct i2c_client *client;
1346 struct saa7115_state *state;
1347 u8 chip_id;
1348
1349 /* Check if the adapter supports the needed features */
1350 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1351 return 0;
1352
7408187d 1353 client = kzalloc(sizeof(struct i2c_client), GFP_KERNEL);
e19b2fcc
HV		 1354 if (client == 0)
1355 return -ENOMEM;
e19b2fcc
HV		 1356 client->addr = address;
1357 client->adapter = adapter;
1358 client->driver = &i2c_driver_saa7115;
e19b2fcc
HV		 1359 snprintf(client->name, sizeof(client->name) - 1, "saa7115");
1360
f167cb4e 1361 v4l_dbg(1, debug, client, "detecting saa7115 client on address 0x%x\n", address << 1);
e19b2fcc
HV		 1362
1363 saa7115_write(client, 0, 5);
1364 chip_id = saa7115_read(client, 0) & 0x0f;
01342358 1365 if (chip_id < 3 && chip_id > 5) {
f167cb4e 1366 v4l_dbg(1, debug, client, "saa7115 not found\n");
e19b2fcc
HV		 1367 kfree(client);
1368 return 0;
1369 }
f5762e44 1370 snprintf(client->name, sizeof(client->name) - 1, "saa711%d",chip_id);
fac9e899 1371 v4l_info(client, "saa711%d found @ 0x%x (%s)\n", chip_id, address << 1, adapter->name);
e19b2fcc 1372
7408187d 1373 state = kzalloc(sizeof(struct saa7115_state), GFP_KERNEL);
e19b2fcc
HV		 1374 i2c_set_clientdata(client, state);
1375 if (state == NULL) {
1376 kfree(client);
1377 return -ENOMEM;
1378 }
e19b2fcc
HV		 1379 state->std = V4L2_STD_NTSC;
1380 state->input = -1;
1381 state->enable = 1;
3faeeae4 1382 state->radio = 0;
e19b2fcc
HV		 1383 state->bright = 128;
1384 state->contrast = 64;
1385 state->hue = 0;
1386 state->sat = 64;
f5762e44
MCC		 1387 switch (chip_id) {
1388 case 3:
1389 state->ident = V4L2_IDENT_SAA7113;
1390 break;
1391 case 4:
1392 state->ident = V4L2_IDENT_SAA7114;
1393 break;
1394 default:
1395 state->ident = V4L2_IDENT_SAA7115;
1396 break;
1397 }
1398
3578d3dd 1399 state->audclk_freq = 48000;
e19b2fcc 1400
f167cb4e 1401 v4l_dbg(1, debug, client, "writing init values\n");
e19b2fcc
HV		 1402
1403 /* init to 60hz/48khz */
01342358 1404 if (state->ident == V4L2_IDENT_SAA7113)
f5762e44
MCC		 1405 saa7115_writeregs(client, saa7113_init_auto_input);
1406 else
1407 saa7115_writeregs(client, saa7115_init_auto_input);
e19b2fcc
HV		 1408 saa7115_writeregs(client, saa7115_init_misc);
1409 saa7115_writeregs(client, saa7115_cfg_60hz_fullres_x);
1410 saa7115_writeregs(client, saa7115_cfg_60hz_fullres_y);
1411 saa7115_writeregs(client, saa7115_cfg_60hz_video);
3578d3dd 1412 saa7115_set_audio_clock_freq(client, state->audclk_freq);
e19b2fcc
HV		 1413 saa7115_writeregs(client, saa7115_cfg_reset_scaler);
1414
1415 i2c_attach_client(client);
1416
f167cb4e 1417 v4l_dbg(1, debug, client, "status: (1E) 0x%02x, (1F) 0x%02x\n",
e19b2fcc
HV		 1418 saa7115_read(client, 0x1e), saa7115_read(client, 0x1f));
1419
1420 return 0;
1421}
1422
1423static int saa7115_probe(struct i2c_adapter *adapter)
1424{
e19b2fcc 1425 if (adapter->class & I2C_CLASS_TV_ANALOG)
e19b2fcc
HV		 1426 return i2c_probe(adapter, &addr_data, &saa7115_attach);
1427 return 0;
1428}
1429
1430static int saa7115_detach(struct i2c_client *client)
1431{
1432 struct saa7115_state *state = i2c_get_clientdata(client);
1433 int err;
1434
1435 err = i2c_detach_client(client);
1436 if (err) {
1437 return err;
1438 }
1439
1440 kfree(state);
1441 kfree(client);
1442 return 0;
1443}
1444
1445/* ----------------------------------------------------------------------- */
1446
1447/* i2c implementation */
1448static struct i2c_driver i2c_driver_saa7115 = {
604f28e2 1449 .driver = {
604f28e2
LR		 1450 .name = "saa7115",
1451 },
e19b2fcc 1452 .id = I2C_DRIVERID_SAA711X,
e19b2fcc
HV		 1453 .attach_adapter = saa7115_probe,
1454 .detach_client = saa7115_detach,
1455 .command = saa7115_command,
e19b2fcc
HV		 1456};
1457
1458
1459static int __init saa7115_init_module(void)
1460{
1461 return i2c_add_driver(&i2c_driver_saa7115);
1462}
1463
1464static void __exit saa7115_cleanup_module(void)
1465{
1466 i2c_del_driver(&i2c_driver_saa7115);
1467}
1468
1469module_init(saa7115_init_module);
1470module_exit(saa7115_cleanup_module);
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