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[net-next-2.6.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
d855497e
MI		 27#include "pvrusb2.h"
28#include "pvrusb2-std.h"
29#include "pvrusb2-util.h"
30#include "pvrusb2-hdw.h"
31#include "pvrusb2-i2c-core.h"
32#include "pvrusb2-tuner.h"
33#include "pvrusb2-eeprom.h"
34#include "pvrusb2-hdw-internal.h"
35#include "pvrusb2-encoder.h"
36#include "pvrusb2-debug.h"
8d364363 37#include "pvrusb2-fx2-cmd.h"
d855497e 38
1bde0289
MI		 39#define TV_MIN_FREQ 55250000L
40#define TV_MAX_FREQ 850000000L
25d8527a 41
83ce57aa
MI		 42/* This defines a minimum interval that the decoder must remain quiet
43 before we are allowed to start it running. */
44#define TIME_MSEC_DECODER_WAIT 50
45
46/* This defines a minimum interval that the encoder must remain quiet
fa98e594
MI		 47 before we are allowed to configure it. I had this originally set to
48 50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
49 things work better when it's set to 100msec. */
50#define TIME_MSEC_ENCODER_WAIT 100
83ce57aa
MI		 51
52/* This defines the minimum interval that the encoder must successfully run
53 before we consider that the encoder has run at least once since its
54 firmware has been loaded. This measurement is in important for cases
55 where we can't do something until we know that the encoder has been run
56 at least once. */
57#define TIME_MSEC_ENCODER_OK 250
58
a0fd1cb1 59static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 60static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 61
ff699e6b 62static int ctlchg;
d855497e 63static int initusbreset = 1;
ff699e6b 64static int procreload;
d855497e
MI		 65static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
66static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
67static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 68static int init_pause_msec;
d855497e
MI		 69
70module_param(ctlchg, int, S_IRUGO|S_IWUSR);
71MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
72module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
73MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
74module_param(initusbreset, int, S_IRUGO|S_IWUSR);
75MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
76module_param(procreload, int, S_IRUGO|S_IWUSR);
77MODULE_PARM_DESC(procreload,
78 "Attempt init failure recovery with firmware reload");
79module_param_array(tuner, int, NULL, 0444);
80MODULE_PARM_DESC(tuner,"specify installed tuner type");
81module_param_array(video_std, int, NULL, 0444);
82MODULE_PARM_DESC(video_std,"specify initial video standard");
83module_param_array(tolerance, int, NULL, 0444);
84MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
85
5a4f5da6
MK		 86/* US Broadcast channel 7 (175.25 MHz) */
87static int default_tv_freq = 175250000L;
88/* 104.3 MHz, a usable FM station for my area */
89static int default_radio_freq = 104300000L;
90
91module_param_named(tv_freq, default_tv_freq, int, 0444);
92MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
93module_param_named(radio_freq, default_radio_freq, int, 0444);
94MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
95
d855497e
MI		 96#define PVR2_CTL_WRITE_ENDPOINT 0x01
97#define PVR2_CTL_READ_ENDPOINT 0x81
98
99#define PVR2_GPIO_IN 0x9008
100#define PVR2_GPIO_OUT 0x900c
101#define PVR2_GPIO_DIR 0x9020
102
103#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
104
105#define PVR2_FIRMWARE_ENDPOINT 0x02
106
107/* size of a firmware chunk */
108#define FIRMWARE_CHUNK_SIZE 0x2000
109
b30d2441
MI		 110/* Define the list of additional controls we'll dynamically construct based
111 on query of the cx2341x module. */
112struct pvr2_mpeg_ids {
113 const char *strid;
114 int id;
115};
116static const struct pvr2_mpeg_ids mpeg_ids[] = {
117 {
118 .strid = "audio_layer",
119 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
120 },{
121 .strid = "audio_bitrate",
122 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
123 },{
124 /* Already using audio_mode elsewhere :-( */
125 .strid = "mpeg_audio_mode",
126 .id = V4L2_CID_MPEG_AUDIO_MODE,
127 },{
128 .strid = "mpeg_audio_mode_extension",
129 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
130 },{
131 .strid = "audio_emphasis",
132 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
133 },{
134 .strid = "audio_crc",
135 .id = V4L2_CID_MPEG_AUDIO_CRC,
136 },{
137 .strid = "video_aspect",
138 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
139 },{
140 .strid = "video_b_frames",
141 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
142 },{
143 .strid = "video_gop_size",
144 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
145 },{
146 .strid = "video_gop_closure",
147 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 148 },{
149 .strid = "video_bitrate_mode",
150 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
151 },{
152 .strid = "video_bitrate",
153 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
154 },{
155 .strid = "video_bitrate_peak",
156 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
157 },{
158 .strid = "video_temporal_decimation",
159 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
160 },{
161 .strid = "stream_type",
162 .id = V4L2_CID_MPEG_STREAM_TYPE,
163 },{
164 .strid = "video_spatial_filter_mode",
165 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
166 },{
167 .strid = "video_spatial_filter",
168 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
169 },{
170 .strid = "video_luma_spatial_filter_type",
171 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
172 },{
173 .strid = "video_chroma_spatial_filter_type",
174 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
175 },{
176 .strid = "video_temporal_filter_mode",
177 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
178 },{
179 .strid = "video_temporal_filter",
180 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
181 },{
182 .strid = "video_median_filter_type",
183 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
184 },{
185 .strid = "video_luma_median_filter_top",
186 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
187 },{
188 .strid = "video_luma_median_filter_bottom",
189 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
190 },{
191 .strid = "video_chroma_median_filter_top",
192 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
193 },{
194 .strid = "video_chroma_median_filter_bottom",
195 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
196 }
197};
eca8ebfc 198#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 199
434449f4 200
d855497e 201static const char *control_values_srate[] = {
434449f4
MI		 202 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
203 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
204 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 205};
206
207
d855497e 208
d855497e
MI		 209static const char *control_values_input[] = {
210 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 211 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 212 [PVR2_CVAL_INPUT_RADIO] = "radio",
213 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
214 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
215};
216
217
218static const char *control_values_audiomode[] = {
219 [V4L2_TUNER_MODE_MONO] = "Mono",
220 [V4L2_TUNER_MODE_STEREO] = "Stereo",
221 [V4L2_TUNER_MODE_LANG1] = "Lang1",
222 [V4L2_TUNER_MODE_LANG2] = "Lang2",
223 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
224};
225
226
227static const char *control_values_hsm[] = {
228 [PVR2_CVAL_HSM_FAIL] = "Fail",
229 [PVR2_CVAL_HSM_HIGH] = "High",
230 [PVR2_CVAL_HSM_FULL] = "Full",
231};
232
233
681c7399
MI		 234static const char *pvr2_state_names[] = {
235 [PVR2_STATE_NONE] = "none",
236 [PVR2_STATE_DEAD] = "dead",
237 [PVR2_STATE_COLD] = "cold",
238 [PVR2_STATE_WARM] = "warm",
239 [PVR2_STATE_ERROR] = "error",
240 [PVR2_STATE_READY] = "ready",
241 [PVR2_STATE_RUN] = "run",
d855497e
MI		 242};
243
681c7399 244
694dca2b 245struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 246 unsigned char id;
247 unsigned char *desc;
248};
249
694dca2b 250static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 251 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
252 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 253 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 254 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
255 {FX2CMD_REG_WRITE, "write encoder register"},
256 {FX2CMD_REG_READ, "read encoder register"},
257 {FX2CMD_MEMSEL, "encoder memsel"},
258 {FX2CMD_I2C_WRITE, "i2c write"},
259 {FX2CMD_I2C_READ, "i2c read"},
260 {FX2CMD_GET_USB_SPEED, "get USB speed"},
261 {FX2CMD_STREAMING_ON, "stream on"},
262 {FX2CMD_STREAMING_OFF, "stream off"},
263 {FX2CMD_FWPOST1, "fwpost1"},
264 {FX2CMD_POWER_OFF, "power off"},
265 {FX2CMD_POWER_ON, "power on"},
266 {FX2CMD_DEEP_RESET, "deep reset"},
267 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
268 {FX2CMD_GET_IR_CODE, "get IR code"},
269 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
270 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
271 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
272 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
273 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
274 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
275 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
276};
277
278
1cb03b76 279static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 280static void pvr2_hdw_state_sched(struct pvr2_hdw *);
281static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 282static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399
MI		 283static void pvr2_hdw_worker_i2c(struct work_struct *work);
284static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 285static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
286static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
287static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 288static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 289static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 290static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 291static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
292static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 293static void pvr2_hdw_quiescent_timeout(unsigned long);
294static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 295static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 296static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 297static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
298 unsigned int timeout,int probe_fl,
299 void *write_data,unsigned int write_len,
300 void *read_data,unsigned int read_len);
d855497e 301
681c7399
MI		 302
303static void trace_stbit(const char *name,int val)
304{
305 pvr2_trace(PVR2_TRACE_STBITS,
306 "State bit %s <-- %s",
307 name,(val ? "true" : "false"));
308}
309
d855497e
MI		 310static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
311{
312 struct pvr2_hdw *hdw = cptr->hdw;
313 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
314 *vp = hdw->freqTable[hdw->freqProgSlot-1];
315 } else {
316 *vp = 0;
317 }
318 return 0;
319}
320
321static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
322{
323 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 324 unsigned int slotId = hdw->freqProgSlot;
325 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
326 hdw->freqTable[slotId-1] = v;
327 /* Handle side effects correctly - if we're tuned to this
328 slot, then forgot the slot id relation since the stored
329 frequency has been changed. */
330 if (hdw->freqSelector) {
331 if (hdw->freqSlotRadio == slotId) {
332 hdw->freqSlotRadio = 0;
333 }
334 } else {
335 if (hdw->freqSlotTelevision == slotId) {
336 hdw->freqSlotTelevision = 0;
337 }
338 }
d855497e
MI		 339 }
340 return 0;
341}
342
343static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
344{
345 *vp = cptr->hdw->freqProgSlot;
346 return 0;
347}
348
349static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
350{
351 struct pvr2_hdw *hdw = cptr->hdw;
352 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
353 hdw->freqProgSlot = v;
354 }
355 return 0;
356}
357
358static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
359{
1bde0289
MI		 360 struct pvr2_hdw *hdw = cptr->hdw;
361 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 362 return 0;
363}
364
1bde0289 365static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 366{
367 unsigned freq = 0;
368 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 369 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
370 if (slotId > 0) {
371 freq = hdw->freqTable[slotId-1];
372 if (!freq) return 0;
373 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 374 }
1bde0289
MI		 375 if (hdw->freqSelector) {
376 hdw->freqSlotRadio = slotId;
377 } else {
378 hdw->freqSlotTelevision = slotId;
d855497e
MI		 379 }
380 return 0;
381}
382
383static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
384{
1bde0289 385 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 386 return 0;
387}
388
389static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
390{
391 return cptr->hdw->freqDirty != 0;
392}
393
394static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
395{
396 cptr->hdw->freqDirty = 0;
397}
398
399static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
400{
1bde0289 401 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 402 return 0;
403}
404
3ad9fc37
MI		 405static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
406{
407 /* Actual maximum depends on the video standard in effect. */
408 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
409 *vp = 480;
410 } else {
411 *vp = 576;
412 }
413 return 0;
414}
415
416static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
417{
989eb154
MI		 418 /* Actual minimum depends on device digitizer type. */
419 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 420 *vp = 75;
421 } else {
422 *vp = 17;
423 }
424 return 0;
425}
426
1bde0289 427static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 428{
1bde0289
MI		 429 *vp = cptr->hdw->input_val;
430 return 0;
431}
432
29bf5b1d
MI		 433static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
434{
1cb03b76 435 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 436}
437
1bde0289
MI		 438static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
439{
1cb03b76 440 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 441}
442
443static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
444{
445 return cptr->hdw->input_dirty != 0;
446}
447
448static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
449{
450 cptr->hdw->input_dirty = 0;
451}
452
5549f54f 453
25d8527a
PK		 454static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
455{
644afdb9
MI		 456 unsigned long fv;
457 struct pvr2_hdw *hdw = cptr->hdw;
458 if (hdw->tuner_signal_stale) {
459 pvr2_i2c_core_status_poll(hdw);
460 }
461 fv = hdw->tuner_signal_info.rangehigh;
462 if (!fv) {
463 /* Safety fallback */
25d8527a 464 *vp = TV_MAX_FREQ;
644afdb9 465 return 0;
25d8527a 466 }
644afdb9
MI		 467 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
468 fv = (fv * 125) / 2;
469 } else {
470 fv = fv * 62500;
471 }
472 *vp = fv;
25d8527a
PK		 473 return 0;
474}
475
476static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
477{
644afdb9
MI		 478 unsigned long fv;
479 struct pvr2_hdw *hdw = cptr->hdw;
480 if (hdw->tuner_signal_stale) {
481 pvr2_i2c_core_status_poll(hdw);
482 }
483 fv = hdw->tuner_signal_info.rangelow;
484 if (!fv) {
485 /* Safety fallback */
25d8527a 486 *vp = TV_MIN_FREQ;
644afdb9
MI		 487 return 0;
488 }
489 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
490 fv = (fv * 125) / 2;
491 } else {
492 fv = fv * 62500;
25d8527a 493 }
644afdb9 494 *vp = fv;
25d8527a
PK		 495 return 0;
496}
497
b30d2441
MI		 498static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
499{
500 return cptr->hdw->enc_stale != 0;
501}
502
503static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
504{
505 cptr->hdw->enc_stale = 0;
681c7399 506 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 507}
508
509static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
510{
511 int ret;
512 struct v4l2_ext_controls cs;
513 struct v4l2_ext_control c1;
514 memset(&cs,0,sizeof(cs));
515 memset(&c1,0,sizeof(c1));
516 cs.controls = &c1;
517 cs.count = 1;
518 c1.id = cptr->info->v4l_id;
01f1e44f 519 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 520 VIDIOC_G_EXT_CTRLS);
521 if (ret) return ret;
522 *vp = c1.value;
523 return 0;
524}
525
526static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
527{
528 int ret;
681c7399 529 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 530 struct v4l2_ext_controls cs;
531 struct v4l2_ext_control c1;
532 memset(&cs,0,sizeof(cs));
533 memset(&c1,0,sizeof(c1));
534 cs.controls = &c1;
535 cs.count = 1;
536 c1.id = cptr->info->v4l_id;
537 c1.value = v;
681c7399
MI		 538 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
539 hdw->state_encoder_run, &cs,
b30d2441 540 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 541 if (ret == -EBUSY) {
542 /* Oops. cx2341x is telling us it's not safe to change
543 this control while we're capturing. Make a note of this
544 fact so that the pipeline will be stopped the next time
545 controls are committed. Then go on ahead and store this
546 change anyway. */
547 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
548 0, &cs,
549 VIDIOC_S_EXT_CTRLS);
550 if (!ret) hdw->enc_unsafe_stale = !0;
551 }
b30d2441 552 if (ret) return ret;
681c7399 553 hdw->enc_stale = !0;
b30d2441
MI		 554 return 0;
555}
556
557static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
558{
559 struct v4l2_queryctrl qctrl;
560 struct pvr2_ctl_info *info;
561 qctrl.id = cptr->info->v4l_id;
562 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
563 /* Strip out the const so we can adjust a function pointer. It's
564 OK to do this here because we know this is a dynamically created
565 control, so the underlying storage for the info pointer is (a)
566 private to us, and (b) not in read-only storage. Either we do
567 this or we significantly complicate the underlying control
568 implementation. */
569 info = (struct pvr2_ctl_info *)(cptr->info);
570 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
571 if (info->set_value) {
a0fd1cb1 572 info->set_value = NULL;
b30d2441
MI		 573 }
574 } else {
575 if (!(info->set_value)) {
576 info->set_value = ctrl_cx2341x_set;
577 }
578 }
579 return qctrl.flags;
580}
581
d855497e
MI		 582static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
583{
681c7399
MI		 584 *vp = cptr->hdw->state_pipeline_req;
585 return 0;
586}
587
588static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
589{
590 *vp = cptr->hdw->master_state;
d855497e
MI		 591 return 0;
592}
593
594static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
595{
596 int result = pvr2_hdw_is_hsm(cptr->hdw);
597 *vp = PVR2_CVAL_HSM_FULL;
598 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
599 if (result) *vp = PVR2_CVAL_HSM_HIGH;
600 return 0;
601}
602
603static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
604{
605 *vp = cptr->hdw->std_mask_avail;
606 return 0;
607}
608
609static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
610{
611 struct pvr2_hdw *hdw = cptr->hdw;
612 v4l2_std_id ns;
613 ns = hdw->std_mask_avail;
614 ns = (ns & ~m) | (v & m);
615 if (ns == hdw->std_mask_avail) return 0;
616 hdw->std_mask_avail = ns;
617 pvr2_hdw_internal_set_std_avail(hdw);
618 pvr2_hdw_internal_find_stdenum(hdw);
619 return 0;
620}
621
622static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
623 char *bufPtr,unsigned int bufSize,
624 unsigned int *len)
625{
626 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
627 return 0;
628}
629
630static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
631 const char *bufPtr,unsigned int bufSize,
632 int *mskp,int *valp)
633{
634 int ret;
635 v4l2_std_id id;
636 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
637 if (ret < 0) return ret;
638 if (mskp) *mskp = id;
639 if (valp) *valp = id;
640 return 0;
641}
642
643static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
644{
645 *vp = cptr->hdw->std_mask_cur;
646 return 0;
647}
648
649static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
650{
651 struct pvr2_hdw *hdw = cptr->hdw;
652 v4l2_std_id ns;
653 ns = hdw->std_mask_cur;
654 ns = (ns & ~m) | (v & m);
655 if (ns == hdw->std_mask_cur) return 0;
656 hdw->std_mask_cur = ns;
657 hdw->std_dirty = !0;
658 pvr2_hdw_internal_find_stdenum(hdw);
659 return 0;
660}
661
662static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
663{
664 return cptr->hdw->std_dirty != 0;
665}
666
667static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
668{
669 cptr->hdw->std_dirty = 0;
670}
671
672static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
673{
18103c57
MI		 674 struct pvr2_hdw *hdw = cptr->hdw;
675 pvr2_i2c_core_status_poll(hdw);
676 *vp = hdw->tuner_signal_info.signal;
677 return 0;
678}
679
680static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
681{
682 int val = 0;
683 unsigned int subchan;
684 struct pvr2_hdw *hdw = cptr->hdw;
644afdb9 685 pvr2_i2c_core_status_poll(hdw);
18103c57
MI		 686 subchan = hdw->tuner_signal_info.rxsubchans;
687 if (subchan & V4L2_TUNER_SUB_MONO) {
688 val |= (1 << V4L2_TUNER_MODE_MONO);
689 }
690 if (subchan & V4L2_TUNER_SUB_STEREO) {
691 val |= (1 << V4L2_TUNER_MODE_STEREO);
692 }
693 if (subchan & V4L2_TUNER_SUB_LANG1) {
694 val |= (1 << V4L2_TUNER_MODE_LANG1);
695 }
696 if (subchan & V4L2_TUNER_SUB_LANG2) {
697 val |= (1 << V4L2_TUNER_MODE_LANG2);
698 }
699 *vp = val;
d855497e
MI		 700 return 0;
701}
702
d855497e
MI		 703
704static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
705{
706 struct pvr2_hdw *hdw = cptr->hdw;
707 if (v < 0) return -EINVAL;
708 if (v > hdw->std_enum_cnt) return -EINVAL;
709 hdw->std_enum_cur = v;
710 if (!v) return 0;
711 v--;
712 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
713 hdw->std_mask_cur = hdw->std_defs[v].id;
714 hdw->std_dirty = !0;
715 return 0;
716}
717
718
719static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
720{
721 *vp = cptr->hdw->std_enum_cur;
722 return 0;
723}
724
725
726static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
727{
728 return cptr->hdw->std_dirty != 0;
729}
730
731
732static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
733{
734 cptr->hdw->std_dirty = 0;
735}
736
737
738#define DEFINT(vmin,vmax) \
739 .type = pvr2_ctl_int, \
740 .def.type_int.min_value = vmin, \
741 .def.type_int.max_value = vmax
742
743#define DEFENUM(tab) \
744 .type = pvr2_ctl_enum, \
27c7b710 745 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 746 .def.type_enum.value_names = tab
747
33213963
MI		 748#define DEFBOOL \
749 .type = pvr2_ctl_bool
750
d855497e
MI		 751#define DEFMASK(msk,tab) \
752 .type = pvr2_ctl_bitmask, \
753 .def.type_bitmask.valid_bits = msk, \
754 .def.type_bitmask.bit_names = tab
755
756#define DEFREF(vname) \
757 .set_value = ctrl_set_##vname, \
758 .get_value = ctrl_get_##vname, \
759 .is_dirty = ctrl_isdirty_##vname, \
760 .clear_dirty = ctrl_cleardirty_##vname
761
762
763#define VCREATE_FUNCS(vname) \
764static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
765{*vp = cptr->hdw->vname##_val; return 0;} \
766static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
767{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
768static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
769{return cptr->hdw->vname##_dirty != 0;} \
770static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
771{cptr->hdw->vname##_dirty = 0;}
772
773VCREATE_FUNCS(brightness)
774VCREATE_FUNCS(contrast)
775VCREATE_FUNCS(saturation)
776VCREATE_FUNCS(hue)
777VCREATE_FUNCS(volume)
778VCREATE_FUNCS(balance)
779VCREATE_FUNCS(bass)
780VCREATE_FUNCS(treble)
781VCREATE_FUNCS(mute)
c05c0462
MI		 782VCREATE_FUNCS(audiomode)
783VCREATE_FUNCS(res_hor)
784VCREATE_FUNCS(res_ver)
d855497e 785VCREATE_FUNCS(srate)
d855497e 786
d855497e
MI		 787/* Table definition of all controls which can be manipulated */
788static const struct pvr2_ctl_info control_defs[] = {
789 {
790 .v4l_id = V4L2_CID_BRIGHTNESS,
791 .desc = "Brightness",
792 .name = "brightness",
793 .default_value = 128,
794 DEFREF(brightness),
795 DEFINT(0,255),
796 },{
797 .v4l_id = V4L2_CID_CONTRAST,
798 .desc = "Contrast",
799 .name = "contrast",
800 .default_value = 68,
801 DEFREF(contrast),
802 DEFINT(0,127),
803 },{
804 .v4l_id = V4L2_CID_SATURATION,
805 .desc = "Saturation",
806 .name = "saturation",
807 .default_value = 64,
808 DEFREF(saturation),
809 DEFINT(0,127),
810 },{
811 .v4l_id = V4L2_CID_HUE,
812 .desc = "Hue",
813 .name = "hue",
814 .default_value = 0,
815 DEFREF(hue),
816 DEFINT(-128,127),
817 },{
818 .v4l_id = V4L2_CID_AUDIO_VOLUME,
819 .desc = "Volume",
820 .name = "volume",
139eecf9 821 .default_value = 62000,
d855497e
MI		 822 DEFREF(volume),
823 DEFINT(0,65535),
824 },{
825 .v4l_id = V4L2_CID_AUDIO_BALANCE,
826 .desc = "Balance",
827 .name = "balance",
828 .default_value = 0,
829 DEFREF(balance),
830 DEFINT(-32768,32767),
831 },{
832 .v4l_id = V4L2_CID_AUDIO_BASS,
833 .desc = "Bass",
834 .name = "bass",
835 .default_value = 0,
836 DEFREF(bass),
837 DEFINT(-32768,32767),
838 },{
839 .v4l_id = V4L2_CID_AUDIO_TREBLE,
840 .desc = "Treble",
841 .name = "treble",
842 .default_value = 0,
843 DEFREF(treble),
844 DEFINT(-32768,32767),
845 },{
846 .v4l_id = V4L2_CID_AUDIO_MUTE,
847 .desc = "Mute",
848 .name = "mute",
849 .default_value = 0,
850 DEFREF(mute),
33213963 851 DEFBOOL,
c05c0462
MI		 852 },{
853 .desc = "Video Source",
854 .name = "input",
855 .internal_id = PVR2_CID_INPUT,
856 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 857 .check_value = ctrl_check_input,
c05c0462
MI		 858 DEFREF(input),
859 DEFENUM(control_values_input),
860 },{
861 .desc = "Audio Mode",
862 .name = "audio_mode",
863 .internal_id = PVR2_CID_AUDIOMODE,
864 .default_value = V4L2_TUNER_MODE_STEREO,
865 DEFREF(audiomode),
866 DEFENUM(control_values_audiomode),
867 },{
868 .desc = "Horizontal capture resolution",
869 .name = "resolution_hor",
870 .internal_id = PVR2_CID_HRES,
871 .default_value = 720,
872 DEFREF(res_hor),
3ad9fc37 873 DEFINT(19,720),
c05c0462
MI		 874 },{
875 .desc = "Vertical capture resolution",
876 .name = "resolution_ver",
877 .internal_id = PVR2_CID_VRES,
878 .default_value = 480,
879 DEFREF(res_ver),
3ad9fc37
MI		 880 DEFINT(17,576),
881 /* Hook in check for video standard and adjust maximum
882 depending on the standard. */
883 .get_max_value = ctrl_vres_max_get,
884 .get_min_value = ctrl_vres_min_get,
d855497e 885 },{
b30d2441 886 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 887 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
888 .desc = "Audio Sampling Frequency",
d855497e 889 .name = "srate",
d855497e
MI		 890 DEFREF(srate),
891 DEFENUM(control_values_srate),
d855497e
MI		 892 },{
893 .desc = "Tuner Frequency (Hz)",
894 .name = "frequency",
895 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 896 .default_value = 0,
d855497e
MI		 897 .set_value = ctrl_freq_set,
898 .get_value = ctrl_freq_get,
899 .is_dirty = ctrl_freq_is_dirty,
900 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 901 DEFINT(0,0),
25d8527a
PK		 902 /* Hook in check for input value (tv/radio) and adjust
903 max/min values accordingly */
904 .get_max_value = ctrl_freq_max_get,
905 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 906 },{
907 .desc = "Channel",
908 .name = "channel",
909 .set_value = ctrl_channel_set,
910 .get_value = ctrl_channel_get,
911 DEFINT(0,FREQTABLE_SIZE),
912 },{
913 .desc = "Channel Program Frequency",
914 .name = "freq_table_value",
915 .set_value = ctrl_channelfreq_set,
916 .get_value = ctrl_channelfreq_get,
644afdb9 917 DEFINT(0,0),
1bde0289
MI		 918 /* Hook in check for input value (tv/radio) and adjust
919 max/min values accordingly */
1bde0289
MI		 920 .get_max_value = ctrl_freq_max_get,
921 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 922 },{
923 .desc = "Channel Program ID",
924 .name = "freq_table_channel",
925 .set_value = ctrl_channelprog_set,
926 .get_value = ctrl_channelprog_get,
927 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 928 },{
929 .desc = "Streaming Enabled",
930 .name = "streaming_enabled",
931 .get_value = ctrl_streamingenabled_get,
33213963 932 DEFBOOL,
d855497e
MI		 933 },{
934 .desc = "USB Speed",
935 .name = "usb_speed",
936 .get_value = ctrl_hsm_get,
937 DEFENUM(control_values_hsm),
681c7399
MI		 938 },{
939 .desc = "Master State",
940 .name = "master_state",
941 .get_value = ctrl_masterstate_get,
942 DEFENUM(pvr2_state_names),
d855497e
MI		 943 },{
944 .desc = "Signal Present",
945 .name = "signal_present",
946 .get_value = ctrl_signal_get,
18103c57
MI		 947 DEFINT(0,65535),
948 },{
949 .desc = "Audio Modes Present",
950 .name = "audio_modes_present",
951 .get_value = ctrl_audio_modes_present_get,
952 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
953 v4l. Nothing outside of this module cares about this,
954 but I reuse it in order to also reuse the
955 control_values_audiomode string table. */
956 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
957 (1 << V4L2_TUNER_MODE_STEREO)|
958 (1 << V4L2_TUNER_MODE_LANG1)|
959 (1 << V4L2_TUNER_MODE_LANG2)),
960 control_values_audiomode),
d855497e
MI		 961 },{
962 .desc = "Video Standards Available Mask",
963 .name = "video_standard_mask_available",
964 .internal_id = PVR2_CID_STDAVAIL,
965 .skip_init = !0,
966 .get_value = ctrl_stdavail_get,
967 .set_value = ctrl_stdavail_set,
968 .val_to_sym = ctrl_std_val_to_sym,
969 .sym_to_val = ctrl_std_sym_to_val,
970 .type = pvr2_ctl_bitmask,
971 },{
972 .desc = "Video Standards In Use Mask",
973 .name = "video_standard_mask_active",
974 .internal_id = PVR2_CID_STDCUR,
975 .skip_init = !0,
976 .get_value = ctrl_stdcur_get,
977 .set_value = ctrl_stdcur_set,
978 .is_dirty = ctrl_stdcur_is_dirty,
979 .clear_dirty = ctrl_stdcur_clear_dirty,
980 .val_to_sym = ctrl_std_val_to_sym,
981 .sym_to_val = ctrl_std_sym_to_val,
982 .type = pvr2_ctl_bitmask,
d855497e
MI		 983 },{
984 .desc = "Video Standard Name",
985 .name = "video_standard",
986 .internal_id = PVR2_CID_STDENUM,
987 .skip_init = !0,
988 .get_value = ctrl_stdenumcur_get,
989 .set_value = ctrl_stdenumcur_set,
990 .is_dirty = ctrl_stdenumcur_is_dirty,
991 .clear_dirty = ctrl_stdenumcur_clear_dirty,
992 .type = pvr2_ctl_enum,
993 }
994};
995
eca8ebfc 996#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 997
998
999const char *pvr2_config_get_name(enum pvr2_config cfg)
1000{
1001 switch (cfg) {
1002 case pvr2_config_empty: return "empty";
1003 case pvr2_config_mpeg: return "mpeg";
1004 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1005 case pvr2_config_pcm: return "pcm";
1006 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1007 }
1008 return "<unknown>";
1009}
1010
1011
1012struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1013{
1014 return hdw->usb_dev;
1015}
1016
1017
1018unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1019{
1020 return hdw->serial_number;
1021}
1022
31a18547
MI		 1023
1024const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1025{
1026 return hdw->bus_info;
1027}
1028
1029
1bde0289
MI		 1030unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1031{
1032 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1033}
1034
1035/* Set the currently tuned frequency and account for all possible
1036 driver-core side effects of this action. */
f55a8712 1037static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1038{
7c74e57e 1039 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1040 if (hdw->freqSelector) {
1041 /* Swing over to radio frequency selection */
1042 hdw->freqSelector = 0;
1043 hdw->freqDirty = !0;
1044 }
1bde0289
MI		 1045 if (hdw->freqValRadio != val) {
1046 hdw->freqValRadio = val;
1047 hdw->freqSlotRadio = 0;
7c74e57e 1048 hdw->freqDirty = !0;
1bde0289 1049 }
7c74e57e 1050 } else {
1bde0289
MI		 1051 if (!(hdw->freqSelector)) {
1052 /* Swing over to television frequency selection */
1053 hdw->freqSelector = 1;
1054 hdw->freqDirty = !0;
1055 }
1bde0289
MI		 1056 if (hdw->freqValTelevision != val) {
1057 hdw->freqValTelevision = val;
1058 hdw->freqSlotTelevision = 0;
7c74e57e 1059 hdw->freqDirty = !0;
1bde0289 1060 }
1bde0289
MI		 1061 }
1062}
1063
d855497e
MI		 1064int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1065{
1066 return hdw->unit_number;
1067}
1068
1069
1070/* Attempt to locate one of the given set of files. Messages are logged
1071 appropriate to what has been found. The return value will be 0 or
1072 greater on success (it will be the index of the file name found) and
1073 fw_entry will be filled in. Otherwise a negative error is returned on
1074 failure. If the return value is -ENOENT then no viable firmware file
1075 could be located. */
1076static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1077 const struct firmware **fw_entry,
1078 const char *fwtypename,
1079 unsigned int fwcount,
1080 const char *fwnames[])
1081{
1082 unsigned int idx;
1083 int ret = -EINVAL;
1084 for (idx = 0; idx < fwcount; idx++) {
1085 ret = request_firmware(fw_entry,
1086 fwnames[idx],
1087 &hdw->usb_dev->dev);
1088 if (!ret) {
1089 trace_firmware("Located %s firmware: %s;"
1090 " uploading...",
1091 fwtypename,
1092 fwnames[idx]);
1093 return idx;
1094 }
1095 if (ret == -ENOENT) continue;
1096 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1097 "request_firmware fatal error with code=%d",ret);
1098 return ret;
1099 }
1100 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1101 "***WARNING***"
1102 " Device %s firmware"
1103 " seems to be missing.",
1104 fwtypename);
1105 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1106 "Did you install the pvrusb2 firmware files"
1107 " in their proper location?");
1108 if (fwcount == 1) {
1109 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1110 "request_firmware unable to locate %s file %s",
1111 fwtypename,fwnames[0]);
1112 } else {
1113 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1114 "request_firmware unable to locate"
1115 " one of the following %s files:",
1116 fwtypename);
1117 for (idx = 0; idx < fwcount; idx++) {
1118 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1119 "request_firmware: Failed to find %s",
1120 fwnames[idx]);
1121 }
1122 }
1123 return ret;
1124}
1125
1126
1127/*
1128 * pvr2_upload_firmware1().
1129 *
1130 * Send the 8051 firmware to the device. After the upload, arrange for
1131 * device to re-enumerate.
1132 *
1133 * NOTE : the pointer to the firmware data given by request_firmware()
1134 * is not suitable for an usb transaction.
1135 *
1136 */
07e337ee 1137static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1138{
a0fd1cb1 1139 const struct firmware *fw_entry = NULL;
d855497e
MI		 1140 void *fw_ptr;
1141 unsigned int pipe;
1142 int ret;
1143 u16 address;
1d643a37 1144
989eb154 1145 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1146 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1147 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1148 "Connected device type defines"
1149 " no firmware to upload; ignoring firmware");
1150 return -ENOTTY;
1d643a37
MI		 1151 }
1152
d855497e
MI		 1153 hdw->fw1_state = FW1_STATE_FAILED; // default result
1154
1155 trace_firmware("pvr2_upload_firmware1");
1156
1157 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1158 hdw->hdw_desc->fx2_firmware.cnt,
1159 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1160 if (ret < 0) {
1161 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1162 return ret;
1163 }
1164
1165 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1166 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1167
1168 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1169
1170 if (fw_entry->size != 0x2000){
1171 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1172 release_firmware(fw_entry);
1173 return -ENOMEM;
1174 }
1175
1176 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1177 if (fw_ptr == NULL){
1178 release_firmware(fw_entry);
1179 return -ENOMEM;
1180 }
1181
1182 /* We have to hold the CPU during firmware upload. */
1183 pvr2_hdw_cpureset_assert(hdw,1);
1184
1185 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1186 chunk. */
1187
1188 ret = 0;
1189 for(address = 0; address < fw_entry->size; address += 0x800) {
1190 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1191 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1192 0, fw_ptr, 0x800, HZ);
1193 }
1194
1195 trace_firmware("Upload done, releasing device's CPU");
1196
1197 /* Now release the CPU. It will disconnect and reconnect later. */
1198 pvr2_hdw_cpureset_assert(hdw,0);
1199
1200 kfree(fw_ptr);
1201 release_firmware(fw_entry);
1202
1203 trace_firmware("Upload done (%d bytes sent)",ret);
1204
1205 /* We should have written 8192 bytes */
1206 if (ret == 8192) {
1207 hdw->fw1_state = FW1_STATE_RELOAD;
1208 return 0;
1209 }
1210
1211 return -EIO;
1212}
1213
1214
1215/*
1216 * pvr2_upload_firmware2()
1217 *
1218 * This uploads encoder firmware on endpoint 2.
1219 *
1220 */
1221
1222int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1223{
a0fd1cb1 1224 const struct firmware *fw_entry = NULL;
d855497e 1225 void *fw_ptr;
90060d32 1226 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1227 int actual_length;
1228 int ret = 0;
1229 int fwidx;
1230 static const char *fw_files[] = {
1231 CX2341X_FIRM_ENC_FILENAME,
1232 };
1233
989eb154 1234 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1235 return 0;
1236 }
1237
d855497e
MI		 1238 trace_firmware("pvr2_upload_firmware2");
1239
1240 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1241 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1242 if (ret < 0) return ret;
1243 fwidx = ret;
1244 ret = 0;
b30d2441
MI		 1245 /* Since we're about to completely reinitialize the encoder,
1246 invalidate our cached copy of its configuration state. Next
1247 time we configure the encoder, then we'll fully configure it. */
1248 hdw->enc_cur_valid = 0;
d855497e 1249
d913d630
MI		 1250 /* Encoder is about to be reset so note that as far as we're
1251 concerned now, the encoder has never been run. */
1252 del_timer_sync(&hdw->encoder_run_timer);
1253 if (hdw->state_encoder_runok) {
1254 hdw->state_encoder_runok = 0;
1255 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1256 }
1257
d855497e
MI		 1258 /* First prepare firmware loading */
1259 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1260 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1261 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1262 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1263 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1264 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1265 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1266 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1267 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1268 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1269 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1270 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1271 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1272 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1273 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1274 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1275 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1276 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1277
1278 if (ret) {
1279 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1280 "firmware2 upload prep failed, ret=%d",ret);
1281 release_firmware(fw_entry);
21684ba9 1282 goto done;
d855497e
MI		 1283 }
1284
1285 /* Now send firmware */
1286
1287 fw_len = fw_entry->size;
1288
90060d32 1289 if (fw_len % sizeof(u32)) {
d855497e
MI		 1290 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1291 "size of %s firmware"
48dc30a1 1292 " must be a multiple of %zu bytes",
90060d32 1293 fw_files[fwidx],sizeof(u32));
d855497e 1294 release_firmware(fw_entry);
21684ba9
MI		 1295 ret = -EINVAL;
1296 goto done;
d855497e
MI		 1297 }
1298
1299 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1300 if (fw_ptr == NULL){
1301 release_firmware(fw_entry);
1302 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1303 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1304 ret = -ENOMEM;
1305 goto done;
d855497e
MI		 1306 }
1307
1308 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1309
90060d32
MI		 1310 fw_done = 0;
1311 for (fw_done = 0; fw_done < fw_len;) {
1312 bcnt = fw_len - fw_done;
1313 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1314 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1315 /* Usbsnoop log shows that we must swap bytes... */
1316 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1317 ((u32 *)fw_ptr)[icnt] =
1318 ___swab32(((u32 *)fw_ptr)[icnt]);
1319
1320 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1321 &actual_length, HZ);
90060d32
MI		 1322 ret |= (actual_length != bcnt);
1323 if (ret) break;
1324 fw_done += bcnt;
d855497e
MI		 1325 }
1326
1327 trace_firmware("upload of %s : %i / %i ",
1328 fw_files[fwidx],fw_done,fw_len);
1329
1330 kfree(fw_ptr);
1331 release_firmware(fw_entry);
1332
1333 if (ret) {
1334 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1335 "firmware2 upload transfer failure");
21684ba9 1336 goto done;
d855497e
MI		 1337 }
1338
1339 /* Finish upload */
1340
1341 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1342 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1343 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1344
1345 if (ret) {
1346 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1347 "firmware2 upload post-proc failure");
d855497e 1348 }
21684ba9
MI		 1349
1350 done:
1df59f0b
MI		 1351 if (hdw->hdw_desc->signal_routing_scheme ==
1352 PVR2_ROUTING_SCHEME_GOTVIEW) {
1353 /* Ensure that GPIO 11 is set to output for GOTVIEW
1354 hardware. */
1355 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1356 }
d855497e
MI		 1357 return ret;
1358}
1359
1360
681c7399
MI		 1361static const char *pvr2_get_state_name(unsigned int st)
1362{
1363 if (st < ARRAY_SIZE(pvr2_state_names)) {
1364 return pvr2_state_names[st];
d855497e 1365 }
681c7399 1366 return "???";
d855497e
MI		 1367}
1368
681c7399 1369static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1370{
681c7399
MI		 1371 if (!hdw->decoder_ctrl) {
1372 if (!hdw->flag_decoder_missed) {
1373 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1374 "WARNING: No decoder present");
1375 hdw->flag_decoder_missed = !0;
1376 trace_stbit("flag_decoder_missed",
1377 hdw->flag_decoder_missed);
1378 }
1379 return -EIO;
1380 }
1381 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1382 return 0;
d855497e
MI		 1383}
1384
1385
681c7399 1386void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
d855497e 1387{
681c7399
MI		 1388 if (hdw->decoder_ctrl == ptr) return;
1389 hdw->decoder_ctrl = ptr;
1390 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1391 hdw->flag_decoder_missed = 0;
1392 trace_stbit("flag_decoder_missed",
1393 hdw->flag_decoder_missed);
1394 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1395 "Decoder has appeared");
1396 pvr2_hdw_state_sched(hdw);
1397 }
d855497e
MI		 1398}
1399
1400
681c7399 1401int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1402{
681c7399 1403 return hdw->master_state;
d855497e
MI		 1404}
1405
1406
681c7399 1407static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1408{
681c7399
MI		 1409 if (!hdw->flag_tripped) return 0;
1410 hdw->flag_tripped = 0;
1411 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1412 "Clearing driver error statuss");
1413 return !0;
d855497e
MI		 1414}
1415
1416
681c7399 1417int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1418{
681c7399 1419 int fl;
d855497e 1420 LOCK_TAKE(hdw->big_lock); do {
681c7399 1421 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1422 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1423 if (fl) pvr2_hdw_state_sched(hdw);
1424 return 0;
d855497e
MI		 1425}
1426
1427
d855497e
MI		 1428
1429
1430int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1431{
681c7399 1432 return hdw->state_pipeline_req != 0;
d855497e
MI		 1433}
1434
1435
1436int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1437{
681c7399 1438 int ret,st;
d855497e 1439 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1440 pvr2_hdw_untrip_unlocked(hdw);
1441 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1442 hdw->state_pipeline_req = enable_flag != 0;
1443 pvr2_trace(PVR2_TRACE_START_STOP,
1444 "/*--TRACE_STREAM--*/ %s",
1445 enable_flag ? "enable" : "disable");
1446 }
1447 pvr2_hdw_state_sched(hdw);
d855497e 1448 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1449 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1450 if (enable_flag) {
1451 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1452 if (st != PVR2_STATE_READY) return -EIO;
1453 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1454 }
1455 }
d855497e
MI		 1456 return 0;
1457}
1458
1459
1460int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1461{
681c7399 1462 int fl;
d855497e 1463 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1464 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1465 hdw->desired_stream_type = config;
1466 hdw->state_pipeline_config = 0;
1467 trace_stbit("state_pipeline_config",
1468 hdw->state_pipeline_config);
1469 pvr2_hdw_state_sched(hdw);
1470 }
d855497e 1471 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1472 if (fl) return 0;
1473 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1474}
1475
1476
1477static int get_default_tuner_type(struct pvr2_hdw *hdw)
1478{
1479 int unit_number = hdw->unit_number;
1480 int tp = -1;
1481 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1482 tp = tuner[unit_number];
1483 }
1484 if (tp < 0) return -EINVAL;
1485 hdw->tuner_type = tp;
aaf7884d 1486 hdw->tuner_updated = !0;
d855497e
MI		 1487 return 0;
1488}
1489
1490
1491static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1492{
1493 int unit_number = hdw->unit_number;
1494 int tp = 0;
1495 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1496 tp = video_std[unit_number];
6a540254 1497 if (tp) return tp;
d855497e 1498 }
6a540254 1499 return 0;
d855497e
MI		 1500}
1501
1502
1503static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1504{
1505 int unit_number = hdw->unit_number;
1506 int tp = 0;
1507 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1508 tp = tolerance[unit_number];
1509 }
1510 return tp;
1511}
1512
1513
1514static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1515{
1516 /* Try a harmless request to fetch the eeprom's address over
1517 endpoint 1. See what happens. Only the full FX2 image can
1518 respond to this. If this probe fails then likely the FX2
1519 firmware needs be loaded. */
1520 int result;
1521 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1522 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1523 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1524 hdw->cmd_buffer,1,
1525 hdw->cmd_buffer,1);
1526 if (result < 0) break;
1527 } while(0); LOCK_GIVE(hdw->ctl_lock);
1528 if (result) {
1529 pvr2_trace(PVR2_TRACE_INIT,
1530 "Probe of device endpoint 1 result status %d",
1531 result);
1532 } else {
1533 pvr2_trace(PVR2_TRACE_INIT,
1534 "Probe of device endpoint 1 succeeded");
1535 }
1536 return result == 0;
1537}
1538
9f66d4ea
MI		 1539struct pvr2_std_hack {
1540 v4l2_std_id pat; /* Pattern to match */
1541 v4l2_std_id msk; /* Which bits we care about */
1542 v4l2_std_id std; /* What additional standards or default to set */
1543};
1544
1545/* This data structure labels specific combinations of standards from
1546 tveeprom that we'll try to recognize. If we recognize one, then assume
1547 a specified default standard to use. This is here because tveeprom only
1548 tells us about available standards not the intended default standard (if
1549 any) for the device in question. We guess the default based on what has
1550 been reported as available. Note that this is only for guessing a
1551 default - which can always be overridden explicitly - and if the user
1552 has otherwise named a default then that default will always be used in
1553 place of this table. */
ebff0330 1554static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1555 { /* PAL(B/G) */
1556 .pat = V4L2_STD_B|V4L2_STD_GH,
1557 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1558 },
1559 { /* NTSC(M) */
1560 .pat = V4L2_STD_MN,
1561 .std = V4L2_STD_NTSC_M,
1562 },
1563 { /* PAL(I) */
1564 .pat = V4L2_STD_PAL_I,
1565 .std = V4L2_STD_PAL_I,
1566 },
1567 { /* SECAM(L/L') */
1568 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1569 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1570 },
1571 { /* PAL(D/D1/K) */
1572 .pat = V4L2_STD_DK,
ea2562d9 1573 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1574 },
1575};
1576
d855497e
MI		 1577static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1578{
1579 char buf[40];
1580 unsigned int bcnt;
3d290bdb 1581 v4l2_std_id std1,std2,std3;
d855497e
MI		 1582
1583 std1 = get_default_standard(hdw);
3d290bdb 1584 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1585
1586 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1587 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1588 "Supported video standard(s) reported available"
1589 " in hardware: %.*s",
d855497e
MI		 1590 bcnt,buf);
1591
1592 hdw->std_mask_avail = hdw->std_mask_eeprom;
1593
3d290bdb 1594 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1595 if (std2) {
1596 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1597 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1598 "Expanding supported video standards"
1599 " to include: %.*s",
1600 bcnt,buf);
1601 hdw->std_mask_avail |= std2;
1602 }
1603
1604 pvr2_hdw_internal_set_std_avail(hdw);
1605
1606 if (std1) {
1607 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1608 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1609 "Initial video standard forced to %.*s",
1610 bcnt,buf);
1611 hdw->std_mask_cur = std1;
1612 hdw->std_dirty = !0;
1613 pvr2_hdw_internal_find_stdenum(hdw);
1614 return;
1615 }
3d290bdb
MI		 1616 if (std3) {
1617 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1618 pvr2_trace(PVR2_TRACE_STD,
1619 "Initial video standard"
1620 " (determined by device type): %.*s",bcnt,buf);
1621 hdw->std_mask_cur = std3;
1622 hdw->std_dirty = !0;
1623 pvr2_hdw_internal_find_stdenum(hdw);
1624 return;
1625 }
d855497e 1626
9f66d4ea
MI		 1627 {
1628 unsigned int idx;
1629 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1630 if (std_eeprom_maps[idx].msk ?
1631 ((std_eeprom_maps[idx].pat ^
1632 hdw->std_mask_eeprom) &
1633 std_eeprom_maps[idx].msk) :
1634 (std_eeprom_maps[idx].pat !=
1635 hdw->std_mask_eeprom)) continue;
1636 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1637 std_eeprom_maps[idx].std);
56585386 1638 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1639 "Initial video standard guessed as %.*s",
1640 bcnt,buf);
1641 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1642 hdw->std_dirty = !0;
1643 pvr2_hdw_internal_find_stdenum(hdw);
1644 return;
1645 }
1646 }
1647
d855497e
MI		 1648 if (hdw->std_enum_cnt > 1) {
1649 // Autoselect the first listed standard
1650 hdw->std_enum_cur = 1;
1651 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1652 hdw->std_dirty = !0;
56585386 1653 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1654 "Initial video standard auto-selected to %s",
1655 hdw->std_defs[hdw->std_enum_cur-1].name);
1656 return;
1657 }
1658
0885ba1d 1659 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1660 "Unable to select a viable initial video standard");
1661}
1662
1663
1664static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1665{
1666 int ret;
1667 unsigned int idx;
1668 struct pvr2_ctrl *cptr;
1669 int reloadFl = 0;
989eb154 1670 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 1671 if (!reloadFl) {
1672 reloadFl =
1673 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1674 == 0);
1675 if (reloadFl) {
1676 pvr2_trace(PVR2_TRACE_INIT,
1677 "USB endpoint config looks strange"
1678 "; possibly firmware needs to be"
1679 " loaded");
1680 }
d855497e 1681 }
1d643a37
MI		 1682 if (!reloadFl) {
1683 reloadFl = !pvr2_hdw_check_firmware(hdw);
1684 if (reloadFl) {
1685 pvr2_trace(PVR2_TRACE_INIT,
1686 "Check for FX2 firmware failed"
1687 "; possibly firmware needs to be"
1688 " loaded");
1689 }
d855497e 1690 }
1d643a37
MI		 1691 if (reloadFl) {
1692 if (pvr2_upload_firmware1(hdw) != 0) {
1693 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1694 "Failure uploading firmware1");
1695 }
1696 return;
d855497e 1697 }
d855497e
MI		 1698 }
1699 hdw->fw1_state = FW1_STATE_OK;
1700
1701 if (initusbreset) {
1702 pvr2_hdw_device_reset(hdw);
1703 }
1704 if (!pvr2_hdw_dev_ok(hdw)) return;
1705
989eb154
MI		 1706 for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1707 request_module(hdw->hdw_desc->client_modules.lst[idx]);
d855497e
MI		 1708 }
1709
989eb154 1710 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 1711 pvr2_hdw_cmd_powerup(hdw);
1712 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 1713 }
1714
31335b13
MI		 1715 /* Take the IR chip out of reset, if appropriate */
1716 if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
1717 pvr2_issue_simple_cmd(hdw,
1718 FX2CMD_HCW_ZILOG_RESET |
1719 (1 << 8) |
1720 ((0) << 16));
1721 }
1722
d855497e
MI		 1723 // This step MUST happen after the earlier powerup step.
1724 pvr2_i2c_core_init(hdw);
1725 if (!pvr2_hdw_dev_ok(hdw)) return;
1726
c05c0462 1727 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 1728 cptr = hdw->controls + idx;
1729 if (cptr->info->skip_init) continue;
1730 if (!cptr->info->set_value) continue;
1731 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1732 }
1733
1bde0289
MI		 1734 /* Set up special default values for the television and radio
1735 frequencies here. It's not really important what these defaults
1736 are, but I set them to something usable in the Chicago area just
1737 to make driver testing a little easier. */
1738
5a4f5da6
MK		 1739 hdw->freqValTelevision = default_tv_freq;
1740 hdw->freqValRadio = default_radio_freq;
1bde0289 1741
d855497e
MI		 1742 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1743 // thread-safe against the normal pvr2_send_request() mechanism.
1744 // (We should make it thread safe).
1745
aaf7884d
MI		 1746 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1747 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 1748 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 1749 if (ret < 0) {
1750 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1751 "Unable to determine location of eeprom,"
1752 " skipping");
1753 } else {
1754 hdw->eeprom_addr = ret;
1755 pvr2_eeprom_analyze(hdw);
1756 if (!pvr2_hdw_dev_ok(hdw)) return;
1757 }
1758 } else {
1759 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1760 hdw->tuner_updated = !0;
1761 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 1762 }
1763
1764 pvr2_hdw_setup_std(hdw);
1765
1766 if (!get_default_tuner_type(hdw)) {
1767 pvr2_trace(PVR2_TRACE_INIT,
1768 "pvr2_hdw_setup: Tuner type overridden to %d",
1769 hdw->tuner_type);
1770 }
1771
d855497e
MI		 1772 pvr2_i2c_core_check_stale(hdw);
1773 hdw->tuner_updated = 0;
1774
1775 if (!pvr2_hdw_dev_ok(hdw)) return;
1776
1df59f0b
MI		 1777 if (hdw->hdw_desc->signal_routing_scheme ==
1778 PVR2_ROUTING_SCHEME_GOTVIEW) {
1779 /* Ensure that GPIO 11 is set to output for GOTVIEW
1780 hardware. */
1781 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1782 }
1783
681c7399 1784 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 1785
1786 hdw->vid_stream = pvr2_stream_create();
1787 if (!pvr2_hdw_dev_ok(hdw)) return;
1788 pvr2_trace(PVR2_TRACE_INIT,
1789 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1790 if (hdw->vid_stream) {
1791 idx = get_default_error_tolerance(hdw);
1792 if (idx) {
1793 pvr2_trace(PVR2_TRACE_INIT,
1794 "pvr2_hdw_setup: video stream %p"
1795 " setting tolerance %u",
1796 hdw->vid_stream,idx);
1797 }
1798 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1799 PVR2_VID_ENDPOINT,idx);
1800 }
1801
1802 if (!pvr2_hdw_dev_ok(hdw)) return;
1803
d855497e 1804 hdw->flag_init_ok = !0;
681c7399
MI		 1805
1806 pvr2_hdw_state_sched(hdw);
d855497e
MI		 1807}
1808
1809
681c7399
MI		 1810/* Set up the structure and attempt to put the device into a usable state.
1811 This can be a time-consuming operation, which is why it is not done
1812 internally as part of the create() step. */
1813static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 1814{
1815 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 1816 do {
d855497e
MI		 1817 pvr2_hdw_setup_low(hdw);
1818 pvr2_trace(PVR2_TRACE_INIT,
1819 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 1820 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 1821 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 1822 if (hdw->flag_init_ok) {
d855497e
MI		 1823 pvr2_trace(
1824 PVR2_TRACE_INFO,
1825 "Device initialization"
1826 " completed successfully.");
1827 break;
1828 }
1829 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1830 pvr2_trace(
1831 PVR2_TRACE_INFO,
1832 "Device microcontroller firmware"
1833 " (re)loaded; it should now reset"
1834 " and reconnect.");
1835 break;
1836 }
1837 pvr2_trace(
1838 PVR2_TRACE_ERROR_LEGS,
1839 "Device initialization was not successful.");
1840 if (hdw->fw1_state == FW1_STATE_MISSING) {
1841 pvr2_trace(
1842 PVR2_TRACE_ERROR_LEGS,
1843 "Giving up since device"
1844 " microcontroller firmware"
1845 " appears to be missing.");
1846 break;
1847 }
1848 }
1849 if (procreload) {
1850 pvr2_trace(
1851 PVR2_TRACE_ERROR_LEGS,
1852 "Attempting pvrusb2 recovery by reloading"
1853 " primary firmware.");
1854 pvr2_trace(
1855 PVR2_TRACE_ERROR_LEGS,
1856 "If this works, device should disconnect"
1857 " and reconnect in a sane state.");
1858 hdw->fw1_state = FW1_STATE_UNKNOWN;
1859 pvr2_upload_firmware1(hdw);
1860 } else {
1861 pvr2_trace(
1862 PVR2_TRACE_ERROR_LEGS,
1863 "***WARNING*** pvrusb2 device hardware"
1864 " appears to be jammed"
1865 " and I can't clear it.");
1866 pvr2_trace(
1867 PVR2_TRACE_ERROR_LEGS,
1868 "You might need to power cycle"
1869 " the pvrusb2 device"
1870 " in order to recover.");
1871 }
681c7399 1872 } while (0);
d855497e 1873 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 1874}
1875
1876
c4a8828d
MI		 1877/* Perform second stage initialization. Set callback pointer first so that
1878 we can avoid a possible initialization race (if the kernel thread runs
1879 before the callback has been set). */
794b1607
MI		 1880int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
1881 void (*callback_func)(void *),
1882 void *callback_data)
c4a8828d
MI		 1883{
1884 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 1885 if (hdw->flag_disconnected) {
1886 /* Handle a race here: If we're already
1887 disconnected by this point, then give up. If we
1888 get past this then we'll remain connected for
1889 the duration of initialization since the entire
1890 initialization sequence is now protected by the
1891 big_lock. */
1892 break;
1893 }
c4a8828d
MI		 1894 hdw->state_data = callback_data;
1895 hdw->state_func = callback_func;
97f26ff6 1896 pvr2_hdw_setup(hdw);
c4a8828d 1897 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 1898 return hdw->flag_init_ok;
c4a8828d
MI		 1899}
1900
1901
1902/* Create, set up, and return a structure for interacting with the
1903 underlying hardware. */
d855497e
MI		 1904struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1905 const struct usb_device_id *devid)
1906{
7fb20fa3 1907 unsigned int idx,cnt1,cnt2,m;
d855497e 1908 struct pvr2_hdw *hdw;
d855497e
MI		 1909 int valid_std_mask;
1910 struct pvr2_ctrl *cptr;
989eb154 1911 const struct pvr2_device_desc *hdw_desc;
d855497e 1912 __u8 ifnum;
b30d2441
MI		 1913 struct v4l2_queryctrl qctrl;
1914 struct pvr2_ctl_info *ciptr;
d855497e 1915
d130fa8a 1916 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 1917
ca545f7c 1918 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 1919 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 1920 hdw,hdw_desc->description);
d855497e 1921 if (!hdw) goto fail;
681c7399
MI		 1922
1923 init_timer(&hdw->quiescent_timer);
1924 hdw->quiescent_timer.data = (unsigned long)hdw;
1925 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1926
1927 init_timer(&hdw->encoder_wait_timer);
1928 hdw->encoder_wait_timer.data = (unsigned long)hdw;
1929 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1930
d913d630
MI		 1931 init_timer(&hdw->encoder_run_timer);
1932 hdw->encoder_run_timer.data = (unsigned long)hdw;
1933 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
1934
681c7399
MI		 1935 hdw->master_state = PVR2_STATE_DEAD;
1936
1937 init_waitqueue_head(&hdw->state_wait_data);
1938
18103c57 1939 hdw->tuner_signal_stale = !0;
b30d2441 1940 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 1941
7fb20fa3
MI		 1942 /* Calculate which inputs are OK */
1943 m = 0;
1944 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 1945 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
1946 m |= 1 << PVR2_CVAL_INPUT_DTV;
1947 }
7fb20fa3
MI		 1948 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
1949 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
1950 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
1951 hdw->input_avail_mask = m;
1cb03b76 1952 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 1953
62433e31
MI		 1954 /* If not a hybrid device, pathway_state never changes. So
1955 initialize it here to what it should forever be. */
1956 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
1957 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
1958 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
1959 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
1960 }
1961
c05c0462 1962 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 1963 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 1964 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 1965 GFP_KERNEL);
1966 if (!hdw->controls) goto fail;
989eb154 1967 hdw->hdw_desc = hdw_desc;
c05c0462
MI		 1968 for (idx = 0; idx < hdw->control_cnt; idx++) {
1969 cptr = hdw->controls + idx;
1970 cptr->hdw = hdw;
1971 }
d855497e
MI		 1972 for (idx = 0; idx < 32; idx++) {
1973 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1974 }
c05c0462 1975 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 1976 cptr = hdw->controls + idx;
d855497e
MI		 1977 cptr->info = control_defs+idx;
1978 }
dbc40a0e
MI		 1979
1980 /* Ensure that default input choice is a valid one. */
1981 m = hdw->input_avail_mask;
1982 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
1983 if (!((1 << idx) & m)) continue;
1984 hdw->input_val = idx;
1985 break;
1986 }
1987
b30d2441 1988 /* Define and configure additional controls from cx2341x module. */
ca545f7c 1989 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 1990 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1991 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 1992 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1993 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1994 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1995 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1996 ciptr->name = mpeg_ids[idx].strid;
1997 ciptr->v4l_id = mpeg_ids[idx].id;
1998 ciptr->skip_init = !0;
1999 ciptr->get_value = ctrl_cx2341x_get;
2000 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2001 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2002 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2003 qctrl.id = ciptr->v4l_id;
2004 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2005 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2006 ciptr->set_value = ctrl_cx2341x_set;
2007 }
2008 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2009 PVR2_CTLD_INFO_DESC_SIZE);
2010 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2011 ciptr->default_value = qctrl.default_value;
2012 switch (qctrl.type) {
2013 default:
2014 case V4L2_CTRL_TYPE_INTEGER:
2015 ciptr->type = pvr2_ctl_int;
2016 ciptr->def.type_int.min_value = qctrl.minimum;
2017 ciptr->def.type_int.max_value = qctrl.maximum;
2018 break;
2019 case V4L2_CTRL_TYPE_BOOLEAN:
2020 ciptr->type = pvr2_ctl_bool;
2021 break;
2022 case V4L2_CTRL_TYPE_MENU:
2023 ciptr->type = pvr2_ctl_enum;
2024 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2025 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2026 ciptr->v4l_id);
b30d2441
MI		 2027 for (cnt1 = 0;
2028 ciptr->def.type_enum.value_names[cnt1] != NULL;
2029 cnt1++) { }
2030 ciptr->def.type_enum.count = cnt1;
2031 break;
2032 }
2033 cptr->info = ciptr;
2034 }
d855497e
MI		 2035
2036 // Initialize video standard enum dynamic control
2037 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2038 if (cptr) {
2039 memcpy(&hdw->std_info_enum,cptr->info,
2040 sizeof(hdw->std_info_enum));
2041 cptr->info = &hdw->std_info_enum;
2042
2043 }
2044 // Initialize control data regarding video standard masks
2045 valid_std_mask = pvr2_std_get_usable();
2046 for (idx = 0; idx < 32; idx++) {
2047 if (!(valid_std_mask & (1 << idx))) continue;
2048 cnt1 = pvr2_std_id_to_str(
2049 hdw->std_mask_names[idx],
2050 sizeof(hdw->std_mask_names[idx])-1,
2051 1 << idx);
2052 hdw->std_mask_names[idx][cnt1] = 0;
2053 }
2054 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2055 if (cptr) {
2056 memcpy(&hdw->std_info_avail,cptr->info,
2057 sizeof(hdw->std_info_avail));
2058 cptr->info = &hdw->std_info_avail;
2059 hdw->std_info_avail.def.type_bitmask.bit_names =
2060 hdw->std_mask_ptrs;
2061 hdw->std_info_avail.def.type_bitmask.valid_bits =
2062 valid_std_mask;
2063 }
2064 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2065 if (cptr) {
2066 memcpy(&hdw->std_info_cur,cptr->info,
2067 sizeof(hdw->std_info_cur));
2068 cptr->info = &hdw->std_info_cur;
2069 hdw->std_info_cur.def.type_bitmask.bit_names =
2070 hdw->std_mask_ptrs;
2071 hdw->std_info_avail.def.type_bitmask.valid_bits =
2072 valid_std_mask;
2073 }
2074
2075 hdw->eeprom_addr = -1;
2076 hdw->unit_number = -1;
8079384e
MI		 2077 hdw->v4l_minor_number_video = -1;
2078 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2079 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2080 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2081 if (!hdw->ctl_write_buffer) goto fail;
2082 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2083 if (!hdw->ctl_read_buffer) goto fail;
2084 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2085 if (!hdw->ctl_write_urb) goto fail;
2086 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2087 if (!hdw->ctl_read_urb) goto fail;
2088
8df0c87c 2089 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2090 for (idx = 0; idx < PVR_NUM; idx++) {
2091 if (unit_pointers[idx]) continue;
2092 hdw->unit_number = idx;
2093 unit_pointers[idx] = hdw;
2094 break;
2095 }
8df0c87c 2096 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2097
2098 cnt1 = 0;
2099 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2100 cnt1 += cnt2;
2101 if (hdw->unit_number >= 0) {
2102 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2103 ('a' + hdw->unit_number));
2104 cnt1 += cnt2;
2105 }
2106 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2107 hdw->name[cnt1] = 0;
2108
681c7399
MI		 2109 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2110 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2111 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
681c7399 2112
d855497e
MI		 2113 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2114 hdw->unit_number,hdw->name);
2115
2116 hdw->tuner_type = -1;
2117 hdw->flag_ok = !0;
d855497e
MI		 2118
2119 hdw->usb_intf = intf;
2120 hdw->usb_dev = interface_to_usbdev(intf);
2121
31a18547
MI		 2122 scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2123 "usb %s address %d",
2124 hdw->usb_dev->dev.bus_id,
2125 hdw->usb_dev->devnum);
2126
d855497e
MI		 2127 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2128 usb_set_interface(hdw->usb_dev,ifnum,0);
2129
2130 mutex_init(&hdw->ctl_lock_mutex);
2131 mutex_init(&hdw->big_lock_mutex);
2132
2133 return hdw;
2134 fail:
2135 if (hdw) {
681c7399 2136 del_timer_sync(&hdw->quiescent_timer);
d913d630 2137 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2138 del_timer_sync(&hdw->encoder_wait_timer);
2139 if (hdw->workqueue) {
2140 flush_workqueue(hdw->workqueue);
2141 destroy_workqueue(hdw->workqueue);
2142 hdw->workqueue = NULL;
2143 }
5e55d2ce
MK		 2144 usb_free_urb(hdw->ctl_read_urb);
2145 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2146 kfree(hdw->ctl_read_buffer);
2147 kfree(hdw->ctl_write_buffer);
2148 kfree(hdw->controls);
2149 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2150 kfree(hdw->std_defs);
2151 kfree(hdw->std_enum_names);
d855497e
MI		 2152 kfree(hdw);
2153 }
a0fd1cb1 2154 return NULL;
d855497e
MI		 2155}
2156
2157
2158/* Remove _all_ associations between this driver and the underlying USB
2159 layer. */
07e337ee 2160static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2161{
2162 if (hdw->flag_disconnected) return;
2163 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2164 if (hdw->ctl_read_urb) {
2165 usb_kill_urb(hdw->ctl_read_urb);
2166 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2167 hdw->ctl_read_urb = NULL;
d855497e
MI		 2168 }
2169 if (hdw->ctl_write_urb) {
2170 usb_kill_urb(hdw->ctl_write_urb);
2171 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2172 hdw->ctl_write_urb = NULL;
d855497e
MI		 2173 }
2174 if (hdw->ctl_read_buffer) {
2175 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2176 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2177 }
2178 if (hdw->ctl_write_buffer) {
2179 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2180 hdw->ctl_write_buffer = NULL;
d855497e 2181 }
d855497e 2182 hdw->flag_disconnected = !0;
a0fd1cb1
MI		 2183 hdw->usb_dev = NULL;
2184 hdw->usb_intf = NULL;
681c7399 2185 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2186}
2187
2188
2189/* Destroy hardware interaction structure */
2190void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2191{
401c27ce 2192 if (!hdw) return;
d855497e 2193 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2194 if (hdw->workqueue) {
2195 flush_workqueue(hdw->workqueue);
2196 destroy_workqueue(hdw->workqueue);
2197 hdw->workqueue = NULL;
2198 }
8f59100a 2199 del_timer_sync(&hdw->quiescent_timer);
d913d630 2200 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2201 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2202 if (hdw->fw_buffer) {
2203 kfree(hdw->fw_buffer);
a0fd1cb1 2204 hdw->fw_buffer = NULL;
d855497e
MI		 2205 }
2206 if (hdw->vid_stream) {
2207 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2208 hdw->vid_stream = NULL;
d855497e 2209 }
d855497e
MI		 2210 if (hdw->decoder_ctrl) {
2211 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2212 }
2213 pvr2_i2c_core_done(hdw);
2214 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2215 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2216 if ((hdw->unit_number >= 0) &&
2217 (hdw->unit_number < PVR_NUM) &&
2218 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2219 unit_pointers[hdw->unit_number] = NULL;
d855497e 2220 }
8df0c87c 2221 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2222 kfree(hdw->controls);
2223 kfree(hdw->mpeg_ctrl_info);
2224 kfree(hdw->std_defs);
2225 kfree(hdw->std_enum_names);
d855497e
MI		 2226 kfree(hdw);
2227}
2228
2229
d855497e
MI		 2230int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2231{
2232 return (hdw && hdw->flag_ok);
2233}
2234
2235
2236/* Called when hardware has been unplugged */
2237void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2238{
2239 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2240 LOCK_TAKE(hdw->big_lock);
2241 LOCK_TAKE(hdw->ctl_lock);
2242 pvr2_hdw_remove_usb_stuff(hdw);
2243 LOCK_GIVE(hdw->ctl_lock);
2244 LOCK_GIVE(hdw->big_lock);
2245}
2246
2247
2248// Attempt to autoselect an appropriate value for std_enum_cur given
2249// whatever is currently in std_mask_cur
07e337ee 2250static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2251{
2252 unsigned int idx;
2253 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2254 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2255 hdw->std_enum_cur = idx;
2256 return;
2257 }
2258 }
2259 hdw->std_enum_cur = 0;
2260}
2261
2262
2263// Calculate correct set of enumerated standards based on currently known
2264// set of available standards bits.
07e337ee 2265static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2266{
2267 struct v4l2_standard *newstd;
2268 unsigned int std_cnt;
2269 unsigned int idx;
2270
2271 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2272
2273 if (hdw->std_defs) {
2274 kfree(hdw->std_defs);
a0fd1cb1 2275 hdw->std_defs = NULL;
d855497e
MI		 2276 }
2277 hdw->std_enum_cnt = 0;
2278 if (hdw->std_enum_names) {
2279 kfree(hdw->std_enum_names);
a0fd1cb1 2280 hdw->std_enum_names = NULL;
d855497e
MI		 2281 }
2282
2283 if (!std_cnt) {
2284 pvr2_trace(
2285 PVR2_TRACE_ERROR_LEGS,
2286 "WARNING: Failed to identify any viable standards");
2287 }
2288 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2289 hdw->std_enum_names[0] = "none";
2290 for (idx = 0; idx < std_cnt; idx++) {
2291 hdw->std_enum_names[idx+1] =
2292 newstd[idx].name;
2293 }
2294 // Set up the dynamic control for this standard
2295 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2296 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2297 hdw->std_defs = newstd;
2298 hdw->std_enum_cnt = std_cnt+1;
2299 hdw->std_enum_cur = 0;
2300 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2301}
2302
2303
2304int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2305 struct v4l2_standard *std,
2306 unsigned int idx)
2307{
2308 int ret = -EINVAL;
2309 if (!idx) return ret;
2310 LOCK_TAKE(hdw->big_lock); do {
2311 if (idx >= hdw->std_enum_cnt) break;
2312 idx--;
2313 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2314 ret = 0;
2315 } while (0); LOCK_GIVE(hdw->big_lock);
2316 return ret;
2317}
2318
2319
2320/* Get the number of defined controls */
2321unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2322{
c05c0462 2323 return hdw->control_cnt;
d855497e
MI		 2324}
2325
2326
2327/* Retrieve a control handle given its index (0..count-1) */
2328struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2329 unsigned int idx)
2330{
a0fd1cb1 2331 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2332 return hdw->controls + idx;
2333}
2334
2335
2336/* Retrieve a control handle given its index (0..count-1) */
2337struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2338 unsigned int ctl_id)
2339{
2340 struct pvr2_ctrl *cptr;
2341 unsigned int idx;
2342 int i;
2343
2344 /* This could be made a lot more efficient, but for now... */
c05c0462 2345 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2346 cptr = hdw->controls + idx;
2347 i = cptr->info->internal_id;
2348 if (i && (i == ctl_id)) return cptr;
2349 }
a0fd1cb1 2350 return NULL;
d855497e
MI		 2351}
2352
2353
a761f431 2354/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2355struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2356{
2357 struct pvr2_ctrl *cptr;
2358 unsigned int idx;
2359 int i;
2360
2361 /* This could be made a lot more efficient, but for now... */
c05c0462 2362 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2363 cptr = hdw->controls + idx;
2364 i = cptr->info->v4l_id;
2365 if (i && (i == ctl_id)) return cptr;
2366 }
a0fd1cb1 2367 return NULL;
d855497e
MI		 2368}
2369
2370
a761f431
MI		 2371/* Given a V4L ID for its immediate predecessor, retrieve the control
2372 structure associated with it. */
2373struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2374 unsigned int ctl_id)
2375{
2376 struct pvr2_ctrl *cptr,*cp2;
2377 unsigned int idx;
2378 int i;
2379
2380 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2381 cp2 = NULL;
a761f431
MI		 2382 for (idx = 0; idx < hdw->control_cnt; idx++) {
2383 cptr = hdw->controls + idx;
2384 i = cptr->info->v4l_id;
2385 if (!i) continue;
2386 if (i <= ctl_id) continue;
2387 if (cp2 && (cp2->info->v4l_id < i)) continue;
2388 cp2 = cptr;
2389 }
2390 return cp2;
a0fd1cb1 2391 return NULL;
a761f431
MI		 2392}
2393
2394
d855497e
MI		 2395static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2396{
2397 switch (tp) {
2398 case pvr2_ctl_int: return "integer";
2399 case pvr2_ctl_enum: return "enum";
33213963 2400 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2401 case pvr2_ctl_bitmask: return "bitmask";
2402 }
2403 return "";
2404}
2405
2406
681c7399
MI		 2407/* Figure out if we need to commit control changes. If so, mark internal
2408 state flags to indicate this fact and return true. Otherwise do nothing
2409 else and return false. */
2410static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 2411{
d855497e
MI		 2412 unsigned int idx;
2413 struct pvr2_ctrl *cptr;
2414 int value;
2415 int commit_flag = 0;
2416 char buf[100];
2417 unsigned int bcnt,ccnt;
2418
c05c0462 2419 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 2420 cptr = hdw->controls + idx;
5fa1247a 2421 if (!cptr->info->is_dirty) continue;
d855497e 2422 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 2423 commit_flag = !0;
d855497e 2424
fe23a280 2425 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 2426 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2427 cptr->info->name);
2428 value = 0;
2429 cptr->info->get_value(cptr,&value);
2430 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2431 buf+bcnt,
2432 sizeof(buf)-bcnt,&ccnt);
2433 bcnt += ccnt;
2434 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2435 get_ctrl_typename(cptr->info->type));
2436 pvr2_trace(PVR2_TRACE_CTL,
2437 "/*--TRACE_COMMIT--*/ %.*s",
2438 bcnt,buf);
2439 }
2440
2441 if (!commit_flag) {
2442 /* Nothing has changed */
2443 return 0;
2444 }
2445
681c7399
MI		 2446 hdw->state_pipeline_config = 0;
2447 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2448 pvr2_hdw_state_sched(hdw);
2449
2450 return !0;
2451}
2452
2453
2454/* Perform all operations needed to commit all control changes. This must
2455 be performed in synchronization with the pipeline state and is thus
2456 expected to be called as part of the driver's worker thread. Return
2457 true if commit successful, otherwise return false to indicate that
2458 commit isn't possible at this time. */
2459static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2460{
2461 unsigned int idx;
2462 struct pvr2_ctrl *cptr;
2463 int disruptive_change;
2464
ab062fe3
MI		 2465 /* Handle some required side effects when the video standard is
2466 changed.... */
d855497e 2467 if (hdw->std_dirty) {
d855497e 2468 int nvres;
00528d9c 2469 int gop_size;
d855497e
MI		 2470 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2471 nvres = 480;
00528d9c 2472 gop_size = 15;
d855497e
MI		 2473 } else {
2474 nvres = 576;
00528d9c 2475 gop_size = 12;
d855497e 2476 }
00528d9c
MI		 2477 /* Rewrite the vertical resolution to be appropriate to the
2478 video standard that has been selected. */
d855497e
MI		 2479 if (nvres != hdw->res_ver_val) {
2480 hdw->res_ver_val = nvres;
2481 hdw->res_ver_dirty = !0;
2482 }
00528d9c
MI		 2483 /* Rewrite the GOP size to be appropriate to the video
2484 standard that has been selected. */
2485 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
2486 struct v4l2_ext_controls cs;
2487 struct v4l2_ext_control c1;
2488 memset(&cs, 0, sizeof(cs));
2489 memset(&c1, 0, sizeof(c1));
2490 cs.controls = &c1;
2491 cs.count = 1;
2492 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
2493 c1.value = gop_size;
2494 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
2495 VIDIOC_S_EXT_CTRLS);
2496 }
d855497e
MI		 2497 }
2498
38d9a2cf 2499 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 2500 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
2501 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
2502 hdw->pathway_state)) {
2503 /* Change of mode being asked for... */
2504 hdw->state_pathway_ok = 0;
e9db1ff2 2505 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 2506 }
2507 if (!hdw->state_pathway_ok) {
2508 /* Can't commit anything until pathway is ok. */
2509 return 0;
2510 }
681c7399
MI		 2511 /* If any of the below has changed, then we can't do the update
2512 while the pipeline is running. Pipeline must be paused first
2513 and decoder -> encoder connection be made quiescent before we
2514 can proceed. */
2515 disruptive_change =
2516 (hdw->std_dirty ||
2517 hdw->enc_unsafe_stale ||
2518 hdw->srate_dirty ||
2519 hdw->res_ver_dirty ||
2520 hdw->res_hor_dirty ||
2521 hdw->input_dirty ||
2522 (hdw->active_stream_type != hdw->desired_stream_type));
2523 if (disruptive_change && !hdw->state_pipeline_idle) {
2524 /* Pipeline is not idle; we can't proceed. Arrange to
2525 cause pipeline to stop so that we can try this again
2526 later.... */
2527 hdw->state_pipeline_pause = !0;
2528 return 0;
275b2e28
PK		 2529 }
2530
b30d2441
MI		 2531 if (hdw->srate_dirty) {
2532 /* Write new sample rate into control structure since
2533 * the master copy is stale. We must track srate
2534 * separate from the mpeg control structure because
2535 * other logic also uses this value. */
2536 struct v4l2_ext_controls cs;
2537 struct v4l2_ext_control c1;
2538 memset(&cs,0,sizeof(cs));
2539 memset(&c1,0,sizeof(c1));
2540 cs.controls = &c1;
2541 cs.count = 1;
2542 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2543 c1.value = hdw->srate_val;
01f1e44f 2544 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 2545 }
c05c0462 2546
d855497e
MI		 2547 /* Scan i2c core at this point - before we clear all the dirty
2548 bits. Various parts of the i2c core will notice dirty bits as
2549 appropriate and arrange to broadcast or directly send updates to
2550 the client drivers in order to keep everything in sync */
2551 pvr2_i2c_core_check_stale(hdw);
2552
c05c0462 2553 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2554 cptr = hdw->controls + idx;
2555 if (!cptr->info->clear_dirty) continue;
2556 cptr->info->clear_dirty(cptr);
2557 }
2558
681c7399
MI		 2559 if (hdw->active_stream_type != hdw->desired_stream_type) {
2560 /* Handle any side effects of stream config here */
2561 hdw->active_stream_type = hdw->desired_stream_type;
2562 }
2563
1df59f0b
MI		 2564 if (hdw->hdw_desc->signal_routing_scheme ==
2565 PVR2_ROUTING_SCHEME_GOTVIEW) {
2566 u32 b;
2567 /* Handle GOTVIEW audio switching */
2568 pvr2_hdw_gpio_get_out(hdw,&b);
2569 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2570 /* Set GPIO 11 */
2571 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
2572 } else {
2573 /* Clear GPIO 11 */
2574 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
2575 }
2576 }
2577
d855497e
MI		 2578 /* Now execute i2c core update */
2579 pvr2_i2c_core_sync(hdw);
2580
62433e31
MI		 2581 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
2582 hdw->state_encoder_run) {
2583 /* If encoder isn't running or it can't be touched, then
2584 this will get worked out later when we start the
2585 encoder. */
681c7399
MI		 2586 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2587 }
d855497e 2588
681c7399
MI		 2589 hdw->state_pipeline_config = !0;
2590 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2591 return !0;
d855497e
MI		 2592}
2593
2594
2595int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2596{
681c7399
MI		 2597 int fl;
2598 LOCK_TAKE(hdw->big_lock);
2599 fl = pvr2_hdw_commit_setup(hdw);
2600 LOCK_GIVE(hdw->big_lock);
2601 if (!fl) return 0;
2602 return pvr2_hdw_wait(hdw,0);
2603}
2604
2605
2606static void pvr2_hdw_worker_i2c(struct work_struct *work)
2607{
2608 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
d855497e 2609 LOCK_TAKE(hdw->big_lock); do {
681c7399 2610 pvr2_i2c_core_sync(hdw);
d855497e 2611 } while (0); LOCK_GIVE(hdw->big_lock);
d855497e
MI		 2612}
2613
2614
681c7399 2615static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 2616{
681c7399
MI		 2617 int fl = 0;
2618 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 2619 LOCK_TAKE(hdw->big_lock); do {
681c7399 2620 fl = pvr2_hdw_state_eval(hdw);
d855497e 2621 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 2622 if (fl && hdw->state_func) {
2623 hdw->state_func(hdw->state_data);
2624 }
d855497e
MI		 2625}
2626
2627
681c7399 2628static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 2629{
681c7399
MI		 2630 return wait_event_interruptible(
2631 hdw->state_wait_data,
2632 (hdw->state_stale == 0) &&
2633 (!state || (hdw->master_state != state)));
2634}
2635
2636
d855497e
MI		 2637/* Return name for this driver instance */
2638const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2639{
2640 return hdw->name;
2641}
2642
2643
78a47101
MI		 2644const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2645{
2646 return hdw->hdw_desc->description;
2647}
2648
2649
2650const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2651{
2652 return hdw->hdw_desc->shortname;
2653}
2654
2655
d855497e
MI		 2656int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2657{
2658 int result;
2659 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 2660 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 2661 result = pvr2_send_request(hdw,
2662 hdw->cmd_buffer,1,
2663 hdw->cmd_buffer,1);
2664 if (result < 0) break;
2665 result = (hdw->cmd_buffer[0] != 0);
2666 } while(0); LOCK_GIVE(hdw->ctl_lock);
2667 return result;
2668}
2669
2670
18103c57
MI		 2671/* Execute poll of tuner status */
2672void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 2673{
d855497e 2674 LOCK_TAKE(hdw->big_lock); do {
18103c57 2675 pvr2_i2c_core_status_poll(hdw);
d855497e 2676 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 2677}
2678
2679
2680/* Return information about the tuner */
2681int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2682{
2683 LOCK_TAKE(hdw->big_lock); do {
2684 if (hdw->tuner_signal_stale) {
2685 pvr2_i2c_core_status_poll(hdw);
2686 }
2687 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2688 } while (0); LOCK_GIVE(hdw->big_lock);
2689 return 0;
d855497e
MI		 2690}
2691
2692
2693/* Get handle to video output stream */
2694struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2695{
2696 return hp->vid_stream;
2697}
2698
2699
2700void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2701{
4f1a3e5b 2702 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e
MI		 2703 LOCK_TAKE(hdw->big_lock); do {
2704 hdw->log_requested = !0;
4f1a3e5b 2705 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
d855497e
MI		 2706 pvr2_i2c_core_check_stale(hdw);
2707 hdw->log_requested = 0;
2708 pvr2_i2c_core_sync(hdw);
b30d2441 2709 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 2710 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 2711 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 2712 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 2713 } while (0); LOCK_GIVE(hdw->big_lock);
2714}
2715
4db666cc
MI		 2716
2717/* Grab EEPROM contents, needed for direct method. */
2718#define EEPROM_SIZE 8192
2719#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2720static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2721{
2722 struct i2c_msg msg[2];
2723 u8 *eeprom;
2724 u8 iadd[2];
2725 u8 addr;
2726 u16 eepromSize;
2727 unsigned int offs;
2728 int ret;
2729 int mode16 = 0;
2730 unsigned pcnt,tcnt;
2731 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2732 if (!eeprom) {
2733 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2734 "Failed to allocate memory"
2735 " required to read eeprom");
2736 return NULL;
2737 }
2738
2739 trace_eeprom("Value for eeprom addr from controller was 0x%x",
2740 hdw->eeprom_addr);
2741 addr = hdw->eeprom_addr;
2742 /* Seems that if the high bit is set, then the *real* eeprom
2743 address is shifted right now bit position (noticed this in
2744 newer PVR USB2 hardware) */
2745 if (addr & 0x80) addr >>= 1;
2746
2747 /* FX2 documentation states that a 16bit-addressed eeprom is
2748 expected if the I2C address is an odd number (yeah, this is
2749 strange but it's what they do) */
2750 mode16 = (addr & 1);
2751 eepromSize = (mode16 ? EEPROM_SIZE : 256);
2752 trace_eeprom("Examining %d byte eeprom at location 0x%x"
2753 " using %d bit addressing",eepromSize,addr,
2754 mode16 ? 16 : 8);
2755
2756 msg[0].addr = addr;
2757 msg[0].flags = 0;
2758 msg[0].len = mode16 ? 2 : 1;
2759 msg[0].buf = iadd;
2760 msg[1].addr = addr;
2761 msg[1].flags = I2C_M_RD;
2762
2763 /* We have to do the actual eeprom data fetch ourselves, because
2764 (1) we're only fetching part of the eeprom, and (2) if we were
2765 getting the whole thing our I2C driver can't grab it in one
2766 pass - which is what tveeprom is otherwise going to attempt */
2767 memset(eeprom,0,EEPROM_SIZE);
2768 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2769 pcnt = 16;
2770 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2771 offs = tcnt + (eepromSize - EEPROM_SIZE);
2772 if (mode16) {
2773 iadd[0] = offs >> 8;
2774 iadd[1] = offs;
2775 } else {
2776 iadd[0] = offs;
2777 }
2778 msg[1].len = pcnt;
2779 msg[1].buf = eeprom+tcnt;
2780 if ((ret = i2c_transfer(&hdw->i2c_adap,
2781 msg,ARRAY_SIZE(msg))) != 2) {
2782 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2783 "eeprom fetch set offs err=%d",ret);
2784 kfree(eeprom);
2785 return NULL;
2786 }
2787 }
2788 return eeprom;
2789}
2790
2791
2792void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2793 int prom_flag,
2794 int enable_flag)
d855497e
MI		 2795{
2796 int ret;
2797 u16 address;
2798 unsigned int pipe;
2799 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 2800 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 2801
2802 if (!enable_flag) {
2803 pvr2_trace(PVR2_TRACE_FIRMWARE,
2804 "Cleaning up after CPU firmware fetch");
2805 kfree(hdw->fw_buffer);
a0fd1cb1 2806 hdw->fw_buffer = NULL;
d855497e 2807 hdw->fw_size = 0;
4db666cc
MI		 2808 if (hdw->fw_cpu_flag) {
2809 /* Now release the CPU. It will disconnect
2810 and reconnect later. */
2811 pvr2_hdw_cpureset_assert(hdw,0);
2812 }
d855497e
MI		 2813 break;
2814 }
2815
4db666cc
MI		 2816 hdw->fw_cpu_flag = (prom_flag == 0);
2817 if (hdw->fw_cpu_flag) {
2818 pvr2_trace(PVR2_TRACE_FIRMWARE,
2819 "Preparing to suck out CPU firmware");
2820 hdw->fw_size = 0x2000;
2821 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2822 if (!hdw->fw_buffer) {
2823 hdw->fw_size = 0;
2824 break;
2825 }
d855497e 2826
4db666cc
MI		 2827 /* We have to hold the CPU during firmware upload. */
2828 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 2829
4db666cc
MI		 2830 /* download the firmware from address 0000-1fff in 2048
2831 (=0x800) bytes chunk. */
d855497e 2832
4db666cc
MI		 2833 pvr2_trace(PVR2_TRACE_FIRMWARE,
2834 "Grabbing CPU firmware");
2835 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2836 for(address = 0; address < hdw->fw_size;
2837 address += 0x800) {
2838 ret = usb_control_msg(hdw->usb_dev,pipe,
2839 0xa0,0xc0,
2840 address,0,
2841 hdw->fw_buffer+address,
2842 0x800,HZ);
2843 if (ret < 0) break;
2844 }
d855497e 2845
4db666cc
MI		 2846 pvr2_trace(PVR2_TRACE_FIRMWARE,
2847 "Done grabbing CPU firmware");
2848 } else {
2849 pvr2_trace(PVR2_TRACE_FIRMWARE,
2850 "Sucking down EEPROM contents");
2851 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2852 if (!hdw->fw_buffer) {
2853 pvr2_trace(PVR2_TRACE_FIRMWARE,
2854 "EEPROM content suck failed.");
2855 break;
2856 }
2857 hdw->fw_size = EEPROM_SIZE;
2858 pvr2_trace(PVR2_TRACE_FIRMWARE,
2859 "Done sucking down EEPROM contents");
2860 }
d855497e
MI		 2861
2862 } while (0); LOCK_GIVE(hdw->big_lock);
2863}
2864
2865
2866/* Return true if we're in a mode for retrieval CPU firmware */
2867int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2868{
5fa1247a 2869 return hdw->fw_buffer != NULL;
d855497e
MI		 2870}
2871
2872
2873int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2874 char *buf,unsigned int cnt)
2875{
2876 int ret = -EINVAL;
2877 LOCK_TAKE(hdw->big_lock); do {
2878 if (!buf) break;
2879 if (!cnt) break;
2880
2881 if (!hdw->fw_buffer) {
2882 ret = -EIO;
2883 break;
2884 }
2885
2886 if (offs >= hdw->fw_size) {
2887 pvr2_trace(PVR2_TRACE_FIRMWARE,
2888 "Read firmware data offs=%d EOF",
2889 offs);
2890 ret = 0;
2891 break;
2892 }
2893
2894 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2895
2896 memcpy(buf,hdw->fw_buffer+offs,cnt);
2897
2898 pvr2_trace(PVR2_TRACE_FIRMWARE,
2899 "Read firmware data offs=%d cnt=%d",
2900 offs,cnt);
2901 ret = cnt;
2902 } while (0); LOCK_GIVE(hdw->big_lock);
2903
2904 return ret;
2905}
2906
2907
fd5a75fe 2908int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 2909 enum pvr2_v4l_type index)
d855497e 2910{
fd5a75fe 2911 switch (index) {
8079384e
MI		 2912 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2913 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2914 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 2915 default: return -1;
2916 }
d855497e
MI		 2917}
2918
2919
2fdf3d9c 2920/* Store a v4l minor device number */
fd5a75fe 2921void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 2922 enum pvr2_v4l_type index,int v)
d855497e 2923{
fd5a75fe 2924 switch (index) {
8079384e
MI		 2925 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2926 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2927 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 2928 default: break;
2929 }
d855497e
MI		 2930}
2931
2932
7d12e780 2933static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 2934{
2935 struct pvr2_hdw *hdw = urb->context;
2936 hdw->ctl_write_pend_flag = 0;
2937 if (hdw->ctl_read_pend_flag) return;
2938 complete(&hdw->ctl_done);
2939}
2940
2941
7d12e780 2942static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 2943{
2944 struct pvr2_hdw *hdw = urb->context;
2945 hdw->ctl_read_pend_flag = 0;
2946 if (hdw->ctl_write_pend_flag) return;
2947 complete(&hdw->ctl_done);
2948}
2949
2950
2951static void pvr2_ctl_timeout(unsigned long data)
2952{
2953 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2954 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2955 hdw->ctl_timeout_flag = !0;
5e55d2ce 2956 if (hdw->ctl_write_pend_flag)
d855497e 2957 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 2958 if (hdw->ctl_read_pend_flag)
d855497e 2959 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 2960 }
2961}
2962
2963
e61b6fc5
MI		 2964/* Issue a command and get a response from the device. This extended
2965 version includes a probe flag (which if set means that device errors
2966 should not be logged or treated as fatal) and a timeout in jiffies.
2967 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 2968static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2969 unsigned int timeout,int probe_fl,
2970 void *write_data,unsigned int write_len,
2971 void *read_data,unsigned int read_len)
d855497e
MI		 2972{
2973 unsigned int idx;
2974 int status = 0;
2975 struct timer_list timer;
2976 if (!hdw->ctl_lock_held) {
2977 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2978 "Attempted to execute control transfer"
2979 " without lock!!");
2980 return -EDEADLK;
2981 }
681c7399 2982 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 2983 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2984 "Attempted to execute control transfer"
2985 " when device not ok");
2986 return -EIO;
2987 }
2988 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2989 if (!probe_fl) {
2990 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2991 "Attempted to execute control transfer"
2992 " when USB is disconnected");
2993 }
2994 return -ENOTTY;
2995 }
2996
2997 /* Ensure that we have sane parameters */
2998 if (!write_data) write_len = 0;
2999 if (!read_data) read_len = 0;
3000 if (write_len > PVR2_CTL_BUFFSIZE) {
3001 pvr2_trace(
3002 PVR2_TRACE_ERROR_LEGS,
3003 "Attempted to execute %d byte"
3004 " control-write transfer (limit=%d)",
3005 write_len,PVR2_CTL_BUFFSIZE);
3006 return -EINVAL;
3007 }
3008 if (read_len > PVR2_CTL_BUFFSIZE) {
3009 pvr2_trace(
3010 PVR2_TRACE_ERROR_LEGS,
3011 "Attempted to execute %d byte"
3012 " control-read transfer (limit=%d)",
3013 write_len,PVR2_CTL_BUFFSIZE);
3014 return -EINVAL;
3015 }
3016 if ((!write_len) && (!read_len)) {
3017 pvr2_trace(
3018 PVR2_TRACE_ERROR_LEGS,
3019 "Attempted to execute null control transfer?");
3020 return -EINVAL;
3021 }
3022
3023
3024 hdw->cmd_debug_state = 1;
3025 if (write_len) {
3026 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3027 } else {
3028 hdw->cmd_debug_code = 0;
3029 }
3030 hdw->cmd_debug_write_len = write_len;
3031 hdw->cmd_debug_read_len = read_len;
3032
3033 /* Initialize common stuff */
3034 init_completion(&hdw->ctl_done);
3035 hdw->ctl_timeout_flag = 0;
3036 hdw->ctl_write_pend_flag = 0;
3037 hdw->ctl_read_pend_flag = 0;
3038 init_timer(&timer);
3039 timer.expires = jiffies + timeout;
3040 timer.data = (unsigned long)hdw;
3041 timer.function = pvr2_ctl_timeout;
3042
3043 if (write_len) {
3044 hdw->cmd_debug_state = 2;
3045 /* Transfer write data to internal buffer */
3046 for (idx = 0; idx < write_len; idx++) {
3047 hdw->ctl_write_buffer[idx] =
3048 ((unsigned char *)write_data)[idx];
3049 }
3050 /* Initiate a write request */
3051 usb_fill_bulk_urb(hdw->ctl_write_urb,
3052 hdw->usb_dev,
3053 usb_sndbulkpipe(hdw->usb_dev,
3054 PVR2_CTL_WRITE_ENDPOINT),
3055 hdw->ctl_write_buffer,
3056 write_len,
3057 pvr2_ctl_write_complete,
3058 hdw);
3059 hdw->ctl_write_urb->actual_length = 0;
3060 hdw->ctl_write_pend_flag = !0;
3061 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3062 if (status < 0) {
3063 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3064 "Failed to submit write-control"
3065 " URB status=%d",status);
3066 hdw->ctl_write_pend_flag = 0;
3067 goto done;
3068 }
3069 }
3070
3071 if (read_len) {
3072 hdw->cmd_debug_state = 3;
3073 memset(hdw->ctl_read_buffer,0x43,read_len);
3074 /* Initiate a read request */
3075 usb_fill_bulk_urb(hdw->ctl_read_urb,
3076 hdw->usb_dev,
3077 usb_rcvbulkpipe(hdw->usb_dev,
3078 PVR2_CTL_READ_ENDPOINT),
3079 hdw->ctl_read_buffer,
3080 read_len,
3081 pvr2_ctl_read_complete,
3082 hdw);
3083 hdw->ctl_read_urb->actual_length = 0;
3084 hdw->ctl_read_pend_flag = !0;
3085 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3086 if (status < 0) {
3087 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3088 "Failed to submit read-control"
3089 " URB status=%d",status);
3090 hdw->ctl_read_pend_flag = 0;
3091 goto done;
3092 }
3093 }
3094
3095 /* Start timer */
3096 add_timer(&timer);
3097
3098 /* Now wait for all I/O to complete */
3099 hdw->cmd_debug_state = 4;
3100 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3101 wait_for_completion(&hdw->ctl_done);
3102 }
3103 hdw->cmd_debug_state = 5;
3104
3105 /* Stop timer */
3106 del_timer_sync(&timer);
3107
3108 hdw->cmd_debug_state = 6;
3109 status = 0;
3110
3111 if (hdw->ctl_timeout_flag) {
3112 status = -ETIMEDOUT;
3113 if (!probe_fl) {
3114 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3115 "Timed out control-write");
3116 }
3117 goto done;
3118 }
3119
3120 if (write_len) {
3121 /* Validate results of write request */
3122 if ((hdw->ctl_write_urb->status != 0) &&
3123 (hdw->ctl_write_urb->status != -ENOENT) &&
3124 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3125 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3126 /* USB subsystem is reporting some kind of failure
3127 on the write */
3128 status = hdw->ctl_write_urb->status;
3129 if (!probe_fl) {
3130 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3131 "control-write URB failure,"
3132 " status=%d",
3133 status);
3134 }
3135 goto done;
3136 }
3137 if (hdw->ctl_write_urb->actual_length < write_len) {
3138 /* Failed to write enough data */
3139 status = -EIO;
3140 if (!probe_fl) {
3141 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3142 "control-write URB short,"
3143 " expected=%d got=%d",
3144 write_len,
3145 hdw->ctl_write_urb->actual_length);
3146 }
3147 goto done;
3148 }
3149 }
3150 if (read_len) {
3151 /* Validate results of read request */
3152 if ((hdw->ctl_read_urb->status != 0) &&
3153 (hdw->ctl_read_urb->status != -ENOENT) &&
3154 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3155 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3156 /* USB subsystem is reporting some kind of failure
3157 on the read */
3158 status = hdw->ctl_read_urb->status;
3159 if (!probe_fl) {
3160 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3161 "control-read URB failure,"
3162 " status=%d",
3163 status);
3164 }
3165 goto done;
3166 }
3167 if (hdw->ctl_read_urb->actual_length < read_len) {
3168 /* Failed to read enough data */
3169 status = -EIO;
3170 if (!probe_fl) {
3171 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3172 "control-read URB short,"
3173 " expected=%d got=%d",
3174 read_len,
3175 hdw->ctl_read_urb->actual_length);
3176 }
3177 goto done;
3178 }
3179 /* Transfer retrieved data out from internal buffer */
3180 for (idx = 0; idx < read_len; idx++) {
3181 ((unsigned char *)read_data)[idx] =
3182 hdw->ctl_read_buffer[idx];
3183 }
3184 }
3185
3186 done:
3187
3188 hdw->cmd_debug_state = 0;
3189 if ((status < 0) && (!probe_fl)) {
681c7399 3190 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3191 }
3192 return status;
3193}
3194
3195
3196int pvr2_send_request(struct pvr2_hdw *hdw,
3197 void *write_data,unsigned int write_len,
3198 void *read_data,unsigned int read_len)
3199{
3200 return pvr2_send_request_ex(hdw,HZ*4,0,
3201 write_data,write_len,
3202 read_data,read_len);
3203}
3204
1c9d10d4
MI		 3205
3206static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3207{
3208 int ret;
3209 unsigned int cnt = 1;
3210 unsigned int args = 0;
3211 LOCK_TAKE(hdw->ctl_lock);
3212 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3213 args = (cmdcode >> 8) & 0xffu;
3214 args = (args > 2) ? 2 : args;
3215 if (args) {
3216 cnt += args;
3217 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3218 if (args > 1) {
3219 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3220 }
3221 }
3222 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3223 unsigned int idx;
3224 unsigned int ccnt,bcnt;
3225 char tbuf[50];
3226 cmdcode &= 0xffu;
3227 bcnt = 0;
3228 ccnt = scnprintf(tbuf+bcnt,
3229 sizeof(tbuf)-bcnt,
3230 "Sending FX2 command 0x%x",cmdcode);
3231 bcnt += ccnt;
3232 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3233 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3234 ccnt = scnprintf(tbuf+bcnt,
3235 sizeof(tbuf)-bcnt,
3236 " \"%s\"",
3237 pvr2_fx2cmd_desc[idx].desc);
3238 bcnt += ccnt;
3239 break;
3240 }
3241 }
3242 if (args) {
3243 ccnt = scnprintf(tbuf+bcnt,
3244 sizeof(tbuf)-bcnt,
3245 " (%u",hdw->cmd_buffer[1]);
3246 bcnt += ccnt;
3247 if (args > 1) {
3248 ccnt = scnprintf(tbuf+bcnt,
3249 sizeof(tbuf)-bcnt,
3250 ",%u",hdw->cmd_buffer[2]);
3251 bcnt += ccnt;
3252 }
3253 ccnt = scnprintf(tbuf+bcnt,
3254 sizeof(tbuf)-bcnt,
3255 ")");
3256 bcnt += ccnt;
3257 }
3258 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3259 }
3260 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3261 LOCK_GIVE(hdw->ctl_lock);
3262 return ret;
3263}
3264
3265
d855497e
MI		 3266int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3267{
3268 int ret;
3269
3270 LOCK_TAKE(hdw->ctl_lock);
3271
8d364363 3272 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3273 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3274 hdw->cmd_buffer[5] = 0;
3275 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3276 hdw->cmd_buffer[7] = reg & 0xff;
3277
3278
3279 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3280
3281 LOCK_GIVE(hdw->ctl_lock);
3282
3283 return ret;
3284}
3285
3286
07e337ee 3287static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3288{
3289 int ret = 0;
3290
3291 LOCK_TAKE(hdw->ctl_lock);
3292
8d364363 3293 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 3294 hdw->cmd_buffer[1] = 0;
3295 hdw->cmd_buffer[2] = 0;
3296 hdw->cmd_buffer[3] = 0;
3297 hdw->cmd_buffer[4] = 0;
3298 hdw->cmd_buffer[5] = 0;
3299 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3300 hdw->cmd_buffer[7] = reg & 0xff;
3301
3302 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3303 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3304
3305 LOCK_GIVE(hdw->ctl_lock);
3306
3307 return ret;
3308}
3309
3310
681c7399 3311void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 3312{
3313 if (!hdw->flag_ok) return;
681c7399
MI		 3314 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3315 "Device being rendered inoperable");
d855497e 3316 if (hdw->vid_stream) {
a0fd1cb1 3317 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 3318 }
681c7399
MI		 3319 hdw->flag_ok = 0;
3320 trace_stbit("flag_ok",hdw->flag_ok);
3321 pvr2_hdw_state_sched(hdw);
d855497e
MI		 3322}
3323
3324
3325void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3326{
3327 int ret;
3328 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 3329 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
d855497e
MI		 3330 if (ret == 1) {
3331 ret = usb_reset_device(hdw->usb_dev);
3332 usb_unlock_device(hdw->usb_dev);
3333 } else {
3334 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3335 "Failed to lock USB device ret=%d",ret);
3336 }
3337 if (init_pause_msec) {
3338 pvr2_trace(PVR2_TRACE_INFO,
3339 "Waiting %u msec for hardware to settle",
3340 init_pause_msec);
3341 msleep(init_pause_msec);
3342 }
3343
3344}
3345
3346
3347void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3348{
3349 char da[1];
3350 unsigned int pipe;
3351 int ret;
3352
3353 if (!hdw->usb_dev) return;
3354
3355 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3356
3357 da[0] = val ? 0x01 : 0x00;
3358
3359 /* Write the CPUCS register on the 8051. The lsb of the register
3360 is the reset bit; a 1 asserts reset while a 0 clears it. */
3361 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3362 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3363 if (ret < 0) {
3364 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3365 "cpureset_assert(%d) error=%d",val,ret);
3366 pvr2_hdw_render_useless(hdw);
3367 }
3368}
3369
3370
3371int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3372{
1c9d10d4 3373 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 3374}
3375
3376
e1edb19a
MK		 3377int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3378{
1c9d10d4 3379 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 3380}
3381
1c9d10d4 3382
e1edb19a
MK		 3383int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3384{
1c9d10d4 3385 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 3386}
3387
d855497e
MI		 3388
3389int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3390{
3391 if (!hdw->decoder_ctrl) {
3392 pvr2_trace(PVR2_TRACE_INIT,
3393 "Unable to reset decoder: nothing attached");
3394 return -ENOTTY;
3395 }
3396
3397 if (!hdw->decoder_ctrl->force_reset) {
3398 pvr2_trace(PVR2_TRACE_INIT,
3399 "Unable to reset decoder: not implemented");
3400 return -ENOTTY;
3401 }
3402
3403 pvr2_trace(PVR2_TRACE_INIT,
3404 "Requesting decoder reset");
3405 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3406 return 0;
3407}
3408
3409
62433e31 3410static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 3411{
1c9d10d4
MI		 3412 hdw->flag_ok = !0;
3413 return pvr2_issue_simple_cmd(hdw,
3414 FX2CMD_HCW_DEMOD_RESETIN |
3415 (1 << 8) |
3416 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 3417}
3418
84147f3d 3419
62433e31 3420static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 3421{
1c9d10d4
MI		 3422 hdw->flag_ok = !0;
3423 return pvr2_issue_simple_cmd(hdw,(onoff ?
3424 FX2CMD_ONAIR_DTV_POWER_ON :
3425 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 3426}
3427
62433e31
MI		 3428
3429static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
3430 int onoff)
84147f3d 3431{
1c9d10d4
MI		 3432 return pvr2_issue_simple_cmd(hdw,(onoff ?
3433 FX2CMD_ONAIR_DTV_STREAMING_ON :
3434 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 3435}
3436
62433e31
MI		 3437
3438static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
3439{
3440 int cmode;
3441 /* Compare digital/analog desired setting with current setting. If
3442 they don't match, fix it... */
3443 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
3444 if (cmode == hdw->pathway_state) {
3445 /* They match; nothing to do */
3446 return;
3447 }
3448
3449 switch (hdw->hdw_desc->digital_control_scheme) {
3450 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3451 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
3452 if (cmode == PVR2_PATHWAY_ANALOG) {
3453 /* If moving to analog mode, also force the decoder
3454 to reset. If no decoder is attached, then it's
3455 ok to ignore this because if/when the decoder
3456 attaches, it will reset itself at that time. */
3457 pvr2_hdw_cmd_decoder_reset(hdw);
3458 }
3459 break;
3460 case PVR2_DIGITAL_SCHEME_ONAIR:
3461 /* Supposedly we should always have the power on whether in
3462 digital or analog mode. But for now do what appears to
3463 work... */
bb0c2fe0 3464 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 3465 break;
3466 default: break;
3467 }
3468
1b9c18c5 3469 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 3470 hdw->pathway_state = cmode;
3471}
3472
3473
e9b59f6e 3474static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 3475{
3476 /* change some GPIO data
3477 *
3478 * note: bit d7 of dir appears to control the LED,
3479 * so we shut it off here.
3480 *
c55a97d7 3481 */
40381cb0 3482 if (onoff) {
c55a97d7 3483 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 3484 } else {
c55a97d7 3485 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 3486 }
c55a97d7 3487 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 3488}
c55a97d7 3489
40381cb0
MI		 3490
3491typedef void (*led_method_func)(struct pvr2_hdw *,int);
3492
3493static led_method_func led_methods[] = {
3494 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
3495};
3496
3497
3498/* Toggle LED */
3499static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
3500{
3501 unsigned int scheme_id;
3502 led_method_func fp;
3503
3504 if ((!onoff) == (!hdw->led_on)) return;
3505
3506 hdw->led_on = onoff != 0;
3507
3508 scheme_id = hdw->hdw_desc->led_scheme;
3509 if (scheme_id < ARRAY_SIZE(led_methods)) {
3510 fp = led_methods[scheme_id];
3511 } else {
3512 fp = NULL;
3513 }
3514
3515 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 3516}
3517
3518
e61b6fc5 3519/* Stop / start video stream transport */
07e337ee 3520static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 3521{
bb0c2fe0
MI		 3522 int ret;
3523
3524 /* If we're in analog mode, then just issue the usual analog
3525 command. */
3526 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3527 return pvr2_issue_simple_cmd(hdw,
3528 (runFl ?
3529 FX2CMD_STREAMING_ON :
3530 FX2CMD_STREAMING_OFF));
3531 /*Note: Not reached */
3532 }
3533
3534 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
3535 /* Whoops, we don't know what mode we're in... */
3536 return -EINVAL;
3537 }
3538
3539 /* To get here we have to be in digital mode. The mechanism here
3540 is unfortunately different for different vendors. So we switch
3541 on the device's digital scheme attribute in order to figure out
3542 what to do. */
3543 switch (hdw->hdw_desc->digital_control_scheme) {
3544 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3545 return pvr2_issue_simple_cmd(hdw,
3546 (runFl ?
3547 FX2CMD_HCW_DTV_STREAMING_ON :
3548 FX2CMD_HCW_DTV_STREAMING_OFF));
3549 case PVR2_DIGITAL_SCHEME_ONAIR:
3550 ret = pvr2_issue_simple_cmd(hdw,
3551 (runFl ?
3552 FX2CMD_STREAMING_ON :
3553 FX2CMD_STREAMING_OFF));
3554 if (ret) return ret;
3555 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
3556 default:
3557 return -EINVAL;
62433e31 3558 }
d855497e
MI		 3559}
3560
3561
62433e31
MI		 3562/* Evaluate whether or not state_pathway_ok can change */
3563static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
3564{
3565 if (hdw->state_pathway_ok) {
3566 /* Nothing to do if pathway is already ok */
3567 return 0;
3568 }
3569 if (!hdw->state_pipeline_idle) {
3570 /* Not allowed to change anything if pipeline is not idle */
3571 return 0;
3572 }
3573 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
3574 hdw->state_pathway_ok = !0;
e9db1ff2 3575 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3576 return !0;
3577}
3578
3579
681c7399
MI		 3580/* Evaluate whether or not state_encoder_ok can change */
3581static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3582{
3583 if (hdw->state_encoder_ok) return 0;
3584 if (hdw->flag_tripped) return 0;
3585 if (hdw->state_encoder_run) return 0;
3586 if (hdw->state_encoder_config) return 0;
3587 if (hdw->state_decoder_run) return 0;
3588 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 3589 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
3590 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
3591 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
3592 return 0;
3593 }
3594
681c7399
MI		 3595 if (pvr2_upload_firmware2(hdw) < 0) {
3596 hdw->flag_tripped = !0;
3597 trace_stbit("flag_tripped",hdw->flag_tripped);
3598 return !0;
3599 }
3600 hdw->state_encoder_ok = !0;
3601 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3602 return !0;
3603}
3604
3605
3606/* Evaluate whether or not state_encoder_config can change */
3607static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3608{
3609 if (hdw->state_encoder_config) {
3610 if (hdw->state_encoder_ok) {
3611 if (hdw->state_pipeline_req &&
3612 !hdw->state_pipeline_pause) return 0;
3613 }
3614 hdw->state_encoder_config = 0;
3615 hdw->state_encoder_waitok = 0;
3616 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3617 /* paranoia - solve race if timer just completed */
3618 del_timer_sync(&hdw->encoder_wait_timer);
3619 } else {
62433e31
MI		 3620 if (!hdw->state_pathway_ok ||
3621 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3622 !hdw->state_encoder_ok ||
681c7399
MI		 3623 !hdw->state_pipeline_idle ||
3624 hdw->state_pipeline_pause ||
3625 !hdw->state_pipeline_req ||
3626 !hdw->state_pipeline_config) {
3627 /* We must reset the enforced wait interval if
3628 anything has happened that might have disturbed
3629 the encoder. This should be a rare case. */
3630 if (timer_pending(&hdw->encoder_wait_timer)) {
3631 del_timer_sync(&hdw->encoder_wait_timer);
3632 }
3633 if (hdw->state_encoder_waitok) {
3634 /* Must clear the state - therefore we did
3635 something to a state bit and must also
3636 return true. */
3637 hdw->state_encoder_waitok = 0;
3638 trace_stbit("state_encoder_waitok",
3639 hdw->state_encoder_waitok);
3640 return !0;
3641 }
3642 return 0;
3643 }
3644 if (!hdw->state_encoder_waitok) {
3645 if (!timer_pending(&hdw->encoder_wait_timer)) {
3646 /* waitok flag wasn't set and timer isn't
3647 running. Check flag once more to avoid
3648 a race then start the timer. This is
3649 the point when we measure out a minimal
3650 quiet interval before doing something to
3651 the encoder. */
3652 if (!hdw->state_encoder_waitok) {
3653 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 3654 jiffies +
3655 (HZ * TIME_MSEC_ENCODER_WAIT
3656 / 1000);
681c7399
MI		 3657 add_timer(&hdw->encoder_wait_timer);
3658 }
3659 }
3660 /* We can't continue until we know we have been
3661 quiet for the interval measured by this
3662 timer. */
3663 return 0;
3664 }
3665 pvr2_encoder_configure(hdw);
3666 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3667 }
3668 trace_stbit("state_encoder_config",hdw->state_encoder_config);
3669 return !0;
3670}
3671
3672
d913d630
MI		 3673/* Return true if the encoder should not be running. */
3674static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
3675{
3676 if (!hdw->state_encoder_ok) {
3677 /* Encoder isn't healthy at the moment, so stop it. */
3678 return !0;
3679 }
3680 if (!hdw->state_pathway_ok) {
3681 /* Mode is not understood at the moment (i.e. it wants to
3682 change), so encoder must be stopped. */
3683 return !0;
3684 }
3685
3686 switch (hdw->pathway_state) {
3687 case PVR2_PATHWAY_ANALOG:
3688 if (!hdw->state_decoder_run) {
3689 /* We're in analog mode and the decoder is not
3690 running; thus the encoder should be stopped as
3691 well. */
3692 return !0;
3693 }
3694 break;
3695 case PVR2_PATHWAY_DIGITAL:
3696 if (hdw->state_encoder_runok) {
3697 /* This is a funny case. We're in digital mode so
3698 really the encoder should be stopped. However
3699 if it really is running, only kill it after
3700 runok has been set. This gives a chance for the
3701 onair quirk to function (encoder must run
3702 briefly first, at least once, before onair
3703 digital streaming can work). */
3704 return !0;
3705 }
3706 break;
3707 default:
3708 /* Unknown mode; so encoder should be stopped. */
3709 return !0;
3710 }
3711
3712 /* If we get here, we haven't found a reason to stop the
3713 encoder. */
3714 return 0;
3715}
3716
3717
3718/* Return true if the encoder should be running. */
3719static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
3720{
3721 if (!hdw->state_encoder_ok) {
3722 /* Don't run the encoder if it isn't healthy... */
3723 return 0;
3724 }
3725 if (!hdw->state_pathway_ok) {
3726 /* Don't run the encoder if we don't (yet) know what mode
3727 we need to be in... */
3728 return 0;
3729 }
3730
3731 switch (hdw->pathway_state) {
3732 case PVR2_PATHWAY_ANALOG:
3733 if (hdw->state_decoder_run) {
3734 /* In analog mode, if the decoder is running, then
3735 run the encoder. */
3736 return !0;
3737 }
3738 break;
3739 case PVR2_PATHWAY_DIGITAL:
3740 if ((hdw->hdw_desc->digital_control_scheme ==
3741 PVR2_DIGITAL_SCHEME_ONAIR) &&
3742 !hdw->state_encoder_runok) {
3743 /* This is a quirk. OnAir hardware won't stream
3744 digital until the encoder has been run at least
3745 once, for a minimal period of time (empiricially
3746 measured to be 1/4 second). So if we're on
3747 OnAir hardware and the encoder has never been
3748 run at all, then start the encoder. Normal
3749 state machine logic in the driver will
3750 automatically handle the remaining bits. */
3751 return !0;
3752 }
3753 break;
3754 default:
3755 /* For completeness (unknown mode; encoder won't run ever) */
3756 break;
3757 }
3758 /* If we get here, then we haven't found any reason to run the
3759 encoder, so don't run it. */
3760 return 0;
3761}
3762
3763
681c7399
MI		 3764/* Evaluate whether or not state_encoder_run can change */
3765static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3766{
3767 if (hdw->state_encoder_run) {
d913d630 3768 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 3769 if (hdw->state_encoder_ok) {
d913d630 3770 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 3771 if (pvr2_encoder_stop(hdw) < 0) return !0;
3772 }
3773 hdw->state_encoder_run = 0;
3774 } else {
d913d630 3775 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 3776 if (pvr2_encoder_start(hdw) < 0) return !0;
3777 hdw->state_encoder_run = !0;
d913d630
MI		 3778 if (!hdw->state_encoder_runok) {
3779 hdw->encoder_run_timer.expires =
83ce57aa 3780 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 3781 add_timer(&hdw->encoder_run_timer);
3782 }
681c7399
MI		 3783 }
3784 trace_stbit("state_encoder_run",hdw->state_encoder_run);
3785 return !0;
3786}
3787
3788
3789/* Timeout function for quiescent timer. */
3790static void pvr2_hdw_quiescent_timeout(unsigned long data)
3791{
3792 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3793 hdw->state_decoder_quiescent = !0;
3794 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3795 hdw->state_stale = !0;
3796 queue_work(hdw->workqueue,&hdw->workpoll);
3797}
3798
3799
3800/* Timeout function for encoder wait timer. */
3801static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3802{
3803 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3804 hdw->state_encoder_waitok = !0;
3805 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3806 hdw->state_stale = !0;
3807 queue_work(hdw->workqueue,&hdw->workpoll);
3808}
3809
3810
d913d630
MI		 3811/* Timeout function for encoder run timer. */
3812static void pvr2_hdw_encoder_run_timeout(unsigned long data)
3813{
3814 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3815 if (!hdw->state_encoder_runok) {
3816 hdw->state_encoder_runok = !0;
3817 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
3818 hdw->state_stale = !0;
3819 queue_work(hdw->workqueue,&hdw->workpoll);
3820 }
3821}
3822
3823
681c7399
MI		 3824/* Evaluate whether or not state_decoder_run can change */
3825static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3826{
3827 if (hdw->state_decoder_run) {
3828 if (hdw->state_encoder_ok) {
3829 if (hdw->state_pipeline_req &&
62433e31
MI		 3830 !hdw->state_pipeline_pause &&
3831 hdw->state_pathway_ok) return 0;
681c7399
MI		 3832 }
3833 if (!hdw->flag_decoder_missed) {
3834 pvr2_decoder_enable(hdw,0);
3835 }
3836 hdw->state_decoder_quiescent = 0;
3837 hdw->state_decoder_run = 0;
3838 /* paranoia - solve race if timer just completed */
3839 del_timer_sync(&hdw->quiescent_timer);
3840 } else {
3841 if (!hdw->state_decoder_quiescent) {
3842 if (!timer_pending(&hdw->quiescent_timer)) {
3843 /* We don't do something about the
3844 quiescent timer until right here because
3845 we also want to catch cases where the
3846 decoder was already not running (like
3847 after initialization) as opposed to
3848 knowing that we had just stopped it.
3849 The second flag check is here to cover a
3850 race - the timer could have run and set
3851 this flag just after the previous check
3852 but before we did the pending check. */
3853 if (!hdw->state_decoder_quiescent) {
3854 hdw->quiescent_timer.expires =
83ce57aa
MI		 3855 jiffies +
3856 (HZ * TIME_MSEC_DECODER_WAIT
3857 / 1000);
681c7399
MI		 3858 add_timer(&hdw->quiescent_timer);
3859 }
3860 }
3861 /* Don't allow decoder to start again until it has
3862 been quiesced first. This little detail should
3863 hopefully further stabilize the encoder. */
3864 return 0;
3865 }
62433e31
MI		 3866 if (!hdw->state_pathway_ok ||
3867 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3868 !hdw->state_pipeline_req ||
681c7399
MI		 3869 hdw->state_pipeline_pause ||
3870 !hdw->state_pipeline_config ||
3871 !hdw->state_encoder_config ||
3872 !hdw->state_encoder_ok) return 0;
3873 del_timer_sync(&hdw->quiescent_timer);
3874 if (hdw->flag_decoder_missed) return 0;
3875 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3876 hdw->state_decoder_quiescent = 0;
3877 hdw->state_decoder_run = !0;
3878 }
3879 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3880 trace_stbit("state_decoder_run",hdw->state_decoder_run);
3881 return !0;
3882}
3883
3884
3885/* Evaluate whether or not state_usbstream_run can change */
3886static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3887{
3888 if (hdw->state_usbstream_run) {
72998b71 3889 int fl = !0;
62433e31 3890 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 3891 fl = (hdw->state_encoder_ok &&
3892 hdw->state_encoder_run);
3893 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
3894 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
3895 fl = hdw->state_encoder_ok;
3896 }
3897 if (fl &&
3898 hdw->state_pipeline_req &&
3899 !hdw->state_pipeline_pause &&
3900 hdw->state_pathway_ok) {
3901 return 0;
681c7399
MI		 3902 }
3903 pvr2_hdw_cmd_usbstream(hdw,0);
3904 hdw->state_usbstream_run = 0;
3905 } else {
62433e31
MI		 3906 if (!hdw->state_pipeline_req ||
3907 hdw->state_pipeline_pause ||
3908 !hdw->state_pathway_ok) return 0;
3909 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3910 if (!hdw->state_encoder_ok ||
3911 !hdw->state_encoder_run) return 0;
72998b71
MI		 3912 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
3913 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
3914 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 3915 if (hdw->state_encoder_run) return 0;
3916 if (hdw->hdw_desc->digital_control_scheme ==
3917 PVR2_DIGITAL_SCHEME_ONAIR) {
3918 /* OnAir digital receivers won't stream
3919 unless the analog encoder has run first.
3920 Why? I have no idea. But don't even
3921 try until we know the analog side is
3922 known to have run. */
3923 if (!hdw->state_encoder_runok) return 0;
3924 }
62433e31 3925 }
681c7399
MI		 3926 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3927 hdw->state_usbstream_run = !0;
3928 }
3929 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3930 return !0;
3931}
3932
3933
3934/* Attempt to configure pipeline, if needed */
3935static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3936{
3937 if (hdw->state_pipeline_config ||
3938 hdw->state_pipeline_pause) return 0;
3939 pvr2_hdw_commit_execute(hdw);
3940 return !0;
3941}
3942
3943
3944/* Update pipeline idle and pipeline pause tracking states based on other
3945 inputs. This must be called whenever the other relevant inputs have
3946 changed. */
3947static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3948{
3949 unsigned int st;
3950 int updatedFl = 0;
3951 /* Update pipeline state */
3952 st = !(hdw->state_encoder_run ||
3953 hdw->state_decoder_run ||
3954 hdw->state_usbstream_run ||
3955 (!hdw->state_decoder_quiescent));
3956 if (!st != !hdw->state_pipeline_idle) {
3957 hdw->state_pipeline_idle = st;
3958 updatedFl = !0;
3959 }
3960 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3961 hdw->state_pipeline_pause = 0;
3962 updatedFl = !0;
3963 }
3964 return updatedFl;
3965}
3966
3967
3968typedef int (*state_eval_func)(struct pvr2_hdw *);
3969
3970/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 3971static const state_eval_func eval_funcs[] = {
62433e31 3972 state_eval_pathway_ok,
681c7399
MI		 3973 state_eval_pipeline_config,
3974 state_eval_encoder_ok,
3975 state_eval_encoder_config,
3976 state_eval_decoder_run,
3977 state_eval_encoder_run,
3978 state_eval_usbstream_run,
3979};
3980
3981
3982/* Process various states and return true if we did anything interesting. */
3983static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3984{
3985 unsigned int i;
3986 int state_updated = 0;
3987 int check_flag;
3988
3989 if (!hdw->state_stale) return 0;
3990 if ((hdw->fw1_state != FW1_STATE_OK) ||
3991 !hdw->flag_ok) {
3992 hdw->state_stale = 0;
3993 return !0;
3994 }
3995 /* This loop is the heart of the entire driver. It keeps trying to
3996 evaluate various bits of driver state until nothing changes for
3997 one full iteration. Each "bit of state" tracks some global
3998 aspect of the driver, e.g. whether decoder should run, if
3999 pipeline is configured, usb streaming is on, etc. We separately
4000 evaluate each of those questions based on other driver state to
4001 arrive at the correct running configuration. */
4002 do {
4003 check_flag = 0;
4004 state_update_pipeline_state(hdw);
4005 /* Iterate over each bit of state */
4006 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4007 if ((*eval_funcs[i])(hdw)) {
4008 check_flag = !0;
4009 state_updated = !0;
4010 state_update_pipeline_state(hdw);
4011 }
4012 }
4013 } while (check_flag && hdw->flag_ok);
4014 hdw->state_stale = 0;
4015 trace_stbit("state_stale",hdw->state_stale);
4016 return state_updated;
4017}
4018
4019
1cb03b76
MI		 4020static unsigned int print_input_mask(unsigned int msk,
4021 char *buf,unsigned int acnt)
4022{
4023 unsigned int idx,ccnt;
4024 unsigned int tcnt = 0;
4025 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4026 if (!((1 << idx) & msk)) continue;
4027 ccnt = scnprintf(buf+tcnt,
4028 acnt-tcnt,
4029 "%s%s",
4030 (tcnt ? ", " : ""),
4031 control_values_input[idx]);
4032 tcnt += ccnt;
4033 }
4034 return tcnt;
4035}
4036
4037
62433e31
MI		 4038static const char *pvr2_pathway_state_name(int id)
4039{
4040 switch (id) {
4041 case PVR2_PATHWAY_ANALOG: return "analog";
4042 case PVR2_PATHWAY_DIGITAL: return "digital";
4043 default: return "unknown";
4044 }
4045}
4046
4047
681c7399
MI		 4048static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4049 char *buf,unsigned int acnt)
4050{
4051 switch (which) {
4052 case 0:
4053 return scnprintf(
4054 buf,acnt,
e9db1ff2 4055 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4056 (hdw->flag_ok ? " <ok>" : " <fail>"),
4057 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4058 (hdw->flag_disconnected ? " <disconnected>" :
4059 " <connected>"),
4060 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4061 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4062 pvr2_pathway_state_name(hdw->pathway_state));
4063
681c7399
MI		 4064 case 1:
4065 return scnprintf(
4066 buf,acnt,
4067 "pipeline:%s%s%s%s",
4068 (hdw->state_pipeline_idle ? " <idle>" : ""),
4069 (hdw->state_pipeline_config ?
4070 " <configok>" : " <stale>"),
4071 (hdw->state_pipeline_req ? " <req>" : ""),
4072 (hdw->state_pipeline_pause ? " <pause>" : ""));
4073 case 2:
4074 return scnprintf(
4075 buf,acnt,
62433e31 4076 "worker:%s%s%s%s%s%s%s",
681c7399
MI		 4077 (hdw->state_decoder_run ?
4078 " <decode:run>" :
4079 (hdw->state_decoder_quiescent ?
4080 "" : " <decode:stop>")),
4081 (hdw->state_decoder_quiescent ?
4082 " <decode:quiescent>" : ""),
4083 (hdw->state_encoder_ok ?
4084 "" : " <encode:init>"),
4085 (hdw->state_encoder_run ?
d913d630
MI		 4086 (hdw->state_encoder_runok ?
4087 " <encode:run>" :
4088 " <encode:firstrun>") :
4089 (hdw->state_encoder_runok ?
4090 " <encode:stop>" :
4091 " <encode:virgin>")),
681c7399
MI		 4092 (hdw->state_encoder_config ?
4093 " <encode:configok>" :
4094 (hdw->state_encoder_waitok ?
b9a37d91 4095 "" : " <encode:waitok>")),
681c7399 4096 (hdw->state_usbstream_run ?
62433e31
MI		 4097 " <usb:run>" : " <usb:stop>"),
4098 (hdw->state_pathway_ok ?
e9db1ff2 4099 " <pathway:ok>" : ""));
681c7399
MI		 4100 case 3:
4101 return scnprintf(
4102 buf,acnt,
4103 "state: %s",
4104 pvr2_get_state_name(hdw->master_state));
ad0992e9 4105 case 4: {
1cb03b76
MI		 4106 unsigned int tcnt = 0;
4107 unsigned int ccnt;
4108
4109 ccnt = scnprintf(buf,
4110 acnt,
4111 "Hardware supported inputs: ");
4112 tcnt += ccnt;
4113 tcnt += print_input_mask(hdw->input_avail_mask,
4114 buf+tcnt,
4115 acnt-tcnt);
4116 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4117 ccnt = scnprintf(buf+tcnt,
4118 acnt-tcnt,
4119 "; allowed inputs: ");
4120 tcnt += ccnt;
4121 tcnt += print_input_mask(hdw->input_allowed_mask,
4122 buf+tcnt,
4123 acnt-tcnt);
4124 }
4125 return tcnt;
4126 }
4127 case 5: {
ad0992e9
MI		 4128 struct pvr2_stream_stats stats;
4129 if (!hdw->vid_stream) break;
4130 pvr2_stream_get_stats(hdw->vid_stream,
4131 &stats,
4132 0);
4133 return scnprintf(
4134 buf,acnt,
4135 "Bytes streamed=%u"
4136 " URBs: queued=%u idle=%u ready=%u"
4137 " processed=%u failed=%u",
4138 stats.bytes_processed,
4139 stats.buffers_in_queue,
4140 stats.buffers_in_idle,
4141 stats.buffers_in_ready,
4142 stats.buffers_processed,
4143 stats.buffers_failed);
4144 }
681c7399
MI		 4145 default: break;
4146 }
4147 return 0;
4148}
4149
4150
4151unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4152 char *buf,unsigned int acnt)
4153{
4154 unsigned int bcnt,ccnt,idx;
4155 bcnt = 0;
4156 LOCK_TAKE(hdw->big_lock);
4157 for (idx = 0; ; idx++) {
4158 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4159 if (!ccnt) break;
4160 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4161 if (!acnt) break;
4162 buf[0] = '\n'; ccnt = 1;
4163 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4164 }
4165 LOCK_GIVE(hdw->big_lock);
4166 return bcnt;
4167}
4168
4169
4170static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4171{
4172 char buf[128];
4173 unsigned int idx,ccnt;
4174
4175 for (idx = 0; ; idx++) {
4176 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4177 if (!ccnt) break;
4178 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4179 }
4180}
4181
4182
4183/* Evaluate and update the driver's current state, taking various actions
4184 as appropriate for the update. */
4185static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4186{
4187 unsigned int st;
4188 int state_updated = 0;
4189 int callback_flag = 0;
1b9c18c5 4190 int analog_mode;
681c7399
MI		 4191
4192 pvr2_trace(PVR2_TRACE_STBITS,
4193 "Drive state check START");
4194 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4195 pvr2_hdw_state_log_state(hdw);
4196 }
4197
4198 /* Process all state and get back over disposition */
4199 state_updated = pvr2_hdw_state_update(hdw);
4200
1b9c18c5
MI		 4201 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4202
681c7399
MI		 4203 /* Update master state based upon all other states. */
4204 if (!hdw->flag_ok) {
4205 st = PVR2_STATE_DEAD;
4206 } else if (hdw->fw1_state != FW1_STATE_OK) {
4207 st = PVR2_STATE_COLD;
72998b71
MI		 4208 } else if ((analog_mode ||
4209 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4210 !hdw->state_encoder_ok) {
681c7399 4211 st = PVR2_STATE_WARM;
1b9c18c5
MI		 4212 } else if (hdw->flag_tripped ||
4213 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 4214 st = PVR2_STATE_ERROR;
62433e31 4215 } else if (hdw->state_usbstream_run &&
1b9c18c5 4216 (!analog_mode ||
62433e31 4217 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 4218 st = PVR2_STATE_RUN;
4219 } else {
4220 st = PVR2_STATE_READY;
4221 }
4222 if (hdw->master_state != st) {
4223 pvr2_trace(PVR2_TRACE_STATE,
4224 "Device state change from %s to %s",
4225 pvr2_get_state_name(hdw->master_state),
4226 pvr2_get_state_name(st));
40381cb0 4227 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 4228 hdw->master_state = st;
4229 state_updated = !0;
4230 callback_flag = !0;
4231 }
4232 if (state_updated) {
4233 /* Trigger anyone waiting on any state changes here. */
4234 wake_up(&hdw->state_wait_data);
4235 }
4236
4237 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4238 pvr2_hdw_state_log_state(hdw);
4239 }
4240 pvr2_trace(PVR2_TRACE_STBITS,
4241 "Drive state check DONE callback=%d",callback_flag);
4242
4243 return callback_flag;
4244}
4245
4246
4247/* Cause kernel thread to check / update driver state */
4248static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4249{
4250 if (hdw->state_stale) return;
4251 hdw->state_stale = !0;
4252 trace_stbit("state_stale",hdw->state_stale);
4253 queue_work(hdw->workqueue,&hdw->workpoll);
4254}
4255
4256
d855497e
MI		 4257int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4258{
4259 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4260}
4261
4262
4263int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4264{
4265 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4266}
4267
4268
4269int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4270{
4271 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4272}
4273
4274
4275int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4276{
4277 u32 cval,nval;
4278 int ret;
4279 if (~msk) {
4280 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4281 if (ret) return ret;
4282 nval = (cval & ~msk) | (val & msk);
4283 pvr2_trace(PVR2_TRACE_GPIO,
4284 "GPIO direction changing 0x%x:0x%x"
4285 " from 0x%x to 0x%x",
4286 msk,val,cval,nval);
4287 } else {
4288 nval = val;
4289 pvr2_trace(PVR2_TRACE_GPIO,
4290 "GPIO direction changing to 0x%x",nval);
4291 }
4292 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4293}
4294
4295
4296int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4297{
4298 u32 cval,nval;
4299 int ret;
4300 if (~msk) {
4301 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4302 if (ret) return ret;
4303 nval = (cval & ~msk) | (val & msk);
4304 pvr2_trace(PVR2_TRACE_GPIO,
4305 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4306 msk,val,cval,nval);
4307 } else {
4308 nval = val;
4309 pvr2_trace(PVR2_TRACE_GPIO,
4310 "GPIO output changing to 0x%x",nval);
4311 }
4312 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4313}
4314
4315
7fb20fa3
MI		 4316unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4317{
4318 return hdw->input_avail_mask;
4319}
4320
4321
1cb03b76
MI		 4322unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
4323{
4324 return hdw->input_allowed_mask;
4325}
4326
4327
4328static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
4329{
4330 if (hdw->input_val != v) {
4331 hdw->input_val = v;
4332 hdw->input_dirty = !0;
4333 }
4334
4335 /* Handle side effects - if we switch to a mode that needs the RF
4336 tuner, then select the right frequency choice as well and mark
4337 it dirty. */
4338 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
4339 hdw->freqSelector = 0;
4340 hdw->freqDirty = !0;
4341 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
4342 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
4343 hdw->freqSelector = 1;
4344 hdw->freqDirty = !0;
4345 }
4346 return 0;
4347}
4348
4349
4350int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
4351 unsigned int change_mask,
4352 unsigned int change_val)
4353{
4354 int ret = 0;
4355 unsigned int nv,m,idx;
4356 LOCK_TAKE(hdw->big_lock);
4357 do {
4358 nv = hdw->input_allowed_mask & ~change_mask;
4359 nv |= (change_val & change_mask);
4360 nv &= hdw->input_avail_mask;
4361 if (!nv) {
4362 /* No legal modes left; return error instead. */
4363 ret = -EPERM;
4364 break;
4365 }
4366 hdw->input_allowed_mask = nv;
4367 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
4368 /* Current mode is still in the allowed mask, so
4369 we're done. */
4370 break;
4371 }
4372 /* Select and switch to a mode that is still in the allowed
4373 mask */
4374 if (!hdw->input_allowed_mask) {
4375 /* Nothing legal; give up */
4376 break;
4377 }
4378 m = hdw->input_allowed_mask;
4379 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
4380 if (!((1 << idx) & m)) continue;
4381 pvr2_hdw_set_input(hdw,idx);
4382 break;
4383 }
4384 } while (0);
4385 LOCK_GIVE(hdw->big_lock);
4386 return ret;
4387}
4388
4389
e61b6fc5 4390/* Find I2C address of eeprom */
07e337ee 4391static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 4392{
4393 int result;
4394 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 4395 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 4396 result = pvr2_send_request(hdw,
4397 hdw->cmd_buffer,1,
4398 hdw->cmd_buffer,1);
4399 if (result < 0) break;
4400 result = hdw->cmd_buffer[0];
4401 } while(0); LOCK_GIVE(hdw->ctl_lock);
4402 return result;
4403}
4404
4405
32ffa9ae 4406int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
f3d092b8
HV		 4407 u32 match_type, u32 match_chip, u64 reg_id,
4408 int setFl,u64 *val_ptr)
32ffa9ae
MI		 4409{
4410#ifdef CONFIG_VIDEO_ADV_DEBUG
32ffa9ae
MI		 4411 struct pvr2_i2c_client *cp;
4412 struct v4l2_register req;
6d98816f
MI		 4413 int stat = 0;
4414 int okFl = 0;
32ffa9ae 4415
201f5c9c
MI		 4416 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
4417
f3d092b8
HV		 4418 req.match_type = match_type;
4419 req.match_chip = match_chip;
32ffa9ae
MI		 4420 req.reg = reg_id;
4421 if (setFl) req.val = *val_ptr;
4422 mutex_lock(&hdw->i2c_list_lock); do {
e77e2c2f 4423 list_for_each_entry(cp, &hdw->i2c_clients, list) {
8481a750
MI		 4424 if (!v4l2_chip_match_i2c_client(
4425 cp->client,
4426 req.match_type, req.match_chip)) {
f3d092b8
HV		 4427 continue;
4428 }
32ffa9ae 4429 stat = pvr2_i2c_client_cmd(
52ebc763
TP		 4430 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
4431 VIDIOC_DBG_G_REGISTER),&req);
32ffa9ae 4432 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 4433 okFl = !0;
4434 break;
32ffa9ae
MI		 4435 }
4436 } while (0); mutex_unlock(&hdw->i2c_list_lock);
6d98816f
MI		 4437 if (okFl) {
4438 return stat;
4439 }
32ffa9ae
MI		 4440 return -EINVAL;
4441#else
4442 return -ENOSYS;
4443#endif
4444}
4445
4446
d855497e
MI		 4447/*
4448 Stuff for Emacs to see, in order to encourage consistent editing style:
4449 *** Local Variables: ***
4450 *** mode: c ***
4451 *** fill-column: 75 ***
4452 *** tab-width: 8 ***
4453 *** c-basic-offset: 8 ***
4454 *** End: ***
4455 */
Clone of davem's net-next-2.6 tree