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V4L/DVB (6688): V4L: fix copy and paste error in dprintk for videobuf-vmalloc.c
[net-next-2.6.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
3 * $Id$
4 *
5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/firmware.h>
d855497e 26#include <linux/videodev2.h>
32ffa9ae 27#include <media/v4l2-common.h>
b2bbaa93 28#include <asm/semaphore.h>
d855497e
MI		 29#include "pvrusb2.h"
30#include "pvrusb2-std.h"
31#include "pvrusb2-util.h"
32#include "pvrusb2-hdw.h"
33#include "pvrusb2-i2c-core.h"
34#include "pvrusb2-tuner.h"
35#include "pvrusb2-eeprom.h"
36#include "pvrusb2-hdw-internal.h"
37#include "pvrusb2-encoder.h"
38#include "pvrusb2-debug.h"
8d364363 39#include "pvrusb2-fx2-cmd.h"
d855497e 40
1bde0289
MI		 41#define TV_MIN_FREQ 55250000L
42#define TV_MAX_FREQ 850000000L
25d8527a 43
d855497e
MI		 44struct usb_device_id pvr2_device_table[] = {
45 [PVR2_HDW_TYPE_29XXX] = { USB_DEVICE(0x2040, 0x2900) },
d855497e 46 [PVR2_HDW_TYPE_24XXX] = { USB_DEVICE(0x2040, 0x2400) },
d855497e
MI		 47 { }
48};
49
50MODULE_DEVICE_TABLE(usb, pvr2_device_table);
51
52static const char *pvr2_device_names[] = {
53 [PVR2_HDW_TYPE_29XXX] = "WinTV PVR USB2 Model Category 29xxxx",
d855497e 54 [PVR2_HDW_TYPE_24XXX] = "WinTV PVR USB2 Model Category 24xxxx",
d855497e
MI		 55};
56
57struct pvr2_string_table {
58 const char **lst;
59 unsigned int cnt;
60};
61
d855497e
MI		 62// Names of other client modules to request for 24xxx model hardware
63static const char *pvr2_client_24xxx[] = {
64 "cx25840",
65 "tuner",
d855497e
MI		 66 "wm8775",
67};
d855497e
MI		 68
69// Names of other client modules to request for 29xxx model hardware
70static const char *pvr2_client_29xxx[] = {
71 "msp3400",
72 "saa7115",
73 "tuner",
d855497e
MI		 74};
75
76static struct pvr2_string_table pvr2_client_lists[] = {
77 [PVR2_HDW_TYPE_29XXX] = {
eca8ebfc 78 pvr2_client_29xxx, ARRAY_SIZE(pvr2_client_29xxx)
d855497e 79 },
d855497e 80 [PVR2_HDW_TYPE_24XXX] = {
eca8ebfc 81 pvr2_client_24xxx, ARRAY_SIZE(pvr2_client_24xxx)
d855497e 82 },
d855497e
MI		 83};
84
a0fd1cb1 85static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 86static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e
MI		 87
88static int ctlchg = 0;
89static int initusbreset = 1;
90static int procreload = 0;
91static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
92static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
93static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
94static int init_pause_msec = 0;
95
96module_param(ctlchg, int, S_IRUGO|S_IWUSR);
97MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
98module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
99MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
100module_param(initusbreset, int, S_IRUGO|S_IWUSR);
101MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
102module_param(procreload, int, S_IRUGO|S_IWUSR);
103MODULE_PARM_DESC(procreload,
104 "Attempt init failure recovery with firmware reload");
105module_param_array(tuner, int, NULL, 0444);
106MODULE_PARM_DESC(tuner,"specify installed tuner type");
107module_param_array(video_std, int, NULL, 0444);
108MODULE_PARM_DESC(video_std,"specify initial video standard");
109module_param_array(tolerance, int, NULL, 0444);
110MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
111
112#define PVR2_CTL_WRITE_ENDPOINT 0x01
113#define PVR2_CTL_READ_ENDPOINT 0x81
114
115#define PVR2_GPIO_IN 0x9008
116#define PVR2_GPIO_OUT 0x900c
117#define PVR2_GPIO_DIR 0x9020
118
119#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
120
121#define PVR2_FIRMWARE_ENDPOINT 0x02
122
123/* size of a firmware chunk */
124#define FIRMWARE_CHUNK_SIZE 0x2000
125
b30d2441
MI		 126/* Define the list of additional controls we'll dynamically construct based
127 on query of the cx2341x module. */
128struct pvr2_mpeg_ids {
129 const char *strid;
130 int id;
131};
132static const struct pvr2_mpeg_ids mpeg_ids[] = {
133 {
134 .strid = "audio_layer",
135 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
136 },{
137 .strid = "audio_bitrate",
138 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
139 },{
140 /* Already using audio_mode elsewhere :-( */
141 .strid = "mpeg_audio_mode",
142 .id = V4L2_CID_MPEG_AUDIO_MODE,
143 },{
144 .strid = "mpeg_audio_mode_extension",
145 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
146 },{
147 .strid = "audio_emphasis",
148 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
149 },{
150 .strid = "audio_crc",
151 .id = V4L2_CID_MPEG_AUDIO_CRC,
152 },{
153 .strid = "video_aspect",
154 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
155 },{
156 .strid = "video_b_frames",
157 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
158 },{
159 .strid = "video_gop_size",
160 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
161 },{
162 .strid = "video_gop_closure",
163 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 164 },{
165 .strid = "video_bitrate_mode",
166 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
167 },{
168 .strid = "video_bitrate",
169 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
170 },{
171 .strid = "video_bitrate_peak",
172 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
173 },{
174 .strid = "video_temporal_decimation",
175 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
176 },{
177 .strid = "stream_type",
178 .id = V4L2_CID_MPEG_STREAM_TYPE,
179 },{
180 .strid = "video_spatial_filter_mode",
181 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
182 },{
183 .strid = "video_spatial_filter",
184 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
185 },{
186 .strid = "video_luma_spatial_filter_type",
187 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
188 },{
189 .strid = "video_chroma_spatial_filter_type",
190 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
191 },{
192 .strid = "video_temporal_filter_mode",
193 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
194 },{
195 .strid = "video_temporal_filter",
196 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
197 },{
198 .strid = "video_median_filter_type",
199 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
200 },{
201 .strid = "video_luma_median_filter_top",
202 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
203 },{
204 .strid = "video_luma_median_filter_bottom",
205 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
206 },{
207 .strid = "video_chroma_median_filter_top",
208 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
209 },{
210 .strid = "video_chroma_median_filter_bottom",
211 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
212 }
213};
eca8ebfc 214#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 215
434449f4 216
d855497e 217static const char *control_values_srate[] = {
434449f4
MI		 218 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
219 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
220 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 221};
222
223
d855497e 224
d855497e
MI		 225static const char *control_values_input[] = {
226 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
227 [PVR2_CVAL_INPUT_RADIO] = "radio",
228 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
229 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
230};
231
232
233static const char *control_values_audiomode[] = {
234 [V4L2_TUNER_MODE_MONO] = "Mono",
235 [V4L2_TUNER_MODE_STEREO] = "Stereo",
236 [V4L2_TUNER_MODE_LANG1] = "Lang1",
237 [V4L2_TUNER_MODE_LANG2] = "Lang2",
238 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
239};
240
241
242static const char *control_values_hsm[] = {
243 [PVR2_CVAL_HSM_FAIL] = "Fail",
244 [PVR2_CVAL_HSM_HIGH] = "High",
245 [PVR2_CVAL_HSM_FULL] = "Full",
246};
247
248
249static const char *control_values_subsystem[] = {
250 [PVR2_SUBSYS_B_ENC_FIRMWARE] = "enc_firmware",
251 [PVR2_SUBSYS_B_ENC_CFG] = "enc_config",
252 [PVR2_SUBSYS_B_DIGITIZER_RUN] = "digitizer_run",
253 [PVR2_SUBSYS_B_USBSTREAM_RUN] = "usbstream_run",
254 [PVR2_SUBSYS_B_ENC_RUN] = "enc_run",
255};
256
1bde0289 257static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
07e337ee
AB		 258static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
259static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw);
260static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 261static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
262static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
263static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw);
264static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
265 unsigned long msk,
266 unsigned long val);
267static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
268 unsigned long msk,
269 unsigned long val);
270static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
271 unsigned int timeout,int probe_fl,
272 void *write_data,unsigned int write_len,
273 void *read_data,unsigned int read_len);
d855497e
MI		 274
275static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
276{
277 struct pvr2_hdw *hdw = cptr->hdw;
278 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
279 *vp = hdw->freqTable[hdw->freqProgSlot-1];
280 } else {
281 *vp = 0;
282 }
283 return 0;
284}
285
286static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
287{
288 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 289 unsigned int slotId = hdw->freqProgSlot;
290 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
291 hdw->freqTable[slotId-1] = v;
292 /* Handle side effects correctly - if we're tuned to this
293 slot, then forgot the slot id relation since the stored
294 frequency has been changed. */
295 if (hdw->freqSelector) {
296 if (hdw->freqSlotRadio == slotId) {
297 hdw->freqSlotRadio = 0;
298 }
299 } else {
300 if (hdw->freqSlotTelevision == slotId) {
301 hdw->freqSlotTelevision = 0;
302 }
303 }
d855497e
MI		 304 }
305 return 0;
306}
307
308static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
309{
310 *vp = cptr->hdw->freqProgSlot;
311 return 0;
312}
313
314static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
315{
316 struct pvr2_hdw *hdw = cptr->hdw;
317 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
318 hdw->freqProgSlot = v;
319 }
320 return 0;
321}
322
323static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
324{
1bde0289
MI		 325 struct pvr2_hdw *hdw = cptr->hdw;
326 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 327 return 0;
328}
329
1bde0289 330static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 331{
332 unsigned freq = 0;
333 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 334 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
335 if (slotId > 0) {
336 freq = hdw->freqTable[slotId-1];
337 if (!freq) return 0;
338 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 339 }
1bde0289
MI		 340 if (hdw->freqSelector) {
341 hdw->freqSlotRadio = slotId;
342 } else {
343 hdw->freqSlotTelevision = slotId;
d855497e
MI		 344 }
345 return 0;
346}
347
348static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
349{
1bde0289 350 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 351 return 0;
352}
353
354static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
355{
356 return cptr->hdw->freqDirty != 0;
357}
358
359static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
360{
361 cptr->hdw->freqDirty = 0;
362}
363
364static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
365{
1bde0289 366 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 367 return 0;
368}
369
3ad9fc37
MI		 370static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
371{
372 /* Actual maximum depends on the video standard in effect. */
373 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
374 *vp = 480;
375 } else {
376 *vp = 576;
377 }
378 return 0;
379}
380
381static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
382{
383 /* Actual minimum depends on device type. */
384 if (cptr->hdw->hdw_type == PVR2_HDW_TYPE_24XXX) {
385 *vp = 75;
386 } else {
387 *vp = 17;
388 }
389 return 0;
390}
391
1bde0289 392static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 393{
1bde0289
MI		 394 *vp = cptr->hdw->input_val;
395 return 0;
396}
397
398static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
399{
400 struct pvr2_hdw *hdw = cptr->hdw;
401
402 if (hdw->input_val != v) {
403 hdw->input_val = v;
404 hdw->input_dirty = !0;
405 }
406
407 /* Handle side effects - if we switch to a mode that needs the RF
408 tuner, then select the right frequency choice as well and mark
409 it dirty. */
410 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
411 hdw->freqSelector = 0;
412 hdw->freqDirty = !0;
413 } else if (hdw->input_val == PVR2_CVAL_INPUT_TV) {
414 hdw->freqSelector = 1;
415 hdw->freqDirty = !0;
5549f54f 416 }
1bde0289
MI		 417 return 0;
418}
419
420static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
421{
422 return cptr->hdw->input_dirty != 0;
423}
424
425static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
426{
427 cptr->hdw->input_dirty = 0;
428}
429
5549f54f 430
25d8527a
PK		 431static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
432{
644afdb9
MI		 433 unsigned long fv;
434 struct pvr2_hdw *hdw = cptr->hdw;
435 if (hdw->tuner_signal_stale) {
436 pvr2_i2c_core_status_poll(hdw);
437 }
438 fv = hdw->tuner_signal_info.rangehigh;
439 if (!fv) {
440 /* Safety fallback */
25d8527a 441 *vp = TV_MAX_FREQ;
644afdb9 442 return 0;
25d8527a 443 }
644afdb9
MI		 444 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
445 fv = (fv * 125) / 2;
446 } else {
447 fv = fv * 62500;
448 }
449 *vp = fv;
25d8527a
PK		 450 return 0;
451}
452
453static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
454{
644afdb9
MI		 455 unsigned long fv;
456 struct pvr2_hdw *hdw = cptr->hdw;
457 if (hdw->tuner_signal_stale) {
458 pvr2_i2c_core_status_poll(hdw);
459 }
460 fv = hdw->tuner_signal_info.rangelow;
461 if (!fv) {
462 /* Safety fallback */
25d8527a 463 *vp = TV_MIN_FREQ;
644afdb9
MI		 464 return 0;
465 }
466 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
467 fv = (fv * 125) / 2;
468 } else {
469 fv = fv * 62500;
25d8527a 470 }
644afdb9 471 *vp = fv;
25d8527a
PK		 472 return 0;
473}
474
b30d2441
MI		 475static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
476{
477 return cptr->hdw->enc_stale != 0;
478}
479
480static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
481{
482 cptr->hdw->enc_stale = 0;
483}
484
485static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
486{
487 int ret;
488 struct v4l2_ext_controls cs;
489 struct v4l2_ext_control c1;
490 memset(&cs,0,sizeof(cs));
491 memset(&c1,0,sizeof(c1));
492 cs.controls = &c1;
493 cs.count = 1;
494 c1.id = cptr->info->v4l_id;
01f1e44f 495 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 496 VIDIOC_G_EXT_CTRLS);
497 if (ret) return ret;
498 *vp = c1.value;
499 return 0;
500}
501
502static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
503{
504 int ret;
505 struct v4l2_ext_controls cs;
506 struct v4l2_ext_control c1;
507 memset(&cs,0,sizeof(cs));
508 memset(&c1,0,sizeof(c1));
509 cs.controls = &c1;
510 cs.count = 1;
511 c1.id = cptr->info->v4l_id;
512 c1.value = v;
01f1e44f 513 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 514 VIDIOC_S_EXT_CTRLS);
515 if (ret) return ret;
516 cptr->hdw->enc_stale = !0;
517 return 0;
518}
519
520static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
521{
522 struct v4l2_queryctrl qctrl;
523 struct pvr2_ctl_info *info;
524 qctrl.id = cptr->info->v4l_id;
525 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
526 /* Strip out the const so we can adjust a function pointer. It's
527 OK to do this here because we know this is a dynamically created
528 control, so the underlying storage for the info pointer is (a)
529 private to us, and (b) not in read-only storage. Either we do
530 this or we significantly complicate the underlying control
531 implementation. */
532 info = (struct pvr2_ctl_info *)(cptr->info);
533 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
534 if (info->set_value) {
a0fd1cb1 535 info->set_value = NULL;
b30d2441
MI		 536 }
537 } else {
538 if (!(info->set_value)) {
539 info->set_value = ctrl_cx2341x_set;
540 }
541 }
542 return qctrl.flags;
543}
544
d855497e
MI		 545static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
546{
547 *vp = cptr->hdw->flag_streaming_enabled;
548 return 0;
549}
550
551static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
552{
553 int result = pvr2_hdw_is_hsm(cptr->hdw);
554 *vp = PVR2_CVAL_HSM_FULL;
555 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
556 if (result) *vp = PVR2_CVAL_HSM_HIGH;
557 return 0;
558}
559
560static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
561{
562 *vp = cptr->hdw->std_mask_avail;
563 return 0;
564}
565
566static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
567{
568 struct pvr2_hdw *hdw = cptr->hdw;
569 v4l2_std_id ns;
570 ns = hdw->std_mask_avail;
571 ns = (ns & ~m) | (v & m);
572 if (ns == hdw->std_mask_avail) return 0;
573 hdw->std_mask_avail = ns;
574 pvr2_hdw_internal_set_std_avail(hdw);
575 pvr2_hdw_internal_find_stdenum(hdw);
576 return 0;
577}
578
579static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
580 char *bufPtr,unsigned int bufSize,
581 unsigned int *len)
582{
583 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
584 return 0;
585}
586
587static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
588 const char *bufPtr,unsigned int bufSize,
589 int *mskp,int *valp)
590{
591 int ret;
592 v4l2_std_id id;
593 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
594 if (ret < 0) return ret;
595 if (mskp) *mskp = id;
596 if (valp) *valp = id;
597 return 0;
598}
599
600static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
601{
602 *vp = cptr->hdw->std_mask_cur;
603 return 0;
604}
605
606static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
607{
608 struct pvr2_hdw *hdw = cptr->hdw;
609 v4l2_std_id ns;
610 ns = hdw->std_mask_cur;
611 ns = (ns & ~m) | (v & m);
612 if (ns == hdw->std_mask_cur) return 0;
613 hdw->std_mask_cur = ns;
614 hdw->std_dirty = !0;
615 pvr2_hdw_internal_find_stdenum(hdw);
616 return 0;
617}
618
619static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
620{
621 return cptr->hdw->std_dirty != 0;
622}
623
624static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
625{
626 cptr->hdw->std_dirty = 0;
627}
628
629static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
630{
18103c57
MI		 631 struct pvr2_hdw *hdw = cptr->hdw;
632 pvr2_i2c_core_status_poll(hdw);
633 *vp = hdw->tuner_signal_info.signal;
634 return 0;
635}
636
637static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
638{
639 int val = 0;
640 unsigned int subchan;
641 struct pvr2_hdw *hdw = cptr->hdw;
644afdb9 642 pvr2_i2c_core_status_poll(hdw);
18103c57
MI		 643 subchan = hdw->tuner_signal_info.rxsubchans;
644 if (subchan & V4L2_TUNER_SUB_MONO) {
645 val |= (1 << V4L2_TUNER_MODE_MONO);
646 }
647 if (subchan & V4L2_TUNER_SUB_STEREO) {
648 val |= (1 << V4L2_TUNER_MODE_STEREO);
649 }
650 if (subchan & V4L2_TUNER_SUB_LANG1) {
651 val |= (1 << V4L2_TUNER_MODE_LANG1);
652 }
653 if (subchan & V4L2_TUNER_SUB_LANG2) {
654 val |= (1 << V4L2_TUNER_MODE_LANG2);
655 }
656 *vp = val;
d855497e
MI		 657 return 0;
658}
659
660static int ctrl_subsys_get(struct pvr2_ctrl *cptr,int *vp)
661{
662 *vp = cptr->hdw->subsys_enabled_mask;
663 return 0;
664}
665
666static int ctrl_subsys_set(struct pvr2_ctrl *cptr,int m,int v)
667{
668 pvr2_hdw_subsys_bit_chg_no_lock(cptr->hdw,m,v);
669 return 0;
670}
671
672static int ctrl_subsys_stream_get(struct pvr2_ctrl *cptr,int *vp)
673{
674 *vp = cptr->hdw->subsys_stream_mask;
675 return 0;
676}
677
678static int ctrl_subsys_stream_set(struct pvr2_ctrl *cptr,int m,int v)
679{
680 pvr2_hdw_subsys_stream_bit_chg_no_lock(cptr->hdw,m,v);
681 return 0;
682}
683
684static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
685{
686 struct pvr2_hdw *hdw = cptr->hdw;
687 if (v < 0) return -EINVAL;
688 if (v > hdw->std_enum_cnt) return -EINVAL;
689 hdw->std_enum_cur = v;
690 if (!v) return 0;
691 v--;
692 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
693 hdw->std_mask_cur = hdw->std_defs[v].id;
694 hdw->std_dirty = !0;
695 return 0;
696}
697
698
699static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
700{
701 *vp = cptr->hdw->std_enum_cur;
702 return 0;
703}
704
705
706static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
707{
708 return cptr->hdw->std_dirty != 0;
709}
710
711
712static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
713{
714 cptr->hdw->std_dirty = 0;
715}
716
717
718#define DEFINT(vmin,vmax) \
719 .type = pvr2_ctl_int, \
720 .def.type_int.min_value = vmin, \
721 .def.type_int.max_value = vmax
722
723#define DEFENUM(tab) \
724 .type = pvr2_ctl_enum, \
27c7b710 725 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 726 .def.type_enum.value_names = tab
727
33213963
MI		 728#define DEFBOOL \
729 .type = pvr2_ctl_bool
730
d855497e
MI		 731#define DEFMASK(msk,tab) \
732 .type = pvr2_ctl_bitmask, \
733 .def.type_bitmask.valid_bits = msk, \
734 .def.type_bitmask.bit_names = tab
735
736#define DEFREF(vname) \
737 .set_value = ctrl_set_##vname, \
738 .get_value = ctrl_get_##vname, \
739 .is_dirty = ctrl_isdirty_##vname, \
740 .clear_dirty = ctrl_cleardirty_##vname
741
742
743#define VCREATE_FUNCS(vname) \
744static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
745{*vp = cptr->hdw->vname##_val; return 0;} \
746static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
747{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
748static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
749{return cptr->hdw->vname##_dirty != 0;} \
750static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
751{cptr->hdw->vname##_dirty = 0;}
752
753VCREATE_FUNCS(brightness)
754VCREATE_FUNCS(contrast)
755VCREATE_FUNCS(saturation)
756VCREATE_FUNCS(hue)
757VCREATE_FUNCS(volume)
758VCREATE_FUNCS(balance)
759VCREATE_FUNCS(bass)
760VCREATE_FUNCS(treble)
761VCREATE_FUNCS(mute)
c05c0462
MI		 762VCREATE_FUNCS(audiomode)
763VCREATE_FUNCS(res_hor)
764VCREATE_FUNCS(res_ver)
d855497e 765VCREATE_FUNCS(srate)
d855497e 766
d855497e
MI		 767/* Table definition of all controls which can be manipulated */
768static const struct pvr2_ctl_info control_defs[] = {
769 {
770 .v4l_id = V4L2_CID_BRIGHTNESS,
771 .desc = "Brightness",
772 .name = "brightness",
773 .default_value = 128,
774 DEFREF(brightness),
775 DEFINT(0,255),
776 },{
777 .v4l_id = V4L2_CID_CONTRAST,
778 .desc = "Contrast",
779 .name = "contrast",
780 .default_value = 68,
781 DEFREF(contrast),
782 DEFINT(0,127),
783 },{
784 .v4l_id = V4L2_CID_SATURATION,
785 .desc = "Saturation",
786 .name = "saturation",
787 .default_value = 64,
788 DEFREF(saturation),
789 DEFINT(0,127),
790 },{
791 .v4l_id = V4L2_CID_HUE,
792 .desc = "Hue",
793 .name = "hue",
794 .default_value = 0,
795 DEFREF(hue),
796 DEFINT(-128,127),
797 },{
798 .v4l_id = V4L2_CID_AUDIO_VOLUME,
799 .desc = "Volume",
800 .name = "volume",
139eecf9 801 .default_value = 62000,
d855497e
MI		 802 DEFREF(volume),
803 DEFINT(0,65535),
804 },{
805 .v4l_id = V4L2_CID_AUDIO_BALANCE,
806 .desc = "Balance",
807 .name = "balance",
808 .default_value = 0,
809 DEFREF(balance),
810 DEFINT(-32768,32767),
811 },{
812 .v4l_id = V4L2_CID_AUDIO_BASS,
813 .desc = "Bass",
814 .name = "bass",
815 .default_value = 0,
816 DEFREF(bass),
817 DEFINT(-32768,32767),
818 },{
819 .v4l_id = V4L2_CID_AUDIO_TREBLE,
820 .desc = "Treble",
821 .name = "treble",
822 .default_value = 0,
823 DEFREF(treble),
824 DEFINT(-32768,32767),
825 },{
826 .v4l_id = V4L2_CID_AUDIO_MUTE,
827 .desc = "Mute",
828 .name = "mute",
829 .default_value = 0,
830 DEFREF(mute),
33213963 831 DEFBOOL,
c05c0462
MI		 832 },{
833 .desc = "Video Source",
834 .name = "input",
835 .internal_id = PVR2_CID_INPUT,
836 .default_value = PVR2_CVAL_INPUT_TV,
837 DEFREF(input),
838 DEFENUM(control_values_input),
839 },{
840 .desc = "Audio Mode",
841 .name = "audio_mode",
842 .internal_id = PVR2_CID_AUDIOMODE,
843 .default_value = V4L2_TUNER_MODE_STEREO,
844 DEFREF(audiomode),
845 DEFENUM(control_values_audiomode),
846 },{
847 .desc = "Horizontal capture resolution",
848 .name = "resolution_hor",
849 .internal_id = PVR2_CID_HRES,
850 .default_value = 720,
851 DEFREF(res_hor),
3ad9fc37 852 DEFINT(19,720),
c05c0462
MI		 853 },{
854 .desc = "Vertical capture resolution",
855 .name = "resolution_ver",
856 .internal_id = PVR2_CID_VRES,
857 .default_value = 480,
858 DEFREF(res_ver),
3ad9fc37
MI		 859 DEFINT(17,576),
860 /* Hook in check for video standard and adjust maximum
861 depending on the standard. */
862 .get_max_value = ctrl_vres_max_get,
863 .get_min_value = ctrl_vres_min_get,
d855497e 864 },{
b30d2441 865 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 866 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
867 .desc = "Audio Sampling Frequency",
d855497e 868 .name = "srate",
d855497e
MI		 869 DEFREF(srate),
870 DEFENUM(control_values_srate),
d855497e
MI		 871 },{
872 .desc = "Tuner Frequency (Hz)",
873 .name = "frequency",
874 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 875 .default_value = 0,
d855497e
MI		 876 .set_value = ctrl_freq_set,
877 .get_value = ctrl_freq_get,
878 .is_dirty = ctrl_freq_is_dirty,
879 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 880 DEFINT(0,0),
25d8527a
PK		 881 /* Hook in check for input value (tv/radio) and adjust
882 max/min values accordingly */
883 .get_max_value = ctrl_freq_max_get,
884 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 885 },{
886 .desc = "Channel",
887 .name = "channel",
888 .set_value = ctrl_channel_set,
889 .get_value = ctrl_channel_get,
890 DEFINT(0,FREQTABLE_SIZE),
891 },{
892 .desc = "Channel Program Frequency",
893 .name = "freq_table_value",
894 .set_value = ctrl_channelfreq_set,
895 .get_value = ctrl_channelfreq_get,
644afdb9 896 DEFINT(0,0),
1bde0289
MI		 897 /* Hook in check for input value (tv/radio) and adjust
898 max/min values accordingly */
1bde0289
MI		 899 .get_max_value = ctrl_freq_max_get,
900 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 901 },{
902 .desc = "Channel Program ID",
903 .name = "freq_table_channel",
904 .set_value = ctrl_channelprog_set,
905 .get_value = ctrl_channelprog_get,
906 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 907 },{
908 .desc = "Streaming Enabled",
909 .name = "streaming_enabled",
910 .get_value = ctrl_streamingenabled_get,
33213963 911 DEFBOOL,
d855497e
MI		 912 },{
913 .desc = "USB Speed",
914 .name = "usb_speed",
915 .get_value = ctrl_hsm_get,
916 DEFENUM(control_values_hsm),
917 },{
918 .desc = "Signal Present",
919 .name = "signal_present",
920 .get_value = ctrl_signal_get,
18103c57
MI		 921 DEFINT(0,65535),
922 },{
923 .desc = "Audio Modes Present",
924 .name = "audio_modes_present",
925 .get_value = ctrl_audio_modes_present_get,
926 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
927 v4l. Nothing outside of this module cares about this,
928 but I reuse it in order to also reuse the
929 control_values_audiomode string table. */
930 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
931 (1 << V4L2_TUNER_MODE_STEREO)|
932 (1 << V4L2_TUNER_MODE_LANG1)|
933 (1 << V4L2_TUNER_MODE_LANG2)),
934 control_values_audiomode),
d855497e
MI		 935 },{
936 .desc = "Video Standards Available Mask",
937 .name = "video_standard_mask_available",
938 .internal_id = PVR2_CID_STDAVAIL,
939 .skip_init = !0,
940 .get_value = ctrl_stdavail_get,
941 .set_value = ctrl_stdavail_set,
942 .val_to_sym = ctrl_std_val_to_sym,
943 .sym_to_val = ctrl_std_sym_to_val,
944 .type = pvr2_ctl_bitmask,
945 },{
946 .desc = "Video Standards In Use Mask",
947 .name = "video_standard_mask_active",
948 .internal_id = PVR2_CID_STDCUR,
949 .skip_init = !0,
950 .get_value = ctrl_stdcur_get,
951 .set_value = ctrl_stdcur_set,
952 .is_dirty = ctrl_stdcur_is_dirty,
953 .clear_dirty = ctrl_stdcur_clear_dirty,
954 .val_to_sym = ctrl_std_val_to_sym,
955 .sym_to_val = ctrl_std_sym_to_val,
956 .type = pvr2_ctl_bitmask,
957 },{
958 .desc = "Subsystem enabled mask",
959 .name = "debug_subsys_mask",
960 .skip_init = !0,
961 .get_value = ctrl_subsys_get,
962 .set_value = ctrl_subsys_set,
963 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
964 },{
965 .desc = "Subsystem stream mask",
966 .name = "debug_subsys_stream_mask",
967 .skip_init = !0,
968 .get_value = ctrl_subsys_stream_get,
969 .set_value = ctrl_subsys_stream_set,
970 DEFMASK(PVR2_SUBSYS_ALL,control_values_subsystem),
971 },{
972 .desc = "Video Standard Name",
973 .name = "video_standard",
974 .internal_id = PVR2_CID_STDENUM,
975 .skip_init = !0,
976 .get_value = ctrl_stdenumcur_get,
977 .set_value = ctrl_stdenumcur_set,
978 .is_dirty = ctrl_stdenumcur_is_dirty,
979 .clear_dirty = ctrl_stdenumcur_clear_dirty,
980 .type = pvr2_ctl_enum,
981 }
982};
983
eca8ebfc 984#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 985
986
987const char *pvr2_config_get_name(enum pvr2_config cfg)
988{
989 switch (cfg) {
990 case pvr2_config_empty: return "empty";
991 case pvr2_config_mpeg: return "mpeg";
992 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 993 case pvr2_config_pcm: return "pcm";
994 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 995 }
996 return "<unknown>";
997}
998
999
1000struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1001{
1002 return hdw->usb_dev;
1003}
1004
1005
1006unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1007{
1008 return hdw->serial_number;
1009}
1010
31a18547
MI		 1011
1012const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1013{
1014 return hdw->bus_info;
1015}
1016
1017
1bde0289
MI		 1018unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1019{
1020 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1021}
1022
1023/* Set the currently tuned frequency and account for all possible
1024 driver-core side effects of this action. */
1025void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1026{
7c74e57e 1027 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1028 if (hdw->freqSelector) {
1029 /* Swing over to radio frequency selection */
1030 hdw->freqSelector = 0;
1031 hdw->freqDirty = !0;
1032 }
1bde0289
MI		 1033 if (hdw->freqValRadio != val) {
1034 hdw->freqValRadio = val;
1035 hdw->freqSlotRadio = 0;
7c74e57e 1036 hdw->freqDirty = !0;
1bde0289 1037 }
7c74e57e 1038 } else {
1bde0289
MI		 1039 if (!(hdw->freqSelector)) {
1040 /* Swing over to television frequency selection */
1041 hdw->freqSelector = 1;
1042 hdw->freqDirty = !0;
1043 }
1bde0289
MI		 1044 if (hdw->freqValTelevision != val) {
1045 hdw->freqValTelevision = val;
1046 hdw->freqSlotTelevision = 0;
7c74e57e 1047 hdw->freqDirty = !0;
1bde0289 1048 }
1bde0289
MI		 1049 }
1050}
1051
d855497e
MI		 1052int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1053{
1054 return hdw->unit_number;
1055}
1056
1057
1058/* Attempt to locate one of the given set of files. Messages are logged
1059 appropriate to what has been found. The return value will be 0 or
1060 greater on success (it will be the index of the file name found) and
1061 fw_entry will be filled in. Otherwise a negative error is returned on
1062 failure. If the return value is -ENOENT then no viable firmware file
1063 could be located. */
1064static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1065 const struct firmware **fw_entry,
1066 const char *fwtypename,
1067 unsigned int fwcount,
1068 const char *fwnames[])
1069{
1070 unsigned int idx;
1071 int ret = -EINVAL;
1072 for (idx = 0; idx < fwcount; idx++) {
1073 ret = request_firmware(fw_entry,
1074 fwnames[idx],
1075 &hdw->usb_dev->dev);
1076 if (!ret) {
1077 trace_firmware("Located %s firmware: %s;"
1078 " uploading...",
1079 fwtypename,
1080 fwnames[idx]);
1081 return idx;
1082 }
1083 if (ret == -ENOENT) continue;
1084 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1085 "request_firmware fatal error with code=%d",ret);
1086 return ret;
1087 }
1088 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1089 "***WARNING***"
1090 " Device %s firmware"
1091 " seems to be missing.",
1092 fwtypename);
1093 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1094 "Did you install the pvrusb2 firmware files"
1095 " in their proper location?");
1096 if (fwcount == 1) {
1097 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1098 "request_firmware unable to locate %s file %s",
1099 fwtypename,fwnames[0]);
1100 } else {
1101 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1102 "request_firmware unable to locate"
1103 " one of the following %s files:",
1104 fwtypename);
1105 for (idx = 0; idx < fwcount; idx++) {
1106 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1107 "request_firmware: Failed to find %s",
1108 fwnames[idx]);
1109 }
1110 }
1111 return ret;
1112}
1113
1114
1115/*
1116 * pvr2_upload_firmware1().
1117 *
1118 * Send the 8051 firmware to the device. After the upload, arrange for
1119 * device to re-enumerate.
1120 *
1121 * NOTE : the pointer to the firmware data given by request_firmware()
1122 * is not suitable for an usb transaction.
1123 *
1124 */
07e337ee 1125static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1126{
a0fd1cb1 1127 const struct firmware *fw_entry = NULL;
d855497e
MI		 1128 void *fw_ptr;
1129 unsigned int pipe;
1130 int ret;
1131 u16 address;
1132 static const char *fw_files_29xxx[] = {
1133 "v4l-pvrusb2-29xxx-01.fw",
1134 };
d855497e
MI		 1135 static const char *fw_files_24xxx[] = {
1136 "v4l-pvrusb2-24xxx-01.fw",
1137 };
d855497e
MI		 1138 static const struct pvr2_string_table fw_file_defs[] = {
1139 [PVR2_HDW_TYPE_29XXX] = {
eca8ebfc 1140 fw_files_29xxx, ARRAY_SIZE(fw_files_29xxx)
d855497e 1141 },
d855497e 1142 [PVR2_HDW_TYPE_24XXX] = {
eca8ebfc 1143 fw_files_24xxx, ARRAY_SIZE(fw_files_24xxx)
d855497e 1144 },
d855497e 1145 };
1d643a37
MI		 1146
1147 if ((hdw->hdw_type >= ARRAY_SIZE(fw_file_defs)) ||
1148 (!fw_file_defs[hdw->hdw_type].lst)) {
1149 hdw->fw1_state = FW1_STATE_OK;
1150 return 0;
1151 }
1152
d855497e
MI		 1153 hdw->fw1_state = FW1_STATE_FAILED; // default result
1154
1155 trace_firmware("pvr2_upload_firmware1");
1156
1157 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1158 fw_file_defs[hdw->hdw_type].cnt,
1159 fw_file_defs[hdw->hdw_type].lst);
1160 if (ret < 0) {
1161 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1162 return ret;
1163 }
1164
1165 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1166 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1167
1168 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1169
1170 if (fw_entry->size != 0x2000){
1171 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1172 release_firmware(fw_entry);
1173 return -ENOMEM;
1174 }
1175
1176 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1177 if (fw_ptr == NULL){
1178 release_firmware(fw_entry);
1179 return -ENOMEM;
1180 }
1181
1182 /* We have to hold the CPU during firmware upload. */
1183 pvr2_hdw_cpureset_assert(hdw,1);
1184
1185 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1186 chunk. */
1187
1188 ret = 0;
1189 for(address = 0; address < fw_entry->size; address += 0x800) {
1190 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1191 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1192 0, fw_ptr, 0x800, HZ);
1193 }
1194
1195 trace_firmware("Upload done, releasing device's CPU");
1196
1197 /* Now release the CPU. It will disconnect and reconnect later. */
1198 pvr2_hdw_cpureset_assert(hdw,0);
1199
1200 kfree(fw_ptr);
1201 release_firmware(fw_entry);
1202
1203 trace_firmware("Upload done (%d bytes sent)",ret);
1204
1205 /* We should have written 8192 bytes */
1206 if (ret == 8192) {
1207 hdw->fw1_state = FW1_STATE_RELOAD;
1208 return 0;
1209 }
1210
1211 return -EIO;
1212}
1213
1214
1215/*
1216 * pvr2_upload_firmware2()
1217 *
1218 * This uploads encoder firmware on endpoint 2.
1219 *
1220 */
1221
1222int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1223{
a0fd1cb1 1224 const struct firmware *fw_entry = NULL;
d855497e 1225 void *fw_ptr;
90060d32 1226 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1227 int actual_length;
1228 int ret = 0;
1229 int fwidx;
1230 static const char *fw_files[] = {
1231 CX2341X_FIRM_ENC_FILENAME,
1232 };
1233
1d643a37
MI		 1234 if ((hdw->hdw_type != PVR2_HDW_TYPE_29XXX) &&
1235 (hdw->hdw_type != PVR2_HDW_TYPE_24XXX)) {
1236 return 0;
1237 }
1238
d855497e
MI		 1239 trace_firmware("pvr2_upload_firmware2");
1240
1241 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1242 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1243 if (ret < 0) return ret;
1244 fwidx = ret;
1245 ret = 0;
b30d2441
MI		 1246 /* Since we're about to completely reinitialize the encoder,
1247 invalidate our cached copy of its configuration state. Next
1248 time we configure the encoder, then we'll fully configure it. */
1249 hdw->enc_cur_valid = 0;
d855497e 1250
9a607f01
MI		 1251 hdw->flag_encoder_ok = 0;
1252
d855497e
MI		 1253 /* First prepare firmware loading */
1254 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1255 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1256 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1257 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1258 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1259 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1260 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1261 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1262 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1263 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1264 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1265 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1266 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1267 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1268 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1269 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
567d7115
MI		 1270 LOCK_TAKE(hdw->ctl_lock); do {
1271 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
89952d13 1272 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
567d7115
MI		 1273 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1274 hdw->cmd_buffer[1] = 0;
89952d13 1275 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
567d7115 1276 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 1277
1278 if (ret) {
1279 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1280 "firmware2 upload prep failed, ret=%d",ret);
1281 release_firmware(fw_entry);
1282 return ret;
1283 }
1284
1285 /* Now send firmware */
1286
1287 fw_len = fw_entry->size;
1288
90060d32 1289 if (fw_len % sizeof(u32)) {
d855497e
MI		 1290 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1291 "size of %s firmware"
48dc30a1 1292 " must be a multiple of %zu bytes",
90060d32 1293 fw_files[fwidx],sizeof(u32));
d855497e
MI		 1294 release_firmware(fw_entry);
1295 return -1;
1296 }
1297
1298 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1299 if (fw_ptr == NULL){
1300 release_firmware(fw_entry);
1301 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1302 "failed to allocate memory for firmware2 upload");
1303 return -ENOMEM;
1304 }
1305
1306 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1307
90060d32
MI		 1308 fw_done = 0;
1309 for (fw_done = 0; fw_done < fw_len;) {
1310 bcnt = fw_len - fw_done;
1311 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1312 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1313 /* Usbsnoop log shows that we must swap bytes... */
1314 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1315 ((u32 *)fw_ptr)[icnt] =
1316 ___swab32(((u32 *)fw_ptr)[icnt]);
1317
1318 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1319 &actual_length, HZ);
90060d32
MI		 1320 ret |= (actual_length != bcnt);
1321 if (ret) break;
1322 fw_done += bcnt;
d855497e
MI		 1323 }
1324
1325 trace_firmware("upload of %s : %i / %i ",
1326 fw_files[fwidx],fw_done,fw_len);
1327
1328 kfree(fw_ptr);
1329 release_firmware(fw_entry);
1330
1331 if (ret) {
1332 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1333 "firmware2 upload transfer failure");
1334 return ret;
1335 }
1336
1337 /* Finish upload */
1338
1339 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1340 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
567d7115
MI		 1341 LOCK_TAKE(hdw->ctl_lock); do {
1342 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1343 hdw->cmd_buffer[1] = 0;
89952d13 1344 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
567d7115 1345 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 1346
1347 if (ret) {
1348 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1349 "firmware2 upload post-proc failure");
1350 } else {
9a607f01 1351 hdw->flag_encoder_ok = !0;
d855497e
MI		 1352 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_FIRMWARE);
1353 }
1354 return ret;
1355}
1356
1357
1358#define FIRMWARE_RECOVERY_BITS \
1359 ((1<<PVR2_SUBSYS_B_ENC_CFG) | \
1360 (1<<PVR2_SUBSYS_B_ENC_RUN) | \
1361 (1<<PVR2_SUBSYS_B_ENC_FIRMWARE) | \
1362 (1<<PVR2_SUBSYS_B_USBSTREAM_RUN))
1363
1364/*
1365
1366 This single function is key to pretty much everything. The pvrusb2
1367 device can logically be viewed as a series of subsystems which can be
1368 stopped / started or unconfigured / configured. To get things streaming,
1369 one must configure everything and start everything, but there may be
1370 various reasons over time to deconfigure something or stop something.
1371 This function handles all of this activity. Everything EVERYWHERE that
1372 must affect a subsystem eventually comes here to do the work.
1373
1374 The current state of all subsystems is represented by a single bit mask,
1375 known as subsys_enabled_mask. The bit positions are defined by the
1376 PVR2_SUBSYS_xxxx macros, with one subsystem per bit position. At any
1377 time the set of configured or active subsystems can be queried just by
1378 looking at that mask. To change bits in that mask, this function here
1379 must be called. The "msk" argument indicates which bit positions to
1380 change, and the "val" argument defines the new values for the positions
1381 defined by "msk".
1382
1383 There is a priority ordering of starting / stopping things, and for
1384 multiple requested changes, this function implements that ordering.
1385 (Thus we will act on a request to load encoder firmware before we
1386 configure the encoder.) In addition to priority ordering, there is a
1387 recovery strategy implemented here. If a particular step fails and we
1388 detect that failure, this function will clear the affected subsystem bits
1389 and restart. Thus we have a means for recovering from a dead encoder:
1390 Clear all bits that correspond to subsystems that we need to restart /
1391 reconfigure and start over.
1392
1393*/
07e337ee
AB		 1394static void pvr2_hdw_subsys_bit_chg_no_lock(struct pvr2_hdw *hdw,
1395 unsigned long msk,
1396 unsigned long val)
d855497e
MI		 1397{
1398 unsigned long nmsk;
1399 unsigned long vmsk;
1400 int ret;
1401 unsigned int tryCount = 0;
1402
1403 if (!hdw->flag_ok) return;
1404
1405 msk &= PVR2_SUBSYS_ALL;
eb8e0ee4
MI		 1406 nmsk = (hdw->subsys_enabled_mask & ~msk) | (val & msk);
1407 nmsk &= PVR2_SUBSYS_ALL;
d855497e
MI		 1408
1409 for (;;) {
1410 tryCount++;
eb8e0ee4
MI		 1411 if (!((nmsk ^ hdw->subsys_enabled_mask) &
1412 PVR2_SUBSYS_ALL)) break;
d855497e
MI		 1413 if (tryCount > 4) {
1414 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1415 "Too many retries when configuring device;"
1416 " giving up");
1417 pvr2_hdw_render_useless(hdw);
1418 break;
1419 }
1420 if (tryCount > 1) {
1421 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1422 "Retrying device reconfiguration");
1423 }
1424 pvr2_trace(PVR2_TRACE_INIT,
1425 "subsys mask changing 0x%lx:0x%lx"
1426 " from 0x%lx to 0x%lx",
1427 msk,val,hdw->subsys_enabled_mask,nmsk);
1428
1429 vmsk = (nmsk ^ hdw->subsys_enabled_mask) &
1430 hdw->subsys_enabled_mask;
1431 if (vmsk) {
1432 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1433 pvr2_trace(PVR2_TRACE_CTL,
1434 "/*---TRACE_CTL----*/"
1435 " pvr2_encoder_stop");
1436 ret = pvr2_encoder_stop(hdw);
1437 if (ret) {
1438 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1439 "Error recovery initiated");
1440 hdw->subsys_enabled_mask &=
1441 ~FIRMWARE_RECOVERY_BITS;
1442 continue;
1443 }
1444 }
1445 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1446 pvr2_trace(PVR2_TRACE_CTL,
1447 "/*---TRACE_CTL----*/"
1448 " pvr2_hdw_cmd_usbstream(0)");
1449 pvr2_hdw_cmd_usbstream(hdw,0);
1450 }
1451 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1452 pvr2_trace(PVR2_TRACE_CTL,
1453 "/*---TRACE_CTL----*/"
1454 " decoder disable");
1455 if (hdw->decoder_ctrl) {
1456 hdw->decoder_ctrl->enable(
1457 hdw->decoder_ctrl->ctxt,0);
1458 } else {
1459 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1460 "WARNING:"
1461 " No decoder present");
1462 }
1463 hdw->subsys_enabled_mask &=
1464 ~(1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1465 }
1466 if (vmsk & PVR2_SUBSYS_CFG_ALL) {
1467 hdw->subsys_enabled_mask &=
1468 ~(vmsk & PVR2_SUBSYS_CFG_ALL);
1469 }
1470 }
1471 vmsk = (nmsk ^ hdw->subsys_enabled_mask) & nmsk;
1472 if (vmsk) {
1473 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_FIRMWARE)) {
1474 pvr2_trace(PVR2_TRACE_CTL,
1475 "/*---TRACE_CTL----*/"
1476 " pvr2_upload_firmware2");
1477 ret = pvr2_upload_firmware2(hdw);
1478 if (ret) {
1479 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1480 "Failure uploading encoder"
1481 " firmware");
1482 pvr2_hdw_render_useless(hdw);
1483 break;
1484 }
1485 }
1486 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_CFG)) {
1487 pvr2_trace(PVR2_TRACE_CTL,
1488 "/*---TRACE_CTL----*/"
1489 " pvr2_encoder_configure");
1490 ret = pvr2_encoder_configure(hdw);
1491 if (ret) {
1492 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1493 "Error recovery initiated");
1494 hdw->subsys_enabled_mask &=
1495 ~FIRMWARE_RECOVERY_BITS;
1496 continue;
1497 }
1498 }
1499 if (vmsk & (1<<PVR2_SUBSYS_B_DIGITIZER_RUN)) {
1500 pvr2_trace(PVR2_TRACE_CTL,
1501 "/*---TRACE_CTL----*/"
1502 " decoder enable");
1503 if (hdw->decoder_ctrl) {
1504 hdw->decoder_ctrl->enable(
1505 hdw->decoder_ctrl->ctxt,!0);
1506 } else {
1507 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1508 "WARNING:"
1509 " No decoder present");
1510 }
1511 hdw->subsys_enabled_mask |=
1512 (1<<PVR2_SUBSYS_B_DIGITIZER_RUN);
1513 }
1514 if (vmsk & (1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) {
1515 pvr2_trace(PVR2_TRACE_CTL,
1516 "/*---TRACE_CTL----*/"
1517 " pvr2_hdw_cmd_usbstream(1)");
1518 pvr2_hdw_cmd_usbstream(hdw,!0);
1519 }
1520 if (vmsk & (1<<PVR2_SUBSYS_B_ENC_RUN)) {
1521 pvr2_trace(PVR2_TRACE_CTL,
1522 "/*---TRACE_CTL----*/"
1523 " pvr2_encoder_start");
1524 ret = pvr2_encoder_start(hdw);
1525 if (ret) {
1526 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1527 "Error recovery initiated");
1528 hdw->subsys_enabled_mask &=
1529 ~FIRMWARE_RECOVERY_BITS;
1530 continue;
1531 }
1532 }
1533 }
1534 }
1535}
1536
1537
1538void pvr2_hdw_subsys_bit_chg(struct pvr2_hdw *hdw,
1539 unsigned long msk,unsigned long val)
1540{
1541 LOCK_TAKE(hdw->big_lock); do {
1542 pvr2_hdw_subsys_bit_chg_no_lock(hdw,msk,val);
1543 } while (0); LOCK_GIVE(hdw->big_lock);
1544}
1545
1546
d855497e
MI		 1547unsigned long pvr2_hdw_subsys_get(struct pvr2_hdw *hdw)
1548{
1549 return hdw->subsys_enabled_mask;
1550}
1551
1552
1553unsigned long pvr2_hdw_subsys_stream_get(struct pvr2_hdw *hdw)
1554{
1555 return hdw->subsys_stream_mask;
1556}
1557
1558
07e337ee
AB		 1559static void pvr2_hdw_subsys_stream_bit_chg_no_lock(struct pvr2_hdw *hdw,
1560 unsigned long msk,
1561 unsigned long val)
d855497e
MI		 1562{
1563 unsigned long val2;
1564 msk &= PVR2_SUBSYS_ALL;
1565 val2 = ((hdw->subsys_stream_mask & ~msk) | (val & msk));
1566 pvr2_trace(PVR2_TRACE_INIT,
1567 "stream mask changing 0x%lx:0x%lx from 0x%lx to 0x%lx",
1568 msk,val,hdw->subsys_stream_mask,val2);
1569 hdw->subsys_stream_mask = val2;
1570}
1571
1572
1573void pvr2_hdw_subsys_stream_bit_chg(struct pvr2_hdw *hdw,
1574 unsigned long msk,
1575 unsigned long val)
1576{
1577 LOCK_TAKE(hdw->big_lock); do {
1578 pvr2_hdw_subsys_stream_bit_chg_no_lock(hdw,msk,val);
1579 } while (0); LOCK_GIVE(hdw->big_lock);
1580}
1581
1582
07e337ee 1583static int pvr2_hdw_set_streaming_no_lock(struct pvr2_hdw *hdw,int enableFl)
d855497e
MI		 1584{
1585 if ((!enableFl) == !(hdw->flag_streaming_enabled)) return 0;
1586 if (enableFl) {
1587 pvr2_trace(PVR2_TRACE_START_STOP,
1588 "/*--TRACE_STREAM--*/ enable");
1589 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,~0);
1590 } else {
1591 pvr2_trace(PVR2_TRACE_START_STOP,
1592 "/*--TRACE_STREAM--*/ disable");
1593 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1594 }
1595 if (!hdw->flag_ok) return -EIO;
1596 hdw->flag_streaming_enabled = enableFl != 0;
1597 return 0;
1598}
1599
1600
1601int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1602{
1603 return hdw->flag_streaming_enabled != 0;
1604}
1605
1606
1607int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1608{
1609 int ret;
1610 LOCK_TAKE(hdw->big_lock); do {
1611 ret = pvr2_hdw_set_streaming_no_lock(hdw,enable_flag);
1612 } while (0); LOCK_GIVE(hdw->big_lock);
1613 return ret;
1614}
1615
1616
07e337ee
AB		 1617static int pvr2_hdw_set_stream_type_no_lock(struct pvr2_hdw *hdw,
1618 enum pvr2_config config)
d855497e
MI		 1619{
1620 unsigned long sm = hdw->subsys_enabled_mask;
1621 if (!hdw->flag_ok) return -EIO;
1622 pvr2_hdw_subsys_bit_chg_no_lock(hdw,hdw->subsys_stream_mask,0);
1623 hdw->config = config;
1624 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,sm);
1625 return 0;
1626}
1627
1628
1629int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1630{
1631 int ret;
1632 if (!hdw->flag_ok) return -EIO;
1633 LOCK_TAKE(hdw->big_lock);
1634 ret = pvr2_hdw_set_stream_type_no_lock(hdw,config);
1635 LOCK_GIVE(hdw->big_lock);
1636 return ret;
1637}
1638
1639
1640static int get_default_tuner_type(struct pvr2_hdw *hdw)
1641{
1642 int unit_number = hdw->unit_number;
1643 int tp = -1;
1644 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1645 tp = tuner[unit_number];
1646 }
1647 if (tp < 0) return -EINVAL;
1648 hdw->tuner_type = tp;
1649 return 0;
1650}
1651
1652
1653static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1654{
1655 int unit_number = hdw->unit_number;
1656 int tp = 0;
1657 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1658 tp = video_std[unit_number];
1659 }
1660 return tp;
1661}
1662
1663
1664static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1665{
1666 int unit_number = hdw->unit_number;
1667 int tp = 0;
1668 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1669 tp = tolerance[unit_number];
1670 }
1671 return tp;
1672}
1673
1674
1675static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1676{
1677 /* Try a harmless request to fetch the eeprom's address over
1678 endpoint 1. See what happens. Only the full FX2 image can
1679 respond to this. If this probe fails then likely the FX2
1680 firmware needs be loaded. */
1681 int result;
1682 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1683 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1684 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1685 hdw->cmd_buffer,1,
1686 hdw->cmd_buffer,1);
1687 if (result < 0) break;
1688 } while(0); LOCK_GIVE(hdw->ctl_lock);
1689 if (result) {
1690 pvr2_trace(PVR2_TRACE_INIT,
1691 "Probe of device endpoint 1 result status %d",
1692 result);
1693 } else {
1694 pvr2_trace(PVR2_TRACE_INIT,
1695 "Probe of device endpoint 1 succeeded");
1696 }
1697 return result == 0;
1698}
1699
9f66d4ea
MI		 1700struct pvr2_std_hack {
1701 v4l2_std_id pat; /* Pattern to match */
1702 v4l2_std_id msk; /* Which bits we care about */
1703 v4l2_std_id std; /* What additional standards or default to set */
1704};
1705
1706/* This data structure labels specific combinations of standards from
1707 tveeprom that we'll try to recognize. If we recognize one, then assume
1708 a specified default standard to use. This is here because tveeprom only
1709 tells us about available standards not the intended default standard (if
1710 any) for the device in question. We guess the default based on what has
1711 been reported as available. Note that this is only for guessing a
1712 default - which can always be overridden explicitly - and if the user
1713 has otherwise named a default then that default will always be used in
1714 place of this table. */
1715const static struct pvr2_std_hack std_eeprom_maps[] = {
1716 { /* PAL(B/G) */
1717 .pat = V4L2_STD_B|V4L2_STD_GH,
1718 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1719 },
1720 { /* NTSC(M) */
1721 .pat = V4L2_STD_MN,
1722 .std = V4L2_STD_NTSC_M,
1723 },
1724 { /* PAL(I) */
1725 .pat = V4L2_STD_PAL_I,
1726 .std = V4L2_STD_PAL_I,
1727 },
1728 { /* SECAM(L/L') */
1729 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1730 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1731 },
1732 { /* PAL(D/D1/K) */
1733 .pat = V4L2_STD_DK,
1734 .std = V4L2_STD_PAL_D/V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1735 },
1736};
1737
d855497e
MI		 1738static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1739{
1740 char buf[40];
1741 unsigned int bcnt;
1742 v4l2_std_id std1,std2;
1743
1744 std1 = get_default_standard(hdw);
1745
1746 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1747 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1748 "Supported video standard(s) reported by eeprom: %.*s",
1749 bcnt,buf);
1750
1751 hdw->std_mask_avail = hdw->std_mask_eeprom;
1752
1753 std2 = std1 & ~hdw->std_mask_avail;
1754 if (std2) {
1755 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1756 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1757 "Expanding supported video standards"
1758 " to include: %.*s",
1759 bcnt,buf);
1760 hdw->std_mask_avail |= std2;
1761 }
1762
1763 pvr2_hdw_internal_set_std_avail(hdw);
1764
1765 if (std1) {
1766 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1767 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1768 "Initial video standard forced to %.*s",
1769 bcnt,buf);
1770 hdw->std_mask_cur = std1;
1771 hdw->std_dirty = !0;
1772 pvr2_hdw_internal_find_stdenum(hdw);
1773 return;
1774 }
1775
9f66d4ea
MI		 1776 {
1777 unsigned int idx;
1778 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1779 if (std_eeprom_maps[idx].msk ?
1780 ((std_eeprom_maps[idx].pat ^
1781 hdw->std_mask_eeprom) &
1782 std_eeprom_maps[idx].msk) :
1783 (std_eeprom_maps[idx].pat !=
1784 hdw->std_mask_eeprom)) continue;
1785 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1786 std_eeprom_maps[idx].std);
56585386 1787 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1788 "Initial video standard guessed as %.*s",
1789 bcnt,buf);
1790 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1791 hdw->std_dirty = !0;
1792 pvr2_hdw_internal_find_stdenum(hdw);
1793 return;
1794 }
1795 }
1796
d855497e
MI		 1797 if (hdw->std_enum_cnt > 1) {
1798 // Autoselect the first listed standard
1799 hdw->std_enum_cur = 1;
1800 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1801 hdw->std_dirty = !0;
56585386 1802 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1803 "Initial video standard auto-selected to %s",
1804 hdw->std_defs[hdw->std_enum_cur-1].name);
1805 return;
1806 }
1807
0885ba1d 1808 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1809 "Unable to select a viable initial video standard");
1810}
1811
1812
1813static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1814{
1815 int ret;
1816 unsigned int idx;
1817 struct pvr2_ctrl *cptr;
1818 int reloadFl = 0;
1d643a37
MI		 1819 if ((hdw->hdw_type == PVR2_HDW_TYPE_29XXX) ||
1820 (hdw->hdw_type == PVR2_HDW_TYPE_24XXX)) {
1821 if (!reloadFl) {
1822 reloadFl =
1823 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1824 == 0);
1825 if (reloadFl) {
1826 pvr2_trace(PVR2_TRACE_INIT,
1827 "USB endpoint config looks strange"
1828 "; possibly firmware needs to be"
1829 " loaded");
1830 }
d855497e 1831 }
1d643a37
MI		 1832 if (!reloadFl) {
1833 reloadFl = !pvr2_hdw_check_firmware(hdw);
1834 if (reloadFl) {
1835 pvr2_trace(PVR2_TRACE_INIT,
1836 "Check for FX2 firmware failed"
1837 "; possibly firmware needs to be"
1838 " loaded");
1839 }
d855497e 1840 }
1d643a37
MI		 1841 if (reloadFl) {
1842 if (pvr2_upload_firmware1(hdw) != 0) {
1843 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1844 "Failure uploading firmware1");
1845 }
1846 return;
d855497e 1847 }
d855497e
MI		 1848 }
1849 hdw->fw1_state = FW1_STATE_OK;
1850
1851 if (initusbreset) {
1852 pvr2_hdw_device_reset(hdw);
1853 }
1854 if (!pvr2_hdw_dev_ok(hdw)) return;
1855
1d643a37
MI		 1856 if (hdw->hdw_type < ARRAY_SIZE(pvr2_client_lists)) {
1857 for (idx = 0;
1858 idx < pvr2_client_lists[hdw->hdw_type].cnt;
1859 idx++) {
1860 request_module(
1861 pvr2_client_lists[hdw->hdw_type].lst[idx]);
1862 }
d855497e
MI		 1863 }
1864
1d643a37
MI		 1865 if ((hdw->hdw_type == PVR2_HDW_TYPE_29XXX) ||
1866 (hdw->hdw_type == PVR2_HDW_TYPE_24XXX)) {
1867 pvr2_hdw_cmd_powerup(hdw);
1868 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e 1869
1d643a37
MI		 1870 if (pvr2_upload_firmware2(hdw)){
1871 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"device unstable!!");
1872 pvr2_hdw_render_useless(hdw);
1873 return;
1874 }
d855497e
MI		 1875 }
1876
1877 // This step MUST happen after the earlier powerup step.
1878 pvr2_i2c_core_init(hdw);
1879 if (!pvr2_hdw_dev_ok(hdw)) return;
1880
c05c0462 1881 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 1882 cptr = hdw->controls + idx;
1883 if (cptr->info->skip_init) continue;
1884 if (!cptr->info->set_value) continue;
1885 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1886 }
1887
1bde0289
MI		 1888 /* Set up special default values for the television and radio
1889 frequencies here. It's not really important what these defaults
1890 are, but I set them to something usable in the Chicago area just
1891 to make driver testing a little easier. */
1892
1893 /* US Broadcast channel 7 (175.25 MHz) */
1894 hdw->freqValTelevision = 175250000L;
1895 /* 104.3 MHz, a usable FM station for my area */
1896 hdw->freqValRadio = 104300000L;
1897
d855497e
MI		 1898 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1899 // thread-safe against the normal pvr2_send_request() mechanism.
1900 // (We should make it thread safe).
1901
1902 ret = pvr2_hdw_get_eeprom_addr(hdw);
1903 if (!pvr2_hdw_dev_ok(hdw)) return;
1904 if (ret < 0) {
1905 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1906 "Unable to determine location of eeprom, skipping");
1907 } else {
1908 hdw->eeprom_addr = ret;
1909 pvr2_eeprom_analyze(hdw);
1910 if (!pvr2_hdw_dev_ok(hdw)) return;
1911 }
1912
1913 pvr2_hdw_setup_std(hdw);
1914
1915 if (!get_default_tuner_type(hdw)) {
1916 pvr2_trace(PVR2_TRACE_INIT,
1917 "pvr2_hdw_setup: Tuner type overridden to %d",
1918 hdw->tuner_type);
1919 }
1920
1921 hdw->tuner_updated = !0;
1922 pvr2_i2c_core_check_stale(hdw);
1923 hdw->tuner_updated = 0;
1924
1925 if (!pvr2_hdw_dev_ok(hdw)) return;
1926
1927 pvr2_hdw_commit_ctl_internal(hdw);
1928 if (!pvr2_hdw_dev_ok(hdw)) return;
1929
1930 hdw->vid_stream = pvr2_stream_create();
1931 if (!pvr2_hdw_dev_ok(hdw)) return;
1932 pvr2_trace(PVR2_TRACE_INIT,
1933 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1934 if (hdw->vid_stream) {
1935 idx = get_default_error_tolerance(hdw);
1936 if (idx) {
1937 pvr2_trace(PVR2_TRACE_INIT,
1938 "pvr2_hdw_setup: video stream %p"
1939 " setting tolerance %u",
1940 hdw->vid_stream,idx);
1941 }
1942 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1943 PVR2_VID_ENDPOINT,idx);
1944 }
1945
1946 if (!pvr2_hdw_dev_ok(hdw)) return;
1947
1948 /* Make sure everything is up to date */
1949 pvr2_i2c_core_sync(hdw);
1950
1951 if (!pvr2_hdw_dev_ok(hdw)) return;
1952
1953 hdw->flag_init_ok = !0;
1954}
1955
1956
1957int pvr2_hdw_setup(struct pvr2_hdw *hdw)
1958{
1959 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1960 LOCK_TAKE(hdw->big_lock); do {
1961 pvr2_hdw_setup_low(hdw);
1962 pvr2_trace(PVR2_TRACE_INIT,
1963 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1964 hdw,hdw->flag_ok,hdw->flag_init_ok);
1965 if (pvr2_hdw_dev_ok(hdw)) {
1966 if (pvr2_hdw_init_ok(hdw)) {
1967 pvr2_trace(
1968 PVR2_TRACE_INFO,
1969 "Device initialization"
1970 " completed successfully.");
1971 break;
1972 }
1973 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1974 pvr2_trace(
1975 PVR2_TRACE_INFO,
1976 "Device microcontroller firmware"
1977 " (re)loaded; it should now reset"
1978 " and reconnect.");
1979 break;
1980 }
1981 pvr2_trace(
1982 PVR2_TRACE_ERROR_LEGS,
1983 "Device initialization was not successful.");
1984 if (hdw->fw1_state == FW1_STATE_MISSING) {
1985 pvr2_trace(
1986 PVR2_TRACE_ERROR_LEGS,
1987 "Giving up since device"
1988 " microcontroller firmware"
1989 " appears to be missing.");
1990 break;
1991 }
1992 }
1993 if (procreload) {
1994 pvr2_trace(
1995 PVR2_TRACE_ERROR_LEGS,
1996 "Attempting pvrusb2 recovery by reloading"
1997 " primary firmware.");
1998 pvr2_trace(
1999 PVR2_TRACE_ERROR_LEGS,
2000 "If this works, device should disconnect"
2001 " and reconnect in a sane state.");
2002 hdw->fw1_state = FW1_STATE_UNKNOWN;
2003 pvr2_upload_firmware1(hdw);
2004 } else {
2005 pvr2_trace(
2006 PVR2_TRACE_ERROR_LEGS,
2007 "***WARNING*** pvrusb2 device hardware"
2008 " appears to be jammed"
2009 " and I can't clear it.");
2010 pvr2_trace(
2011 PVR2_TRACE_ERROR_LEGS,
2012 "You might need to power cycle"
2013 " the pvrusb2 device"
2014 " in order to recover.");
2015 }
2016 } while (0); LOCK_GIVE(hdw->big_lock);
2017 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2018 return hdw->flag_init_ok;
2019}
2020
2021
2022/* Create and return a structure for interacting with the underlying
2023 hardware */
2024struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2025 const struct usb_device_id *devid)
2026{
2027 unsigned int idx,cnt1,cnt2;
2028 struct pvr2_hdw *hdw;
2029 unsigned int hdw_type;
2030 int valid_std_mask;
2031 struct pvr2_ctrl *cptr;
2032 __u8 ifnum;
b30d2441
MI		 2033 struct v4l2_queryctrl qctrl;
2034 struct pvr2_ctl_info *ciptr;
d855497e
MI		 2035
2036 hdw_type = devid - pvr2_device_table;
eca8ebfc 2037 if (hdw_type >= ARRAY_SIZE(pvr2_device_names)) {
d855497e
MI		 2038 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2039 "Bogus device type of %u reported",hdw_type);
a0fd1cb1 2040 return NULL;
d855497e
MI		 2041 }
2042
ca545f7c 2043 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e
MI		 2044 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2045 hdw,pvr2_device_names[hdw_type]);
2046 if (!hdw) goto fail;
18103c57 2047 hdw->tuner_signal_stale = !0;
b30d2441 2048 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2049
c05c0462 2050 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2051 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2052 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2053 GFP_KERNEL);
2054 if (!hdw->controls) goto fail;
d855497e 2055 hdw->hdw_type = hdw_type;
c05c0462
MI		 2056 for (idx = 0; idx < hdw->control_cnt; idx++) {
2057 cptr = hdw->controls + idx;
2058 cptr->hdw = hdw;
2059 }
d855497e
MI		 2060 for (idx = 0; idx < 32; idx++) {
2061 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2062 }
c05c0462 2063 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2064 cptr = hdw->controls + idx;
d855497e
MI		 2065 cptr->info = control_defs+idx;
2066 }
b30d2441 2067 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2068 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2069 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2070 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2071 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2072 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2073 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2074 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2075 ciptr->name = mpeg_ids[idx].strid;
2076 ciptr->v4l_id = mpeg_ids[idx].id;
2077 ciptr->skip_init = !0;
2078 ciptr->get_value = ctrl_cx2341x_get;
2079 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2080 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2081 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2082 qctrl.id = ciptr->v4l_id;
2083 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2084 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2085 ciptr->set_value = ctrl_cx2341x_set;
2086 }
2087 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2088 PVR2_CTLD_INFO_DESC_SIZE);
2089 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2090 ciptr->default_value = qctrl.default_value;
2091 switch (qctrl.type) {
2092 default:
2093 case V4L2_CTRL_TYPE_INTEGER:
2094 ciptr->type = pvr2_ctl_int;
2095 ciptr->def.type_int.min_value = qctrl.minimum;
2096 ciptr->def.type_int.max_value = qctrl.maximum;
2097 break;
2098 case V4L2_CTRL_TYPE_BOOLEAN:
2099 ciptr->type = pvr2_ctl_bool;
2100 break;
2101 case V4L2_CTRL_TYPE_MENU:
2102 ciptr->type = pvr2_ctl_enum;
2103 ciptr->def.type_enum.value_names =
2104 cx2341x_ctrl_get_menu(ciptr->v4l_id);
2105 for (cnt1 = 0;
2106 ciptr->def.type_enum.value_names[cnt1] != NULL;
2107 cnt1++) { }
2108 ciptr->def.type_enum.count = cnt1;
2109 break;
2110 }
2111 cptr->info = ciptr;
2112 }
d855497e
MI		 2113
2114 // Initialize video standard enum dynamic control
2115 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2116 if (cptr) {
2117 memcpy(&hdw->std_info_enum,cptr->info,
2118 sizeof(hdw->std_info_enum));
2119 cptr->info = &hdw->std_info_enum;
2120
2121 }
2122 // Initialize control data regarding video standard masks
2123 valid_std_mask = pvr2_std_get_usable();
2124 for (idx = 0; idx < 32; idx++) {
2125 if (!(valid_std_mask & (1 << idx))) continue;
2126 cnt1 = pvr2_std_id_to_str(
2127 hdw->std_mask_names[idx],
2128 sizeof(hdw->std_mask_names[idx])-1,
2129 1 << idx);
2130 hdw->std_mask_names[idx][cnt1] = 0;
2131 }
2132 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2133 if (cptr) {
2134 memcpy(&hdw->std_info_avail,cptr->info,
2135 sizeof(hdw->std_info_avail));
2136 cptr->info = &hdw->std_info_avail;
2137 hdw->std_info_avail.def.type_bitmask.bit_names =
2138 hdw->std_mask_ptrs;
2139 hdw->std_info_avail.def.type_bitmask.valid_bits =
2140 valid_std_mask;
2141 }
2142 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2143 if (cptr) {
2144 memcpy(&hdw->std_info_cur,cptr->info,
2145 sizeof(hdw->std_info_cur));
2146 cptr->info = &hdw->std_info_cur;
2147 hdw->std_info_cur.def.type_bitmask.bit_names =
2148 hdw->std_mask_ptrs;
2149 hdw->std_info_avail.def.type_bitmask.valid_bits =
2150 valid_std_mask;
2151 }
2152
2153 hdw->eeprom_addr = -1;
2154 hdw->unit_number = -1;
8079384e
MI		 2155 hdw->v4l_minor_number_video = -1;
2156 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2157 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2158 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2159 if (!hdw->ctl_write_buffer) goto fail;
2160 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2161 if (!hdw->ctl_read_buffer) goto fail;
2162 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2163 if (!hdw->ctl_write_urb) goto fail;
2164 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2165 if (!hdw->ctl_read_urb) goto fail;
2166
8df0c87c 2167 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2168 for (idx = 0; idx < PVR_NUM; idx++) {
2169 if (unit_pointers[idx]) continue;
2170 hdw->unit_number = idx;
2171 unit_pointers[idx] = hdw;
2172 break;
2173 }
8df0c87c 2174 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2175
2176 cnt1 = 0;
2177 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2178 cnt1 += cnt2;
2179 if (hdw->unit_number >= 0) {
2180 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2181 ('a' + hdw->unit_number));
2182 cnt1 += cnt2;
2183 }
2184 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2185 hdw->name[cnt1] = 0;
2186
2187 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2188 hdw->unit_number,hdw->name);
2189
2190 hdw->tuner_type = -1;
2191 hdw->flag_ok = !0;
2192 /* Initialize the mask of subsystems that we will shut down when we
2193 stop streaming. */
2194 hdw->subsys_stream_mask = PVR2_SUBSYS_RUN_ALL;
2195 hdw->subsys_stream_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
2196
2197 pvr2_trace(PVR2_TRACE_INIT,"subsys_stream_mask: 0x%lx",
2198 hdw->subsys_stream_mask);
2199
2200 hdw->usb_intf = intf;
2201 hdw->usb_dev = interface_to_usbdev(intf);
2202
31a18547
MI		 2203 scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2204 "usb %s address %d",
2205 hdw->usb_dev->dev.bus_id,
2206 hdw->usb_dev->devnum);
2207
d855497e
MI		 2208 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2209 usb_set_interface(hdw->usb_dev,ifnum,0);
2210
2211 mutex_init(&hdw->ctl_lock_mutex);
2212 mutex_init(&hdw->big_lock_mutex);
2213
2214 return hdw;
2215 fail:
2216 if (hdw) {
5e55d2ce
MK		 2217 usb_free_urb(hdw->ctl_read_urb);
2218 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2219 kfree(hdw->ctl_read_buffer);
2220 kfree(hdw->ctl_write_buffer);
2221 kfree(hdw->controls);
2222 kfree(hdw->mpeg_ctrl_info);
d855497e
MI		 2223 kfree(hdw);
2224 }
a0fd1cb1 2225 return NULL;
d855497e
MI		 2226}
2227
2228
2229/* Remove _all_ associations between this driver and the underlying USB
2230 layer. */
07e337ee 2231static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2232{
2233 if (hdw->flag_disconnected) return;
2234 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2235 if (hdw->ctl_read_urb) {
2236 usb_kill_urb(hdw->ctl_read_urb);
2237 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2238 hdw->ctl_read_urb = NULL;
d855497e
MI		 2239 }
2240 if (hdw->ctl_write_urb) {
2241 usb_kill_urb(hdw->ctl_write_urb);
2242 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2243 hdw->ctl_write_urb = NULL;
d855497e
MI		 2244 }
2245 if (hdw->ctl_read_buffer) {
2246 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2247 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2248 }
2249 if (hdw->ctl_write_buffer) {
2250 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2251 hdw->ctl_write_buffer = NULL;
d855497e
MI		 2252 }
2253 pvr2_hdw_render_useless_unlocked(hdw);
2254 hdw->flag_disconnected = !0;
a0fd1cb1
MI		 2255 hdw->usb_dev = NULL;
2256 hdw->usb_intf = NULL;
d855497e
MI		 2257}
2258
2259
2260/* Destroy hardware interaction structure */
2261void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2262{
401c27ce 2263 if (!hdw) return;
d855497e
MI		 2264 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2265 if (hdw->fw_buffer) {
2266 kfree(hdw->fw_buffer);
a0fd1cb1 2267 hdw->fw_buffer = NULL;
d855497e
MI		 2268 }
2269 if (hdw->vid_stream) {
2270 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2271 hdw->vid_stream = NULL;
d855497e 2272 }
d855497e
MI		 2273 if (hdw->decoder_ctrl) {
2274 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2275 }
2276 pvr2_i2c_core_done(hdw);
2277 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2278 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2279 if ((hdw->unit_number >= 0) &&
2280 (hdw->unit_number < PVR_NUM) &&
2281 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2282 unit_pointers[hdw->unit_number] = NULL;
d855497e 2283 }
8df0c87c 2284 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2285 kfree(hdw->controls);
2286 kfree(hdw->mpeg_ctrl_info);
2287 kfree(hdw->std_defs);
2288 kfree(hdw->std_enum_names);
d855497e
MI		 2289 kfree(hdw);
2290}
2291
2292
2293int pvr2_hdw_init_ok(struct pvr2_hdw *hdw)
2294{
2295 return hdw->flag_init_ok;
2296}
2297
2298
2299int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2300{
2301 return (hdw && hdw->flag_ok);
2302}
2303
2304
2305/* Called when hardware has been unplugged */
2306void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2307{
2308 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2309 LOCK_TAKE(hdw->big_lock);
2310 LOCK_TAKE(hdw->ctl_lock);
2311 pvr2_hdw_remove_usb_stuff(hdw);
2312 LOCK_GIVE(hdw->ctl_lock);
2313 LOCK_GIVE(hdw->big_lock);
2314}
2315
2316
2317// Attempt to autoselect an appropriate value for std_enum_cur given
2318// whatever is currently in std_mask_cur
07e337ee 2319static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2320{
2321 unsigned int idx;
2322 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2323 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2324 hdw->std_enum_cur = idx;
2325 return;
2326 }
2327 }
2328 hdw->std_enum_cur = 0;
2329}
2330
2331
2332// Calculate correct set of enumerated standards based on currently known
2333// set of available standards bits.
07e337ee 2334static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2335{
2336 struct v4l2_standard *newstd;
2337 unsigned int std_cnt;
2338 unsigned int idx;
2339
2340 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2341
2342 if (hdw->std_defs) {
2343 kfree(hdw->std_defs);
a0fd1cb1 2344 hdw->std_defs = NULL;
d855497e
MI		 2345 }
2346 hdw->std_enum_cnt = 0;
2347 if (hdw->std_enum_names) {
2348 kfree(hdw->std_enum_names);
a0fd1cb1 2349 hdw->std_enum_names = NULL;
d855497e
MI		 2350 }
2351
2352 if (!std_cnt) {
2353 pvr2_trace(
2354 PVR2_TRACE_ERROR_LEGS,
2355 "WARNING: Failed to identify any viable standards");
2356 }
2357 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2358 hdw->std_enum_names[0] = "none";
2359 for (idx = 0; idx < std_cnt; idx++) {
2360 hdw->std_enum_names[idx+1] =
2361 newstd[idx].name;
2362 }
2363 // Set up the dynamic control for this standard
2364 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2365 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2366 hdw->std_defs = newstd;
2367 hdw->std_enum_cnt = std_cnt+1;
2368 hdw->std_enum_cur = 0;
2369 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2370}
2371
2372
2373int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2374 struct v4l2_standard *std,
2375 unsigned int idx)
2376{
2377 int ret = -EINVAL;
2378 if (!idx) return ret;
2379 LOCK_TAKE(hdw->big_lock); do {
2380 if (idx >= hdw->std_enum_cnt) break;
2381 idx--;
2382 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2383 ret = 0;
2384 } while (0); LOCK_GIVE(hdw->big_lock);
2385 return ret;
2386}
2387
2388
2389/* Get the number of defined controls */
2390unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2391{
c05c0462 2392 return hdw->control_cnt;
d855497e
MI		 2393}
2394
2395
2396/* Retrieve a control handle given its index (0..count-1) */
2397struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2398 unsigned int idx)
2399{
a0fd1cb1 2400 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2401 return hdw->controls + idx;
2402}
2403
2404
2405/* Retrieve a control handle given its index (0..count-1) */
2406struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2407 unsigned int ctl_id)
2408{
2409 struct pvr2_ctrl *cptr;
2410 unsigned int idx;
2411 int i;
2412
2413 /* This could be made a lot more efficient, but for now... */
c05c0462 2414 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2415 cptr = hdw->controls + idx;
2416 i = cptr->info->internal_id;
2417 if (i && (i == ctl_id)) return cptr;
2418 }
a0fd1cb1 2419 return NULL;
d855497e
MI		 2420}
2421
2422
a761f431 2423/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2424struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2425{
2426 struct pvr2_ctrl *cptr;
2427 unsigned int idx;
2428 int i;
2429
2430 /* This could be made a lot more efficient, but for now... */
c05c0462 2431 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2432 cptr = hdw->controls + idx;
2433 i = cptr->info->v4l_id;
2434 if (i && (i == ctl_id)) return cptr;
2435 }
a0fd1cb1 2436 return NULL;
d855497e
MI		 2437}
2438
2439
a761f431
MI		 2440/* Given a V4L ID for its immediate predecessor, retrieve the control
2441 structure associated with it. */
2442struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2443 unsigned int ctl_id)
2444{
2445 struct pvr2_ctrl *cptr,*cp2;
2446 unsigned int idx;
2447 int i;
2448
2449 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2450 cp2 = NULL;
a761f431
MI		 2451 for (idx = 0; idx < hdw->control_cnt; idx++) {
2452 cptr = hdw->controls + idx;
2453 i = cptr->info->v4l_id;
2454 if (!i) continue;
2455 if (i <= ctl_id) continue;
2456 if (cp2 && (cp2->info->v4l_id < i)) continue;
2457 cp2 = cptr;
2458 }
2459 return cp2;
a0fd1cb1 2460 return NULL;
a761f431
MI		 2461}
2462
2463
d855497e
MI		 2464static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2465{
2466 switch (tp) {
2467 case pvr2_ctl_int: return "integer";
2468 case pvr2_ctl_enum: return "enum";
33213963 2469 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2470 case pvr2_ctl_bitmask: return "bitmask";
2471 }
2472 return "";
2473}
2474
2475
2476/* Commit all control changes made up to this point. Subsystems can be
2477 indirectly affected by these changes. For a given set of things being
2478 committed, we'll clear the affected subsystem bits and then once we're
2479 done committing everything we'll make a request to restore the subsystem
2480 state(s) back to their previous value before this function was called.
2481 Thus we can automatically reconfigure affected pieces of the driver as
2482 controls are changed. */
07e337ee 2483static int pvr2_hdw_commit_ctl_internal(struct pvr2_hdw *hdw)
d855497e
MI		 2484{
2485 unsigned long saved_subsys_mask = hdw->subsys_enabled_mask;
2486 unsigned long stale_subsys_mask = 0;
2487 unsigned int idx;
2488 struct pvr2_ctrl *cptr;
2489 int value;
2490 int commit_flag = 0;
2491 char buf[100];
2492 unsigned int bcnt,ccnt;
2493
c05c0462 2494 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2495 cptr = hdw->controls + idx;
2496 if (cptr->info->is_dirty == 0) continue;
2497 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 2498 commit_flag = !0;
d855497e 2499
fe23a280 2500 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 2501 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2502 cptr->info->name);
2503 value = 0;
2504 cptr->info->get_value(cptr,&value);
2505 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2506 buf+bcnt,
2507 sizeof(buf)-bcnt,&ccnt);
2508 bcnt += ccnt;
2509 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2510 get_ctrl_typename(cptr->info->type));
2511 pvr2_trace(PVR2_TRACE_CTL,
2512 "/*--TRACE_COMMIT--*/ %.*s",
2513 bcnt,buf);
2514 }
2515
2516 if (!commit_flag) {
2517 /* Nothing has changed */
2518 return 0;
2519 }
2520
2521 /* When video standard changes, reset the hres and vres values -
2522 but if the user has pending changes there, then let the changes
2523 take priority. */
2524 if (hdw->std_dirty) {
2525 /* Rewrite the vertical resolution to be appropriate to the
2526 video standard that has been selected. */
2527 int nvres;
2528 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2529 nvres = 480;
2530 } else {
2531 nvres = 576;
2532 }
2533 if (nvres != hdw->res_ver_val) {
2534 hdw->res_ver_val = nvres;
2535 hdw->res_ver_dirty = !0;
2536 }
d855497e
MI		 2537 }
2538
2539 if (hdw->std_dirty ||
434449f4
MI		 2540 hdw->enc_stale ||
2541 hdw->srate_dirty ||
2542 hdw->res_ver_dirty ||
2543 hdw->res_hor_dirty ||
b46cfa80 2544 0) {
d855497e
MI		 2545 /* If any of this changes, then the encoder needs to be
2546 reconfigured, and we need to reset the stream. */
2547 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
d855497e
MI		 2548 }
2549
275b2e28
PK		 2550 if (hdw->input_dirty) {
2551 /* pk: If input changes to or from radio, then the encoder
2552 needs to be restarted (for ENC_MUTE_VIDEO to work) */
2553 stale_subsys_mask |= (1<<PVR2_SUBSYS_B_ENC_RUN);
2554 }
2555
2556
b30d2441
MI		 2557 if (hdw->srate_dirty) {
2558 /* Write new sample rate into control structure since
2559 * the master copy is stale. We must track srate
2560 * separate from the mpeg control structure because
2561 * other logic also uses this value. */
2562 struct v4l2_ext_controls cs;
2563 struct v4l2_ext_control c1;
2564 memset(&cs,0,sizeof(cs));
2565 memset(&c1,0,sizeof(c1));
2566 cs.controls = &c1;
2567 cs.count = 1;
2568 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2569 c1.value = hdw->srate_val;
01f1e44f 2570 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 2571 }
c05c0462 2572
d855497e
MI		 2573 /* Scan i2c core at this point - before we clear all the dirty
2574 bits. Various parts of the i2c core will notice dirty bits as
2575 appropriate and arrange to broadcast or directly send updates to
2576 the client drivers in order to keep everything in sync */
2577 pvr2_i2c_core_check_stale(hdw);
2578
c05c0462 2579 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2580 cptr = hdw->controls + idx;
2581 if (!cptr->info->clear_dirty) continue;
2582 cptr->info->clear_dirty(cptr);
2583 }
2584
2585 /* Now execute i2c core update */
2586 pvr2_i2c_core_sync(hdw);
2587
2588 pvr2_hdw_subsys_bit_chg_no_lock(hdw,stale_subsys_mask,0);
2589 pvr2_hdw_subsys_bit_chg_no_lock(hdw,~0,saved_subsys_mask);
2590
2591 return 0;
2592}
2593
2594
2595int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2596{
2597 LOCK_TAKE(hdw->big_lock); do {
2598 pvr2_hdw_commit_ctl_internal(hdw);
2599 } while (0); LOCK_GIVE(hdw->big_lock);
2600 return 0;
2601}
2602
2603
2604void pvr2_hdw_poll(struct pvr2_hdw *hdw)
2605{
2606 LOCK_TAKE(hdw->big_lock); do {
2607 pvr2_i2c_core_sync(hdw);
2608 } while (0); LOCK_GIVE(hdw->big_lock);
2609}
2610
2611
2612void pvr2_hdw_setup_poll_trigger(struct pvr2_hdw *hdw,
2613 void (*func)(void *),
2614 void *data)
2615{
2616 LOCK_TAKE(hdw->big_lock); do {
2617 hdw->poll_trigger_func = func;
2618 hdw->poll_trigger_data = data;
2619 } while (0); LOCK_GIVE(hdw->big_lock);
2620}
2621
2622
2623void pvr2_hdw_poll_trigger_unlocked(struct pvr2_hdw *hdw)
2624{
2625 if (hdw->poll_trigger_func) {
2626 hdw->poll_trigger_func(hdw->poll_trigger_data);
2627 }
2628}
2629
d855497e
MI		 2630/* Return name for this driver instance */
2631const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2632{
2633 return hdw->name;
2634}
2635
2636
d855497e
MI		 2637int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2638{
2639 int result;
2640 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 2641 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 2642 result = pvr2_send_request(hdw,
2643 hdw->cmd_buffer,1,
2644 hdw->cmd_buffer,1);
2645 if (result < 0) break;
2646 result = (hdw->cmd_buffer[0] != 0);
2647 } while(0); LOCK_GIVE(hdw->ctl_lock);
2648 return result;
2649}
2650
2651
18103c57
MI		 2652/* Execute poll of tuner status */
2653void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 2654{
d855497e 2655 LOCK_TAKE(hdw->big_lock); do {
18103c57 2656 pvr2_i2c_core_status_poll(hdw);
d855497e 2657 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 2658}
2659
2660
2661/* Return information about the tuner */
2662int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2663{
2664 LOCK_TAKE(hdw->big_lock); do {
2665 if (hdw->tuner_signal_stale) {
2666 pvr2_i2c_core_status_poll(hdw);
2667 }
2668 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2669 } while (0); LOCK_GIVE(hdw->big_lock);
2670 return 0;
d855497e
MI		 2671}
2672
2673
2674/* Get handle to video output stream */
2675struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2676{
2677 return hp->vid_stream;
2678}
2679
2680
2681void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2682{
4f1a3e5b 2683 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e
MI		 2684 LOCK_TAKE(hdw->big_lock); do {
2685 hdw->log_requested = !0;
4f1a3e5b 2686 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
d855497e
MI		 2687 pvr2_i2c_core_check_stale(hdw);
2688 hdw->log_requested = 0;
2689 pvr2_i2c_core_sync(hdw);
b30d2441 2690 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 2691 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
4f1a3e5b 2692 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 2693 } while (0); LOCK_GIVE(hdw->big_lock);
2694}
2695
4db666cc
MI		 2696
2697/* Grab EEPROM contents, needed for direct method. */
2698#define EEPROM_SIZE 8192
2699#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2700static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2701{
2702 struct i2c_msg msg[2];
2703 u8 *eeprom;
2704 u8 iadd[2];
2705 u8 addr;
2706 u16 eepromSize;
2707 unsigned int offs;
2708 int ret;
2709 int mode16 = 0;
2710 unsigned pcnt,tcnt;
2711 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2712 if (!eeprom) {
2713 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2714 "Failed to allocate memory"
2715 " required to read eeprom");
2716 return NULL;
2717 }
2718
2719 trace_eeprom("Value for eeprom addr from controller was 0x%x",
2720 hdw->eeprom_addr);
2721 addr = hdw->eeprom_addr;
2722 /* Seems that if the high bit is set, then the *real* eeprom
2723 address is shifted right now bit position (noticed this in
2724 newer PVR USB2 hardware) */
2725 if (addr & 0x80) addr >>= 1;
2726
2727 /* FX2 documentation states that a 16bit-addressed eeprom is
2728 expected if the I2C address is an odd number (yeah, this is
2729 strange but it's what they do) */
2730 mode16 = (addr & 1);
2731 eepromSize = (mode16 ? EEPROM_SIZE : 256);
2732 trace_eeprom("Examining %d byte eeprom at location 0x%x"
2733 " using %d bit addressing",eepromSize,addr,
2734 mode16 ? 16 : 8);
2735
2736 msg[0].addr = addr;
2737 msg[0].flags = 0;
2738 msg[0].len = mode16 ? 2 : 1;
2739 msg[0].buf = iadd;
2740 msg[1].addr = addr;
2741 msg[1].flags = I2C_M_RD;
2742
2743 /* We have to do the actual eeprom data fetch ourselves, because
2744 (1) we're only fetching part of the eeprom, and (2) if we were
2745 getting the whole thing our I2C driver can't grab it in one
2746 pass - which is what tveeprom is otherwise going to attempt */
2747 memset(eeprom,0,EEPROM_SIZE);
2748 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2749 pcnt = 16;
2750 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2751 offs = tcnt + (eepromSize - EEPROM_SIZE);
2752 if (mode16) {
2753 iadd[0] = offs >> 8;
2754 iadd[1] = offs;
2755 } else {
2756 iadd[0] = offs;
2757 }
2758 msg[1].len = pcnt;
2759 msg[1].buf = eeprom+tcnt;
2760 if ((ret = i2c_transfer(&hdw->i2c_adap,
2761 msg,ARRAY_SIZE(msg))) != 2) {
2762 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2763 "eeprom fetch set offs err=%d",ret);
2764 kfree(eeprom);
2765 return NULL;
2766 }
2767 }
2768 return eeprom;
2769}
2770
2771
2772void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2773 int prom_flag,
2774 int enable_flag)
d855497e
MI		 2775{
2776 int ret;
2777 u16 address;
2778 unsigned int pipe;
2779 LOCK_TAKE(hdw->big_lock); do {
2780 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2781
2782 if (!enable_flag) {
2783 pvr2_trace(PVR2_TRACE_FIRMWARE,
2784 "Cleaning up after CPU firmware fetch");
2785 kfree(hdw->fw_buffer);
a0fd1cb1 2786 hdw->fw_buffer = NULL;
d855497e 2787 hdw->fw_size = 0;
4db666cc
MI		 2788 if (hdw->fw_cpu_flag) {
2789 /* Now release the CPU. It will disconnect
2790 and reconnect later. */
2791 pvr2_hdw_cpureset_assert(hdw,0);
2792 }
d855497e
MI		 2793 break;
2794 }
2795
4db666cc
MI		 2796 hdw->fw_cpu_flag = (prom_flag == 0);
2797 if (hdw->fw_cpu_flag) {
2798 pvr2_trace(PVR2_TRACE_FIRMWARE,
2799 "Preparing to suck out CPU firmware");
2800 hdw->fw_size = 0x2000;
2801 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2802 if (!hdw->fw_buffer) {
2803 hdw->fw_size = 0;
2804 break;
2805 }
d855497e 2806
4db666cc
MI		 2807 /* We have to hold the CPU during firmware upload. */
2808 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 2809
4db666cc
MI		 2810 /* download the firmware from address 0000-1fff in 2048
2811 (=0x800) bytes chunk. */
d855497e 2812
4db666cc
MI		 2813 pvr2_trace(PVR2_TRACE_FIRMWARE,
2814 "Grabbing CPU firmware");
2815 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2816 for(address = 0; address < hdw->fw_size;
2817 address += 0x800) {
2818 ret = usb_control_msg(hdw->usb_dev,pipe,
2819 0xa0,0xc0,
2820 address,0,
2821 hdw->fw_buffer+address,
2822 0x800,HZ);
2823 if (ret < 0) break;
2824 }
d855497e 2825
4db666cc
MI		 2826 pvr2_trace(PVR2_TRACE_FIRMWARE,
2827 "Done grabbing CPU firmware");
2828 } else {
2829 pvr2_trace(PVR2_TRACE_FIRMWARE,
2830 "Sucking down EEPROM contents");
2831 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2832 if (!hdw->fw_buffer) {
2833 pvr2_trace(PVR2_TRACE_FIRMWARE,
2834 "EEPROM content suck failed.");
2835 break;
2836 }
2837 hdw->fw_size = EEPROM_SIZE;
2838 pvr2_trace(PVR2_TRACE_FIRMWARE,
2839 "Done sucking down EEPROM contents");
2840 }
d855497e
MI		 2841
2842 } while (0); LOCK_GIVE(hdw->big_lock);
2843}
2844
2845
2846/* Return true if we're in a mode for retrieval CPU firmware */
2847int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2848{
2849 return hdw->fw_buffer != 0;
2850}
2851
2852
2853int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2854 char *buf,unsigned int cnt)
2855{
2856 int ret = -EINVAL;
2857 LOCK_TAKE(hdw->big_lock); do {
2858 if (!buf) break;
2859 if (!cnt) break;
2860
2861 if (!hdw->fw_buffer) {
2862 ret = -EIO;
2863 break;
2864 }
2865
2866 if (offs >= hdw->fw_size) {
2867 pvr2_trace(PVR2_TRACE_FIRMWARE,
2868 "Read firmware data offs=%d EOF",
2869 offs);
2870 ret = 0;
2871 break;
2872 }
2873
2874 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2875
2876 memcpy(buf,hdw->fw_buffer+offs,cnt);
2877
2878 pvr2_trace(PVR2_TRACE_FIRMWARE,
2879 "Read firmware data offs=%d cnt=%d",
2880 offs,cnt);
2881 ret = cnt;
2882 } while (0); LOCK_GIVE(hdw->big_lock);
2883
2884 return ret;
2885}
2886
2887
fd5a75fe 2888int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 2889 enum pvr2_v4l_type index)
d855497e 2890{
fd5a75fe 2891 switch (index) {
8079384e
MI		 2892 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2893 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2894 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 2895 default: return -1;
2896 }
d855497e
MI		 2897}
2898
2899
2fdf3d9c 2900/* Store a v4l minor device number */
fd5a75fe 2901void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 2902 enum pvr2_v4l_type index,int v)
d855497e 2903{
fd5a75fe 2904 switch (index) {
8079384e
MI		 2905 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2906 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2907 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 2908 default: break;
2909 }
d855497e
MI		 2910}
2911
2912
7d12e780 2913static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 2914{
2915 struct pvr2_hdw *hdw = urb->context;
2916 hdw->ctl_write_pend_flag = 0;
2917 if (hdw->ctl_read_pend_flag) return;
2918 complete(&hdw->ctl_done);
2919}
2920
2921
7d12e780 2922static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 2923{
2924 struct pvr2_hdw *hdw = urb->context;
2925 hdw->ctl_read_pend_flag = 0;
2926 if (hdw->ctl_write_pend_flag) return;
2927 complete(&hdw->ctl_done);
2928}
2929
2930
2931static void pvr2_ctl_timeout(unsigned long data)
2932{
2933 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2934 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2935 hdw->ctl_timeout_flag = !0;
5e55d2ce 2936 if (hdw->ctl_write_pend_flag)
d855497e 2937 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 2938 if (hdw->ctl_read_pend_flag)
d855497e 2939 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 2940 }
2941}
2942
2943
e61b6fc5
MI		 2944/* Issue a command and get a response from the device. This extended
2945 version includes a probe flag (which if set means that device errors
2946 should not be logged or treated as fatal) and a timeout in jiffies.
2947 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 2948static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2949 unsigned int timeout,int probe_fl,
2950 void *write_data,unsigned int write_len,
2951 void *read_data,unsigned int read_len)
d855497e
MI		 2952{
2953 unsigned int idx;
2954 int status = 0;
2955 struct timer_list timer;
2956 if (!hdw->ctl_lock_held) {
2957 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2958 "Attempted to execute control transfer"
2959 " without lock!!");
2960 return -EDEADLK;
2961 }
2962 if ((!hdw->flag_ok) && !probe_fl) {
2963 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2964 "Attempted to execute control transfer"
2965 " when device not ok");
2966 return -EIO;
2967 }
2968 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2969 if (!probe_fl) {
2970 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2971 "Attempted to execute control transfer"
2972 " when USB is disconnected");
2973 }
2974 return -ENOTTY;
2975 }
2976
2977 /* Ensure that we have sane parameters */
2978 if (!write_data) write_len = 0;
2979 if (!read_data) read_len = 0;
2980 if (write_len > PVR2_CTL_BUFFSIZE) {
2981 pvr2_trace(
2982 PVR2_TRACE_ERROR_LEGS,
2983 "Attempted to execute %d byte"
2984 " control-write transfer (limit=%d)",
2985 write_len,PVR2_CTL_BUFFSIZE);
2986 return -EINVAL;
2987 }
2988 if (read_len > PVR2_CTL_BUFFSIZE) {
2989 pvr2_trace(
2990 PVR2_TRACE_ERROR_LEGS,
2991 "Attempted to execute %d byte"
2992 " control-read transfer (limit=%d)",
2993 write_len,PVR2_CTL_BUFFSIZE);
2994 return -EINVAL;
2995 }
2996 if ((!write_len) && (!read_len)) {
2997 pvr2_trace(
2998 PVR2_TRACE_ERROR_LEGS,
2999 "Attempted to execute null control transfer?");
3000 return -EINVAL;
3001 }
3002
3003
3004 hdw->cmd_debug_state = 1;
3005 if (write_len) {
3006 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3007 } else {
3008 hdw->cmd_debug_code = 0;
3009 }
3010 hdw->cmd_debug_write_len = write_len;
3011 hdw->cmd_debug_read_len = read_len;
3012
3013 /* Initialize common stuff */
3014 init_completion(&hdw->ctl_done);
3015 hdw->ctl_timeout_flag = 0;
3016 hdw->ctl_write_pend_flag = 0;
3017 hdw->ctl_read_pend_flag = 0;
3018 init_timer(&timer);
3019 timer.expires = jiffies + timeout;
3020 timer.data = (unsigned long)hdw;
3021 timer.function = pvr2_ctl_timeout;
3022
3023 if (write_len) {
3024 hdw->cmd_debug_state = 2;
3025 /* Transfer write data to internal buffer */
3026 for (idx = 0; idx < write_len; idx++) {
3027 hdw->ctl_write_buffer[idx] =
3028 ((unsigned char *)write_data)[idx];
3029 }
3030 /* Initiate a write request */
3031 usb_fill_bulk_urb(hdw->ctl_write_urb,
3032 hdw->usb_dev,
3033 usb_sndbulkpipe(hdw->usb_dev,
3034 PVR2_CTL_WRITE_ENDPOINT),
3035 hdw->ctl_write_buffer,
3036 write_len,
3037 pvr2_ctl_write_complete,
3038 hdw);
3039 hdw->ctl_write_urb->actual_length = 0;
3040 hdw->ctl_write_pend_flag = !0;
3041 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3042 if (status < 0) {
3043 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3044 "Failed to submit write-control"
3045 " URB status=%d",status);
3046 hdw->ctl_write_pend_flag = 0;
3047 goto done;
3048 }
3049 }
3050
3051 if (read_len) {
3052 hdw->cmd_debug_state = 3;
3053 memset(hdw->ctl_read_buffer,0x43,read_len);
3054 /* Initiate a read request */
3055 usb_fill_bulk_urb(hdw->ctl_read_urb,
3056 hdw->usb_dev,
3057 usb_rcvbulkpipe(hdw->usb_dev,
3058 PVR2_CTL_READ_ENDPOINT),
3059 hdw->ctl_read_buffer,
3060 read_len,
3061 pvr2_ctl_read_complete,
3062 hdw);
3063 hdw->ctl_read_urb->actual_length = 0;
3064 hdw->ctl_read_pend_flag = !0;
3065 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3066 if (status < 0) {
3067 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3068 "Failed to submit read-control"
3069 " URB status=%d",status);
3070 hdw->ctl_read_pend_flag = 0;
3071 goto done;
3072 }
3073 }
3074
3075 /* Start timer */
3076 add_timer(&timer);
3077
3078 /* Now wait for all I/O to complete */
3079 hdw->cmd_debug_state = 4;
3080 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3081 wait_for_completion(&hdw->ctl_done);
3082 }
3083 hdw->cmd_debug_state = 5;
3084
3085 /* Stop timer */
3086 del_timer_sync(&timer);
3087
3088 hdw->cmd_debug_state = 6;
3089 status = 0;
3090
3091 if (hdw->ctl_timeout_flag) {
3092 status = -ETIMEDOUT;
3093 if (!probe_fl) {
3094 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3095 "Timed out control-write");
3096 }
3097 goto done;
3098 }
3099
3100 if (write_len) {
3101 /* Validate results of write request */
3102 if ((hdw->ctl_write_urb->status != 0) &&
3103 (hdw->ctl_write_urb->status != -ENOENT) &&
3104 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3105 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3106 /* USB subsystem is reporting some kind of failure
3107 on the write */
3108 status = hdw->ctl_write_urb->status;
3109 if (!probe_fl) {
3110 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3111 "control-write URB failure,"
3112 " status=%d",
3113 status);
3114 }
3115 goto done;
3116 }
3117 if (hdw->ctl_write_urb->actual_length < write_len) {
3118 /* Failed to write enough data */
3119 status = -EIO;
3120 if (!probe_fl) {
3121 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3122 "control-write URB short,"
3123 " expected=%d got=%d",
3124 write_len,
3125 hdw->ctl_write_urb->actual_length);
3126 }
3127 goto done;
3128 }
3129 }
3130 if (read_len) {
3131 /* Validate results of read request */
3132 if ((hdw->ctl_read_urb->status != 0) &&
3133 (hdw->ctl_read_urb->status != -ENOENT) &&
3134 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3135 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3136 /* USB subsystem is reporting some kind of failure
3137 on the read */
3138 status = hdw->ctl_read_urb->status;
3139 if (!probe_fl) {
3140 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3141 "control-read URB failure,"
3142 " status=%d",
3143 status);
3144 }
3145 goto done;
3146 }
3147 if (hdw->ctl_read_urb->actual_length < read_len) {
3148 /* Failed to read enough data */
3149 status = -EIO;
3150 if (!probe_fl) {
3151 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3152 "control-read URB short,"
3153 " expected=%d got=%d",
3154 read_len,
3155 hdw->ctl_read_urb->actual_length);
3156 }
3157 goto done;
3158 }
3159 /* Transfer retrieved data out from internal buffer */
3160 for (idx = 0; idx < read_len; idx++) {
3161 ((unsigned char *)read_data)[idx] =
3162 hdw->ctl_read_buffer[idx];
3163 }
3164 }
3165
3166 done:
3167
3168 hdw->cmd_debug_state = 0;
3169 if ((status < 0) && (!probe_fl)) {
3170 pvr2_hdw_render_useless_unlocked(hdw);
3171 }
3172 return status;
3173}
3174
3175
3176int pvr2_send_request(struct pvr2_hdw *hdw,
3177 void *write_data,unsigned int write_len,
3178 void *read_data,unsigned int read_len)
3179{
3180 return pvr2_send_request_ex(hdw,HZ*4,0,
3181 write_data,write_len,
3182 read_data,read_len);
3183}
3184
3185int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3186{
3187 int ret;
3188
3189 LOCK_TAKE(hdw->ctl_lock);
3190
8d364363 3191 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3192 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3193 hdw->cmd_buffer[5] = 0;
3194 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3195 hdw->cmd_buffer[7] = reg & 0xff;
3196
3197
3198 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3199
3200 LOCK_GIVE(hdw->ctl_lock);
3201
3202 return ret;
3203}
3204
3205
07e337ee 3206static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3207{
3208 int ret = 0;
3209
3210 LOCK_TAKE(hdw->ctl_lock);
3211
8d364363 3212 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 3213 hdw->cmd_buffer[1] = 0;
3214 hdw->cmd_buffer[2] = 0;
3215 hdw->cmd_buffer[3] = 0;
3216 hdw->cmd_buffer[4] = 0;
3217 hdw->cmd_buffer[5] = 0;
3218 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3219 hdw->cmd_buffer[7] = reg & 0xff;
3220
3221 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3222 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3223
3224 LOCK_GIVE(hdw->ctl_lock);
3225
3226 return ret;
3227}
3228
3229
07e337ee 3230static void pvr2_hdw_render_useless_unlocked(struct pvr2_hdw *hdw)
d855497e
MI		 3231{
3232 if (!hdw->flag_ok) return;
3233 pvr2_trace(PVR2_TRACE_INIT,"render_useless");
3234 hdw->flag_ok = 0;
3235 if (hdw->vid_stream) {
a0fd1cb1 3236 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e
MI		 3237 }
3238 hdw->flag_streaming_enabled = 0;
3239 hdw->subsys_enabled_mask = 0;
3240}
3241
3242
3243void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3244{
3245 LOCK_TAKE(hdw->ctl_lock);
3246 pvr2_hdw_render_useless_unlocked(hdw);
3247 LOCK_GIVE(hdw->ctl_lock);
3248}
3249
3250
3251void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3252{
3253 int ret;
3254 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 3255 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
d855497e
MI		 3256 if (ret == 1) {
3257 ret = usb_reset_device(hdw->usb_dev);
3258 usb_unlock_device(hdw->usb_dev);
3259 } else {
3260 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3261 "Failed to lock USB device ret=%d",ret);
3262 }
3263 if (init_pause_msec) {
3264 pvr2_trace(PVR2_TRACE_INFO,
3265 "Waiting %u msec for hardware to settle",
3266 init_pause_msec);
3267 msleep(init_pause_msec);
3268 }
3269
3270}
3271
3272
3273void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3274{
3275 char da[1];
3276 unsigned int pipe;
3277 int ret;
3278
3279 if (!hdw->usb_dev) return;
3280
3281 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3282
3283 da[0] = val ? 0x01 : 0x00;
3284
3285 /* Write the CPUCS register on the 8051. The lsb of the register
3286 is the reset bit; a 1 asserts reset while a 0 clears it. */
3287 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3288 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3289 if (ret < 0) {
3290 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3291 "cpureset_assert(%d) error=%d",val,ret);
3292 pvr2_hdw_render_useless(hdw);
3293 }
3294}
3295
3296
3297int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3298{
3299 int status;
3300 LOCK_TAKE(hdw->ctl_lock); do {
3301 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
3302 hdw->flag_ok = !0;
8d364363 3303 hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET;
a0fd1cb1 3304 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3305 } while (0); LOCK_GIVE(hdw->ctl_lock);
3306 return status;
3307}
3308
3309
3310int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3311{
3312 int status;
3313 LOCK_TAKE(hdw->ctl_lock); do {
3314 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
8d364363 3315 hdw->cmd_buffer[0] = FX2CMD_POWER_ON;
a0fd1cb1 3316 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3317 } while (0); LOCK_GIVE(hdw->ctl_lock);
3318 return status;
3319}
3320
3321
3322int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3323{
3324 if (!hdw->decoder_ctrl) {
3325 pvr2_trace(PVR2_TRACE_INIT,
3326 "Unable to reset decoder: nothing attached");
3327 return -ENOTTY;
3328 }
3329
3330 if (!hdw->decoder_ctrl->force_reset) {
3331 pvr2_trace(PVR2_TRACE_INIT,
3332 "Unable to reset decoder: not implemented");
3333 return -ENOTTY;
3334 }
3335
3336 pvr2_trace(PVR2_TRACE_INIT,
3337 "Requesting decoder reset");
3338 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3339 return 0;
3340}
3341
3342
e61b6fc5 3343/* Stop / start video stream transport */
07e337ee 3344static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e
MI		 3345{
3346 int status;
3347 LOCK_TAKE(hdw->ctl_lock); do {
8d364363
MK		 3348 hdw->cmd_buffer[0] =
3349 (runFl ? FX2CMD_STREAMING_ON : FX2CMD_STREAMING_OFF);
a0fd1cb1 3350 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3351 } while (0); LOCK_GIVE(hdw->ctl_lock);
3352 if (!status) {
3353 hdw->subsys_enabled_mask =
3354 ((hdw->subsys_enabled_mask &
3355 ~(1<<PVR2_SUBSYS_B_USBSTREAM_RUN)) |
3356 (runFl ? (1<<PVR2_SUBSYS_B_USBSTREAM_RUN) : 0));
3357 }
3358 return status;
3359}
3360
3361
3362void pvr2_hdw_get_debug_info(const struct pvr2_hdw *hdw,
3363 struct pvr2_hdw_debug_info *ptr)
3364{
3365 ptr->big_lock_held = hdw->big_lock_held;
3366 ptr->ctl_lock_held = hdw->ctl_lock_held;
3367 ptr->flag_ok = hdw->flag_ok;
3368 ptr->flag_disconnected = hdw->flag_disconnected;
3369 ptr->flag_init_ok = hdw->flag_init_ok;
3370 ptr->flag_streaming_enabled = hdw->flag_streaming_enabled;
3371 ptr->subsys_flags = hdw->subsys_enabled_mask;
3372 ptr->cmd_debug_state = hdw->cmd_debug_state;
3373 ptr->cmd_code = hdw->cmd_debug_code;
3374 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3375 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3376 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3377 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3378 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3379 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3380 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3381}
3382
3383
3384int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3385{
3386 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3387}
3388
3389
3390int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3391{
3392 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3393}
3394
3395
3396int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3397{
3398 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3399}
3400
3401
3402int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3403{
3404 u32 cval,nval;
3405 int ret;
3406 if (~msk) {
3407 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3408 if (ret) return ret;
3409 nval = (cval & ~msk) | (val & msk);
3410 pvr2_trace(PVR2_TRACE_GPIO,
3411 "GPIO direction changing 0x%x:0x%x"
3412 " from 0x%x to 0x%x",
3413 msk,val,cval,nval);
3414 } else {
3415 nval = val;
3416 pvr2_trace(PVR2_TRACE_GPIO,
3417 "GPIO direction changing to 0x%x",nval);
3418 }
3419 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3420}
3421
3422
3423int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3424{
3425 u32 cval,nval;
3426 int ret;
3427 if (~msk) {
3428 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3429 if (ret) return ret;
3430 nval = (cval & ~msk) | (val & msk);
3431 pvr2_trace(PVR2_TRACE_GPIO,
3432 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3433 msk,val,cval,nval);
3434 } else {
3435 nval = val;
3436 pvr2_trace(PVR2_TRACE_GPIO,
3437 "GPIO output changing to 0x%x",nval);
3438 }
3439 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3440}
3441
3442
e61b6fc5 3443/* Find I2C address of eeprom */
07e337ee 3444static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 3445{
3446 int result;
3447 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3448 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 3449 result = pvr2_send_request(hdw,
3450 hdw->cmd_buffer,1,
3451 hdw->cmd_buffer,1);
3452 if (result < 0) break;
3453 result = hdw->cmd_buffer[0];
3454 } while(0); LOCK_GIVE(hdw->ctl_lock);
3455 return result;
3456}
3457
3458
32ffa9ae 3459int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
f3d092b8
HV		 3460 u32 match_type, u32 match_chip, u64 reg_id,
3461 int setFl,u64 *val_ptr)
32ffa9ae
MI		 3462{
3463#ifdef CONFIG_VIDEO_ADV_DEBUG
32ffa9ae
MI		 3464 struct pvr2_i2c_client *cp;
3465 struct v4l2_register req;
6d98816f
MI		 3466 int stat = 0;
3467 int okFl = 0;
32ffa9ae 3468
201f5c9c
MI		 3469 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
3470
f3d092b8
HV		 3471 req.match_type = match_type;
3472 req.match_chip = match_chip;
32ffa9ae
MI		 3473 req.reg = reg_id;
3474 if (setFl) req.val = *val_ptr;
3475 mutex_lock(&hdw->i2c_list_lock); do {
e77e2c2f 3476 list_for_each_entry(cp, &hdw->i2c_clients, list) {
8481a750
MI		 3477 if (!v4l2_chip_match_i2c_client(
3478 cp->client,
3479 req.match_type, req.match_chip)) {
f3d092b8
HV		 3480 continue;
3481 }
32ffa9ae 3482 stat = pvr2_i2c_client_cmd(
52ebc763
TP		 3483 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
3484 VIDIOC_DBG_G_REGISTER),&req);
32ffa9ae 3485 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 3486 okFl = !0;
3487 break;
32ffa9ae
MI		 3488 }
3489 } while (0); mutex_unlock(&hdw->i2c_list_lock);
6d98816f
MI		 3490 if (okFl) {
3491 return stat;
3492 }
32ffa9ae
MI		 3493 return -EINVAL;
3494#else
3495 return -ENOSYS;
3496#endif
3497}
3498
3499
d855497e
MI		 3500/*
3501 Stuff for Emacs to see, in order to encourage consistent editing style:
3502 *** Local Variables: ***
3503 *** mode: c ***
3504 *** fill-column: 75 ***
3505 *** tab-width: 8 ***
3506 *** c-basic-offset: 8 ***
3507 *** End: ***
3508 */
Clone of davem's net-next-2.6 tree