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V4L/DVB (7700): pvrusb2: Make FX2 command codes unsigned constants
[net-next-2.6.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
3 * $Id$
4 *
5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/firmware.h>
d855497e 26#include <linux/videodev2.h>
32ffa9ae 27#include <media/v4l2-common.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
33#include "pvrusb2-tuner.h"
34#include "pvrusb2-eeprom.h"
35#include "pvrusb2-hdw-internal.h"
36#include "pvrusb2-encoder.h"
37#include "pvrusb2-debug.h"
8d364363 38#include "pvrusb2-fx2-cmd.h"
d855497e 39
1bde0289
MI		 40#define TV_MIN_FREQ 55250000L
41#define TV_MAX_FREQ 850000000L
25d8527a 42
a0fd1cb1 43static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 44static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 45
ff699e6b 46static int ctlchg;
d855497e 47static int initusbreset = 1;
ff699e6b 48static int procreload;
d855497e
MI		 49static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
50static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
51static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 52static int init_pause_msec;
d855497e
MI		 53
54module_param(ctlchg, int, S_IRUGO|S_IWUSR);
55MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
56module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
57MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
58module_param(initusbreset, int, S_IRUGO|S_IWUSR);
59MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
60module_param(procreload, int, S_IRUGO|S_IWUSR);
61MODULE_PARM_DESC(procreload,
62 "Attempt init failure recovery with firmware reload");
63module_param_array(tuner, int, NULL, 0444);
64MODULE_PARM_DESC(tuner,"specify installed tuner type");
65module_param_array(video_std, int, NULL, 0444);
66MODULE_PARM_DESC(video_std,"specify initial video standard");
67module_param_array(tolerance, int, NULL, 0444);
68MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
69
70#define PVR2_CTL_WRITE_ENDPOINT 0x01
71#define PVR2_CTL_READ_ENDPOINT 0x81
72
73#define PVR2_GPIO_IN 0x9008
74#define PVR2_GPIO_OUT 0x900c
75#define PVR2_GPIO_DIR 0x9020
76
77#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
78
79#define PVR2_FIRMWARE_ENDPOINT 0x02
80
81/* size of a firmware chunk */
82#define FIRMWARE_CHUNK_SIZE 0x2000
83
b30d2441
MI		 84/* Define the list of additional controls we'll dynamically construct based
85 on query of the cx2341x module. */
86struct pvr2_mpeg_ids {
87 const char *strid;
88 int id;
89};
90static const struct pvr2_mpeg_ids mpeg_ids[] = {
91 {
92 .strid = "audio_layer",
93 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
94 },{
95 .strid = "audio_bitrate",
96 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
97 },{
98 /* Already using audio_mode elsewhere :-( */
99 .strid = "mpeg_audio_mode",
100 .id = V4L2_CID_MPEG_AUDIO_MODE,
101 },{
102 .strid = "mpeg_audio_mode_extension",
103 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
104 },{
105 .strid = "audio_emphasis",
106 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
107 },{
108 .strid = "audio_crc",
109 .id = V4L2_CID_MPEG_AUDIO_CRC,
110 },{
111 .strid = "video_aspect",
112 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
113 },{
114 .strid = "video_b_frames",
115 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
116 },{
117 .strid = "video_gop_size",
118 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
119 },{
120 .strid = "video_gop_closure",
121 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 122 },{
123 .strid = "video_bitrate_mode",
124 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
125 },{
126 .strid = "video_bitrate",
127 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
128 },{
129 .strid = "video_bitrate_peak",
130 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
131 },{
132 .strid = "video_temporal_decimation",
133 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
134 },{
135 .strid = "stream_type",
136 .id = V4L2_CID_MPEG_STREAM_TYPE,
137 },{
138 .strid = "video_spatial_filter_mode",
139 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
140 },{
141 .strid = "video_spatial_filter",
142 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
143 },{
144 .strid = "video_luma_spatial_filter_type",
145 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
146 },{
147 .strid = "video_chroma_spatial_filter_type",
148 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
149 },{
150 .strid = "video_temporal_filter_mode",
151 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
152 },{
153 .strid = "video_temporal_filter",
154 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
155 },{
156 .strid = "video_median_filter_type",
157 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
158 },{
159 .strid = "video_luma_median_filter_top",
160 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
161 },{
162 .strid = "video_luma_median_filter_bottom",
163 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
164 },{
165 .strid = "video_chroma_median_filter_top",
166 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
167 },{
168 .strid = "video_chroma_median_filter_bottom",
169 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
170 }
171};
eca8ebfc 172#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 173
434449f4 174
d855497e 175static const char *control_values_srate[] = {
434449f4
MI		 176 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
177 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
178 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 179};
180
181
d855497e 182
d855497e
MI		 183static const char *control_values_input[] = {
184 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 185 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 186 [PVR2_CVAL_INPUT_RADIO] = "radio",
187 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
188 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
189};
190
191
192static const char *control_values_audiomode[] = {
193 [V4L2_TUNER_MODE_MONO] = "Mono",
194 [V4L2_TUNER_MODE_STEREO] = "Stereo",
195 [V4L2_TUNER_MODE_LANG1] = "Lang1",
196 [V4L2_TUNER_MODE_LANG2] = "Lang2",
197 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
198};
199
200
201static const char *control_values_hsm[] = {
202 [PVR2_CVAL_HSM_FAIL] = "Fail",
203 [PVR2_CVAL_HSM_HIGH] = "High",
204 [PVR2_CVAL_HSM_FULL] = "Full",
205};
206
207
681c7399
MI		 208static const char *pvr2_state_names[] = {
209 [PVR2_STATE_NONE] = "none",
210 [PVR2_STATE_DEAD] = "dead",
211 [PVR2_STATE_COLD] = "cold",
212 [PVR2_STATE_WARM] = "warm",
213 [PVR2_STATE_ERROR] = "error",
214 [PVR2_STATE_READY] = "ready",
215 [PVR2_STATE_RUN] = "run",
d855497e
MI		 216};
217
681c7399
MI		 218
219static void pvr2_hdw_state_sched(struct pvr2_hdw *);
220static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 221static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399
MI		 222static void pvr2_hdw_worker_i2c(struct work_struct *work);
223static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 224static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
225static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
226static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 227static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 228static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 229static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 230static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
231static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399
MI		 232static void pvr2_hdw_quiescent_timeout(unsigned long);
233static void pvr2_hdw_encoder_wait_timeout(unsigned long);
07e337ee
AB		 234static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
235 unsigned int timeout,int probe_fl,
236 void *write_data,unsigned int write_len,
237 void *read_data,unsigned int read_len);
d855497e 238
681c7399
MI		 239
240static void trace_stbit(const char *name,int val)
241{
242 pvr2_trace(PVR2_TRACE_STBITS,
243 "State bit %s <-- %s",
244 name,(val ? "true" : "false"));
245}
246
d855497e
MI		 247static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
248{
249 struct pvr2_hdw *hdw = cptr->hdw;
250 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
251 *vp = hdw->freqTable[hdw->freqProgSlot-1];
252 } else {
253 *vp = 0;
254 }
255 return 0;
256}
257
258static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
259{
260 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 261 unsigned int slotId = hdw->freqProgSlot;
262 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
263 hdw->freqTable[slotId-1] = v;
264 /* Handle side effects correctly - if we're tuned to this
265 slot, then forgot the slot id relation since the stored
266 frequency has been changed. */
267 if (hdw->freqSelector) {
268 if (hdw->freqSlotRadio == slotId) {
269 hdw->freqSlotRadio = 0;
270 }
271 } else {
272 if (hdw->freqSlotTelevision == slotId) {
273 hdw->freqSlotTelevision = 0;
274 }
275 }
d855497e
MI		 276 }
277 return 0;
278}
279
280static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
281{
282 *vp = cptr->hdw->freqProgSlot;
283 return 0;
284}
285
286static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
287{
288 struct pvr2_hdw *hdw = cptr->hdw;
289 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
290 hdw->freqProgSlot = v;
291 }
292 return 0;
293}
294
295static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
296{
1bde0289
MI		 297 struct pvr2_hdw *hdw = cptr->hdw;
298 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 299 return 0;
300}
301
1bde0289 302static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 303{
304 unsigned freq = 0;
305 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 306 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
307 if (slotId > 0) {
308 freq = hdw->freqTable[slotId-1];
309 if (!freq) return 0;
310 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 311 }
1bde0289
MI		 312 if (hdw->freqSelector) {
313 hdw->freqSlotRadio = slotId;
314 } else {
315 hdw->freqSlotTelevision = slotId;
d855497e
MI		 316 }
317 return 0;
318}
319
320static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
321{
1bde0289 322 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 323 return 0;
324}
325
326static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
327{
328 return cptr->hdw->freqDirty != 0;
329}
330
331static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
332{
333 cptr->hdw->freqDirty = 0;
334}
335
336static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
337{
1bde0289 338 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 339 return 0;
340}
341
3ad9fc37
MI		 342static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
343{
344 /* Actual maximum depends on the video standard in effect. */
345 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
346 *vp = 480;
347 } else {
348 *vp = 576;
349 }
350 return 0;
351}
352
353static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
354{
989eb154
MI		 355 /* Actual minimum depends on device digitizer type. */
356 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 357 *vp = 75;
358 } else {
359 *vp = 17;
360 }
361 return 0;
362}
363
1bde0289 364static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 365{
1bde0289
MI		 366 *vp = cptr->hdw->input_val;
367 return 0;
368}
369
29bf5b1d
MI		 370static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
371{
7fb20fa3 372 return ((1 << v) & cptr->hdw->input_avail_mask) != 0;
29bf5b1d
MI		 373}
374
1bde0289
MI		 375static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
376{
377 struct pvr2_hdw *hdw = cptr->hdw;
378
379 if (hdw->input_val != v) {
380 hdw->input_val = v;
381 hdw->input_dirty = !0;
382 }
383
384 /* Handle side effects - if we switch to a mode that needs the RF
385 tuner, then select the right frequency choice as well and mark
386 it dirty. */
387 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
388 hdw->freqSelector = 0;
389 hdw->freqDirty = !0;
29bf5b1d
MI		 390 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
391 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
1bde0289
MI		 392 hdw->freqSelector = 1;
393 hdw->freqDirty = !0;
5549f54f 394 }
1bde0289
MI		 395 return 0;
396}
397
398static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
399{
400 return cptr->hdw->input_dirty != 0;
401}
402
403static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
404{
405 cptr->hdw->input_dirty = 0;
406}
407
5549f54f 408
25d8527a
PK		 409static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
410{
644afdb9
MI		 411 unsigned long fv;
412 struct pvr2_hdw *hdw = cptr->hdw;
413 if (hdw->tuner_signal_stale) {
414 pvr2_i2c_core_status_poll(hdw);
415 }
416 fv = hdw->tuner_signal_info.rangehigh;
417 if (!fv) {
418 /* Safety fallback */
25d8527a 419 *vp = TV_MAX_FREQ;
644afdb9 420 return 0;
25d8527a 421 }
644afdb9
MI		 422 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
423 fv = (fv * 125) / 2;
424 } else {
425 fv = fv * 62500;
426 }
427 *vp = fv;
25d8527a
PK		 428 return 0;
429}
430
431static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
432{
644afdb9
MI		 433 unsigned long fv;
434 struct pvr2_hdw *hdw = cptr->hdw;
435 if (hdw->tuner_signal_stale) {
436 pvr2_i2c_core_status_poll(hdw);
437 }
438 fv = hdw->tuner_signal_info.rangelow;
439 if (!fv) {
440 /* Safety fallback */
25d8527a 441 *vp = TV_MIN_FREQ;
644afdb9
MI		 442 return 0;
443 }
444 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
445 fv = (fv * 125) / 2;
446 } else {
447 fv = fv * 62500;
25d8527a 448 }
644afdb9 449 *vp = fv;
25d8527a
PK		 450 return 0;
451}
452
b30d2441
MI		 453static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
454{
455 return cptr->hdw->enc_stale != 0;
456}
457
458static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
459{
460 cptr->hdw->enc_stale = 0;
681c7399 461 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 462}
463
464static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
465{
466 int ret;
467 struct v4l2_ext_controls cs;
468 struct v4l2_ext_control c1;
469 memset(&cs,0,sizeof(cs));
470 memset(&c1,0,sizeof(c1));
471 cs.controls = &c1;
472 cs.count = 1;
473 c1.id = cptr->info->v4l_id;
01f1e44f 474 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 475 VIDIOC_G_EXT_CTRLS);
476 if (ret) return ret;
477 *vp = c1.value;
478 return 0;
479}
480
481static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
482{
483 int ret;
681c7399 484 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 485 struct v4l2_ext_controls cs;
486 struct v4l2_ext_control c1;
487 memset(&cs,0,sizeof(cs));
488 memset(&c1,0,sizeof(c1));
489 cs.controls = &c1;
490 cs.count = 1;
491 c1.id = cptr->info->v4l_id;
492 c1.value = v;
681c7399
MI		 493 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
494 hdw->state_encoder_run, &cs,
b30d2441 495 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 496 if (ret == -EBUSY) {
497 /* Oops. cx2341x is telling us it's not safe to change
498 this control while we're capturing. Make a note of this
499 fact so that the pipeline will be stopped the next time
500 controls are committed. Then go on ahead and store this
501 change anyway. */
502 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
503 0, &cs,
504 VIDIOC_S_EXT_CTRLS);
505 if (!ret) hdw->enc_unsafe_stale = !0;
506 }
b30d2441 507 if (ret) return ret;
681c7399 508 hdw->enc_stale = !0;
b30d2441
MI		 509 return 0;
510}
511
512static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
513{
514 struct v4l2_queryctrl qctrl;
515 struct pvr2_ctl_info *info;
516 qctrl.id = cptr->info->v4l_id;
517 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
518 /* Strip out the const so we can adjust a function pointer. It's
519 OK to do this here because we know this is a dynamically created
520 control, so the underlying storage for the info pointer is (a)
521 private to us, and (b) not in read-only storage. Either we do
522 this or we significantly complicate the underlying control
523 implementation. */
524 info = (struct pvr2_ctl_info *)(cptr->info);
525 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
526 if (info->set_value) {
a0fd1cb1 527 info->set_value = NULL;
b30d2441
MI		 528 }
529 } else {
530 if (!(info->set_value)) {
531 info->set_value = ctrl_cx2341x_set;
532 }
533 }
534 return qctrl.flags;
535}
536
d855497e
MI		 537static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
538{
681c7399
MI		 539 *vp = cptr->hdw->state_pipeline_req;
540 return 0;
541}
542
543static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
544{
545 *vp = cptr->hdw->master_state;
d855497e
MI		 546 return 0;
547}
548
549static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
550{
551 int result = pvr2_hdw_is_hsm(cptr->hdw);
552 *vp = PVR2_CVAL_HSM_FULL;
553 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
554 if (result) *vp = PVR2_CVAL_HSM_HIGH;
555 return 0;
556}
557
558static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
559{
560 *vp = cptr->hdw->std_mask_avail;
561 return 0;
562}
563
564static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
565{
566 struct pvr2_hdw *hdw = cptr->hdw;
567 v4l2_std_id ns;
568 ns = hdw->std_mask_avail;
569 ns = (ns & ~m) | (v & m);
570 if (ns == hdw->std_mask_avail) return 0;
571 hdw->std_mask_avail = ns;
572 pvr2_hdw_internal_set_std_avail(hdw);
573 pvr2_hdw_internal_find_stdenum(hdw);
574 return 0;
575}
576
577static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
578 char *bufPtr,unsigned int bufSize,
579 unsigned int *len)
580{
581 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
582 return 0;
583}
584
585static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
586 const char *bufPtr,unsigned int bufSize,
587 int *mskp,int *valp)
588{
589 int ret;
590 v4l2_std_id id;
591 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
592 if (ret < 0) return ret;
593 if (mskp) *mskp = id;
594 if (valp) *valp = id;
595 return 0;
596}
597
598static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
599{
600 *vp = cptr->hdw->std_mask_cur;
601 return 0;
602}
603
604static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
605{
606 struct pvr2_hdw *hdw = cptr->hdw;
607 v4l2_std_id ns;
608 ns = hdw->std_mask_cur;
609 ns = (ns & ~m) | (v & m);
610 if (ns == hdw->std_mask_cur) return 0;
611 hdw->std_mask_cur = ns;
612 hdw->std_dirty = !0;
613 pvr2_hdw_internal_find_stdenum(hdw);
614 return 0;
615}
616
617static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
618{
619 return cptr->hdw->std_dirty != 0;
620}
621
622static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
623{
624 cptr->hdw->std_dirty = 0;
625}
626
627static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
628{
18103c57
MI		 629 struct pvr2_hdw *hdw = cptr->hdw;
630 pvr2_i2c_core_status_poll(hdw);
631 *vp = hdw->tuner_signal_info.signal;
632 return 0;
633}
634
635static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
636{
637 int val = 0;
638 unsigned int subchan;
639 struct pvr2_hdw *hdw = cptr->hdw;
644afdb9 640 pvr2_i2c_core_status_poll(hdw);
18103c57
MI		 641 subchan = hdw->tuner_signal_info.rxsubchans;
642 if (subchan & V4L2_TUNER_SUB_MONO) {
643 val |= (1 << V4L2_TUNER_MODE_MONO);
644 }
645 if (subchan & V4L2_TUNER_SUB_STEREO) {
646 val |= (1 << V4L2_TUNER_MODE_STEREO);
647 }
648 if (subchan & V4L2_TUNER_SUB_LANG1) {
649 val |= (1 << V4L2_TUNER_MODE_LANG1);
650 }
651 if (subchan & V4L2_TUNER_SUB_LANG2) {
652 val |= (1 << V4L2_TUNER_MODE_LANG2);
653 }
654 *vp = val;
d855497e
MI		 655 return 0;
656}
657
d855497e
MI		 658
659static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
660{
661 struct pvr2_hdw *hdw = cptr->hdw;
662 if (v < 0) return -EINVAL;
663 if (v > hdw->std_enum_cnt) return -EINVAL;
664 hdw->std_enum_cur = v;
665 if (!v) return 0;
666 v--;
667 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
668 hdw->std_mask_cur = hdw->std_defs[v].id;
669 hdw->std_dirty = !0;
670 return 0;
671}
672
673
674static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
675{
676 *vp = cptr->hdw->std_enum_cur;
677 return 0;
678}
679
680
681static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
682{
683 return cptr->hdw->std_dirty != 0;
684}
685
686
687static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
688{
689 cptr->hdw->std_dirty = 0;
690}
691
692
693#define DEFINT(vmin,vmax) \
694 .type = pvr2_ctl_int, \
695 .def.type_int.min_value = vmin, \
696 .def.type_int.max_value = vmax
697
698#define DEFENUM(tab) \
699 .type = pvr2_ctl_enum, \
27c7b710 700 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 701 .def.type_enum.value_names = tab
702
33213963
MI		 703#define DEFBOOL \
704 .type = pvr2_ctl_bool
705
d855497e
MI		 706#define DEFMASK(msk,tab) \
707 .type = pvr2_ctl_bitmask, \
708 .def.type_bitmask.valid_bits = msk, \
709 .def.type_bitmask.bit_names = tab
710
711#define DEFREF(vname) \
712 .set_value = ctrl_set_##vname, \
713 .get_value = ctrl_get_##vname, \
714 .is_dirty = ctrl_isdirty_##vname, \
715 .clear_dirty = ctrl_cleardirty_##vname
716
717
718#define VCREATE_FUNCS(vname) \
719static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
720{*vp = cptr->hdw->vname##_val; return 0;} \
721static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
722{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
723static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
724{return cptr->hdw->vname##_dirty != 0;} \
725static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
726{cptr->hdw->vname##_dirty = 0;}
727
728VCREATE_FUNCS(brightness)
729VCREATE_FUNCS(contrast)
730VCREATE_FUNCS(saturation)
731VCREATE_FUNCS(hue)
732VCREATE_FUNCS(volume)
733VCREATE_FUNCS(balance)
734VCREATE_FUNCS(bass)
735VCREATE_FUNCS(treble)
736VCREATE_FUNCS(mute)
c05c0462
MI		 737VCREATE_FUNCS(audiomode)
738VCREATE_FUNCS(res_hor)
739VCREATE_FUNCS(res_ver)
d855497e 740VCREATE_FUNCS(srate)
d855497e 741
d855497e
MI		 742/* Table definition of all controls which can be manipulated */
743static const struct pvr2_ctl_info control_defs[] = {
744 {
745 .v4l_id = V4L2_CID_BRIGHTNESS,
746 .desc = "Brightness",
747 .name = "brightness",
748 .default_value = 128,
749 DEFREF(brightness),
750 DEFINT(0,255),
751 },{
752 .v4l_id = V4L2_CID_CONTRAST,
753 .desc = "Contrast",
754 .name = "contrast",
755 .default_value = 68,
756 DEFREF(contrast),
757 DEFINT(0,127),
758 },{
759 .v4l_id = V4L2_CID_SATURATION,
760 .desc = "Saturation",
761 .name = "saturation",
762 .default_value = 64,
763 DEFREF(saturation),
764 DEFINT(0,127),
765 },{
766 .v4l_id = V4L2_CID_HUE,
767 .desc = "Hue",
768 .name = "hue",
769 .default_value = 0,
770 DEFREF(hue),
771 DEFINT(-128,127),
772 },{
773 .v4l_id = V4L2_CID_AUDIO_VOLUME,
774 .desc = "Volume",
775 .name = "volume",
139eecf9 776 .default_value = 62000,
d855497e
MI		 777 DEFREF(volume),
778 DEFINT(0,65535),
779 },{
780 .v4l_id = V4L2_CID_AUDIO_BALANCE,
781 .desc = "Balance",
782 .name = "balance",
783 .default_value = 0,
784 DEFREF(balance),
785 DEFINT(-32768,32767),
786 },{
787 .v4l_id = V4L2_CID_AUDIO_BASS,
788 .desc = "Bass",
789 .name = "bass",
790 .default_value = 0,
791 DEFREF(bass),
792 DEFINT(-32768,32767),
793 },{
794 .v4l_id = V4L2_CID_AUDIO_TREBLE,
795 .desc = "Treble",
796 .name = "treble",
797 .default_value = 0,
798 DEFREF(treble),
799 DEFINT(-32768,32767),
800 },{
801 .v4l_id = V4L2_CID_AUDIO_MUTE,
802 .desc = "Mute",
803 .name = "mute",
804 .default_value = 0,
805 DEFREF(mute),
33213963 806 DEFBOOL,
c05c0462
MI		 807 },{
808 .desc = "Video Source",
809 .name = "input",
810 .internal_id = PVR2_CID_INPUT,
811 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 812 .check_value = ctrl_check_input,
c05c0462
MI		 813 DEFREF(input),
814 DEFENUM(control_values_input),
815 },{
816 .desc = "Audio Mode",
817 .name = "audio_mode",
818 .internal_id = PVR2_CID_AUDIOMODE,
819 .default_value = V4L2_TUNER_MODE_STEREO,
820 DEFREF(audiomode),
821 DEFENUM(control_values_audiomode),
822 },{
823 .desc = "Horizontal capture resolution",
824 .name = "resolution_hor",
825 .internal_id = PVR2_CID_HRES,
826 .default_value = 720,
827 DEFREF(res_hor),
3ad9fc37 828 DEFINT(19,720),
c05c0462
MI		 829 },{
830 .desc = "Vertical capture resolution",
831 .name = "resolution_ver",
832 .internal_id = PVR2_CID_VRES,
833 .default_value = 480,
834 DEFREF(res_ver),
3ad9fc37
MI		 835 DEFINT(17,576),
836 /* Hook in check for video standard and adjust maximum
837 depending on the standard. */
838 .get_max_value = ctrl_vres_max_get,
839 .get_min_value = ctrl_vres_min_get,
d855497e 840 },{
b30d2441 841 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 842 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
843 .desc = "Audio Sampling Frequency",
d855497e 844 .name = "srate",
d855497e
MI		 845 DEFREF(srate),
846 DEFENUM(control_values_srate),
d855497e
MI		 847 },{
848 .desc = "Tuner Frequency (Hz)",
849 .name = "frequency",
850 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 851 .default_value = 0,
d855497e
MI		 852 .set_value = ctrl_freq_set,
853 .get_value = ctrl_freq_get,
854 .is_dirty = ctrl_freq_is_dirty,
855 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 856 DEFINT(0,0),
25d8527a
PK		 857 /* Hook in check for input value (tv/radio) and adjust
858 max/min values accordingly */
859 .get_max_value = ctrl_freq_max_get,
860 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 861 },{
862 .desc = "Channel",
863 .name = "channel",
864 .set_value = ctrl_channel_set,
865 .get_value = ctrl_channel_get,
866 DEFINT(0,FREQTABLE_SIZE),
867 },{
868 .desc = "Channel Program Frequency",
869 .name = "freq_table_value",
870 .set_value = ctrl_channelfreq_set,
871 .get_value = ctrl_channelfreq_get,
644afdb9 872 DEFINT(0,0),
1bde0289
MI		 873 /* Hook in check for input value (tv/radio) and adjust
874 max/min values accordingly */
1bde0289
MI		 875 .get_max_value = ctrl_freq_max_get,
876 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 877 },{
878 .desc = "Channel Program ID",
879 .name = "freq_table_channel",
880 .set_value = ctrl_channelprog_set,
881 .get_value = ctrl_channelprog_get,
882 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 883 },{
884 .desc = "Streaming Enabled",
885 .name = "streaming_enabled",
886 .get_value = ctrl_streamingenabled_get,
33213963 887 DEFBOOL,
d855497e
MI		 888 },{
889 .desc = "USB Speed",
890 .name = "usb_speed",
891 .get_value = ctrl_hsm_get,
892 DEFENUM(control_values_hsm),
681c7399
MI		 893 },{
894 .desc = "Master State",
895 .name = "master_state",
896 .get_value = ctrl_masterstate_get,
897 DEFENUM(pvr2_state_names),
d855497e
MI		 898 },{
899 .desc = "Signal Present",
900 .name = "signal_present",
901 .get_value = ctrl_signal_get,
18103c57
MI		 902 DEFINT(0,65535),
903 },{
904 .desc = "Audio Modes Present",
905 .name = "audio_modes_present",
906 .get_value = ctrl_audio_modes_present_get,
907 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
908 v4l. Nothing outside of this module cares about this,
909 but I reuse it in order to also reuse the
910 control_values_audiomode string table. */
911 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
912 (1 << V4L2_TUNER_MODE_STEREO)|
913 (1 << V4L2_TUNER_MODE_LANG1)|
914 (1 << V4L2_TUNER_MODE_LANG2)),
915 control_values_audiomode),
d855497e
MI		 916 },{
917 .desc = "Video Standards Available Mask",
918 .name = "video_standard_mask_available",
919 .internal_id = PVR2_CID_STDAVAIL,
920 .skip_init = !0,
921 .get_value = ctrl_stdavail_get,
922 .set_value = ctrl_stdavail_set,
923 .val_to_sym = ctrl_std_val_to_sym,
924 .sym_to_val = ctrl_std_sym_to_val,
925 .type = pvr2_ctl_bitmask,
926 },{
927 .desc = "Video Standards In Use Mask",
928 .name = "video_standard_mask_active",
929 .internal_id = PVR2_CID_STDCUR,
930 .skip_init = !0,
931 .get_value = ctrl_stdcur_get,
932 .set_value = ctrl_stdcur_set,
933 .is_dirty = ctrl_stdcur_is_dirty,
934 .clear_dirty = ctrl_stdcur_clear_dirty,
935 .val_to_sym = ctrl_std_val_to_sym,
936 .sym_to_val = ctrl_std_sym_to_val,
937 .type = pvr2_ctl_bitmask,
d855497e
MI		 938 },{
939 .desc = "Video Standard Name",
940 .name = "video_standard",
941 .internal_id = PVR2_CID_STDENUM,
942 .skip_init = !0,
943 .get_value = ctrl_stdenumcur_get,
944 .set_value = ctrl_stdenumcur_set,
945 .is_dirty = ctrl_stdenumcur_is_dirty,
946 .clear_dirty = ctrl_stdenumcur_clear_dirty,
947 .type = pvr2_ctl_enum,
948 }
949};
950
eca8ebfc 951#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 952
953
954const char *pvr2_config_get_name(enum pvr2_config cfg)
955{
956 switch (cfg) {
957 case pvr2_config_empty: return "empty";
958 case pvr2_config_mpeg: return "mpeg";
959 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 960 case pvr2_config_pcm: return "pcm";
961 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 962 }
963 return "<unknown>";
964}
965
966
967struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
968{
969 return hdw->usb_dev;
970}
971
972
973unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
974{
975 return hdw->serial_number;
976}
977
31a18547
MI		 978
979const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
980{
981 return hdw->bus_info;
982}
983
984
1bde0289
MI		 985unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
986{
987 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
988}
989
990/* Set the currently tuned frequency and account for all possible
991 driver-core side effects of this action. */
992void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
993{
7c74e57e 994 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 995 if (hdw->freqSelector) {
996 /* Swing over to radio frequency selection */
997 hdw->freqSelector = 0;
998 hdw->freqDirty = !0;
999 }
1bde0289
MI		 1000 if (hdw->freqValRadio != val) {
1001 hdw->freqValRadio = val;
1002 hdw->freqSlotRadio = 0;
7c74e57e 1003 hdw->freqDirty = !0;
1bde0289 1004 }
7c74e57e 1005 } else {
1bde0289
MI		 1006 if (!(hdw->freqSelector)) {
1007 /* Swing over to television frequency selection */
1008 hdw->freqSelector = 1;
1009 hdw->freqDirty = !0;
1010 }
1bde0289
MI		 1011 if (hdw->freqValTelevision != val) {
1012 hdw->freqValTelevision = val;
1013 hdw->freqSlotTelevision = 0;
7c74e57e 1014 hdw->freqDirty = !0;
1bde0289 1015 }
1bde0289
MI		 1016 }
1017}
1018
d855497e
MI		 1019int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1020{
1021 return hdw->unit_number;
1022}
1023
1024
1025/* Attempt to locate one of the given set of files. Messages are logged
1026 appropriate to what has been found. The return value will be 0 or
1027 greater on success (it will be the index of the file name found) and
1028 fw_entry will be filled in. Otherwise a negative error is returned on
1029 failure. If the return value is -ENOENT then no viable firmware file
1030 could be located. */
1031static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1032 const struct firmware **fw_entry,
1033 const char *fwtypename,
1034 unsigned int fwcount,
1035 const char *fwnames[])
1036{
1037 unsigned int idx;
1038 int ret = -EINVAL;
1039 for (idx = 0; idx < fwcount; idx++) {
1040 ret = request_firmware(fw_entry,
1041 fwnames[idx],
1042 &hdw->usb_dev->dev);
1043 if (!ret) {
1044 trace_firmware("Located %s firmware: %s;"
1045 " uploading...",
1046 fwtypename,
1047 fwnames[idx]);
1048 return idx;
1049 }
1050 if (ret == -ENOENT) continue;
1051 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1052 "request_firmware fatal error with code=%d",ret);
1053 return ret;
1054 }
1055 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1056 "***WARNING***"
1057 " Device %s firmware"
1058 " seems to be missing.",
1059 fwtypename);
1060 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1061 "Did you install the pvrusb2 firmware files"
1062 " in their proper location?");
1063 if (fwcount == 1) {
1064 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1065 "request_firmware unable to locate %s file %s",
1066 fwtypename,fwnames[0]);
1067 } else {
1068 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1069 "request_firmware unable to locate"
1070 " one of the following %s files:",
1071 fwtypename);
1072 for (idx = 0; idx < fwcount; idx++) {
1073 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1074 "request_firmware: Failed to find %s",
1075 fwnames[idx]);
1076 }
1077 }
1078 return ret;
1079}
1080
1081
1082/*
1083 * pvr2_upload_firmware1().
1084 *
1085 * Send the 8051 firmware to the device. After the upload, arrange for
1086 * device to re-enumerate.
1087 *
1088 * NOTE : the pointer to the firmware data given by request_firmware()
1089 * is not suitable for an usb transaction.
1090 *
1091 */
07e337ee 1092static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1093{
a0fd1cb1 1094 const struct firmware *fw_entry = NULL;
d855497e
MI		 1095 void *fw_ptr;
1096 unsigned int pipe;
1097 int ret;
1098 u16 address;
1d643a37 1099
989eb154 1100 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1101 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1102 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1103 "Connected device type defines"
1104 " no firmware to upload; ignoring firmware");
1105 return -ENOTTY;
1d643a37
MI		 1106 }
1107
d855497e
MI		 1108 hdw->fw1_state = FW1_STATE_FAILED; // default result
1109
1110 trace_firmware("pvr2_upload_firmware1");
1111
1112 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1113 hdw->hdw_desc->fx2_firmware.cnt,
1114 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1115 if (ret < 0) {
1116 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1117 return ret;
1118 }
1119
1120 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1121 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1122
1123 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1124
1125 if (fw_entry->size != 0x2000){
1126 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1127 release_firmware(fw_entry);
1128 return -ENOMEM;
1129 }
1130
1131 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1132 if (fw_ptr == NULL){
1133 release_firmware(fw_entry);
1134 return -ENOMEM;
1135 }
1136
1137 /* We have to hold the CPU during firmware upload. */
1138 pvr2_hdw_cpureset_assert(hdw,1);
1139
1140 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1141 chunk. */
1142
1143 ret = 0;
1144 for(address = 0; address < fw_entry->size; address += 0x800) {
1145 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1146 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1147 0, fw_ptr, 0x800, HZ);
1148 }
1149
1150 trace_firmware("Upload done, releasing device's CPU");
1151
1152 /* Now release the CPU. It will disconnect and reconnect later. */
1153 pvr2_hdw_cpureset_assert(hdw,0);
1154
1155 kfree(fw_ptr);
1156 release_firmware(fw_entry);
1157
1158 trace_firmware("Upload done (%d bytes sent)",ret);
1159
1160 /* We should have written 8192 bytes */
1161 if (ret == 8192) {
1162 hdw->fw1_state = FW1_STATE_RELOAD;
1163 return 0;
1164 }
1165
1166 return -EIO;
1167}
1168
1169
1170/*
1171 * pvr2_upload_firmware2()
1172 *
1173 * This uploads encoder firmware on endpoint 2.
1174 *
1175 */
1176
1177int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1178{
a0fd1cb1 1179 const struct firmware *fw_entry = NULL;
d855497e 1180 void *fw_ptr;
90060d32 1181 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1182 int actual_length;
1183 int ret = 0;
1184 int fwidx;
1185 static const char *fw_files[] = {
1186 CX2341X_FIRM_ENC_FILENAME,
1187 };
1188
989eb154 1189 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1190 return 0;
1191 }
1192
d855497e
MI		 1193 trace_firmware("pvr2_upload_firmware2");
1194
1195 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1196 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1197 if (ret < 0) return ret;
1198 fwidx = ret;
1199 ret = 0;
b30d2441
MI		 1200 /* Since we're about to completely reinitialize the encoder,
1201 invalidate our cached copy of its configuration state. Next
1202 time we configure the encoder, then we'll fully configure it. */
1203 hdw->enc_cur_valid = 0;
d855497e
MI		 1204
1205 /* First prepare firmware loading */
1206 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1207 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1208 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1209 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1210 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1211 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1212 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1213 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1214 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1215 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1216 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1217 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1218 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1219 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1220 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1221 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
567d7115
MI		 1222 LOCK_TAKE(hdw->ctl_lock); do {
1223 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
89952d13 1224 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
567d7115
MI		 1225 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1226 hdw->cmd_buffer[1] = 0;
89952d13 1227 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
567d7115 1228 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 1229
1230 if (ret) {
1231 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1232 "firmware2 upload prep failed, ret=%d",ret);
1233 release_firmware(fw_entry);
1234 return ret;
1235 }
1236
1237 /* Now send firmware */
1238
1239 fw_len = fw_entry->size;
1240
90060d32 1241 if (fw_len % sizeof(u32)) {
d855497e
MI		 1242 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1243 "size of %s firmware"
48dc30a1 1244 " must be a multiple of %zu bytes",
90060d32 1245 fw_files[fwidx],sizeof(u32));
d855497e
MI		 1246 release_firmware(fw_entry);
1247 return -1;
1248 }
1249
1250 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1251 if (fw_ptr == NULL){
1252 release_firmware(fw_entry);
1253 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1254 "failed to allocate memory for firmware2 upload");
1255 return -ENOMEM;
1256 }
1257
1258 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1259
90060d32
MI		 1260 fw_done = 0;
1261 for (fw_done = 0; fw_done < fw_len;) {
1262 bcnt = fw_len - fw_done;
1263 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1264 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1265 /* Usbsnoop log shows that we must swap bytes... */
1266 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1267 ((u32 *)fw_ptr)[icnt] =
1268 ___swab32(((u32 *)fw_ptr)[icnt]);
1269
1270 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1271 &actual_length, HZ);
90060d32
MI		 1272 ret |= (actual_length != bcnt);
1273 if (ret) break;
1274 fw_done += bcnt;
d855497e
MI		 1275 }
1276
1277 trace_firmware("upload of %s : %i / %i ",
1278 fw_files[fwidx],fw_done,fw_len);
1279
1280 kfree(fw_ptr);
1281 release_firmware(fw_entry);
1282
1283 if (ret) {
1284 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1285 "firmware2 upload transfer failure");
1286 return ret;
1287 }
1288
1289 /* Finish upload */
1290
1291 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1292 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
567d7115
MI		 1293 LOCK_TAKE(hdw->ctl_lock); do {
1294 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1295 hdw->cmd_buffer[1] = 0;
89952d13 1296 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
567d7115 1297 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 1298
1299 if (ret) {
1300 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1301 "firmware2 upload post-proc failure");
d855497e
MI		 1302 }
1303 return ret;
1304}
1305
1306
681c7399
MI		 1307static const char *pvr2_get_state_name(unsigned int st)
1308{
1309 if (st < ARRAY_SIZE(pvr2_state_names)) {
1310 return pvr2_state_names[st];
d855497e 1311 }
681c7399 1312 return "???";
d855497e
MI		 1313}
1314
681c7399 1315static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1316{
681c7399
MI		 1317 if (!hdw->decoder_ctrl) {
1318 if (!hdw->flag_decoder_missed) {
1319 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1320 "WARNING: No decoder present");
1321 hdw->flag_decoder_missed = !0;
1322 trace_stbit("flag_decoder_missed",
1323 hdw->flag_decoder_missed);
1324 }
1325 return -EIO;
1326 }
1327 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1328 return 0;
d855497e
MI		 1329}
1330
1331
681c7399 1332void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
d855497e 1333{
681c7399
MI		 1334 if (hdw->decoder_ctrl == ptr) return;
1335 hdw->decoder_ctrl = ptr;
1336 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1337 hdw->flag_decoder_missed = 0;
1338 trace_stbit("flag_decoder_missed",
1339 hdw->flag_decoder_missed);
1340 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1341 "Decoder has appeared");
1342 pvr2_hdw_state_sched(hdw);
1343 }
d855497e
MI		 1344}
1345
1346
681c7399 1347int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1348{
681c7399 1349 return hdw->master_state;
d855497e
MI		 1350}
1351
1352
681c7399 1353static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1354{
681c7399
MI		 1355 if (!hdw->flag_tripped) return 0;
1356 hdw->flag_tripped = 0;
1357 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1358 "Clearing driver error statuss");
1359 return !0;
d855497e
MI		 1360}
1361
1362
681c7399 1363int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1364{
681c7399 1365 int fl;
d855497e 1366 LOCK_TAKE(hdw->big_lock); do {
681c7399 1367 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1368 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1369 if (fl) pvr2_hdw_state_sched(hdw);
1370 return 0;
d855497e
MI		 1371}
1372
1373
681c7399 1374const char *pvr2_hdw_get_state_name(unsigned int id)
d855497e 1375{
681c7399
MI		 1376 if (id >= ARRAY_SIZE(pvr2_state_names)) return NULL;
1377 return pvr2_state_names[id];
d855497e
MI		 1378}
1379
1380
1381int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1382{
681c7399 1383 return hdw->state_pipeline_req != 0;
d855497e
MI		 1384}
1385
1386
1387int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1388{
681c7399 1389 int ret,st;
d855497e 1390 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1391 pvr2_hdw_untrip_unlocked(hdw);
1392 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1393 hdw->state_pipeline_req = enable_flag != 0;
1394 pvr2_trace(PVR2_TRACE_START_STOP,
1395 "/*--TRACE_STREAM--*/ %s",
1396 enable_flag ? "enable" : "disable");
1397 }
1398 pvr2_hdw_state_sched(hdw);
d855497e 1399 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1400 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1401 if (enable_flag) {
1402 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1403 if (st != PVR2_STATE_READY) return -EIO;
1404 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1405 }
1406 }
d855497e
MI		 1407 return 0;
1408}
1409
1410
1411int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1412{
681c7399 1413 int fl;
d855497e 1414 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1415 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1416 hdw->desired_stream_type = config;
1417 hdw->state_pipeline_config = 0;
1418 trace_stbit("state_pipeline_config",
1419 hdw->state_pipeline_config);
1420 pvr2_hdw_state_sched(hdw);
1421 }
d855497e 1422 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1423 if (fl) return 0;
1424 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1425}
1426
1427
1428static int get_default_tuner_type(struct pvr2_hdw *hdw)
1429{
1430 int unit_number = hdw->unit_number;
1431 int tp = -1;
1432 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1433 tp = tuner[unit_number];
1434 }
1435 if (tp < 0) return -EINVAL;
1436 hdw->tuner_type = tp;
aaf7884d 1437 hdw->tuner_updated = !0;
d855497e
MI		 1438 return 0;
1439}
1440
1441
1442static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1443{
1444 int unit_number = hdw->unit_number;
1445 int tp = 0;
1446 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1447 tp = video_std[unit_number];
6a540254 1448 if (tp) return tp;
d855497e 1449 }
6a540254 1450 return 0;
d855497e
MI		 1451}
1452
1453
1454static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1455{
1456 int unit_number = hdw->unit_number;
1457 int tp = 0;
1458 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1459 tp = tolerance[unit_number];
1460 }
1461 return tp;
1462}
1463
1464
1465static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1466{
1467 /* Try a harmless request to fetch the eeprom's address over
1468 endpoint 1. See what happens. Only the full FX2 image can
1469 respond to this. If this probe fails then likely the FX2
1470 firmware needs be loaded. */
1471 int result;
1472 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1473 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1474 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1475 hdw->cmd_buffer,1,
1476 hdw->cmd_buffer,1);
1477 if (result < 0) break;
1478 } while(0); LOCK_GIVE(hdw->ctl_lock);
1479 if (result) {
1480 pvr2_trace(PVR2_TRACE_INIT,
1481 "Probe of device endpoint 1 result status %d",
1482 result);
1483 } else {
1484 pvr2_trace(PVR2_TRACE_INIT,
1485 "Probe of device endpoint 1 succeeded");
1486 }
1487 return result == 0;
1488}
1489
9f66d4ea
MI		 1490struct pvr2_std_hack {
1491 v4l2_std_id pat; /* Pattern to match */
1492 v4l2_std_id msk; /* Which bits we care about */
1493 v4l2_std_id std; /* What additional standards or default to set */
1494};
1495
1496/* This data structure labels specific combinations of standards from
1497 tveeprom that we'll try to recognize. If we recognize one, then assume
1498 a specified default standard to use. This is here because tveeprom only
1499 tells us about available standards not the intended default standard (if
1500 any) for the device in question. We guess the default based on what has
1501 been reported as available. Note that this is only for guessing a
1502 default - which can always be overridden explicitly - and if the user
1503 has otherwise named a default then that default will always be used in
1504 place of this table. */
ebff0330 1505static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1506 { /* PAL(B/G) */
1507 .pat = V4L2_STD_B|V4L2_STD_GH,
1508 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1509 },
1510 { /* NTSC(M) */
1511 .pat = V4L2_STD_MN,
1512 .std = V4L2_STD_NTSC_M,
1513 },
1514 { /* PAL(I) */
1515 .pat = V4L2_STD_PAL_I,
1516 .std = V4L2_STD_PAL_I,
1517 },
1518 { /* SECAM(L/L') */
1519 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1520 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1521 },
1522 { /* PAL(D/D1/K) */
1523 .pat = V4L2_STD_DK,
ea2562d9 1524 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1525 },
1526};
1527
d855497e
MI		 1528static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1529{
1530 char buf[40];
1531 unsigned int bcnt;
3d290bdb 1532 v4l2_std_id std1,std2,std3;
d855497e
MI		 1533
1534 std1 = get_default_standard(hdw);
3d290bdb 1535 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1536
1537 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1538 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1539 "Supported video standard(s) reported available"
1540 " in hardware: %.*s",
d855497e
MI		 1541 bcnt,buf);
1542
1543 hdw->std_mask_avail = hdw->std_mask_eeprom;
1544
3d290bdb 1545 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1546 if (std2) {
1547 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1548 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1549 "Expanding supported video standards"
1550 " to include: %.*s",
1551 bcnt,buf);
1552 hdw->std_mask_avail |= std2;
1553 }
1554
1555 pvr2_hdw_internal_set_std_avail(hdw);
1556
1557 if (std1) {
1558 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1559 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1560 "Initial video standard forced to %.*s",
1561 bcnt,buf);
1562 hdw->std_mask_cur = std1;
1563 hdw->std_dirty = !0;
1564 pvr2_hdw_internal_find_stdenum(hdw);
1565 return;
1566 }
3d290bdb
MI		 1567 if (std3) {
1568 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1569 pvr2_trace(PVR2_TRACE_STD,
1570 "Initial video standard"
1571 " (determined by device type): %.*s",bcnt,buf);
1572 hdw->std_mask_cur = std3;
1573 hdw->std_dirty = !0;
1574 pvr2_hdw_internal_find_stdenum(hdw);
1575 return;
1576 }
d855497e 1577
9f66d4ea
MI		 1578 {
1579 unsigned int idx;
1580 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1581 if (std_eeprom_maps[idx].msk ?
1582 ((std_eeprom_maps[idx].pat ^
1583 hdw->std_mask_eeprom) &
1584 std_eeprom_maps[idx].msk) :
1585 (std_eeprom_maps[idx].pat !=
1586 hdw->std_mask_eeprom)) continue;
1587 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1588 std_eeprom_maps[idx].std);
56585386 1589 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1590 "Initial video standard guessed as %.*s",
1591 bcnt,buf);
1592 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1593 hdw->std_dirty = !0;
1594 pvr2_hdw_internal_find_stdenum(hdw);
1595 return;
1596 }
1597 }
1598
d855497e
MI		 1599 if (hdw->std_enum_cnt > 1) {
1600 // Autoselect the first listed standard
1601 hdw->std_enum_cur = 1;
1602 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1603 hdw->std_dirty = !0;
56585386 1604 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1605 "Initial video standard auto-selected to %s",
1606 hdw->std_defs[hdw->std_enum_cur-1].name);
1607 return;
1608 }
1609
0885ba1d 1610 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1611 "Unable to select a viable initial video standard");
1612}
1613
1614
1615static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1616{
1617 int ret;
1618 unsigned int idx;
1619 struct pvr2_ctrl *cptr;
1620 int reloadFl = 0;
989eb154 1621 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 1622 if (!reloadFl) {
1623 reloadFl =
1624 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1625 == 0);
1626 if (reloadFl) {
1627 pvr2_trace(PVR2_TRACE_INIT,
1628 "USB endpoint config looks strange"
1629 "; possibly firmware needs to be"
1630 " loaded");
1631 }
d855497e 1632 }
1d643a37
MI		 1633 if (!reloadFl) {
1634 reloadFl = !pvr2_hdw_check_firmware(hdw);
1635 if (reloadFl) {
1636 pvr2_trace(PVR2_TRACE_INIT,
1637 "Check for FX2 firmware failed"
1638 "; possibly firmware needs to be"
1639 " loaded");
1640 }
d855497e 1641 }
1d643a37
MI		 1642 if (reloadFl) {
1643 if (pvr2_upload_firmware1(hdw) != 0) {
1644 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1645 "Failure uploading firmware1");
1646 }
1647 return;
d855497e 1648 }
d855497e
MI		 1649 }
1650 hdw->fw1_state = FW1_STATE_OK;
1651
1652 if (initusbreset) {
1653 pvr2_hdw_device_reset(hdw);
1654 }
1655 if (!pvr2_hdw_dev_ok(hdw)) return;
1656
989eb154
MI		 1657 for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1658 request_module(hdw->hdw_desc->client_modules.lst[idx]);
d855497e
MI		 1659 }
1660
989eb154 1661 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 1662 pvr2_hdw_cmd_powerup(hdw);
1663 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 1664 }
1665
1666 // This step MUST happen after the earlier powerup step.
1667 pvr2_i2c_core_init(hdw);
1668 if (!pvr2_hdw_dev_ok(hdw)) return;
1669
c05c0462 1670 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 1671 cptr = hdw->controls + idx;
1672 if (cptr->info->skip_init) continue;
1673 if (!cptr->info->set_value) continue;
1674 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1675 }
1676
1bde0289
MI		 1677 /* Set up special default values for the television and radio
1678 frequencies here. It's not really important what these defaults
1679 are, but I set them to something usable in the Chicago area just
1680 to make driver testing a little easier. */
1681
1682 /* US Broadcast channel 7 (175.25 MHz) */
1683 hdw->freqValTelevision = 175250000L;
1684 /* 104.3 MHz, a usable FM station for my area */
1685 hdw->freqValRadio = 104300000L;
1686
d855497e
MI		 1687 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1688 // thread-safe against the normal pvr2_send_request() mechanism.
1689 // (We should make it thread safe).
1690
aaf7884d
MI		 1691 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1692 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 1693 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 1694 if (ret < 0) {
1695 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1696 "Unable to determine location of eeprom,"
1697 " skipping");
1698 } else {
1699 hdw->eeprom_addr = ret;
1700 pvr2_eeprom_analyze(hdw);
1701 if (!pvr2_hdw_dev_ok(hdw)) return;
1702 }
1703 } else {
1704 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1705 hdw->tuner_updated = !0;
1706 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 1707 }
1708
1709 pvr2_hdw_setup_std(hdw);
1710
1711 if (!get_default_tuner_type(hdw)) {
1712 pvr2_trace(PVR2_TRACE_INIT,
1713 "pvr2_hdw_setup: Tuner type overridden to %d",
1714 hdw->tuner_type);
1715 }
1716
d855497e
MI		 1717 pvr2_i2c_core_check_stale(hdw);
1718 hdw->tuner_updated = 0;
1719
1720 if (!pvr2_hdw_dev_ok(hdw)) return;
1721
681c7399 1722 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 1723
1724 hdw->vid_stream = pvr2_stream_create();
1725 if (!pvr2_hdw_dev_ok(hdw)) return;
1726 pvr2_trace(PVR2_TRACE_INIT,
1727 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1728 if (hdw->vid_stream) {
1729 idx = get_default_error_tolerance(hdw);
1730 if (idx) {
1731 pvr2_trace(PVR2_TRACE_INIT,
1732 "pvr2_hdw_setup: video stream %p"
1733 " setting tolerance %u",
1734 hdw->vid_stream,idx);
1735 }
1736 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1737 PVR2_VID_ENDPOINT,idx);
1738 }
1739
1740 if (!pvr2_hdw_dev_ok(hdw)) return;
1741
d855497e 1742 hdw->flag_init_ok = !0;
681c7399
MI		 1743
1744 pvr2_hdw_state_sched(hdw);
d855497e
MI		 1745}
1746
1747
681c7399
MI		 1748/* Set up the structure and attempt to put the device into a usable state.
1749 This can be a time-consuming operation, which is why it is not done
1750 internally as part of the create() step. */
1751static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 1752{
1753 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 1754 do {
d855497e
MI		 1755 pvr2_hdw_setup_low(hdw);
1756 pvr2_trace(PVR2_TRACE_INIT,
1757 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 1758 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 1759 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 1760 if (hdw->flag_init_ok) {
d855497e
MI		 1761 pvr2_trace(
1762 PVR2_TRACE_INFO,
1763 "Device initialization"
1764 " completed successfully.");
1765 break;
1766 }
1767 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1768 pvr2_trace(
1769 PVR2_TRACE_INFO,
1770 "Device microcontroller firmware"
1771 " (re)loaded; it should now reset"
1772 " and reconnect.");
1773 break;
1774 }
1775 pvr2_trace(
1776 PVR2_TRACE_ERROR_LEGS,
1777 "Device initialization was not successful.");
1778 if (hdw->fw1_state == FW1_STATE_MISSING) {
1779 pvr2_trace(
1780 PVR2_TRACE_ERROR_LEGS,
1781 "Giving up since device"
1782 " microcontroller firmware"
1783 " appears to be missing.");
1784 break;
1785 }
1786 }
1787 if (procreload) {
1788 pvr2_trace(
1789 PVR2_TRACE_ERROR_LEGS,
1790 "Attempting pvrusb2 recovery by reloading"
1791 " primary firmware.");
1792 pvr2_trace(
1793 PVR2_TRACE_ERROR_LEGS,
1794 "If this works, device should disconnect"
1795 " and reconnect in a sane state.");
1796 hdw->fw1_state = FW1_STATE_UNKNOWN;
1797 pvr2_upload_firmware1(hdw);
1798 } else {
1799 pvr2_trace(
1800 PVR2_TRACE_ERROR_LEGS,
1801 "***WARNING*** pvrusb2 device hardware"
1802 " appears to be jammed"
1803 " and I can't clear it.");
1804 pvr2_trace(
1805 PVR2_TRACE_ERROR_LEGS,
1806 "You might need to power cycle"
1807 " the pvrusb2 device"
1808 " in order to recover.");
1809 }
681c7399 1810 } while (0);
d855497e 1811 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 1812}
1813
1814
c4a8828d
MI		 1815/* Perform second stage initialization. Set callback pointer first so that
1816 we can avoid a possible initialization race (if the kernel thread runs
1817 before the callback has been set). */
794b1607
MI		 1818int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
1819 void (*callback_func)(void *),
1820 void *callback_data)
c4a8828d
MI		 1821{
1822 LOCK_TAKE(hdw->big_lock); do {
1823 hdw->state_data = callback_data;
1824 hdw->state_func = callback_func;
1825 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607
MI		 1826 pvr2_hdw_setup(hdw);
1827 return hdw->flag_init_ok;
c4a8828d
MI		 1828}
1829
1830
1831/* Create, set up, and return a structure for interacting with the
1832 underlying hardware. */
d855497e
MI		 1833struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1834 const struct usb_device_id *devid)
1835{
7fb20fa3 1836 unsigned int idx,cnt1,cnt2,m;
d855497e 1837 struct pvr2_hdw *hdw;
d855497e
MI		 1838 int valid_std_mask;
1839 struct pvr2_ctrl *cptr;
989eb154 1840 const struct pvr2_device_desc *hdw_desc;
d855497e 1841 __u8 ifnum;
b30d2441
MI		 1842 struct v4l2_queryctrl qctrl;
1843 struct pvr2_ctl_info *ciptr;
d855497e 1844
d130fa8a 1845 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 1846
ca545f7c 1847 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 1848 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 1849 hdw,hdw_desc->description);
d855497e 1850 if (!hdw) goto fail;
681c7399
MI		 1851
1852 init_timer(&hdw->quiescent_timer);
1853 hdw->quiescent_timer.data = (unsigned long)hdw;
1854 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1855
1856 init_timer(&hdw->encoder_wait_timer);
1857 hdw->encoder_wait_timer.data = (unsigned long)hdw;
1858 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1859
1860 hdw->master_state = PVR2_STATE_DEAD;
1861
1862 init_waitqueue_head(&hdw->state_wait_data);
1863
18103c57 1864 hdw->tuner_signal_stale = !0;
b30d2441 1865 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 1866
7fb20fa3
MI		 1867 /* Calculate which inputs are OK */
1868 m = 0;
1869 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 1870 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
1871 m |= 1 << PVR2_CVAL_INPUT_DTV;
1872 }
7fb20fa3
MI		 1873 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
1874 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
1875 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
1876 hdw->input_avail_mask = m;
1877
62433e31
MI		 1878 /* If not a hybrid device, pathway_state never changes. So
1879 initialize it here to what it should forever be. */
1880 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
1881 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
1882 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
1883 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
1884 }
1885
c05c0462 1886 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 1887 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 1888 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 1889 GFP_KERNEL);
1890 if (!hdw->controls) goto fail;
989eb154 1891 hdw->hdw_desc = hdw_desc;
c05c0462
MI		 1892 for (idx = 0; idx < hdw->control_cnt; idx++) {
1893 cptr = hdw->controls + idx;
1894 cptr->hdw = hdw;
1895 }
d855497e
MI		 1896 for (idx = 0; idx < 32; idx++) {
1897 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1898 }
c05c0462 1899 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 1900 cptr = hdw->controls + idx;
d855497e
MI		 1901 cptr->info = control_defs+idx;
1902 }
dbc40a0e
MI		 1903
1904 /* Ensure that default input choice is a valid one. */
1905 m = hdw->input_avail_mask;
1906 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
1907 if (!((1 << idx) & m)) continue;
1908 hdw->input_val = idx;
1909 break;
1910 }
1911
b30d2441 1912 /* Define and configure additional controls from cx2341x module. */
ca545f7c 1913 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 1914 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1915 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 1916 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1917 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1918 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1919 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1920 ciptr->name = mpeg_ids[idx].strid;
1921 ciptr->v4l_id = mpeg_ids[idx].id;
1922 ciptr->skip_init = !0;
1923 ciptr->get_value = ctrl_cx2341x_get;
1924 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1925 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1926 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1927 qctrl.id = ciptr->v4l_id;
1928 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1929 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1930 ciptr->set_value = ctrl_cx2341x_set;
1931 }
1932 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1933 PVR2_CTLD_INFO_DESC_SIZE);
1934 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1935 ciptr->default_value = qctrl.default_value;
1936 switch (qctrl.type) {
1937 default:
1938 case V4L2_CTRL_TYPE_INTEGER:
1939 ciptr->type = pvr2_ctl_int;
1940 ciptr->def.type_int.min_value = qctrl.minimum;
1941 ciptr->def.type_int.max_value = qctrl.maximum;
1942 break;
1943 case V4L2_CTRL_TYPE_BOOLEAN:
1944 ciptr->type = pvr2_ctl_bool;
1945 break;
1946 case V4L2_CTRL_TYPE_MENU:
1947 ciptr->type = pvr2_ctl_enum;
1948 ciptr->def.type_enum.value_names =
1949 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1950 for (cnt1 = 0;
1951 ciptr->def.type_enum.value_names[cnt1] != NULL;
1952 cnt1++) { }
1953 ciptr->def.type_enum.count = cnt1;
1954 break;
1955 }
1956 cptr->info = ciptr;
1957 }
d855497e
MI		 1958
1959 // Initialize video standard enum dynamic control
1960 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1961 if (cptr) {
1962 memcpy(&hdw->std_info_enum,cptr->info,
1963 sizeof(hdw->std_info_enum));
1964 cptr->info = &hdw->std_info_enum;
1965
1966 }
1967 // Initialize control data regarding video standard masks
1968 valid_std_mask = pvr2_std_get_usable();
1969 for (idx = 0; idx < 32; idx++) {
1970 if (!(valid_std_mask & (1 << idx))) continue;
1971 cnt1 = pvr2_std_id_to_str(
1972 hdw->std_mask_names[idx],
1973 sizeof(hdw->std_mask_names[idx])-1,
1974 1 << idx);
1975 hdw->std_mask_names[idx][cnt1] = 0;
1976 }
1977 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1978 if (cptr) {
1979 memcpy(&hdw->std_info_avail,cptr->info,
1980 sizeof(hdw->std_info_avail));
1981 cptr->info = &hdw->std_info_avail;
1982 hdw->std_info_avail.def.type_bitmask.bit_names =
1983 hdw->std_mask_ptrs;
1984 hdw->std_info_avail.def.type_bitmask.valid_bits =
1985 valid_std_mask;
1986 }
1987 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1988 if (cptr) {
1989 memcpy(&hdw->std_info_cur,cptr->info,
1990 sizeof(hdw->std_info_cur));
1991 cptr->info = &hdw->std_info_cur;
1992 hdw->std_info_cur.def.type_bitmask.bit_names =
1993 hdw->std_mask_ptrs;
1994 hdw->std_info_avail.def.type_bitmask.valid_bits =
1995 valid_std_mask;
1996 }
1997
1998 hdw->eeprom_addr = -1;
1999 hdw->unit_number = -1;
8079384e
MI		 2000 hdw->v4l_minor_number_video = -1;
2001 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2002 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2003 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2004 if (!hdw->ctl_write_buffer) goto fail;
2005 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2006 if (!hdw->ctl_read_buffer) goto fail;
2007 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2008 if (!hdw->ctl_write_urb) goto fail;
2009 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2010 if (!hdw->ctl_read_urb) goto fail;
2011
8df0c87c 2012 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2013 for (idx = 0; idx < PVR_NUM; idx++) {
2014 if (unit_pointers[idx]) continue;
2015 hdw->unit_number = idx;
2016 unit_pointers[idx] = hdw;
2017 break;
2018 }
8df0c87c 2019 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2020
2021 cnt1 = 0;
2022 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2023 cnt1 += cnt2;
2024 if (hdw->unit_number >= 0) {
2025 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2026 ('a' + hdw->unit_number));
2027 cnt1 += cnt2;
2028 }
2029 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2030 hdw->name[cnt1] = 0;
2031
681c7399
MI		 2032 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2033 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2034 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
681c7399 2035
d855497e
MI		 2036 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2037 hdw->unit_number,hdw->name);
2038
2039 hdw->tuner_type = -1;
2040 hdw->flag_ok = !0;
d855497e
MI		 2041
2042 hdw->usb_intf = intf;
2043 hdw->usb_dev = interface_to_usbdev(intf);
2044
31a18547
MI		 2045 scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2046 "usb %s address %d",
2047 hdw->usb_dev->dev.bus_id,
2048 hdw->usb_dev->devnum);
2049
d855497e
MI		 2050 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2051 usb_set_interface(hdw->usb_dev,ifnum,0);
2052
2053 mutex_init(&hdw->ctl_lock_mutex);
2054 mutex_init(&hdw->big_lock_mutex);
2055
2056 return hdw;
2057 fail:
2058 if (hdw) {
681c7399
MI		 2059 del_timer_sync(&hdw->quiescent_timer);
2060 del_timer_sync(&hdw->encoder_wait_timer);
2061 if (hdw->workqueue) {
2062 flush_workqueue(hdw->workqueue);
2063 destroy_workqueue(hdw->workqueue);
2064 hdw->workqueue = NULL;
2065 }
5e55d2ce
MK		 2066 usb_free_urb(hdw->ctl_read_urb);
2067 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2068 kfree(hdw->ctl_read_buffer);
2069 kfree(hdw->ctl_write_buffer);
2070 kfree(hdw->controls);
2071 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2072 kfree(hdw->std_defs);
2073 kfree(hdw->std_enum_names);
d855497e
MI		 2074 kfree(hdw);
2075 }
a0fd1cb1 2076 return NULL;
d855497e
MI		 2077}
2078
2079
2080/* Remove _all_ associations between this driver and the underlying USB
2081 layer. */
07e337ee 2082static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2083{
2084 if (hdw->flag_disconnected) return;
2085 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2086 if (hdw->ctl_read_urb) {
2087 usb_kill_urb(hdw->ctl_read_urb);
2088 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2089 hdw->ctl_read_urb = NULL;
d855497e
MI		 2090 }
2091 if (hdw->ctl_write_urb) {
2092 usb_kill_urb(hdw->ctl_write_urb);
2093 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2094 hdw->ctl_write_urb = NULL;
d855497e
MI		 2095 }
2096 if (hdw->ctl_read_buffer) {
2097 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2098 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2099 }
2100 if (hdw->ctl_write_buffer) {
2101 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2102 hdw->ctl_write_buffer = NULL;
d855497e 2103 }
d855497e 2104 hdw->flag_disconnected = !0;
a0fd1cb1
MI		 2105 hdw->usb_dev = NULL;
2106 hdw->usb_intf = NULL;
681c7399 2107 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2108}
2109
2110
2111/* Destroy hardware interaction structure */
2112void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2113{
401c27ce 2114 if (!hdw) return;
d855497e 2115 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2116 if (hdw->workqueue) {
2117 flush_workqueue(hdw->workqueue);
2118 destroy_workqueue(hdw->workqueue);
2119 hdw->workqueue = NULL;
2120 }
8f59100a
MI		 2121 del_timer_sync(&hdw->quiescent_timer);
2122 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2123 if (hdw->fw_buffer) {
2124 kfree(hdw->fw_buffer);
a0fd1cb1 2125 hdw->fw_buffer = NULL;
d855497e
MI		 2126 }
2127 if (hdw->vid_stream) {
2128 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2129 hdw->vid_stream = NULL;
d855497e 2130 }
d855497e
MI		 2131 if (hdw->decoder_ctrl) {
2132 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2133 }
2134 pvr2_i2c_core_done(hdw);
2135 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2136 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2137 if ((hdw->unit_number >= 0) &&
2138 (hdw->unit_number < PVR_NUM) &&
2139 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2140 unit_pointers[hdw->unit_number] = NULL;
d855497e 2141 }
8df0c87c 2142 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2143 kfree(hdw->controls);
2144 kfree(hdw->mpeg_ctrl_info);
2145 kfree(hdw->std_defs);
2146 kfree(hdw->std_enum_names);
d855497e
MI		 2147 kfree(hdw);
2148}
2149
2150
d855497e
MI		 2151int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2152{
2153 return (hdw && hdw->flag_ok);
2154}
2155
2156
2157/* Called when hardware has been unplugged */
2158void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2159{
2160 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2161 LOCK_TAKE(hdw->big_lock);
2162 LOCK_TAKE(hdw->ctl_lock);
2163 pvr2_hdw_remove_usb_stuff(hdw);
2164 LOCK_GIVE(hdw->ctl_lock);
2165 LOCK_GIVE(hdw->big_lock);
2166}
2167
2168
2169// Attempt to autoselect an appropriate value for std_enum_cur given
2170// whatever is currently in std_mask_cur
07e337ee 2171static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2172{
2173 unsigned int idx;
2174 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2175 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2176 hdw->std_enum_cur = idx;
2177 return;
2178 }
2179 }
2180 hdw->std_enum_cur = 0;
2181}
2182
2183
2184// Calculate correct set of enumerated standards based on currently known
2185// set of available standards bits.
07e337ee 2186static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2187{
2188 struct v4l2_standard *newstd;
2189 unsigned int std_cnt;
2190 unsigned int idx;
2191
2192 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2193
2194 if (hdw->std_defs) {
2195 kfree(hdw->std_defs);
a0fd1cb1 2196 hdw->std_defs = NULL;
d855497e
MI		 2197 }
2198 hdw->std_enum_cnt = 0;
2199 if (hdw->std_enum_names) {
2200 kfree(hdw->std_enum_names);
a0fd1cb1 2201 hdw->std_enum_names = NULL;
d855497e
MI		 2202 }
2203
2204 if (!std_cnt) {
2205 pvr2_trace(
2206 PVR2_TRACE_ERROR_LEGS,
2207 "WARNING: Failed to identify any viable standards");
2208 }
2209 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2210 hdw->std_enum_names[0] = "none";
2211 for (idx = 0; idx < std_cnt; idx++) {
2212 hdw->std_enum_names[idx+1] =
2213 newstd[idx].name;
2214 }
2215 // Set up the dynamic control for this standard
2216 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2217 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2218 hdw->std_defs = newstd;
2219 hdw->std_enum_cnt = std_cnt+1;
2220 hdw->std_enum_cur = 0;
2221 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2222}
2223
2224
2225int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2226 struct v4l2_standard *std,
2227 unsigned int idx)
2228{
2229 int ret = -EINVAL;
2230 if (!idx) return ret;
2231 LOCK_TAKE(hdw->big_lock); do {
2232 if (idx >= hdw->std_enum_cnt) break;
2233 idx--;
2234 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2235 ret = 0;
2236 } while (0); LOCK_GIVE(hdw->big_lock);
2237 return ret;
2238}
2239
2240
2241/* Get the number of defined controls */
2242unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2243{
c05c0462 2244 return hdw->control_cnt;
d855497e
MI		 2245}
2246
2247
2248/* Retrieve a control handle given its index (0..count-1) */
2249struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2250 unsigned int idx)
2251{
a0fd1cb1 2252 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2253 return hdw->controls + idx;
2254}
2255
2256
2257/* Retrieve a control handle given its index (0..count-1) */
2258struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2259 unsigned int ctl_id)
2260{
2261 struct pvr2_ctrl *cptr;
2262 unsigned int idx;
2263 int i;
2264
2265 /* This could be made a lot more efficient, but for now... */
c05c0462 2266 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2267 cptr = hdw->controls + idx;
2268 i = cptr->info->internal_id;
2269 if (i && (i == ctl_id)) return cptr;
2270 }
a0fd1cb1 2271 return NULL;
d855497e
MI		 2272}
2273
2274
a761f431 2275/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2276struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2277{
2278 struct pvr2_ctrl *cptr;
2279 unsigned int idx;
2280 int i;
2281
2282 /* This could be made a lot more efficient, but for now... */
c05c0462 2283 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2284 cptr = hdw->controls + idx;
2285 i = cptr->info->v4l_id;
2286 if (i && (i == ctl_id)) return cptr;
2287 }
a0fd1cb1 2288 return NULL;
d855497e
MI		 2289}
2290
2291
a761f431
MI		 2292/* Given a V4L ID for its immediate predecessor, retrieve the control
2293 structure associated with it. */
2294struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2295 unsigned int ctl_id)
2296{
2297 struct pvr2_ctrl *cptr,*cp2;
2298 unsigned int idx;
2299 int i;
2300
2301 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2302 cp2 = NULL;
a761f431
MI		 2303 for (idx = 0; idx < hdw->control_cnt; idx++) {
2304 cptr = hdw->controls + idx;
2305 i = cptr->info->v4l_id;
2306 if (!i) continue;
2307 if (i <= ctl_id) continue;
2308 if (cp2 && (cp2->info->v4l_id < i)) continue;
2309 cp2 = cptr;
2310 }
2311 return cp2;
a0fd1cb1 2312 return NULL;
a761f431
MI		 2313}
2314
2315
d855497e
MI		 2316static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2317{
2318 switch (tp) {
2319 case pvr2_ctl_int: return "integer";
2320 case pvr2_ctl_enum: return "enum";
33213963 2321 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2322 case pvr2_ctl_bitmask: return "bitmask";
2323 }
2324 return "";
2325}
2326
2327
681c7399
MI		 2328/* Figure out if we need to commit control changes. If so, mark internal
2329 state flags to indicate this fact and return true. Otherwise do nothing
2330 else and return false. */
2331static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 2332{
d855497e
MI		 2333 unsigned int idx;
2334 struct pvr2_ctrl *cptr;
2335 int value;
2336 int commit_flag = 0;
2337 char buf[100];
2338 unsigned int bcnt,ccnt;
2339
c05c0462 2340 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 2341 cptr = hdw->controls + idx;
5fa1247a 2342 if (!cptr->info->is_dirty) continue;
d855497e 2343 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 2344 commit_flag = !0;
d855497e 2345
fe23a280 2346 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 2347 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2348 cptr->info->name);
2349 value = 0;
2350 cptr->info->get_value(cptr,&value);
2351 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2352 buf+bcnt,
2353 sizeof(buf)-bcnt,&ccnt);
2354 bcnt += ccnt;
2355 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2356 get_ctrl_typename(cptr->info->type));
2357 pvr2_trace(PVR2_TRACE_CTL,
2358 "/*--TRACE_COMMIT--*/ %.*s",
2359 bcnt,buf);
2360 }
2361
2362 if (!commit_flag) {
2363 /* Nothing has changed */
2364 return 0;
2365 }
2366
681c7399
MI		 2367 hdw->state_pipeline_config = 0;
2368 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2369 pvr2_hdw_state_sched(hdw);
2370
2371 return !0;
2372}
2373
2374
2375/* Perform all operations needed to commit all control changes. This must
2376 be performed in synchronization with the pipeline state and is thus
2377 expected to be called as part of the driver's worker thread. Return
2378 true if commit successful, otherwise return false to indicate that
2379 commit isn't possible at this time. */
2380static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2381{
2382 unsigned int idx;
2383 struct pvr2_ctrl *cptr;
2384 int disruptive_change;
2385
d855497e
MI		 2386 /* When video standard changes, reset the hres and vres values -
2387 but if the user has pending changes there, then let the changes
2388 take priority. */
2389 if (hdw->std_dirty) {
2390 /* Rewrite the vertical resolution to be appropriate to the
2391 video standard that has been selected. */
2392 int nvres;
2393 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2394 nvres = 480;
2395 } else {
2396 nvres = 576;
2397 }
2398 if (nvres != hdw->res_ver_val) {
2399 hdw->res_ver_val = nvres;
2400 hdw->res_ver_dirty = !0;
2401 }
d855497e
MI		 2402 }
2403
38d9a2cf 2404 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 2405 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
2406 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
2407 hdw->pathway_state)) {
2408 /* Change of mode being asked for... */
2409 hdw->state_pathway_ok = 0;
e9db1ff2 2410 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 2411 }
2412 if (!hdw->state_pathway_ok) {
2413 /* Can't commit anything until pathway is ok. */
2414 return 0;
2415 }
681c7399
MI		 2416 /* If any of the below has changed, then we can't do the update
2417 while the pipeline is running. Pipeline must be paused first
2418 and decoder -> encoder connection be made quiescent before we
2419 can proceed. */
2420 disruptive_change =
2421 (hdw->std_dirty ||
2422 hdw->enc_unsafe_stale ||
2423 hdw->srate_dirty ||
2424 hdw->res_ver_dirty ||
2425 hdw->res_hor_dirty ||
2426 hdw->input_dirty ||
2427 (hdw->active_stream_type != hdw->desired_stream_type));
2428 if (disruptive_change && !hdw->state_pipeline_idle) {
2429 /* Pipeline is not idle; we can't proceed. Arrange to
2430 cause pipeline to stop so that we can try this again
2431 later.... */
2432 hdw->state_pipeline_pause = !0;
2433 return 0;
275b2e28
PK		 2434 }
2435
b30d2441
MI		 2436 if (hdw->srate_dirty) {
2437 /* Write new sample rate into control structure since
2438 * the master copy is stale. We must track srate
2439 * separate from the mpeg control structure because
2440 * other logic also uses this value. */
2441 struct v4l2_ext_controls cs;
2442 struct v4l2_ext_control c1;
2443 memset(&cs,0,sizeof(cs));
2444 memset(&c1,0,sizeof(c1));
2445 cs.controls = &c1;
2446 cs.count = 1;
2447 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2448 c1.value = hdw->srate_val;
01f1e44f 2449 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 2450 }
c05c0462 2451
d855497e
MI		 2452 /* Scan i2c core at this point - before we clear all the dirty
2453 bits. Various parts of the i2c core will notice dirty bits as
2454 appropriate and arrange to broadcast or directly send updates to
2455 the client drivers in order to keep everything in sync */
2456 pvr2_i2c_core_check_stale(hdw);
2457
c05c0462 2458 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2459 cptr = hdw->controls + idx;
2460 if (!cptr->info->clear_dirty) continue;
2461 cptr->info->clear_dirty(cptr);
2462 }
2463
681c7399
MI		 2464 if (hdw->active_stream_type != hdw->desired_stream_type) {
2465 /* Handle any side effects of stream config here */
2466 hdw->active_stream_type = hdw->desired_stream_type;
2467 }
2468
d855497e
MI		 2469 /* Now execute i2c core update */
2470 pvr2_i2c_core_sync(hdw);
2471
62433e31
MI		 2472 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
2473 hdw->state_encoder_run) {
2474 /* If encoder isn't running or it can't be touched, then
2475 this will get worked out later when we start the
2476 encoder. */
681c7399
MI		 2477 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2478 }
d855497e 2479
681c7399
MI		 2480 hdw->state_pipeline_config = !0;
2481 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2482 return !0;
d855497e
MI		 2483}
2484
2485
2486int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2487{
681c7399
MI		 2488 int fl;
2489 LOCK_TAKE(hdw->big_lock);
2490 fl = pvr2_hdw_commit_setup(hdw);
2491 LOCK_GIVE(hdw->big_lock);
2492 if (!fl) return 0;
2493 return pvr2_hdw_wait(hdw,0);
2494}
2495
2496
2497static void pvr2_hdw_worker_i2c(struct work_struct *work)
2498{
2499 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
d855497e 2500 LOCK_TAKE(hdw->big_lock); do {
681c7399 2501 pvr2_i2c_core_sync(hdw);
d855497e 2502 } while (0); LOCK_GIVE(hdw->big_lock);
d855497e
MI		 2503}
2504
2505
681c7399 2506static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 2507{
681c7399
MI		 2508 int fl = 0;
2509 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 2510 LOCK_TAKE(hdw->big_lock); do {
681c7399 2511 fl = pvr2_hdw_state_eval(hdw);
d855497e 2512 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 2513 if (fl && hdw->state_func) {
2514 hdw->state_func(hdw->state_data);
2515 }
d855497e
MI		 2516}
2517
2518
681c7399 2519static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 2520{
681c7399
MI		 2521 return wait_event_interruptible(
2522 hdw->state_wait_data,
2523 (hdw->state_stale == 0) &&
2524 (!state || (hdw->master_state != state)));
2525}
2526
2527
d855497e
MI		 2528/* Return name for this driver instance */
2529const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2530{
2531 return hdw->name;
2532}
2533
2534
78a47101
MI		 2535const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2536{
2537 return hdw->hdw_desc->description;
2538}
2539
2540
2541const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2542{
2543 return hdw->hdw_desc->shortname;
2544}
2545
2546
d855497e
MI		 2547int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2548{
2549 int result;
2550 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 2551 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 2552 result = pvr2_send_request(hdw,
2553 hdw->cmd_buffer,1,
2554 hdw->cmd_buffer,1);
2555 if (result < 0) break;
2556 result = (hdw->cmd_buffer[0] != 0);
2557 } while(0); LOCK_GIVE(hdw->ctl_lock);
2558 return result;
2559}
2560
2561
18103c57
MI		 2562/* Execute poll of tuner status */
2563void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 2564{
d855497e 2565 LOCK_TAKE(hdw->big_lock); do {
18103c57 2566 pvr2_i2c_core_status_poll(hdw);
d855497e 2567 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 2568}
2569
2570
2571/* Return information about the tuner */
2572int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2573{
2574 LOCK_TAKE(hdw->big_lock); do {
2575 if (hdw->tuner_signal_stale) {
2576 pvr2_i2c_core_status_poll(hdw);
2577 }
2578 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2579 } while (0); LOCK_GIVE(hdw->big_lock);
2580 return 0;
d855497e
MI		 2581}
2582
2583
2584/* Get handle to video output stream */
2585struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2586{
2587 return hp->vid_stream;
2588}
2589
2590
2591void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2592{
4f1a3e5b 2593 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e
MI		 2594 LOCK_TAKE(hdw->big_lock); do {
2595 hdw->log_requested = !0;
4f1a3e5b 2596 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
d855497e
MI		 2597 pvr2_i2c_core_check_stale(hdw);
2598 hdw->log_requested = 0;
2599 pvr2_i2c_core_sync(hdw);
b30d2441 2600 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 2601 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 2602 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 2603 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 2604 } while (0); LOCK_GIVE(hdw->big_lock);
2605}
2606
4db666cc
MI		 2607
2608/* Grab EEPROM contents, needed for direct method. */
2609#define EEPROM_SIZE 8192
2610#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2611static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2612{
2613 struct i2c_msg msg[2];
2614 u8 *eeprom;
2615 u8 iadd[2];
2616 u8 addr;
2617 u16 eepromSize;
2618 unsigned int offs;
2619 int ret;
2620 int mode16 = 0;
2621 unsigned pcnt,tcnt;
2622 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2623 if (!eeprom) {
2624 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2625 "Failed to allocate memory"
2626 " required to read eeprom");
2627 return NULL;
2628 }
2629
2630 trace_eeprom("Value for eeprom addr from controller was 0x%x",
2631 hdw->eeprom_addr);
2632 addr = hdw->eeprom_addr;
2633 /* Seems that if the high bit is set, then the *real* eeprom
2634 address is shifted right now bit position (noticed this in
2635 newer PVR USB2 hardware) */
2636 if (addr & 0x80) addr >>= 1;
2637
2638 /* FX2 documentation states that a 16bit-addressed eeprom is
2639 expected if the I2C address is an odd number (yeah, this is
2640 strange but it's what they do) */
2641 mode16 = (addr & 1);
2642 eepromSize = (mode16 ? EEPROM_SIZE : 256);
2643 trace_eeprom("Examining %d byte eeprom at location 0x%x"
2644 " using %d bit addressing",eepromSize,addr,
2645 mode16 ? 16 : 8);
2646
2647 msg[0].addr = addr;
2648 msg[0].flags = 0;
2649 msg[0].len = mode16 ? 2 : 1;
2650 msg[0].buf = iadd;
2651 msg[1].addr = addr;
2652 msg[1].flags = I2C_M_RD;
2653
2654 /* We have to do the actual eeprom data fetch ourselves, because
2655 (1) we're only fetching part of the eeprom, and (2) if we were
2656 getting the whole thing our I2C driver can't grab it in one
2657 pass - which is what tveeprom is otherwise going to attempt */
2658 memset(eeprom,0,EEPROM_SIZE);
2659 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2660 pcnt = 16;
2661 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2662 offs = tcnt + (eepromSize - EEPROM_SIZE);
2663 if (mode16) {
2664 iadd[0] = offs >> 8;
2665 iadd[1] = offs;
2666 } else {
2667 iadd[0] = offs;
2668 }
2669 msg[1].len = pcnt;
2670 msg[1].buf = eeprom+tcnt;
2671 if ((ret = i2c_transfer(&hdw->i2c_adap,
2672 msg,ARRAY_SIZE(msg))) != 2) {
2673 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2674 "eeprom fetch set offs err=%d",ret);
2675 kfree(eeprom);
2676 return NULL;
2677 }
2678 }
2679 return eeprom;
2680}
2681
2682
2683void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2684 int prom_flag,
2685 int enable_flag)
d855497e
MI		 2686{
2687 int ret;
2688 u16 address;
2689 unsigned int pipe;
2690 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 2691 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 2692
2693 if (!enable_flag) {
2694 pvr2_trace(PVR2_TRACE_FIRMWARE,
2695 "Cleaning up after CPU firmware fetch");
2696 kfree(hdw->fw_buffer);
a0fd1cb1 2697 hdw->fw_buffer = NULL;
d855497e 2698 hdw->fw_size = 0;
4db666cc
MI		 2699 if (hdw->fw_cpu_flag) {
2700 /* Now release the CPU. It will disconnect
2701 and reconnect later. */
2702 pvr2_hdw_cpureset_assert(hdw,0);
2703 }
d855497e
MI		 2704 break;
2705 }
2706
4db666cc
MI		 2707 hdw->fw_cpu_flag = (prom_flag == 0);
2708 if (hdw->fw_cpu_flag) {
2709 pvr2_trace(PVR2_TRACE_FIRMWARE,
2710 "Preparing to suck out CPU firmware");
2711 hdw->fw_size = 0x2000;
2712 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2713 if (!hdw->fw_buffer) {
2714 hdw->fw_size = 0;
2715 break;
2716 }
d855497e 2717
4db666cc
MI		 2718 /* We have to hold the CPU during firmware upload. */
2719 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 2720
4db666cc
MI		 2721 /* download the firmware from address 0000-1fff in 2048
2722 (=0x800) bytes chunk. */
d855497e 2723
4db666cc
MI		 2724 pvr2_trace(PVR2_TRACE_FIRMWARE,
2725 "Grabbing CPU firmware");
2726 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2727 for(address = 0; address < hdw->fw_size;
2728 address += 0x800) {
2729 ret = usb_control_msg(hdw->usb_dev,pipe,
2730 0xa0,0xc0,
2731 address,0,
2732 hdw->fw_buffer+address,
2733 0x800,HZ);
2734 if (ret < 0) break;
2735 }
d855497e 2736
4db666cc
MI		 2737 pvr2_trace(PVR2_TRACE_FIRMWARE,
2738 "Done grabbing CPU firmware");
2739 } else {
2740 pvr2_trace(PVR2_TRACE_FIRMWARE,
2741 "Sucking down EEPROM contents");
2742 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2743 if (!hdw->fw_buffer) {
2744 pvr2_trace(PVR2_TRACE_FIRMWARE,
2745 "EEPROM content suck failed.");
2746 break;
2747 }
2748 hdw->fw_size = EEPROM_SIZE;
2749 pvr2_trace(PVR2_TRACE_FIRMWARE,
2750 "Done sucking down EEPROM contents");
2751 }
d855497e
MI		 2752
2753 } while (0); LOCK_GIVE(hdw->big_lock);
2754}
2755
2756
2757/* Return true if we're in a mode for retrieval CPU firmware */
2758int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2759{
5fa1247a 2760 return hdw->fw_buffer != NULL;
d855497e
MI		 2761}
2762
2763
2764int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2765 char *buf,unsigned int cnt)
2766{
2767 int ret = -EINVAL;
2768 LOCK_TAKE(hdw->big_lock); do {
2769 if (!buf) break;
2770 if (!cnt) break;
2771
2772 if (!hdw->fw_buffer) {
2773 ret = -EIO;
2774 break;
2775 }
2776
2777 if (offs >= hdw->fw_size) {
2778 pvr2_trace(PVR2_TRACE_FIRMWARE,
2779 "Read firmware data offs=%d EOF",
2780 offs);
2781 ret = 0;
2782 break;
2783 }
2784
2785 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2786
2787 memcpy(buf,hdw->fw_buffer+offs,cnt);
2788
2789 pvr2_trace(PVR2_TRACE_FIRMWARE,
2790 "Read firmware data offs=%d cnt=%d",
2791 offs,cnt);
2792 ret = cnt;
2793 } while (0); LOCK_GIVE(hdw->big_lock);
2794
2795 return ret;
2796}
2797
2798
fd5a75fe 2799int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 2800 enum pvr2_v4l_type index)
d855497e 2801{
fd5a75fe 2802 switch (index) {
8079384e
MI		 2803 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2804 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2805 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 2806 default: return -1;
2807 }
d855497e
MI		 2808}
2809
2810
2fdf3d9c 2811/* Store a v4l minor device number */
fd5a75fe 2812void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 2813 enum pvr2_v4l_type index,int v)
d855497e 2814{
fd5a75fe 2815 switch (index) {
8079384e
MI		 2816 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2817 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2818 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 2819 default: break;
2820 }
d855497e
MI		 2821}
2822
2823
7d12e780 2824static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 2825{
2826 struct pvr2_hdw *hdw = urb->context;
2827 hdw->ctl_write_pend_flag = 0;
2828 if (hdw->ctl_read_pend_flag) return;
2829 complete(&hdw->ctl_done);
2830}
2831
2832
7d12e780 2833static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 2834{
2835 struct pvr2_hdw *hdw = urb->context;
2836 hdw->ctl_read_pend_flag = 0;
2837 if (hdw->ctl_write_pend_flag) return;
2838 complete(&hdw->ctl_done);
2839}
2840
2841
2842static void pvr2_ctl_timeout(unsigned long data)
2843{
2844 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2845 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2846 hdw->ctl_timeout_flag = !0;
5e55d2ce 2847 if (hdw->ctl_write_pend_flag)
d855497e 2848 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 2849 if (hdw->ctl_read_pend_flag)
d855497e 2850 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 2851 }
2852}
2853
2854
e61b6fc5
MI		 2855/* Issue a command and get a response from the device. This extended
2856 version includes a probe flag (which if set means that device errors
2857 should not be logged or treated as fatal) and a timeout in jiffies.
2858 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 2859static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2860 unsigned int timeout,int probe_fl,
2861 void *write_data,unsigned int write_len,
2862 void *read_data,unsigned int read_len)
d855497e
MI		 2863{
2864 unsigned int idx;
2865 int status = 0;
2866 struct timer_list timer;
2867 if (!hdw->ctl_lock_held) {
2868 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2869 "Attempted to execute control transfer"
2870 " without lock!!");
2871 return -EDEADLK;
2872 }
681c7399 2873 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 2874 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2875 "Attempted to execute control transfer"
2876 " when device not ok");
2877 return -EIO;
2878 }
2879 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2880 if (!probe_fl) {
2881 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2882 "Attempted to execute control transfer"
2883 " when USB is disconnected");
2884 }
2885 return -ENOTTY;
2886 }
2887
2888 /* Ensure that we have sane parameters */
2889 if (!write_data) write_len = 0;
2890 if (!read_data) read_len = 0;
2891 if (write_len > PVR2_CTL_BUFFSIZE) {
2892 pvr2_trace(
2893 PVR2_TRACE_ERROR_LEGS,
2894 "Attempted to execute %d byte"
2895 " control-write transfer (limit=%d)",
2896 write_len,PVR2_CTL_BUFFSIZE);
2897 return -EINVAL;
2898 }
2899 if (read_len > PVR2_CTL_BUFFSIZE) {
2900 pvr2_trace(
2901 PVR2_TRACE_ERROR_LEGS,
2902 "Attempted to execute %d byte"
2903 " control-read transfer (limit=%d)",
2904 write_len,PVR2_CTL_BUFFSIZE);
2905 return -EINVAL;
2906 }
2907 if ((!write_len) && (!read_len)) {
2908 pvr2_trace(
2909 PVR2_TRACE_ERROR_LEGS,
2910 "Attempted to execute null control transfer?");
2911 return -EINVAL;
2912 }
2913
2914
2915 hdw->cmd_debug_state = 1;
2916 if (write_len) {
2917 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2918 } else {
2919 hdw->cmd_debug_code = 0;
2920 }
2921 hdw->cmd_debug_write_len = write_len;
2922 hdw->cmd_debug_read_len = read_len;
2923
2924 /* Initialize common stuff */
2925 init_completion(&hdw->ctl_done);
2926 hdw->ctl_timeout_flag = 0;
2927 hdw->ctl_write_pend_flag = 0;
2928 hdw->ctl_read_pend_flag = 0;
2929 init_timer(&timer);
2930 timer.expires = jiffies + timeout;
2931 timer.data = (unsigned long)hdw;
2932 timer.function = pvr2_ctl_timeout;
2933
2934 if (write_len) {
2935 hdw->cmd_debug_state = 2;
2936 /* Transfer write data to internal buffer */
2937 for (idx = 0; idx < write_len; idx++) {
2938 hdw->ctl_write_buffer[idx] =
2939 ((unsigned char *)write_data)[idx];
2940 }
2941 /* Initiate a write request */
2942 usb_fill_bulk_urb(hdw->ctl_write_urb,
2943 hdw->usb_dev,
2944 usb_sndbulkpipe(hdw->usb_dev,
2945 PVR2_CTL_WRITE_ENDPOINT),
2946 hdw->ctl_write_buffer,
2947 write_len,
2948 pvr2_ctl_write_complete,
2949 hdw);
2950 hdw->ctl_write_urb->actual_length = 0;
2951 hdw->ctl_write_pend_flag = !0;
2952 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2953 if (status < 0) {
2954 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2955 "Failed to submit write-control"
2956 " URB status=%d",status);
2957 hdw->ctl_write_pend_flag = 0;
2958 goto done;
2959 }
2960 }
2961
2962 if (read_len) {
2963 hdw->cmd_debug_state = 3;
2964 memset(hdw->ctl_read_buffer,0x43,read_len);
2965 /* Initiate a read request */
2966 usb_fill_bulk_urb(hdw->ctl_read_urb,
2967 hdw->usb_dev,
2968 usb_rcvbulkpipe(hdw->usb_dev,
2969 PVR2_CTL_READ_ENDPOINT),
2970 hdw->ctl_read_buffer,
2971 read_len,
2972 pvr2_ctl_read_complete,
2973 hdw);
2974 hdw->ctl_read_urb->actual_length = 0;
2975 hdw->ctl_read_pend_flag = !0;
2976 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2977 if (status < 0) {
2978 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2979 "Failed to submit read-control"
2980 " URB status=%d",status);
2981 hdw->ctl_read_pend_flag = 0;
2982 goto done;
2983 }
2984 }
2985
2986 /* Start timer */
2987 add_timer(&timer);
2988
2989 /* Now wait for all I/O to complete */
2990 hdw->cmd_debug_state = 4;
2991 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2992 wait_for_completion(&hdw->ctl_done);
2993 }
2994 hdw->cmd_debug_state = 5;
2995
2996 /* Stop timer */
2997 del_timer_sync(&timer);
2998
2999 hdw->cmd_debug_state = 6;
3000 status = 0;
3001
3002 if (hdw->ctl_timeout_flag) {
3003 status = -ETIMEDOUT;
3004 if (!probe_fl) {
3005 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3006 "Timed out control-write");
3007 }
3008 goto done;
3009 }
3010
3011 if (write_len) {
3012 /* Validate results of write request */
3013 if ((hdw->ctl_write_urb->status != 0) &&
3014 (hdw->ctl_write_urb->status != -ENOENT) &&
3015 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3016 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3017 /* USB subsystem is reporting some kind of failure
3018 on the write */
3019 status = hdw->ctl_write_urb->status;
3020 if (!probe_fl) {
3021 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3022 "control-write URB failure,"
3023 " status=%d",
3024 status);
3025 }
3026 goto done;
3027 }
3028 if (hdw->ctl_write_urb->actual_length < write_len) {
3029 /* Failed to write enough data */
3030 status = -EIO;
3031 if (!probe_fl) {
3032 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3033 "control-write URB short,"
3034 " expected=%d got=%d",
3035 write_len,
3036 hdw->ctl_write_urb->actual_length);
3037 }
3038 goto done;
3039 }
3040 }
3041 if (read_len) {
3042 /* Validate results of read request */
3043 if ((hdw->ctl_read_urb->status != 0) &&
3044 (hdw->ctl_read_urb->status != -ENOENT) &&
3045 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3046 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3047 /* USB subsystem is reporting some kind of failure
3048 on the read */
3049 status = hdw->ctl_read_urb->status;
3050 if (!probe_fl) {
3051 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3052 "control-read URB failure,"
3053 " status=%d",
3054 status);
3055 }
3056 goto done;
3057 }
3058 if (hdw->ctl_read_urb->actual_length < read_len) {
3059 /* Failed to read enough data */
3060 status = -EIO;
3061 if (!probe_fl) {
3062 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3063 "control-read URB short,"
3064 " expected=%d got=%d",
3065 read_len,
3066 hdw->ctl_read_urb->actual_length);
3067 }
3068 goto done;
3069 }
3070 /* Transfer retrieved data out from internal buffer */
3071 for (idx = 0; idx < read_len; idx++) {
3072 ((unsigned char *)read_data)[idx] =
3073 hdw->ctl_read_buffer[idx];
3074 }
3075 }
3076
3077 done:
3078
3079 hdw->cmd_debug_state = 0;
3080 if ((status < 0) && (!probe_fl)) {
681c7399 3081 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3082 }
3083 return status;
3084}
3085
3086
3087int pvr2_send_request(struct pvr2_hdw *hdw,
3088 void *write_data,unsigned int write_len,
3089 void *read_data,unsigned int read_len)
3090{
3091 return pvr2_send_request_ex(hdw,HZ*4,0,
3092 write_data,write_len,
3093 read_data,read_len);
3094}
3095
3096int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3097{
3098 int ret;
3099
3100 LOCK_TAKE(hdw->ctl_lock);
3101
8d364363 3102 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 3103 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3104 hdw->cmd_buffer[5] = 0;
3105 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3106 hdw->cmd_buffer[7] = reg & 0xff;
3107
3108
3109 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3110
3111 LOCK_GIVE(hdw->ctl_lock);
3112
3113 return ret;
3114}
3115
3116
07e337ee 3117static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 3118{
3119 int ret = 0;
3120
3121 LOCK_TAKE(hdw->ctl_lock);
3122
8d364363 3123 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 3124 hdw->cmd_buffer[1] = 0;
3125 hdw->cmd_buffer[2] = 0;
3126 hdw->cmd_buffer[3] = 0;
3127 hdw->cmd_buffer[4] = 0;
3128 hdw->cmd_buffer[5] = 0;
3129 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3130 hdw->cmd_buffer[7] = reg & 0xff;
3131
3132 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3133 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3134
3135 LOCK_GIVE(hdw->ctl_lock);
3136
3137 return ret;
3138}
3139
3140
681c7399 3141void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 3142{
3143 if (!hdw->flag_ok) return;
681c7399
MI		 3144 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3145 "Device being rendered inoperable");
d855497e 3146 if (hdw->vid_stream) {
a0fd1cb1 3147 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 3148 }
681c7399
MI		 3149 hdw->flag_ok = 0;
3150 trace_stbit("flag_ok",hdw->flag_ok);
3151 pvr2_hdw_state_sched(hdw);
d855497e
MI		 3152}
3153
3154
3155void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3156{
3157 int ret;
3158 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 3159 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
d855497e
MI		 3160 if (ret == 1) {
3161 ret = usb_reset_device(hdw->usb_dev);
3162 usb_unlock_device(hdw->usb_dev);
3163 } else {
3164 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3165 "Failed to lock USB device ret=%d",ret);
3166 }
3167 if (init_pause_msec) {
3168 pvr2_trace(PVR2_TRACE_INFO,
3169 "Waiting %u msec for hardware to settle",
3170 init_pause_msec);
3171 msleep(init_pause_msec);
3172 }
3173
3174}
3175
3176
3177void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3178{
3179 char da[1];
3180 unsigned int pipe;
3181 int ret;
3182
3183 if (!hdw->usb_dev) return;
3184
3185 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3186
3187 da[0] = val ? 0x01 : 0x00;
3188
3189 /* Write the CPUCS register on the 8051. The lsb of the register
3190 is the reset bit; a 1 asserts reset while a 0 clears it. */
3191 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3192 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3193 if (ret < 0) {
3194 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3195 "cpureset_assert(%d) error=%d",val,ret);
3196 pvr2_hdw_render_useless(hdw);
3197 }
3198}
3199
3200
3201int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3202{
3203 int status;
3204 LOCK_TAKE(hdw->ctl_lock); do {
3205 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
8d364363 3206 hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET;
a0fd1cb1 3207 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e
MI		 3208 } while (0); LOCK_GIVE(hdw->ctl_lock);
3209 return status;
3210}
3211
3212
e1edb19a 3213static int pvr2_hdw_cmd_power_ctrl(struct pvr2_hdw *hdw, int onoff)
d855497e
MI		 3214{
3215 int status;
3216 LOCK_TAKE(hdw->ctl_lock); do {
e1edb19a
MK		 3217 if (onoff) {
3218 pvr2_trace(PVR2_TRACE_INIT, "Requesting powerup");
3219 hdw->cmd_buffer[0] = FX2CMD_POWER_ON;
3220 } else {
3221 pvr2_trace(PVR2_TRACE_INIT, "Requesting powerdown");
3222 hdw->cmd_buffer[0] = FX2CMD_POWER_OFF;
3223 }
3224 status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0);
d855497e
MI		 3225 } while (0); LOCK_GIVE(hdw->ctl_lock);
3226 return status;
3227}
3228
e1edb19a
MK		 3229int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3230{
3231 return pvr2_hdw_cmd_power_ctrl(hdw, 1);
3232}
3233
3234int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3235{
3236 return pvr2_hdw_cmd_power_ctrl(hdw, 0);
3237}
3238
d855497e
MI		 3239
3240int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3241{
3242 if (!hdw->decoder_ctrl) {
3243 pvr2_trace(PVR2_TRACE_INIT,
3244 "Unable to reset decoder: nothing attached");
3245 return -ENOTTY;
3246 }
3247
3248 if (!hdw->decoder_ctrl->force_reset) {
3249 pvr2_trace(PVR2_TRACE_INIT,
3250 "Unable to reset decoder: not implemented");
3251 return -ENOTTY;
3252 }
3253
3254 pvr2_trace(PVR2_TRACE_INIT,
3255 "Requesting decoder reset");
3256 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3257 return 0;
3258}
3259
3260
62433e31 3261static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d
MI		 3262{
3263 int status;
3264
3265 LOCK_TAKE(hdw->ctl_lock); do {
62433e31
MI		 3266 pvr2_trace(PVR2_TRACE_INIT,
3267 "Issuing fe demod wake command (%s)",
3268 (onoff ? "on" : "off"));
84147f3d
MI		 3269 hdw->flag_ok = !0;
3270 hdw->cmd_buffer[0] = FX2CMD_HCW_DEMOD_RESETIN;
3271 hdw->cmd_buffer[1] = onoff;
3272 status = pvr2_send_request(hdw, hdw->cmd_buffer, 2, NULL, 0);
3273 } while (0); LOCK_GIVE(hdw->ctl_lock);
3274
3275 return status;
3276}
3277
84147f3d 3278
62433e31 3279static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d
MI		 3280{
3281 int status;
3282
3283 LOCK_TAKE(hdw->ctl_lock); do {
62433e31
MI		 3284 pvr2_trace(PVR2_TRACE_INIT,
3285 "Issuing fe power command to CPLD (%s)",
3286 (onoff ? "on" : "off"));
84147f3d
MI		 3287 hdw->flag_ok = !0;
3288 hdw->cmd_buffer[0] =
3289 (onoff ? FX2CMD_ONAIR_DTV_POWER_ON :
3290 FX2CMD_ONAIR_DTV_POWER_OFF);
3291 status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0);
3292 } while (0); LOCK_GIVE(hdw->ctl_lock);
3293
3294 return status;
3295}
3296
62433e31
MI		 3297
3298static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
3299 int onoff)
84147f3d
MI		 3300{
3301 int status;
3302 LOCK_TAKE(hdw->ctl_lock); do {
62433e31
MI		 3303 pvr2_trace(PVR2_TRACE_INIT,
3304 "Issuing onair digital setup command (%s)",
3305 (onoff ? "on" : "off"));
84147f3d
MI		 3306 hdw->cmd_buffer[0] =
3307 (onoff ? FX2CMD_ONAIR_DTV_STREAMING_ON :
3308 FX2CMD_ONAIR_DTV_STREAMING_OFF);
3309 status = pvr2_send_request(hdw, hdw->cmd_buffer, 1, NULL, 0);
3310 } while (0); LOCK_GIVE(hdw->ctl_lock);
3311 return status;
3312}
3313
62433e31
MI		 3314
3315static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
3316{
3317 int cmode;
3318 /* Compare digital/analog desired setting with current setting. If
3319 they don't match, fix it... */
3320 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
3321 if (cmode == hdw->pathway_state) {
3322 /* They match; nothing to do */
3323 return;
3324 }
3325
3326 switch (hdw->hdw_desc->digital_control_scheme) {
3327 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3328 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
3329 if (cmode == PVR2_PATHWAY_ANALOG) {
3330 /* If moving to analog mode, also force the decoder
3331 to reset. If no decoder is attached, then it's
3332 ok to ignore this because if/when the decoder
3333 attaches, it will reset itself at that time. */
3334 pvr2_hdw_cmd_decoder_reset(hdw);
3335 }
3336 break;
3337 case PVR2_DIGITAL_SCHEME_ONAIR:
3338 /* Supposedly we should always have the power on whether in
3339 digital or analog mode. But for now do what appears to
3340 work... */
3341 if (digitalFl) pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,!0);
3342 pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,digitalFl);
3343 if (!digitalFl) pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,0);
3344 break;
3345 default: break;
3346 }
3347
1b9c18c5 3348 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 3349 hdw->pathway_state = cmode;
3350}
3351
3352
40381cb0 3353void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 3354{
3355 /* change some GPIO data
3356 *
3357 * note: bit d7 of dir appears to control the LED,
3358 * so we shut it off here.
3359 *
c55a97d7 3360 */
40381cb0 3361 if (onoff) {
c55a97d7 3362 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 3363 } else {
c55a97d7 3364 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 3365 }
c55a97d7 3366 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 3367}
c55a97d7 3368
40381cb0
MI		 3369
3370typedef void (*led_method_func)(struct pvr2_hdw *,int);
3371
3372static led_method_func led_methods[] = {
3373 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
3374};
3375
3376
3377/* Toggle LED */
3378static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
3379{
3380 unsigned int scheme_id;
3381 led_method_func fp;
3382
3383 if ((!onoff) == (!hdw->led_on)) return;
3384
3385 hdw->led_on = onoff != 0;
3386
3387 scheme_id = hdw->hdw_desc->led_scheme;
3388 if (scheme_id < ARRAY_SIZE(led_methods)) {
3389 fp = led_methods[scheme_id];
3390 } else {
3391 fp = NULL;
3392 }
3393
3394 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 3395}
3396
3397
e61b6fc5 3398/* Stop / start video stream transport */
07e337ee 3399static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 3400{
62433e31
MI		 3401 int status,cc;
3402 if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
98e184d9
MI		 3403 (hdw->hdw_desc->digital_control_scheme ==
3404 PVR2_DIGITAL_SCHEME_HAUPPAUGE)) {
62433e31
MI		 3405 cc = (runFl ?
3406 FX2CMD_HCW_DTV_STREAMING_ON :
3407 FX2CMD_HCW_DTV_STREAMING_OFF);
3408 } else {
3409 cc = (runFl ?
3410 FX2CMD_STREAMING_ON :
3411 FX2CMD_STREAMING_OFF);
3412 }
3413
d855497e 3414 LOCK_TAKE(hdw->ctl_lock); do {
62433e31 3415 hdw->cmd_buffer[0] = cc;
a0fd1cb1 3416 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
d855497e 3417 } while (0); LOCK_GIVE(hdw->ctl_lock);
d855497e
MI		 3418 return status;
3419}
3420
3421
62433e31
MI		 3422/* Evaluate whether or not state_pathway_ok can change */
3423static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
3424{
3425 if (hdw->state_pathway_ok) {
3426 /* Nothing to do if pathway is already ok */
3427 return 0;
3428 }
3429 if (!hdw->state_pipeline_idle) {
3430 /* Not allowed to change anything if pipeline is not idle */
3431 return 0;
3432 }
3433 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
3434 hdw->state_pathway_ok = !0;
e9db1ff2 3435 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3436 return !0;
3437}
3438
3439
681c7399
MI		 3440/* Evaluate whether or not state_encoder_ok can change */
3441static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3442{
3443 if (hdw->state_encoder_ok) return 0;
3444 if (hdw->flag_tripped) return 0;
3445 if (hdw->state_encoder_run) return 0;
3446 if (hdw->state_encoder_config) return 0;
3447 if (hdw->state_decoder_run) return 0;
3448 if (hdw->state_usbstream_run) return 0;
62433e31 3449 if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) return 0;
681c7399
MI		 3450 if (pvr2_upload_firmware2(hdw) < 0) {
3451 hdw->flag_tripped = !0;
3452 trace_stbit("flag_tripped",hdw->flag_tripped);
3453 return !0;
3454 }
3455 hdw->state_encoder_ok = !0;
3456 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3457 return !0;
3458}
3459
3460
3461/* Evaluate whether or not state_encoder_config can change */
3462static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3463{
3464 if (hdw->state_encoder_config) {
3465 if (hdw->state_encoder_ok) {
3466 if (hdw->state_pipeline_req &&
3467 !hdw->state_pipeline_pause) return 0;
3468 }
3469 hdw->state_encoder_config = 0;
3470 hdw->state_encoder_waitok = 0;
3471 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3472 /* paranoia - solve race if timer just completed */
3473 del_timer_sync(&hdw->encoder_wait_timer);
3474 } else {
62433e31
MI		 3475 if (!hdw->state_pathway_ok ||
3476 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3477 !hdw->state_encoder_ok ||
681c7399
MI		 3478 !hdw->state_pipeline_idle ||
3479 hdw->state_pipeline_pause ||
3480 !hdw->state_pipeline_req ||
3481 !hdw->state_pipeline_config) {
3482 /* We must reset the enforced wait interval if
3483 anything has happened that might have disturbed
3484 the encoder. This should be a rare case. */
3485 if (timer_pending(&hdw->encoder_wait_timer)) {
3486 del_timer_sync(&hdw->encoder_wait_timer);
3487 }
3488 if (hdw->state_encoder_waitok) {
3489 /* Must clear the state - therefore we did
3490 something to a state bit and must also
3491 return true. */
3492 hdw->state_encoder_waitok = 0;
3493 trace_stbit("state_encoder_waitok",
3494 hdw->state_encoder_waitok);
3495 return !0;
3496 }
3497 return 0;
3498 }
3499 if (!hdw->state_encoder_waitok) {
3500 if (!timer_pending(&hdw->encoder_wait_timer)) {
3501 /* waitok flag wasn't set and timer isn't
3502 running. Check flag once more to avoid
3503 a race then start the timer. This is
3504 the point when we measure out a minimal
3505 quiet interval before doing something to
3506 the encoder. */
3507 if (!hdw->state_encoder_waitok) {
3508 hdw->encoder_wait_timer.expires =
3509 jiffies + (HZ*50/1000);
3510 add_timer(&hdw->encoder_wait_timer);
3511 }
3512 }
3513 /* We can't continue until we know we have been
3514 quiet for the interval measured by this
3515 timer. */
3516 return 0;
3517 }
3518 pvr2_encoder_configure(hdw);
3519 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3520 }
3521 trace_stbit("state_encoder_config",hdw->state_encoder_config);
3522 return !0;
3523}
3524
3525
3526/* Evaluate whether or not state_encoder_run can change */
3527static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3528{
3529 if (hdw->state_encoder_run) {
3530 if (hdw->state_encoder_ok) {
62433e31
MI		 3531 if (hdw->state_decoder_run &&
3532 hdw->state_pathway_ok) return 0;
681c7399
MI		 3533 if (pvr2_encoder_stop(hdw) < 0) return !0;
3534 }
3535 hdw->state_encoder_run = 0;
3536 } else {
3537 if (!hdw->state_encoder_ok) return 0;
3538 if (!hdw->state_decoder_run) return 0;
62433e31
MI		 3539 if (!hdw->state_pathway_ok) return 0;
3540 if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) return 0;
681c7399
MI		 3541 if (pvr2_encoder_start(hdw) < 0) return !0;
3542 hdw->state_encoder_run = !0;
3543 }
3544 trace_stbit("state_encoder_run",hdw->state_encoder_run);
3545 return !0;
3546}
3547
3548
3549/* Timeout function for quiescent timer. */
3550static void pvr2_hdw_quiescent_timeout(unsigned long data)
3551{
3552 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3553 hdw->state_decoder_quiescent = !0;
3554 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3555 hdw->state_stale = !0;
3556 queue_work(hdw->workqueue,&hdw->workpoll);
3557}
3558
3559
3560/* Timeout function for encoder wait timer. */
3561static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3562{
3563 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3564 hdw->state_encoder_waitok = !0;
3565 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3566 hdw->state_stale = !0;
3567 queue_work(hdw->workqueue,&hdw->workpoll);
3568}
3569
3570
3571/* Evaluate whether or not state_decoder_run can change */
3572static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3573{
3574 if (hdw->state_decoder_run) {
3575 if (hdw->state_encoder_ok) {
3576 if (hdw->state_pipeline_req &&
62433e31
MI		 3577 !hdw->state_pipeline_pause &&
3578 hdw->state_pathway_ok) return 0;
681c7399
MI		 3579 }
3580 if (!hdw->flag_decoder_missed) {
3581 pvr2_decoder_enable(hdw,0);
3582 }
3583 hdw->state_decoder_quiescent = 0;
3584 hdw->state_decoder_run = 0;
3585 /* paranoia - solve race if timer just completed */
3586 del_timer_sync(&hdw->quiescent_timer);
3587 } else {
3588 if (!hdw->state_decoder_quiescent) {
3589 if (!timer_pending(&hdw->quiescent_timer)) {
3590 /* We don't do something about the
3591 quiescent timer until right here because
3592 we also want to catch cases where the
3593 decoder was already not running (like
3594 after initialization) as opposed to
3595 knowing that we had just stopped it.
3596 The second flag check is here to cover a
3597 race - the timer could have run and set
3598 this flag just after the previous check
3599 but before we did the pending check. */
3600 if (!hdw->state_decoder_quiescent) {
3601 hdw->quiescent_timer.expires =
3602 jiffies + (HZ*50/1000);
3603 add_timer(&hdw->quiescent_timer);
3604 }
3605 }
3606 /* Don't allow decoder to start again until it has
3607 been quiesced first. This little detail should
3608 hopefully further stabilize the encoder. */
3609 return 0;
3610 }
62433e31
MI		 3611 if (!hdw->state_pathway_ok ||
3612 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3613 !hdw->state_pipeline_req ||
681c7399
MI		 3614 hdw->state_pipeline_pause ||
3615 !hdw->state_pipeline_config ||
3616 !hdw->state_encoder_config ||
3617 !hdw->state_encoder_ok) return 0;
3618 del_timer_sync(&hdw->quiescent_timer);
3619 if (hdw->flag_decoder_missed) return 0;
3620 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3621 hdw->state_decoder_quiescent = 0;
3622 hdw->state_decoder_run = !0;
3623 }
3624 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3625 trace_stbit("state_decoder_run",hdw->state_decoder_run);
3626 return !0;
3627}
3628
3629
3630/* Evaluate whether or not state_usbstream_run can change */
3631static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3632{
3633 if (hdw->state_usbstream_run) {
62433e31
MI		 3634 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3635 if (hdw->state_encoder_ok &&
3636 hdw->state_encoder_run &&
3637 hdw->state_pathway_ok) return 0;
3638 } else {
3639 if (hdw->state_pipeline_req &&
3640 !hdw->state_pipeline_pause &&
3641 hdw->state_pathway_ok) return 0;
681c7399
MI		 3642 }
3643 pvr2_hdw_cmd_usbstream(hdw,0);
3644 hdw->state_usbstream_run = 0;
3645 } else {
62433e31
MI		 3646 if (!hdw->state_pipeline_req ||
3647 hdw->state_pipeline_pause ||
3648 !hdw->state_pathway_ok) return 0;
3649 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3650 if (!hdw->state_encoder_ok ||
3651 !hdw->state_encoder_run) return 0;
3652 }
681c7399
MI		 3653 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3654 hdw->state_usbstream_run = !0;
3655 }
3656 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3657 return !0;
3658}
3659
3660
3661/* Attempt to configure pipeline, if needed */
3662static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3663{
3664 if (hdw->state_pipeline_config ||
3665 hdw->state_pipeline_pause) return 0;
3666 pvr2_hdw_commit_execute(hdw);
3667 return !0;
3668}
3669
3670
3671/* Update pipeline idle and pipeline pause tracking states based on other
3672 inputs. This must be called whenever the other relevant inputs have
3673 changed. */
3674static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3675{
3676 unsigned int st;
3677 int updatedFl = 0;
3678 /* Update pipeline state */
3679 st = !(hdw->state_encoder_run ||
3680 hdw->state_decoder_run ||
3681 hdw->state_usbstream_run ||
3682 (!hdw->state_decoder_quiescent));
3683 if (!st != !hdw->state_pipeline_idle) {
3684 hdw->state_pipeline_idle = st;
3685 updatedFl = !0;
3686 }
3687 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3688 hdw->state_pipeline_pause = 0;
3689 updatedFl = !0;
3690 }
3691 return updatedFl;
3692}
3693
3694
3695typedef int (*state_eval_func)(struct pvr2_hdw *);
3696
3697/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 3698static const state_eval_func eval_funcs[] = {
62433e31 3699 state_eval_pathway_ok,
681c7399
MI		 3700 state_eval_pipeline_config,
3701 state_eval_encoder_ok,
3702 state_eval_encoder_config,
3703 state_eval_decoder_run,
3704 state_eval_encoder_run,
3705 state_eval_usbstream_run,
3706};
3707
3708
3709/* Process various states and return true if we did anything interesting. */
3710static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3711{
3712 unsigned int i;
3713 int state_updated = 0;
3714 int check_flag;
3715
3716 if (!hdw->state_stale) return 0;
3717 if ((hdw->fw1_state != FW1_STATE_OK) ||
3718 !hdw->flag_ok) {
3719 hdw->state_stale = 0;
3720 return !0;
3721 }
3722 /* This loop is the heart of the entire driver. It keeps trying to
3723 evaluate various bits of driver state until nothing changes for
3724 one full iteration. Each "bit of state" tracks some global
3725 aspect of the driver, e.g. whether decoder should run, if
3726 pipeline is configured, usb streaming is on, etc. We separately
3727 evaluate each of those questions based on other driver state to
3728 arrive at the correct running configuration. */
3729 do {
3730 check_flag = 0;
3731 state_update_pipeline_state(hdw);
3732 /* Iterate over each bit of state */
3733 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3734 if ((*eval_funcs[i])(hdw)) {
3735 check_flag = !0;
3736 state_updated = !0;
3737 state_update_pipeline_state(hdw);
3738 }
3739 }
3740 } while (check_flag && hdw->flag_ok);
3741 hdw->state_stale = 0;
3742 trace_stbit("state_stale",hdw->state_stale);
3743 return state_updated;
3744}
3745
3746
62433e31
MI		 3747static const char *pvr2_pathway_state_name(int id)
3748{
3749 switch (id) {
3750 case PVR2_PATHWAY_ANALOG: return "analog";
3751 case PVR2_PATHWAY_DIGITAL: return "digital";
3752 default: return "unknown";
3753 }
3754}
3755
3756
681c7399
MI		 3757static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
3758 char *buf,unsigned int acnt)
3759{
3760 switch (which) {
3761 case 0:
3762 return scnprintf(
3763 buf,acnt,
e9db1ff2 3764 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 3765 (hdw->flag_ok ? " <ok>" : " <fail>"),
3766 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
3767 (hdw->flag_disconnected ? " <disconnected>" :
3768 " <connected>"),
3769 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 3770 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
3771 pvr2_pathway_state_name(hdw->pathway_state));
3772
681c7399
MI		 3773 case 1:
3774 return scnprintf(
3775 buf,acnt,
3776 "pipeline:%s%s%s%s",
3777 (hdw->state_pipeline_idle ? " <idle>" : ""),
3778 (hdw->state_pipeline_config ?
3779 " <configok>" : " <stale>"),
3780 (hdw->state_pipeline_req ? " <req>" : ""),
3781 (hdw->state_pipeline_pause ? " <pause>" : ""));
3782 case 2:
3783 return scnprintf(
3784 buf,acnt,
62433e31 3785 "worker:%s%s%s%s%s%s%s",
681c7399
MI		 3786 (hdw->state_decoder_run ?
3787 " <decode:run>" :
3788 (hdw->state_decoder_quiescent ?
3789 "" : " <decode:stop>")),
3790 (hdw->state_decoder_quiescent ?
3791 " <decode:quiescent>" : ""),
3792 (hdw->state_encoder_ok ?
3793 "" : " <encode:init>"),
3794 (hdw->state_encoder_run ?
3795 " <encode:run>" : " <encode:stop>"),
3796 (hdw->state_encoder_config ?
3797 " <encode:configok>" :
3798 (hdw->state_encoder_waitok ?
b9a37d91 3799 "" : " <encode:waitok>")),
681c7399 3800 (hdw->state_usbstream_run ?
62433e31
MI		 3801 " <usb:run>" : " <usb:stop>"),
3802 (hdw->state_pathway_ok ?
e9db1ff2 3803 " <pathway:ok>" : ""));
681c7399
MI		 3804 case 3:
3805 return scnprintf(
3806 buf,acnt,
3807 "state: %s",
3808 pvr2_get_state_name(hdw->master_state));
ad0992e9
MI		 3809 case 4: {
3810 struct pvr2_stream_stats stats;
3811 if (!hdw->vid_stream) break;
3812 pvr2_stream_get_stats(hdw->vid_stream,
3813 &stats,
3814 0);
3815 return scnprintf(
3816 buf,acnt,
3817 "Bytes streamed=%u"
3818 " URBs: queued=%u idle=%u ready=%u"
3819 " processed=%u failed=%u",
3820 stats.bytes_processed,
3821 stats.buffers_in_queue,
3822 stats.buffers_in_idle,
3823 stats.buffers_in_ready,
3824 stats.buffers_processed,
3825 stats.buffers_failed);
3826 }
681c7399
MI		 3827 default: break;
3828 }
3829 return 0;
3830}
3831
3832
3833unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
3834 char *buf,unsigned int acnt)
3835{
3836 unsigned int bcnt,ccnt,idx;
3837 bcnt = 0;
3838 LOCK_TAKE(hdw->big_lock);
3839 for (idx = 0; ; idx++) {
3840 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
3841 if (!ccnt) break;
3842 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3843 if (!acnt) break;
3844 buf[0] = '\n'; ccnt = 1;
3845 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3846 }
3847 LOCK_GIVE(hdw->big_lock);
3848 return bcnt;
3849}
3850
3851
3852static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
3853{
3854 char buf[128];
3855 unsigned int idx,ccnt;
3856
3857 for (idx = 0; ; idx++) {
3858 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
3859 if (!ccnt) break;
3860 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
3861 }
3862}
3863
3864
3865/* Evaluate and update the driver's current state, taking various actions
3866 as appropriate for the update. */
3867static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
3868{
3869 unsigned int st;
3870 int state_updated = 0;
3871 int callback_flag = 0;
1b9c18c5 3872 int analog_mode;
681c7399
MI		 3873
3874 pvr2_trace(PVR2_TRACE_STBITS,
3875 "Drive state check START");
3876 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3877 pvr2_hdw_state_log_state(hdw);
3878 }
3879
3880 /* Process all state and get back over disposition */
3881 state_updated = pvr2_hdw_state_update(hdw);
3882
1b9c18c5
MI		 3883 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
3884
681c7399
MI		 3885 /* Update master state based upon all other states. */
3886 if (!hdw->flag_ok) {
3887 st = PVR2_STATE_DEAD;
3888 } else if (hdw->fw1_state != FW1_STATE_OK) {
3889 st = PVR2_STATE_COLD;
1b9c18c5 3890 } else if (analog_mode && !hdw->state_encoder_ok) {
681c7399 3891 st = PVR2_STATE_WARM;
1b9c18c5
MI		 3892 } else if (hdw->flag_tripped ||
3893 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 3894 st = PVR2_STATE_ERROR;
62433e31 3895 } else if (hdw->state_usbstream_run &&
1b9c18c5 3896 (!analog_mode ||
62433e31 3897 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 3898 st = PVR2_STATE_RUN;
3899 } else {
3900 st = PVR2_STATE_READY;
3901 }
3902 if (hdw->master_state != st) {
3903 pvr2_trace(PVR2_TRACE_STATE,
3904 "Device state change from %s to %s",
3905 pvr2_get_state_name(hdw->master_state),
3906 pvr2_get_state_name(st));
40381cb0 3907 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 3908 hdw->master_state = st;
3909 state_updated = !0;
3910 callback_flag = !0;
3911 }
3912 if (state_updated) {
3913 /* Trigger anyone waiting on any state changes here. */
3914 wake_up(&hdw->state_wait_data);
3915 }
3916
3917 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3918 pvr2_hdw_state_log_state(hdw);
3919 }
3920 pvr2_trace(PVR2_TRACE_STBITS,
3921 "Drive state check DONE callback=%d",callback_flag);
3922
3923 return callback_flag;
3924}
3925
3926
3927/* Cause kernel thread to check / update driver state */
3928static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
3929{
3930 if (hdw->state_stale) return;
3931 hdw->state_stale = !0;
3932 trace_stbit("state_stale",hdw->state_stale);
3933 queue_work(hdw->workqueue,&hdw->workpoll);
3934}
3935
3936
3937void pvr2_hdw_get_debug_info_unlocked(const struct pvr2_hdw *hdw,
3938 struct pvr2_hdw_debug_info *ptr)
d855497e
MI		 3939{
3940 ptr->big_lock_held = hdw->big_lock_held;
3941 ptr->ctl_lock_held = hdw->ctl_lock_held;
d855497e
MI		 3942 ptr->flag_disconnected = hdw->flag_disconnected;
3943 ptr->flag_init_ok = hdw->flag_init_ok;
681c7399
MI		 3944 ptr->flag_ok = hdw->flag_ok;
3945 ptr->fw1_state = hdw->fw1_state;
3946 ptr->flag_decoder_missed = hdw->flag_decoder_missed;
3947 ptr->flag_tripped = hdw->flag_tripped;
3948 ptr->state_encoder_ok = hdw->state_encoder_ok;
3949 ptr->state_encoder_run = hdw->state_encoder_run;
3950 ptr->state_decoder_run = hdw->state_decoder_run;
3951 ptr->state_usbstream_run = hdw->state_usbstream_run;
3952 ptr->state_decoder_quiescent = hdw->state_decoder_quiescent;
3953 ptr->state_pipeline_config = hdw->state_pipeline_config;
3954 ptr->state_pipeline_req = hdw->state_pipeline_req;
3955 ptr->state_pipeline_pause = hdw->state_pipeline_pause;
3956 ptr->state_pipeline_idle = hdw->state_pipeline_idle;
d855497e
MI		 3957 ptr->cmd_debug_state = hdw->cmd_debug_state;
3958 ptr->cmd_code = hdw->cmd_debug_code;
3959 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3960 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3961 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3962 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3963 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3964 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3965 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3966}
3967
3968
681c7399
MI		 3969void pvr2_hdw_get_debug_info_locked(struct pvr2_hdw *hdw,
3970 struct pvr2_hdw_debug_info *ptr)
3971{
3972 LOCK_TAKE(hdw->ctl_lock); do {
3973 pvr2_hdw_get_debug_info_unlocked(hdw,ptr);
3974 } while(0); LOCK_GIVE(hdw->ctl_lock);
3975}
3976
3977
d855497e
MI		 3978int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3979{
3980 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3981}
3982
3983
3984int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3985{
3986 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3987}
3988
3989
3990int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3991{
3992 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3993}
3994
3995
3996int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3997{
3998 u32 cval,nval;
3999 int ret;
4000 if (~msk) {
4001 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4002 if (ret) return ret;
4003 nval = (cval & ~msk) | (val & msk);
4004 pvr2_trace(PVR2_TRACE_GPIO,
4005 "GPIO direction changing 0x%x:0x%x"
4006 " from 0x%x to 0x%x",
4007 msk,val,cval,nval);
4008 } else {
4009 nval = val;
4010 pvr2_trace(PVR2_TRACE_GPIO,
4011 "GPIO direction changing to 0x%x",nval);
4012 }
4013 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4014}
4015
4016
4017int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4018{
4019 u32 cval,nval;
4020 int ret;
4021 if (~msk) {
4022 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4023 if (ret) return ret;
4024 nval = (cval & ~msk) | (val & msk);
4025 pvr2_trace(PVR2_TRACE_GPIO,
4026 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4027 msk,val,cval,nval);
4028 } else {
4029 nval = val;
4030 pvr2_trace(PVR2_TRACE_GPIO,
4031 "GPIO output changing to 0x%x",nval);
4032 }
4033 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4034}
4035
4036
7fb20fa3
MI		 4037unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4038{
4039 return hdw->input_avail_mask;
4040}
4041
4042
e61b6fc5 4043/* Find I2C address of eeprom */
07e337ee 4044static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 4045{
4046 int result;
4047 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 4048 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 4049 result = pvr2_send_request(hdw,
4050 hdw->cmd_buffer,1,
4051 hdw->cmd_buffer,1);
4052 if (result < 0) break;
4053 result = hdw->cmd_buffer[0];
4054 } while(0); LOCK_GIVE(hdw->ctl_lock);
4055 return result;
4056}
4057
4058
32ffa9ae 4059int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
f3d092b8
HV		 4060 u32 match_type, u32 match_chip, u64 reg_id,
4061 int setFl,u64 *val_ptr)
32ffa9ae
MI		 4062{
4063#ifdef CONFIG_VIDEO_ADV_DEBUG
32ffa9ae
MI		 4064 struct pvr2_i2c_client *cp;
4065 struct v4l2_register req;
6d98816f
MI		 4066 int stat = 0;
4067 int okFl = 0;
32ffa9ae 4068
201f5c9c
MI		 4069 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
4070
f3d092b8
HV		 4071 req.match_type = match_type;
4072 req.match_chip = match_chip;
32ffa9ae
MI		 4073 req.reg = reg_id;
4074 if (setFl) req.val = *val_ptr;
4075 mutex_lock(&hdw->i2c_list_lock); do {
e77e2c2f 4076 list_for_each_entry(cp, &hdw->i2c_clients, list) {
8481a750
MI		 4077 if (!v4l2_chip_match_i2c_client(
4078 cp->client,
4079 req.match_type, req.match_chip)) {
f3d092b8
HV		 4080 continue;
4081 }
32ffa9ae 4082 stat = pvr2_i2c_client_cmd(
52ebc763
TP		 4083 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
4084 VIDIOC_DBG_G_REGISTER),&req);
32ffa9ae 4085 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 4086 okFl = !0;
4087 break;
32ffa9ae
MI		 4088 }
4089 } while (0); mutex_unlock(&hdw->i2c_list_lock);
6d98816f
MI		 4090 if (okFl) {
4091 return stat;
4092 }
32ffa9ae
MI		 4093 return -EINVAL;
4094#else
4095 return -ENOSYS;
4096#endif
4097}
4098
4099
d855497e
MI		 4100/*
4101 Stuff for Emacs to see, in order to encourage consistent editing style:
4102 *** Local Variables: ***
4103 *** mode: c ***
4104 *** fill-column: 75 ***
4105 *** tab-width: 8 ***
4106 *** c-basic-offset: 8 ***
4107 *** End: ***
4108 */
Clone of davem's net-next-2.6 tree