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Merge branch 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...
[net-next-2.6.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
CommitLineData
d855497e
MI		 1/*
2 *
d855497e
MI		 3 *
4 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21#include <linux/errno.h>
22#include <linux/string.h>
23#include <linux/slab.h>
24#include <linux/firmware.h>
d855497e 25#include <linux/videodev2.h>
32ffa9ae 26#include <media/v4l2-common.h>
75212a02 27#include <media/tuner.h>
d855497e
MI		 28#include "pvrusb2.h"
29#include "pvrusb2-std.h"
30#include "pvrusb2-util.h"
31#include "pvrusb2-hdw.h"
32#include "pvrusb2-i2c-core.h"
d855497e
MI		 33#include "pvrusb2-eeprom.h"
34#include "pvrusb2-hdw-internal.h"
35#include "pvrusb2-encoder.h"
36#include "pvrusb2-debug.h"
8d364363 37#include "pvrusb2-fx2-cmd.h"
5f6dae80 38#include "pvrusb2-wm8775.h"
6f956512 39#include "pvrusb2-video-v4l.h"
634ba268 40#include "pvrusb2-cx2584x-v4l.h"
2a6b627f 41#include "pvrusb2-cs53l32a.h"
76891d65 42#include "pvrusb2-audio.h"
d855497e 43
1bde0289
MI		 44#define TV_MIN_FREQ 55250000L
45#define TV_MAX_FREQ 850000000L
25d8527a 46
83ce57aa
MI		 47/* This defines a minimum interval that the decoder must remain quiet
48 before we are allowed to start it running. */
49#define TIME_MSEC_DECODER_WAIT 50
50
6e931375
MI		 51/* This defines a minimum interval that the decoder must be allowed to run
52 before we can safely begin using its streaming output. */
53#define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
54
83ce57aa 55/* This defines a minimum interval that the encoder must remain quiet
91b5b489
MI		 56 before we are allowed to configure it. */
57#define TIME_MSEC_ENCODER_WAIT 50
83ce57aa
MI		 58
59/* This defines the minimum interval that the encoder must successfully run
60 before we consider that the encoder has run at least once since its
61 firmware has been loaded. This measurement is in important for cases
62 where we can't do something until we know that the encoder has been run
63 at least once. */
64#define TIME_MSEC_ENCODER_OK 250
65
a0fd1cb1 66static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
8df0c87c 67static DEFINE_MUTEX(pvr2_unit_mtx);
d855497e 68
ff699e6b 69static int ctlchg;
ff699e6b 70static int procreload;
d855497e
MI		 71static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
72static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
73static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
ff699e6b 74static int init_pause_msec;
d855497e
MI		 75
76module_param(ctlchg, int, S_IRUGO|S_IWUSR);
77MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
78module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
79MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
d855497e
MI		 80module_param(procreload, int, S_IRUGO|S_IWUSR);
81MODULE_PARM_DESC(procreload,
82 "Attempt init failure recovery with firmware reload");
83module_param_array(tuner, int, NULL, 0444);
84MODULE_PARM_DESC(tuner,"specify installed tuner type");
85module_param_array(video_std, int, NULL, 0444);
86MODULE_PARM_DESC(video_std,"specify initial video standard");
87module_param_array(tolerance, int, NULL, 0444);
88MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
89
6f441ed7
MI		 90/* US Broadcast channel 3 (61.25 MHz), to help with testing */
91static int default_tv_freq = 61250000L;
5a4f5da6
MK		 92/* 104.3 MHz, a usable FM station for my area */
93static int default_radio_freq = 104300000L;
94
95module_param_named(tv_freq, default_tv_freq, int, 0444);
96MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
97module_param_named(radio_freq, default_radio_freq, int, 0444);
98MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
99
d855497e
MI		 100#define PVR2_CTL_WRITE_ENDPOINT 0x01
101#define PVR2_CTL_READ_ENDPOINT 0x81
102
103#define PVR2_GPIO_IN 0x9008
104#define PVR2_GPIO_OUT 0x900c
105#define PVR2_GPIO_DIR 0x9020
106
107#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
108
109#define PVR2_FIRMWARE_ENDPOINT 0x02
110
111/* size of a firmware chunk */
112#define FIRMWARE_CHUNK_SIZE 0x2000
113
edb9dcb8
MI		 114typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
115 struct v4l2_subdev *);
116
117static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
4ecbc28d 118 [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
6f956512 119 [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
76891d65 120 [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
634ba268 121 [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
2a6b627f 122 [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
edb9dcb8
MI		 123};
124
e9c64a78
MI		 125static const char *module_names[] = {
126 [PVR2_CLIENT_ID_MSP3400] = "msp3400",
127 [PVR2_CLIENT_ID_CX25840] = "cx25840",
128 [PVR2_CLIENT_ID_SAA7115] = "saa7115",
129 [PVR2_CLIENT_ID_TUNER] = "tuner",
bb65242a 130 [PVR2_CLIENT_ID_DEMOD] = "tuner",
851981a1 131 [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
5f6dae80 132 [PVR2_CLIENT_ID_WM8775] = "wm8775",
e9c64a78
MI		 133};
134
135
136static const unsigned char *module_i2c_addresses[] = {
137 [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
bb65242a 138 [PVR2_CLIENT_ID_DEMOD] = "\x43",
1dfe6c77
MI		 139 [PVR2_CLIENT_ID_MSP3400] = "\x40",
140 [PVR2_CLIENT_ID_SAA7115] = "\x21",
ae111f76 141 [PVR2_CLIENT_ID_WM8775] = "\x1b",
0b467014 142 [PVR2_CLIENT_ID_CX25840] = "\x44",
23334a22 143 [PVR2_CLIENT_ID_CS53L32A] = "\x11",
e9c64a78
MI		 144};
145
146
27eab384
MI		 147static const char *ir_scheme_names[] = {
148 [PVR2_IR_SCHEME_NONE] = "none",
149 [PVR2_IR_SCHEME_29XXX] = "29xxx",
150 [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
151 [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
152 [PVR2_IR_SCHEME_ZILOG] = "Zilog",
153};
154
155
b30d2441
MI		 156/* Define the list of additional controls we'll dynamically construct based
157 on query of the cx2341x module. */
158struct pvr2_mpeg_ids {
159 const char *strid;
160 int id;
161};
162static const struct pvr2_mpeg_ids mpeg_ids[] = {
163 {
164 .strid = "audio_layer",
165 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
166 },{
167 .strid = "audio_bitrate",
168 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
169 },{
170 /* Already using audio_mode elsewhere :-( */
171 .strid = "mpeg_audio_mode",
172 .id = V4L2_CID_MPEG_AUDIO_MODE,
173 },{
174 .strid = "mpeg_audio_mode_extension",
175 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
176 },{
177 .strid = "audio_emphasis",
178 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
179 },{
180 .strid = "audio_crc",
181 .id = V4L2_CID_MPEG_AUDIO_CRC,
182 },{
183 .strid = "video_aspect",
184 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
185 },{
186 .strid = "video_b_frames",
187 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
188 },{
189 .strid = "video_gop_size",
190 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
191 },{
192 .strid = "video_gop_closure",
193 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
b30d2441
MI		 194 },{
195 .strid = "video_bitrate_mode",
196 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
197 },{
198 .strid = "video_bitrate",
199 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
200 },{
201 .strid = "video_bitrate_peak",
202 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
203 },{
204 .strid = "video_temporal_decimation",
205 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
206 },{
207 .strid = "stream_type",
208 .id = V4L2_CID_MPEG_STREAM_TYPE,
209 },{
210 .strid = "video_spatial_filter_mode",
211 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
212 },{
213 .strid = "video_spatial_filter",
214 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
215 },{
216 .strid = "video_luma_spatial_filter_type",
217 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
218 },{
219 .strid = "video_chroma_spatial_filter_type",
220 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
221 },{
222 .strid = "video_temporal_filter_mode",
223 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
224 },{
225 .strid = "video_temporal_filter",
226 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
227 },{
228 .strid = "video_median_filter_type",
229 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
230 },{
231 .strid = "video_luma_median_filter_top",
232 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
233 },{
234 .strid = "video_luma_median_filter_bottom",
235 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
236 },{
237 .strid = "video_chroma_median_filter_top",
238 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
239 },{
240 .strid = "video_chroma_median_filter_bottom",
241 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
242 }
243};
eca8ebfc 244#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
c05c0462 245
434449f4 246
d855497e 247static const char *control_values_srate[] = {
434449f4
MI		 248 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
249 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
250 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
d855497e
MI		 251};
252
253
d855497e 254
d855497e
MI		 255static const char *control_values_input[] = {
256 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
29bf5b1d 257 [PVR2_CVAL_INPUT_DTV] = "dtv",
d855497e
MI		 258 [PVR2_CVAL_INPUT_RADIO] = "radio",
259 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
260 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
261};
262
263
264static const char *control_values_audiomode[] = {
265 [V4L2_TUNER_MODE_MONO] = "Mono",
266 [V4L2_TUNER_MODE_STEREO] = "Stereo",
267 [V4L2_TUNER_MODE_LANG1] = "Lang1",
268 [V4L2_TUNER_MODE_LANG2] = "Lang2",
269 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
270};
271
272
273static const char *control_values_hsm[] = {
274 [PVR2_CVAL_HSM_FAIL] = "Fail",
275 [PVR2_CVAL_HSM_HIGH] = "High",
276 [PVR2_CVAL_HSM_FULL] = "Full",
277};
278
279
681c7399
MI		 280static const char *pvr2_state_names[] = {
281 [PVR2_STATE_NONE] = "none",
282 [PVR2_STATE_DEAD] = "dead",
283 [PVR2_STATE_COLD] = "cold",
284 [PVR2_STATE_WARM] = "warm",
285 [PVR2_STATE_ERROR] = "error",
286 [PVR2_STATE_READY] = "ready",
287 [PVR2_STATE_RUN] = "run",
d855497e
MI		 288};
289
681c7399 290
694dca2b 291struct pvr2_fx2cmd_descdef {
1c9d10d4
MI		 292 unsigned char id;
293 unsigned char *desc;
294};
295
694dca2b 296static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
1c9d10d4
MI		 297 {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
298 {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
31335b13 299 {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
1c9d10d4
MI		 300 {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
301 {FX2CMD_REG_WRITE, "write encoder register"},
302 {FX2CMD_REG_READ, "read encoder register"},
303 {FX2CMD_MEMSEL, "encoder memsel"},
304 {FX2CMD_I2C_WRITE, "i2c write"},
305 {FX2CMD_I2C_READ, "i2c read"},
306 {FX2CMD_GET_USB_SPEED, "get USB speed"},
307 {FX2CMD_STREAMING_ON, "stream on"},
308 {FX2CMD_STREAMING_OFF, "stream off"},
309 {FX2CMD_FWPOST1, "fwpost1"},
310 {FX2CMD_POWER_OFF, "power off"},
311 {FX2CMD_POWER_ON, "power on"},
312 {FX2CMD_DEEP_RESET, "deep reset"},
313 {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
314 {FX2CMD_GET_IR_CODE, "get IR code"},
315 {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
316 {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
317 {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
318 {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
319 {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
320 {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
321 {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
322};
323
324
1cb03b76 325static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
681c7399
MI		 326static void pvr2_hdw_state_sched(struct pvr2_hdw *);
327static int pvr2_hdw_state_eval(struct pvr2_hdw *);
1bde0289 328static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
681c7399 329static void pvr2_hdw_worker_poll(struct work_struct *work);
681c7399
MI		 330static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
331static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
332static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
07e337ee 333static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
681c7399 334static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
07e337ee 335static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
07e337ee
AB		 336static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
337static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
681c7399 338static void pvr2_hdw_quiescent_timeout(unsigned long);
6e931375 339static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
681c7399 340static void pvr2_hdw_encoder_wait_timeout(unsigned long);
d913d630 341static void pvr2_hdw_encoder_run_timeout(unsigned long);
1c9d10d4 342static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
07e337ee
AB		 343static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
344 unsigned int timeout,int probe_fl,
345 void *write_data,unsigned int write_len,
346 void *read_data,unsigned int read_len);
432907f7 347static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
d855497e 348
681c7399
MI		 349
350static void trace_stbit(const char *name,int val)
351{
352 pvr2_trace(PVR2_TRACE_STBITS,
353 "State bit %s <-- %s",
354 name,(val ? "true" : "false"));
355}
356
d855497e
MI		 357static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
358{
359 struct pvr2_hdw *hdw = cptr->hdw;
360 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
361 *vp = hdw->freqTable[hdw->freqProgSlot-1];
362 } else {
363 *vp = 0;
364 }
365 return 0;
366}
367
368static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
369{
370 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 371 unsigned int slotId = hdw->freqProgSlot;
372 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
373 hdw->freqTable[slotId-1] = v;
374 /* Handle side effects correctly - if we're tuned to this
375 slot, then forgot the slot id relation since the stored
376 frequency has been changed. */
377 if (hdw->freqSelector) {
378 if (hdw->freqSlotRadio == slotId) {
379 hdw->freqSlotRadio = 0;
380 }
381 } else {
382 if (hdw->freqSlotTelevision == slotId) {
383 hdw->freqSlotTelevision = 0;
384 }
385 }
d855497e
MI		 386 }
387 return 0;
388}
389
390static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
391{
392 *vp = cptr->hdw->freqProgSlot;
393 return 0;
394}
395
396static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
397{
398 struct pvr2_hdw *hdw = cptr->hdw;
399 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
400 hdw->freqProgSlot = v;
401 }
402 return 0;
403}
404
405static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
406{
1bde0289
MI		 407 struct pvr2_hdw *hdw = cptr->hdw;
408 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
d855497e
MI		 409 return 0;
410}
411
1bde0289 412static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
d855497e
MI		 413{
414 unsigned freq = 0;
415 struct pvr2_hdw *hdw = cptr->hdw;
1bde0289
MI		 416 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
417 if (slotId > 0) {
418 freq = hdw->freqTable[slotId-1];
419 if (!freq) return 0;
420 pvr2_hdw_set_cur_freq(hdw,freq);
d855497e 421 }
1bde0289
MI		 422 if (hdw->freqSelector) {
423 hdw->freqSlotRadio = slotId;
424 } else {
425 hdw->freqSlotTelevision = slotId;
d855497e
MI		 426 }
427 return 0;
428}
429
430static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
431{
1bde0289 432 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
d855497e
MI		 433 return 0;
434}
435
436static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
437{
438 return cptr->hdw->freqDirty != 0;
439}
440
441static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
442{
443 cptr->hdw->freqDirty = 0;
444}
445
446static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
447{
1bde0289 448 pvr2_hdw_set_cur_freq(cptr->hdw,v);
d855497e
MI		 449 return 0;
450}
451
e784bfb9 452static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
453{
432907f7
MI		 454 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
455 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
456 if (stat != 0) {
432907f7 457 return stat;
e784bfb9 458 }
432907f7 459 *left = cap->bounds.left;
e784bfb9 460 return 0;
461}
462
463static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
464{
432907f7
MI		 465 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
466 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
467 if (stat != 0) {
432907f7
MI		 468 return stat;
469 }
470 *left = cap->bounds.left;
471 if (cap->bounds.width > cptr->hdw->cropw_val) {
432907f7 472 *left += cap->bounds.width - cptr->hdw->cropw_val;
e784bfb9 473 }
474 return 0;
475}
476
477static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
478{
432907f7
MI		 479 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
480 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
481 if (stat != 0) {
432907f7 482 return stat;
e784bfb9 483 }
432907f7 484 *top = cap->bounds.top;
e784bfb9 485 return 0;
486}
487
432907f7 488static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
3ad9fc37 489{
432907f7
MI		 490 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
491 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
492 if (stat != 0) {
432907f7
MI		 493 return stat;
494 }
495 *top = cap->bounds.top;
496 if (cap->bounds.height > cptr->hdw->croph_val) {
432907f7 497 *top += cap->bounds.height - cptr->hdw->croph_val;
3ad9fc37
MI		 498 }
499 return 0;
500}
501
432907f7
MI		 502static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
503{
504 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
505 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
506 if (stat != 0) {
432907f7
MI		 507 return stat;
508 }
509 *val = 0;
510 if (cap->bounds.width > cptr->hdw->cropl_val) {
432907f7
MI		 511 *val = cap->bounds.width - cptr->hdw->cropl_val;
512 }
513 return 0;
514}
515
516static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
517{
518 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
519 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
520 if (stat != 0) {
432907f7
MI		 521 return stat;
522 }
523 *val = 0;
524 if (cap->bounds.height > cptr->hdw->cropt_val) {
432907f7
MI		 525 *val = cap->bounds.height - cptr->hdw->cropt_val;
526 }
527 return 0;
528}
529
530static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
531{
532 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
533 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
534 if (stat != 0) {
432907f7
MI		 535 return stat;
536 }
537 *val = cap->bounds.left;
538 return 0;
539}
540
541static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
542{
543 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
544 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
545 if (stat != 0) {
432907f7
MI		 546 return stat;
547 }
548 *val = cap->bounds.top;
549 return 0;
550}
551
552static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
553{
554 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
555 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
556 if (stat != 0) {
432907f7
MI		 557 return stat;
558 }
559 *val = cap->bounds.width;
560 return 0;
561}
562
563static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
564{
565 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
566 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
567 if (stat != 0) {
432907f7
MI		 568 return stat;
569 }
570 *val = cap->bounds.height;
571 return 0;
572}
573
574static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
575{
576 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
577 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
578 if (stat != 0) {
432907f7
MI		 579 return stat;
580 }
581 *val = cap->defrect.left;
582 return 0;
583}
584
585static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
586{
587 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
588 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
589 if (stat != 0) {
432907f7
MI		 590 return stat;
591 }
592 *val = cap->defrect.top;
593 return 0;
594}
595
596static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
597{
598 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
599 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
600 if (stat != 0) {
432907f7
MI		 601 return stat;
602 }
603 *val = cap->defrect.width;
604 return 0;
605}
606
607static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
608{
609 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
610 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
611 if (stat != 0) {
432907f7
MI		 612 return stat;
613 }
614 *val = cap->defrect.height;
615 return 0;
616}
617
618static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
619{
620 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
621 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
622 if (stat != 0) {
432907f7
MI		 623 return stat;
624 }
625 *val = cap->pixelaspect.numerator;
626 return 0;
627}
628
629static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
630{
631 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
632 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
633 if (stat != 0) {
432907f7
MI		 634 return stat;
635 }
636 *val = cap->pixelaspect.denominator;
637 return 0;
638}
639
640static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
e784bfb9 641{
432907f7
MI		 642 /* Actual maximum depends on the video standard in effect. */
643 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
644 *vp = 480;
e784bfb9 645 } else {
432907f7 646 *vp = 576;
e784bfb9 647 }
648 return 0;
649}
650
3ad9fc37
MI		 651static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
652{
989eb154
MI		 653 /* Actual minimum depends on device digitizer type. */
654 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
3ad9fc37
MI		 655 *vp = 75;
656 } else {
657 *vp = 17;
658 }
659 return 0;
660}
661
1bde0289 662static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
5549f54f 663{
1bde0289
MI		 664 *vp = cptr->hdw->input_val;
665 return 0;
666}
667
29bf5b1d
MI		 668static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
669{
1cb03b76 670 return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
29bf5b1d
MI		 671}
672
1bde0289
MI		 673static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
674{
1cb03b76 675 return pvr2_hdw_set_input(cptr->hdw,v);
1bde0289
MI		 676}
677
678static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
679{
680 return cptr->hdw->input_dirty != 0;
681}
682
683static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
684{
685 cptr->hdw->input_dirty = 0;
686}
687
5549f54f 688
25d8527a
PK		 689static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
690{
644afdb9
MI		 691 unsigned long fv;
692 struct pvr2_hdw *hdw = cptr->hdw;
693 if (hdw->tuner_signal_stale) {
a51f5000 694 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 695 }
696 fv = hdw->tuner_signal_info.rangehigh;
697 if (!fv) {
698 /* Safety fallback */
25d8527a 699 *vp = TV_MAX_FREQ;
644afdb9 700 return 0;
25d8527a 701 }
644afdb9
MI		 702 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
703 fv = (fv * 125) / 2;
704 } else {
705 fv = fv * 62500;
706 }
707 *vp = fv;
25d8527a
PK		 708 return 0;
709}
710
711static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
712{
644afdb9
MI		 713 unsigned long fv;
714 struct pvr2_hdw *hdw = cptr->hdw;
715 if (hdw->tuner_signal_stale) {
a51f5000 716 pvr2_hdw_status_poll(hdw);
644afdb9
MI		 717 }
718 fv = hdw->tuner_signal_info.rangelow;
719 if (!fv) {
720 /* Safety fallback */
25d8527a 721 *vp = TV_MIN_FREQ;
644afdb9
MI		 722 return 0;
723 }
724 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
725 fv = (fv * 125) / 2;
726 } else {
727 fv = fv * 62500;
25d8527a 728 }
644afdb9 729 *vp = fv;
25d8527a
PK		 730 return 0;
731}
732
b30d2441
MI		 733static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
734{
735 return cptr->hdw->enc_stale != 0;
736}
737
738static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
739{
740 cptr->hdw->enc_stale = 0;
681c7399 741 cptr->hdw->enc_unsafe_stale = 0;
b30d2441
MI		 742}
743
744static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
745{
746 int ret;
747 struct v4l2_ext_controls cs;
748 struct v4l2_ext_control c1;
749 memset(&cs,0,sizeof(cs));
750 memset(&c1,0,sizeof(c1));
751 cs.controls = &c1;
752 cs.count = 1;
753 c1.id = cptr->info->v4l_id;
01f1e44f 754 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
b30d2441
MI		 755 VIDIOC_G_EXT_CTRLS);
756 if (ret) return ret;
757 *vp = c1.value;
758 return 0;
759}
760
761static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
762{
763 int ret;
681c7399 764 struct pvr2_hdw *hdw = cptr->hdw;
b30d2441
MI		 765 struct v4l2_ext_controls cs;
766 struct v4l2_ext_control c1;
767 memset(&cs,0,sizeof(cs));
768 memset(&c1,0,sizeof(c1));
769 cs.controls = &c1;
770 cs.count = 1;
771 c1.id = cptr->info->v4l_id;
772 c1.value = v;
681c7399
MI		 773 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
774 hdw->state_encoder_run, &cs,
b30d2441 775 VIDIOC_S_EXT_CTRLS);
681c7399
MI		 776 if (ret == -EBUSY) {
777 /* Oops. cx2341x is telling us it's not safe to change
778 this control while we're capturing. Make a note of this
779 fact so that the pipeline will be stopped the next time
780 controls are committed. Then go on ahead and store this
781 change anyway. */
782 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
783 0, &cs,
784 VIDIOC_S_EXT_CTRLS);
785 if (!ret) hdw->enc_unsafe_stale = !0;
786 }
b30d2441 787 if (ret) return ret;
681c7399 788 hdw->enc_stale = !0;
b30d2441
MI		 789 return 0;
790}
791
792static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
793{
794 struct v4l2_queryctrl qctrl;
795 struct pvr2_ctl_info *info;
796 qctrl.id = cptr->info->v4l_id;
797 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
798 /* Strip out the const so we can adjust a function pointer. It's
799 OK to do this here because we know this is a dynamically created
800 control, so the underlying storage for the info pointer is (a)
801 private to us, and (b) not in read-only storage. Either we do
802 this or we significantly complicate the underlying control
803 implementation. */
804 info = (struct pvr2_ctl_info *)(cptr->info);
805 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
806 if (info->set_value) {
a0fd1cb1 807 info->set_value = NULL;
b30d2441
MI		 808 }
809 } else {
810 if (!(info->set_value)) {
811 info->set_value = ctrl_cx2341x_set;
812 }
813 }
814 return qctrl.flags;
815}
816
d855497e
MI		 817static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
818{
681c7399
MI		 819 *vp = cptr->hdw->state_pipeline_req;
820 return 0;
821}
822
823static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
824{
825 *vp = cptr->hdw->master_state;
d855497e
MI		 826 return 0;
827}
828
829static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
830{
831 int result = pvr2_hdw_is_hsm(cptr->hdw);
832 *vp = PVR2_CVAL_HSM_FULL;
833 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
834 if (result) *vp = PVR2_CVAL_HSM_HIGH;
835 return 0;
836}
837
838static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
839{
840 *vp = cptr->hdw->std_mask_avail;
841 return 0;
842}
843
844static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
845{
846 struct pvr2_hdw *hdw = cptr->hdw;
847 v4l2_std_id ns;
848 ns = hdw->std_mask_avail;
849 ns = (ns & ~m) | (v & m);
850 if (ns == hdw->std_mask_avail) return 0;
851 hdw->std_mask_avail = ns;
852 pvr2_hdw_internal_set_std_avail(hdw);
853 pvr2_hdw_internal_find_stdenum(hdw);
854 return 0;
855}
856
857static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
858 char *bufPtr,unsigned int bufSize,
859 unsigned int *len)
860{
861 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
862 return 0;
863}
864
865static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
866 const char *bufPtr,unsigned int bufSize,
867 int *mskp,int *valp)
868{
869 int ret;
870 v4l2_std_id id;
871 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
872 if (ret < 0) return ret;
873 if (mskp) *mskp = id;
874 if (valp) *valp = id;
875 return 0;
876}
877
878static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
879{
880 *vp = cptr->hdw->std_mask_cur;
881 return 0;
882}
883
884static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
885{
886 struct pvr2_hdw *hdw = cptr->hdw;
887 v4l2_std_id ns;
888 ns = hdw->std_mask_cur;
889 ns = (ns & ~m) | (v & m);
890 if (ns == hdw->std_mask_cur) return 0;
891 hdw->std_mask_cur = ns;
892 hdw->std_dirty = !0;
893 pvr2_hdw_internal_find_stdenum(hdw);
894 return 0;
895}
896
897static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
898{
899 return cptr->hdw->std_dirty != 0;
900}
901
902static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
903{
904 cptr->hdw->std_dirty = 0;
905}
906
907static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
908{
18103c57 909 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 910 pvr2_hdw_status_poll(hdw);
18103c57
MI		 911 *vp = hdw->tuner_signal_info.signal;
912 return 0;
913}
914
915static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
916{
917 int val = 0;
918 unsigned int subchan;
919 struct pvr2_hdw *hdw = cptr->hdw;
a51f5000 920 pvr2_hdw_status_poll(hdw);
18103c57
MI		 921 subchan = hdw->tuner_signal_info.rxsubchans;
922 if (subchan & V4L2_TUNER_SUB_MONO) {
923 val |= (1 << V4L2_TUNER_MODE_MONO);
924 }
925 if (subchan & V4L2_TUNER_SUB_STEREO) {
926 val |= (1 << V4L2_TUNER_MODE_STEREO);
927 }
928 if (subchan & V4L2_TUNER_SUB_LANG1) {
929 val |= (1 << V4L2_TUNER_MODE_LANG1);
930 }
931 if (subchan & V4L2_TUNER_SUB_LANG2) {
932 val |= (1 << V4L2_TUNER_MODE_LANG2);
933 }
934 *vp = val;
d855497e
MI		 935 return 0;
936}
937
d855497e
MI		 938
939static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
940{
941 struct pvr2_hdw *hdw = cptr->hdw;
942 if (v < 0) return -EINVAL;
943 if (v > hdw->std_enum_cnt) return -EINVAL;
944 hdw->std_enum_cur = v;
945 if (!v) return 0;
946 v--;
947 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
948 hdw->std_mask_cur = hdw->std_defs[v].id;
949 hdw->std_dirty = !0;
950 return 0;
951}
952
953
954static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
955{
956 *vp = cptr->hdw->std_enum_cur;
957 return 0;
958}
959
960
961static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
962{
963 return cptr->hdw->std_dirty != 0;
964}
965
966
967static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
968{
969 cptr->hdw->std_dirty = 0;
970}
971
972
973#define DEFINT(vmin,vmax) \
974 .type = pvr2_ctl_int, \
975 .def.type_int.min_value = vmin, \
976 .def.type_int.max_value = vmax
977
978#define DEFENUM(tab) \
979 .type = pvr2_ctl_enum, \
27c7b710 980 .def.type_enum.count = ARRAY_SIZE(tab), \
d855497e
MI		 981 .def.type_enum.value_names = tab
982
33213963
MI		 983#define DEFBOOL \
984 .type = pvr2_ctl_bool
985
d855497e
MI		 986#define DEFMASK(msk,tab) \
987 .type = pvr2_ctl_bitmask, \
988 .def.type_bitmask.valid_bits = msk, \
989 .def.type_bitmask.bit_names = tab
990
991#define DEFREF(vname) \
992 .set_value = ctrl_set_##vname, \
993 .get_value = ctrl_get_##vname, \
994 .is_dirty = ctrl_isdirty_##vname, \
995 .clear_dirty = ctrl_cleardirty_##vname
996
997
998#define VCREATE_FUNCS(vname) \
999static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
1000{*vp = cptr->hdw->vname##_val; return 0;} \
1001static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
1002{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1003static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1004{return cptr->hdw->vname##_dirty != 0;} \
1005static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1006{cptr->hdw->vname##_dirty = 0;}
1007
1008VCREATE_FUNCS(brightness)
1009VCREATE_FUNCS(contrast)
1010VCREATE_FUNCS(saturation)
1011VCREATE_FUNCS(hue)
1012VCREATE_FUNCS(volume)
1013VCREATE_FUNCS(balance)
1014VCREATE_FUNCS(bass)
1015VCREATE_FUNCS(treble)
1016VCREATE_FUNCS(mute)
e784bfb9 1017VCREATE_FUNCS(cropl)
1018VCREATE_FUNCS(cropt)
1019VCREATE_FUNCS(cropw)
1020VCREATE_FUNCS(croph)
c05c0462
MI		 1021VCREATE_FUNCS(audiomode)
1022VCREATE_FUNCS(res_hor)
1023VCREATE_FUNCS(res_ver)
d855497e 1024VCREATE_FUNCS(srate)
d855497e 1025
d855497e
MI		 1026/* Table definition of all controls which can be manipulated */
1027static const struct pvr2_ctl_info control_defs[] = {
1028 {
1029 .v4l_id = V4L2_CID_BRIGHTNESS,
1030 .desc = "Brightness",
1031 .name = "brightness",
1032 .default_value = 128,
1033 DEFREF(brightness),
1034 DEFINT(0,255),
1035 },{
1036 .v4l_id = V4L2_CID_CONTRAST,
1037 .desc = "Contrast",
1038 .name = "contrast",
1039 .default_value = 68,
1040 DEFREF(contrast),
1041 DEFINT(0,127),
1042 },{
1043 .v4l_id = V4L2_CID_SATURATION,
1044 .desc = "Saturation",
1045 .name = "saturation",
1046 .default_value = 64,
1047 DEFREF(saturation),
1048 DEFINT(0,127),
1049 },{
1050 .v4l_id = V4L2_CID_HUE,
1051 .desc = "Hue",
1052 .name = "hue",
1053 .default_value = 0,
1054 DEFREF(hue),
1055 DEFINT(-128,127),
1056 },{
1057 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1058 .desc = "Volume",
1059 .name = "volume",
139eecf9 1060 .default_value = 62000,
d855497e
MI		 1061 DEFREF(volume),
1062 DEFINT(0,65535),
1063 },{
1064 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1065 .desc = "Balance",
1066 .name = "balance",
1067 .default_value = 0,
1068 DEFREF(balance),
1069 DEFINT(-32768,32767),
1070 },{
1071 .v4l_id = V4L2_CID_AUDIO_BASS,
1072 .desc = "Bass",
1073 .name = "bass",
1074 .default_value = 0,
1075 DEFREF(bass),
1076 DEFINT(-32768,32767),
1077 },{
1078 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1079 .desc = "Treble",
1080 .name = "treble",
1081 .default_value = 0,
1082 DEFREF(treble),
1083 DEFINT(-32768,32767),
1084 },{
1085 .v4l_id = V4L2_CID_AUDIO_MUTE,
1086 .desc = "Mute",
1087 .name = "mute",
1088 .default_value = 0,
1089 DEFREF(mute),
33213963 1090 DEFBOOL,
e784bfb9 1091 }, {
432907f7 1092 .desc = "Capture crop left margin",
e784bfb9 1093 .name = "crop_left",
1094 .internal_id = PVR2_CID_CROPL,
1095 .default_value = 0,
1096 DEFREF(cropl),
1097 DEFINT(-129, 340),
1098 .get_min_value = ctrl_cropl_min_get,
1099 .get_max_value = ctrl_cropl_max_get,
432907f7 1100 .get_def_value = ctrl_get_cropcapdl,
e784bfb9 1101 }, {
432907f7 1102 .desc = "Capture crop top margin",
e784bfb9 1103 .name = "crop_top",
1104 .internal_id = PVR2_CID_CROPT,
1105 .default_value = 0,
1106 DEFREF(cropt),
1107 DEFINT(-35, 544),
1108 .get_min_value = ctrl_cropt_min_get,
1109 .get_max_value = ctrl_cropt_max_get,
432907f7 1110 .get_def_value = ctrl_get_cropcapdt,
e784bfb9 1111 }, {
432907f7 1112 .desc = "Capture crop width",
e784bfb9 1113 .name = "crop_width",
1114 .internal_id = PVR2_CID_CROPW,
1115 .default_value = 720,
1116 DEFREF(cropw),
432907f7
MI		 1117 .get_max_value = ctrl_cropw_max_get,
1118 .get_def_value = ctrl_get_cropcapdw,
e784bfb9 1119 }, {
432907f7 1120 .desc = "Capture crop height",
e784bfb9 1121 .name = "crop_height",
1122 .internal_id = PVR2_CID_CROPH,
1123 .default_value = 480,
1124 DEFREF(croph),
432907f7
MI		 1125 .get_max_value = ctrl_croph_max_get,
1126 .get_def_value = ctrl_get_cropcapdh,
1127 }, {
1128 .desc = "Capture capability pixel aspect numerator",
1129 .name = "cropcap_pixel_numerator",
1130 .internal_id = PVR2_CID_CROPCAPPAN,
1131 .get_value = ctrl_get_cropcappan,
1132 }, {
1133 .desc = "Capture capability pixel aspect denominator",
1134 .name = "cropcap_pixel_denominator",
1135 .internal_id = PVR2_CID_CROPCAPPAD,
1136 .get_value = ctrl_get_cropcappad,
1137 }, {
1138 .desc = "Capture capability bounds top",
1139 .name = "cropcap_bounds_top",
1140 .internal_id = PVR2_CID_CROPCAPBT,
1141 .get_value = ctrl_get_cropcapbt,
1142 }, {
1143 .desc = "Capture capability bounds left",
1144 .name = "cropcap_bounds_left",
1145 .internal_id = PVR2_CID_CROPCAPBL,
1146 .get_value = ctrl_get_cropcapbl,
1147 }, {
1148 .desc = "Capture capability bounds width",
1149 .name = "cropcap_bounds_width",
1150 .internal_id = PVR2_CID_CROPCAPBW,
1151 .get_value = ctrl_get_cropcapbw,
1152 }, {
1153 .desc = "Capture capability bounds height",
1154 .name = "cropcap_bounds_height",
1155 .internal_id = PVR2_CID_CROPCAPBH,
1156 .get_value = ctrl_get_cropcapbh,
c05c0462
MI		 1157 },{
1158 .desc = "Video Source",
1159 .name = "input",
1160 .internal_id = PVR2_CID_INPUT,
1161 .default_value = PVR2_CVAL_INPUT_TV,
29bf5b1d 1162 .check_value = ctrl_check_input,
c05c0462
MI		 1163 DEFREF(input),
1164 DEFENUM(control_values_input),
1165 },{
1166 .desc = "Audio Mode",
1167 .name = "audio_mode",
1168 .internal_id = PVR2_CID_AUDIOMODE,
1169 .default_value = V4L2_TUNER_MODE_STEREO,
1170 DEFREF(audiomode),
1171 DEFENUM(control_values_audiomode),
1172 },{
1173 .desc = "Horizontal capture resolution",
1174 .name = "resolution_hor",
1175 .internal_id = PVR2_CID_HRES,
1176 .default_value = 720,
1177 DEFREF(res_hor),
3ad9fc37 1178 DEFINT(19,720),
c05c0462
MI		 1179 },{
1180 .desc = "Vertical capture resolution",
1181 .name = "resolution_ver",
1182 .internal_id = PVR2_CID_VRES,
1183 .default_value = 480,
1184 DEFREF(res_ver),
3ad9fc37
MI		 1185 DEFINT(17,576),
1186 /* Hook in check for video standard and adjust maximum
1187 depending on the standard. */
1188 .get_max_value = ctrl_vres_max_get,
1189 .get_min_value = ctrl_vres_min_get,
d855497e 1190 },{
b30d2441 1191 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
434449f4
MI		 1192 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1193 .desc = "Audio Sampling Frequency",
d855497e 1194 .name = "srate",
d855497e
MI		 1195 DEFREF(srate),
1196 DEFENUM(control_values_srate),
d855497e
MI		 1197 },{
1198 .desc = "Tuner Frequency (Hz)",
1199 .name = "frequency",
1200 .internal_id = PVR2_CID_FREQUENCY,
1bde0289 1201 .default_value = 0,
d855497e
MI		 1202 .set_value = ctrl_freq_set,
1203 .get_value = ctrl_freq_get,
1204 .is_dirty = ctrl_freq_is_dirty,
1205 .clear_dirty = ctrl_freq_clear_dirty,
644afdb9 1206 DEFINT(0,0),
25d8527a
PK		 1207 /* Hook in check for input value (tv/radio) and adjust
1208 max/min values accordingly */
1209 .get_max_value = ctrl_freq_max_get,
1210 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1211 },{
1212 .desc = "Channel",
1213 .name = "channel",
1214 .set_value = ctrl_channel_set,
1215 .get_value = ctrl_channel_get,
1216 DEFINT(0,FREQTABLE_SIZE),
1217 },{
1218 .desc = "Channel Program Frequency",
1219 .name = "freq_table_value",
1220 .set_value = ctrl_channelfreq_set,
1221 .get_value = ctrl_channelfreq_get,
644afdb9 1222 DEFINT(0,0),
1bde0289
MI		 1223 /* Hook in check for input value (tv/radio) and adjust
1224 max/min values accordingly */
1bde0289
MI		 1225 .get_max_value = ctrl_freq_max_get,
1226 .get_min_value = ctrl_freq_min_get,
d855497e
MI		 1227 },{
1228 .desc = "Channel Program ID",
1229 .name = "freq_table_channel",
1230 .set_value = ctrl_channelprog_set,
1231 .get_value = ctrl_channelprog_get,
1232 DEFINT(0,FREQTABLE_SIZE),
d855497e
MI		 1233 },{
1234 .desc = "Streaming Enabled",
1235 .name = "streaming_enabled",
1236 .get_value = ctrl_streamingenabled_get,
33213963 1237 DEFBOOL,
d855497e
MI		 1238 },{
1239 .desc = "USB Speed",
1240 .name = "usb_speed",
1241 .get_value = ctrl_hsm_get,
1242 DEFENUM(control_values_hsm),
681c7399
MI		 1243 },{
1244 .desc = "Master State",
1245 .name = "master_state",
1246 .get_value = ctrl_masterstate_get,
1247 DEFENUM(pvr2_state_names),
d855497e
MI		 1248 },{
1249 .desc = "Signal Present",
1250 .name = "signal_present",
1251 .get_value = ctrl_signal_get,
18103c57
MI		 1252 DEFINT(0,65535),
1253 },{
1254 .desc = "Audio Modes Present",
1255 .name = "audio_modes_present",
1256 .get_value = ctrl_audio_modes_present_get,
1257 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1258 v4l. Nothing outside of this module cares about this,
1259 but I reuse it in order to also reuse the
1260 control_values_audiomode string table. */
1261 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1262 (1 << V4L2_TUNER_MODE_STEREO)|
1263 (1 << V4L2_TUNER_MODE_LANG1)|
1264 (1 << V4L2_TUNER_MODE_LANG2)),
1265 control_values_audiomode),
d855497e
MI		 1266 },{
1267 .desc = "Video Standards Available Mask",
1268 .name = "video_standard_mask_available",
1269 .internal_id = PVR2_CID_STDAVAIL,
1270 .skip_init = !0,
1271 .get_value = ctrl_stdavail_get,
1272 .set_value = ctrl_stdavail_set,
1273 .val_to_sym = ctrl_std_val_to_sym,
1274 .sym_to_val = ctrl_std_sym_to_val,
1275 .type = pvr2_ctl_bitmask,
1276 },{
1277 .desc = "Video Standards In Use Mask",
1278 .name = "video_standard_mask_active",
1279 .internal_id = PVR2_CID_STDCUR,
1280 .skip_init = !0,
1281 .get_value = ctrl_stdcur_get,
1282 .set_value = ctrl_stdcur_set,
1283 .is_dirty = ctrl_stdcur_is_dirty,
1284 .clear_dirty = ctrl_stdcur_clear_dirty,
1285 .val_to_sym = ctrl_std_val_to_sym,
1286 .sym_to_val = ctrl_std_sym_to_val,
1287 .type = pvr2_ctl_bitmask,
d855497e
MI		 1288 },{
1289 .desc = "Video Standard Name",
1290 .name = "video_standard",
1291 .internal_id = PVR2_CID_STDENUM,
1292 .skip_init = !0,
1293 .get_value = ctrl_stdenumcur_get,
1294 .set_value = ctrl_stdenumcur_set,
1295 .is_dirty = ctrl_stdenumcur_is_dirty,
1296 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1297 .type = pvr2_ctl_enum,
1298 }
1299};
1300
eca8ebfc 1301#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
d855497e
MI		 1302
1303
1304const char *pvr2_config_get_name(enum pvr2_config cfg)
1305{
1306 switch (cfg) {
1307 case pvr2_config_empty: return "empty";
1308 case pvr2_config_mpeg: return "mpeg";
1309 case pvr2_config_vbi: return "vbi";
16eb40d3
MI		 1310 case pvr2_config_pcm: return "pcm";
1311 case pvr2_config_rawvideo: return "raw video";
d855497e
MI		 1312 }
1313 return "<unknown>";
1314}
1315
1316
1317struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1318{
1319 return hdw->usb_dev;
1320}
1321
1322
1323unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1324{
1325 return hdw->serial_number;
1326}
1327
31a18547
MI		 1328
1329const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1330{
1331 return hdw->bus_info;
1332}
1333
1334
13a88797
MI		 1335const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1336{
1337 return hdw->identifier;
1338}
1339
1340
1bde0289
MI		 1341unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1342{
1343 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1344}
1345
1346/* Set the currently tuned frequency and account for all possible
1347 driver-core side effects of this action. */
f55a8712 1348static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1bde0289 1349{
7c74e57e 1350 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1bde0289
MI		 1351 if (hdw->freqSelector) {
1352 /* Swing over to radio frequency selection */
1353 hdw->freqSelector = 0;
1354 hdw->freqDirty = !0;
1355 }
1bde0289
MI		 1356 if (hdw->freqValRadio != val) {
1357 hdw->freqValRadio = val;
1358 hdw->freqSlotRadio = 0;
7c74e57e 1359 hdw->freqDirty = !0;
1bde0289 1360 }
7c74e57e 1361 } else {
1bde0289
MI		 1362 if (!(hdw->freqSelector)) {
1363 /* Swing over to television frequency selection */
1364 hdw->freqSelector = 1;
1365 hdw->freqDirty = !0;
1366 }
1bde0289
MI		 1367 if (hdw->freqValTelevision != val) {
1368 hdw->freqValTelevision = val;
1369 hdw->freqSlotTelevision = 0;
7c74e57e 1370 hdw->freqDirty = !0;
1bde0289 1371 }
1bde0289
MI		 1372 }
1373}
1374
d855497e
MI		 1375int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1376{
1377 return hdw->unit_number;
1378}
1379
1380
1381/* Attempt to locate one of the given set of files. Messages are logged
1382 appropriate to what has been found. The return value will be 0 or
1383 greater on success (it will be the index of the file name found) and
1384 fw_entry will be filled in. Otherwise a negative error is returned on
1385 failure. If the return value is -ENOENT then no viable firmware file
1386 could be located. */
1387static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1388 const struct firmware **fw_entry,
1389 const char *fwtypename,
1390 unsigned int fwcount,
1391 const char *fwnames[])
1392{
1393 unsigned int idx;
1394 int ret = -EINVAL;
1395 for (idx = 0; idx < fwcount; idx++) {
1396 ret = request_firmware(fw_entry,
1397 fwnames[idx],
1398 &hdw->usb_dev->dev);
1399 if (!ret) {
1400 trace_firmware("Located %s firmware: %s;"
1401 " uploading...",
1402 fwtypename,
1403 fwnames[idx]);
1404 return idx;
1405 }
1406 if (ret == -ENOENT) continue;
1407 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1408 "request_firmware fatal error with code=%d",ret);
1409 return ret;
1410 }
1411 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1412 "***WARNING***"
1413 " Device %s firmware"
1414 " seems to be missing.",
1415 fwtypename);
1416 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1417 "Did you install the pvrusb2 firmware files"
1418 " in their proper location?");
1419 if (fwcount == 1) {
1420 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1421 "request_firmware unable to locate %s file %s",
1422 fwtypename,fwnames[0]);
1423 } else {
1424 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1425 "request_firmware unable to locate"
1426 " one of the following %s files:",
1427 fwtypename);
1428 for (idx = 0; idx < fwcount; idx++) {
1429 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1430 "request_firmware: Failed to find %s",
1431 fwnames[idx]);
1432 }
1433 }
1434 return ret;
1435}
1436
1437
1438/*
1439 * pvr2_upload_firmware1().
1440 *
1441 * Send the 8051 firmware to the device. After the upload, arrange for
1442 * device to re-enumerate.
1443 *
1444 * NOTE : the pointer to the firmware data given by request_firmware()
1445 * is not suitable for an usb transaction.
1446 *
1447 */
07e337ee 1448static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
d855497e 1449{
a0fd1cb1 1450 const struct firmware *fw_entry = NULL;
d855497e
MI		 1451 void *fw_ptr;
1452 unsigned int pipe;
9081d901 1453 unsigned int fwsize;
d855497e
MI		 1454 int ret;
1455 u16 address;
1d643a37 1456
989eb154 1457 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37 1458 hdw->fw1_state = FW1_STATE_OK;
56dcbfa0
MI		 1459 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1460 "Connected device type defines"
1461 " no firmware to upload; ignoring firmware");
1462 return -ENOTTY;
1d643a37
MI		 1463 }
1464
d855497e
MI		 1465 hdw->fw1_state = FW1_STATE_FAILED; // default result
1466
1467 trace_firmware("pvr2_upload_firmware1");
1468
1469 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
989eb154
MI		 1470 hdw->hdw_desc->fx2_firmware.cnt,
1471 hdw->hdw_desc->fx2_firmware.lst);
d855497e
MI		 1472 if (ret < 0) {
1473 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1474 return ret;
1475 }
1476
d855497e
MI		 1477 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1478
1479 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
9081d901 1480 fwsize = fw_entry->size;
d855497e 1481
9081d901
MI		 1482 if ((fwsize != 0x2000) &&
1483 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
c21c2db4
MI		 1484 if (hdw->hdw_desc->flag_fx2_16kb) {
1485 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1486 "Wrong fx2 firmware size"
1487 " (expected 8192 or 16384, got %u)",
9081d901 1488 fwsize);
c21c2db4
MI		 1489 } else {
1490 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1491 "Wrong fx2 firmware size"
1492 " (expected 8192, got %u)",
9081d901 1493 fwsize);
c21c2db4 1494 }
d855497e
MI		 1495 release_firmware(fw_entry);
1496 return -ENOMEM;
1497 }
1498
1499 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1500 if (fw_ptr == NULL){
1501 release_firmware(fw_entry);
1502 return -ENOMEM;
1503 }
1504
1505 /* We have to hold the CPU during firmware upload. */
1506 pvr2_hdw_cpureset_assert(hdw,1);
1507
1508 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1509 chunk. */
1510
1511 ret = 0;
9081d901 1512 for (address = 0; address < fwsize; address += 0x800) {
d855497e
MI		 1513 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1514 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1515 0, fw_ptr, 0x800, HZ);
1516 }
1517
1518 trace_firmware("Upload done, releasing device's CPU");
1519
1520 /* Now release the CPU. It will disconnect and reconnect later. */
1521 pvr2_hdw_cpureset_assert(hdw,0);
1522
1523 kfree(fw_ptr);
1524 release_firmware(fw_entry);
1525
1526 trace_firmware("Upload done (%d bytes sent)",ret);
1527
75727460
GF		 1528 /* We should have written fwsize bytes */
1529 if (ret == fwsize) {
d855497e
MI		 1530 hdw->fw1_state = FW1_STATE_RELOAD;
1531 return 0;
1532 }
1533
1534 return -EIO;
1535}
1536
1537
1538/*
1539 * pvr2_upload_firmware2()
1540 *
1541 * This uploads encoder firmware on endpoint 2.
1542 *
1543 */
1544
1545int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1546{
a0fd1cb1 1547 const struct firmware *fw_entry = NULL;
d855497e 1548 void *fw_ptr;
90060d32 1549 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
d855497e
MI		 1550 int actual_length;
1551 int ret = 0;
1552 int fwidx;
1553 static const char *fw_files[] = {
1554 CX2341X_FIRM_ENC_FILENAME,
1555 };
1556
989eb154 1557 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1d643a37
MI		 1558 return 0;
1559 }
1560
d855497e
MI		 1561 trace_firmware("pvr2_upload_firmware2");
1562
1563 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
eca8ebfc 1564 ARRAY_SIZE(fw_files), fw_files);
d855497e
MI		 1565 if (ret < 0) return ret;
1566 fwidx = ret;
1567 ret = 0;
b30d2441
MI		 1568 /* Since we're about to completely reinitialize the encoder,
1569 invalidate our cached copy of its configuration state. Next
1570 time we configure the encoder, then we'll fully configure it. */
1571 hdw->enc_cur_valid = 0;
d855497e 1572
d913d630
MI		 1573 /* Encoder is about to be reset so note that as far as we're
1574 concerned now, the encoder has never been run. */
1575 del_timer_sync(&hdw->encoder_run_timer);
1576 if (hdw->state_encoder_runok) {
1577 hdw->state_encoder_runok = 0;
1578 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1579 }
1580
d855497e
MI		 1581 /* First prepare firmware loading */
1582 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1583 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1584 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1585 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1586 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1587 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1588 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1589 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1590 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1591 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1592 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1593 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1594 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1595 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1596 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1597 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1c9d10d4
MI		 1598 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1599 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1600
1601 if (ret) {
1602 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1603 "firmware2 upload prep failed, ret=%d",ret);
1604 release_firmware(fw_entry);
21684ba9 1605 goto done;
d855497e
MI		 1606 }
1607
1608 /* Now send firmware */
1609
1610 fw_len = fw_entry->size;
1611
90060d32 1612 if (fw_len % sizeof(u32)) {
d855497e
MI		 1613 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1614 "size of %s firmware"
48dc30a1 1615 " must be a multiple of %zu bytes",
90060d32 1616 fw_files[fwidx],sizeof(u32));
d855497e 1617 release_firmware(fw_entry);
21684ba9
MI		 1618 ret = -EINVAL;
1619 goto done;
d855497e
MI		 1620 }
1621
1622 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1623 if (fw_ptr == NULL){
1624 release_firmware(fw_entry);
1625 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1626 "failed to allocate memory for firmware2 upload");
21684ba9
MI		 1627 ret = -ENOMEM;
1628 goto done;
d855497e
MI		 1629 }
1630
1631 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1632
90060d32
MI		 1633 fw_done = 0;
1634 for (fw_done = 0; fw_done < fw_len;) {
1635 bcnt = fw_len - fw_done;
1636 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1637 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1638 /* Usbsnoop log shows that we must swap bytes... */
5f33df14
MI		 1639 /* Some background info: The data being swapped here is a
1640 firmware image destined for the mpeg encoder chip that
1641 lives at the other end of a USB endpoint. The encoder
1642 chip always talks in 32 bit chunks and its storage is
1643 organized into 32 bit words. However from the file
1644 system to the encoder chip everything is purely a byte
1645 stream. The firmware file's contents are always 32 bit
1646 swapped from what the encoder expects. Thus the need
1647 always exists to swap the bytes regardless of the endian
1648 type of the host processor and therefore swab32() makes
1649 the most sense. */
90060d32 1650 for (icnt = 0; icnt < bcnt/4 ; icnt++)
513edce6 1651 ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
90060d32
MI		 1652
1653 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
d855497e 1654 &actual_length, HZ);
90060d32
MI		 1655 ret |= (actual_length != bcnt);
1656 if (ret) break;
1657 fw_done += bcnt;
d855497e
MI		 1658 }
1659
1660 trace_firmware("upload of %s : %i / %i ",
1661 fw_files[fwidx],fw_done,fw_len);
1662
1663 kfree(fw_ptr);
1664 release_firmware(fw_entry);
1665
1666 if (ret) {
1667 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1668 "firmware2 upload transfer failure");
21684ba9 1669 goto done;
d855497e
MI		 1670 }
1671
1672 /* Finish upload */
1673
1674 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1675 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1c9d10d4 1676 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
d855497e
MI		 1677
1678 if (ret) {
1679 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1680 "firmware2 upload post-proc failure");
d855497e 1681 }
21684ba9
MI		 1682
1683 done:
1df59f0b
MI		 1684 if (hdw->hdw_desc->signal_routing_scheme ==
1685 PVR2_ROUTING_SCHEME_GOTVIEW) {
1686 /* Ensure that GPIO 11 is set to output for GOTVIEW
1687 hardware. */
1688 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1689 }
d855497e
MI		 1690 return ret;
1691}
1692
1693
681c7399
MI		 1694static const char *pvr2_get_state_name(unsigned int st)
1695{
1696 if (st < ARRAY_SIZE(pvr2_state_names)) {
1697 return pvr2_state_names[st];
d855497e 1698 }
681c7399 1699 return "???";
d855497e
MI		 1700}
1701
681c7399 1702static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
d855497e 1703{
af78e16b
MI		 1704 /* Even though we really only care about the video decoder chip at
1705 this point, we'll broadcast stream on/off to all sub-devices
1706 anyway, just in case somebody else wants to hear the
1707 command... */
e260508d
MI		 1708 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1709 (enablefl ? "on" : "off"));
af78e16b 1710 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
3ccc646b 1711 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
af78e16b
MI		 1712 if (hdw->decoder_client_id) {
1713 /* We get here if the encoder has been noticed. Otherwise
1714 we'll issue a warning to the user (which should
1715 normally never happen). */
1716 return 0;
1717 }
1718 if (!hdw->flag_decoder_missed) {
1719 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1720 "WARNING: No decoder present");
1721 hdw->flag_decoder_missed = !0;
1722 trace_stbit("flag_decoder_missed",
1723 hdw->flag_decoder_missed);
1724 }
1725 return -EIO;
d855497e
MI		 1726}
1727
1728
681c7399 1729int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
d855497e 1730{
681c7399 1731 return hdw->master_state;
d855497e
MI		 1732}
1733
1734
681c7399 1735static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
d855497e 1736{
681c7399
MI		 1737 if (!hdw->flag_tripped) return 0;
1738 hdw->flag_tripped = 0;
1739 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1740 "Clearing driver error statuss");
1741 return !0;
d855497e
MI		 1742}
1743
1744
681c7399 1745int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
d855497e 1746{
681c7399 1747 int fl;
d855497e 1748 LOCK_TAKE(hdw->big_lock); do {
681c7399 1749 fl = pvr2_hdw_untrip_unlocked(hdw);
d855497e 1750 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1751 if (fl) pvr2_hdw_state_sched(hdw);
1752 return 0;
d855497e
MI		 1753}
1754
1755
d855497e
MI		 1756
1757
1758int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1759{
681c7399 1760 return hdw->state_pipeline_req != 0;
d855497e
MI		 1761}
1762
1763
1764int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1765{
681c7399 1766 int ret,st;
d855497e 1767 LOCK_TAKE(hdw->big_lock); do {
681c7399
MI		 1768 pvr2_hdw_untrip_unlocked(hdw);
1769 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1770 hdw->state_pipeline_req = enable_flag != 0;
1771 pvr2_trace(PVR2_TRACE_START_STOP,
1772 "/*--TRACE_STREAM--*/ %s",
1773 enable_flag ? "enable" : "disable");
1774 }
1775 pvr2_hdw_state_sched(hdw);
d855497e 1776 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1777 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1778 if (enable_flag) {
1779 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1780 if (st != PVR2_STATE_READY) return -EIO;
1781 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1782 }
1783 }
d855497e
MI		 1784 return 0;
1785}
1786
1787
1788int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1789{
681c7399 1790 int fl;
d855497e 1791 LOCK_TAKE(hdw->big_lock);
681c7399
MI		 1792 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1793 hdw->desired_stream_type = config;
1794 hdw->state_pipeline_config = 0;
1795 trace_stbit("state_pipeline_config",
1796 hdw->state_pipeline_config);
1797 pvr2_hdw_state_sched(hdw);
1798 }
d855497e 1799 LOCK_GIVE(hdw->big_lock);
681c7399
MI		 1800 if (fl) return 0;
1801 return pvr2_hdw_wait(hdw,0);
d855497e
MI		 1802}
1803
1804
1805static int get_default_tuner_type(struct pvr2_hdw *hdw)
1806{
1807 int unit_number = hdw->unit_number;
1808 int tp = -1;
1809 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1810 tp = tuner[unit_number];
1811 }
1812 if (tp < 0) return -EINVAL;
1813 hdw->tuner_type = tp;
aaf7884d 1814 hdw->tuner_updated = !0;
d855497e
MI		 1815 return 0;
1816}
1817
1818
1819static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1820{
1821 int unit_number = hdw->unit_number;
1822 int tp = 0;
1823 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1824 tp = video_std[unit_number];
6a540254 1825 if (tp) return tp;
d855497e 1826 }
6a540254 1827 return 0;
d855497e
MI		 1828}
1829
1830
1831static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1832{
1833 int unit_number = hdw->unit_number;
1834 int tp = 0;
1835 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1836 tp = tolerance[unit_number];
1837 }
1838 return tp;
1839}
1840
1841
1842static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1843{
1844 /* Try a harmless request to fetch the eeprom's address over
1845 endpoint 1. See what happens. Only the full FX2 image can
1846 respond to this. If this probe fails then likely the FX2
1847 firmware needs be loaded. */
1848 int result;
1849 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 1850 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 1851 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1852 hdw->cmd_buffer,1,
1853 hdw->cmd_buffer,1);
1854 if (result < 0) break;
1855 } while(0); LOCK_GIVE(hdw->ctl_lock);
1856 if (result) {
1857 pvr2_trace(PVR2_TRACE_INIT,
1858 "Probe of device endpoint 1 result status %d",
1859 result);
1860 } else {
1861 pvr2_trace(PVR2_TRACE_INIT,
1862 "Probe of device endpoint 1 succeeded");
1863 }
1864 return result == 0;
1865}
1866
9f66d4ea
MI		 1867struct pvr2_std_hack {
1868 v4l2_std_id pat; /* Pattern to match */
1869 v4l2_std_id msk; /* Which bits we care about */
1870 v4l2_std_id std; /* What additional standards or default to set */
1871};
1872
1873/* This data structure labels specific combinations of standards from
1874 tveeprom that we'll try to recognize. If we recognize one, then assume
1875 a specified default standard to use. This is here because tveeprom only
1876 tells us about available standards not the intended default standard (if
1877 any) for the device in question. We guess the default based on what has
1878 been reported as available. Note that this is only for guessing a
1879 default - which can always be overridden explicitly - and if the user
1880 has otherwise named a default then that default will always be used in
1881 place of this table. */
ebff0330 1882static const struct pvr2_std_hack std_eeprom_maps[] = {
9f66d4ea
MI		 1883 { /* PAL(B/G) */
1884 .pat = V4L2_STD_B|V4L2_STD_GH,
1885 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1886 },
1887 { /* NTSC(M) */
1888 .pat = V4L2_STD_MN,
1889 .std = V4L2_STD_NTSC_M,
1890 },
1891 { /* PAL(I) */
1892 .pat = V4L2_STD_PAL_I,
1893 .std = V4L2_STD_PAL_I,
1894 },
1895 { /* SECAM(L/L') */
1896 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1897 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1898 },
1899 { /* PAL(D/D1/K) */
1900 .pat = V4L2_STD_DK,
ea2562d9 1901 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
9f66d4ea
MI		 1902 },
1903};
1904
d855497e
MI		 1905static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1906{
1907 char buf[40];
1908 unsigned int bcnt;
3d290bdb 1909 v4l2_std_id std1,std2,std3;
d855497e
MI		 1910
1911 std1 = get_default_standard(hdw);
3d290bdb 1912 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
d855497e
MI		 1913
1914 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
56585386 1915 pvr2_trace(PVR2_TRACE_STD,
56dcbfa0
MI		 1916 "Supported video standard(s) reported available"
1917 " in hardware: %.*s",
d855497e
MI		 1918 bcnt,buf);
1919
1920 hdw->std_mask_avail = hdw->std_mask_eeprom;
1921
3d290bdb 1922 std2 = (std1|std3) & ~hdw->std_mask_avail;
d855497e
MI		 1923 if (std2) {
1924 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
56585386 1925 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1926 "Expanding supported video standards"
1927 " to include: %.*s",
1928 bcnt,buf);
1929 hdw->std_mask_avail |= std2;
1930 }
1931
1932 pvr2_hdw_internal_set_std_avail(hdw);
1933
1934 if (std1) {
1935 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
56585386 1936 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1937 "Initial video standard forced to %.*s",
1938 bcnt,buf);
1939 hdw->std_mask_cur = std1;
1940 hdw->std_dirty = !0;
1941 pvr2_hdw_internal_find_stdenum(hdw);
1942 return;
1943 }
3d290bdb
MI		 1944 if (std3) {
1945 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1946 pvr2_trace(PVR2_TRACE_STD,
1947 "Initial video standard"
1948 " (determined by device type): %.*s",bcnt,buf);
1949 hdw->std_mask_cur = std3;
1950 hdw->std_dirty = !0;
1951 pvr2_hdw_internal_find_stdenum(hdw);
1952 return;
1953 }
d855497e 1954
9f66d4ea
MI		 1955 {
1956 unsigned int idx;
1957 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1958 if (std_eeprom_maps[idx].msk ?
1959 ((std_eeprom_maps[idx].pat ^
1960 hdw->std_mask_eeprom) &
1961 std_eeprom_maps[idx].msk) :
1962 (std_eeprom_maps[idx].pat !=
1963 hdw->std_mask_eeprom)) continue;
1964 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1965 std_eeprom_maps[idx].std);
56585386 1966 pvr2_trace(PVR2_TRACE_STD,
9f66d4ea
MI		 1967 "Initial video standard guessed as %.*s",
1968 bcnt,buf);
1969 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1970 hdw->std_dirty = !0;
1971 pvr2_hdw_internal_find_stdenum(hdw);
1972 return;
1973 }
1974 }
1975
d855497e
MI		 1976 if (hdw->std_enum_cnt > 1) {
1977 // Autoselect the first listed standard
1978 hdw->std_enum_cur = 1;
1979 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1980 hdw->std_dirty = !0;
56585386 1981 pvr2_trace(PVR2_TRACE_STD,
d855497e
MI		 1982 "Initial video standard auto-selected to %s",
1983 hdw->std_defs[hdw->std_enum_cur-1].name);
1984 return;
1985 }
1986
0885ba1d 1987 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
d855497e
MI		 1988 "Unable to select a viable initial video standard");
1989}
1990
1991
e9c64a78
MI		 1992static unsigned int pvr2_copy_i2c_addr_list(
1993 unsigned short *dst, const unsigned char *src,
1994 unsigned int dst_max)
1995{
3ab8d295 1996 unsigned int cnt = 0;
e9c64a78
MI		 1997 if (!src) return 0;
1998 while (src[cnt] && (cnt + 1) < dst_max) {
1999 dst[cnt] = src[cnt];
2000 cnt++;
2001 }
2002 dst[cnt] = I2C_CLIENT_END;
2003 return cnt;
2004}
2005
2006
e17d787c
MI		 2007static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
2008{
2009 /*
2010 Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
2011 for cx25840 causes that module to correctly set up its video
2012 scaling. This is really a problem in the cx25840 module itself,
2013 but we work around it here. The problem has not been seen in
2014 ivtv because there VBI is supported and set up. We don't do VBI
2015 here (at least not yet) and thus we never attempted to even set
2016 it up.
2017 */
2018 struct v4l2_format fmt;
2019 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2020 /* We're not using a cx25840 so don't enable the hack */
2021 return;
2022 }
2023
2024 pvr2_trace(PVR2_TRACE_INIT,
2025 "Module ID %u:"
2026 " Executing cx25840 VBI hack",
2027 hdw->decoder_client_id);
2028 memset(&fmt, 0, sizeof(fmt));
2029 fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2030 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
09419af3 2031 vbi, s_sliced_fmt, &fmt.fmt.sliced);
e17d787c
MI		 2032}
2033
2034
1ab5e74f
MI		 2035static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2036 const struct pvr2_device_client_desc *cd)
e9c64a78
MI		 2037{
2038 const char *fname;
2039 unsigned char mid;
2040 struct v4l2_subdev *sd;
2041 unsigned int i2ccnt;
2042 const unsigned char *p;
2043 /* Arbitrary count - max # i2c addresses we will probe */
2044 unsigned short i2caddr[25];
2045
2046 mid = cd->module_id;
2047 fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2048 if (!fname) {
2049 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2050 "Module ID %u for device %s has no name?"
2051 " The driver might have a configuration problem.",
e9c64a78
MI		 2052 mid,
2053 hdw->hdw_desc->description);
1ab5e74f 2054 return -EINVAL;
e9c64a78 2055 }
bd14d4f8
MI		 2056 pvr2_trace(PVR2_TRACE_INIT,
2057 "Module ID %u (%s) for device %s being loaded...",
2058 mid, fname,
2059 hdw->hdw_desc->description);
e9c64a78
MI		 2060
2061 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2062 ARRAY_SIZE(i2caddr));
2063 if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2064 module_i2c_addresses[mid] : NULL) != NULL)) {
2065 /* Second chance: Try default i2c address list */
2066 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2067 ARRAY_SIZE(i2caddr));
bd14d4f8
MI		 2068 if (i2ccnt) {
2069 pvr2_trace(PVR2_TRACE_INIT,
2070 "Module ID %u:"
2071 " Using default i2c address list",
2072 mid);
2073 }
e9c64a78
MI		 2074 }
2075
2076 if (!i2ccnt) {
2077 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1ab5e74f 2078 "Module ID %u (%s) for device %s:"
27108147
MI		 2079 " No i2c addresses."
2080 " The driver might have a configuration problem.",
1ab5e74f
MI		 2081 mid, fname, hdw->hdw_desc->description);
2082 return -EINVAL;
e9c64a78
MI		 2083 }
2084
e9c64a78 2085 if (i2ccnt == 1) {
bd14d4f8
MI		 2086 pvr2_trace(PVR2_TRACE_INIT,
2087 "Module ID %u:"
2088 " Setting up with specified i2c address 0x%x",
2089 mid, i2caddr[0]);
e6574f2f 2090 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
d4c03123 2091 NULL, fname,
53dacb15 2092 i2caddr[0], NULL);
e9c64a78 2093 } else {
bd14d4f8
MI		 2094 pvr2_trace(PVR2_TRACE_INIT,
2095 "Module ID %u:"
2096 " Setting up with address probe list",
2097 mid);
53dacb15 2098 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
d4c03123 2099 NULL, fname,
53dacb15 2100 0, i2caddr);
e9c64a78
MI		 2101 }
2102
446dfdc6
MI		 2103 if (!sd) {
2104 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
27108147
MI		 2105 "Module ID %u (%s) for device %s failed to load."
2106 " Possible missing sub-device kernel module or"
2107 " initialization failure within module.",
1ab5e74f
MI		 2108 mid, fname, hdw->hdw_desc->description);
2109 return -EIO;
446dfdc6
MI		 2110 }
2111
2112 /* Tag this sub-device instance with the module ID we know about.
2113 In other places we'll use that tag to determine if the instance
2114 requires special handling. */
2115 sd->grp_id = mid;
2116
bd14d4f8 2117 pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
a932f507 2118
e9c64a78 2119
00e5f736
MI		 2120 /* client-specific setup... */
2121 switch (mid) {
2122 case PVR2_CLIENT_ID_CX25840:
00e5f736
MI		 2123 case PVR2_CLIENT_ID_SAA7115:
2124 hdw->decoder_client_id = mid;
2125 break;
2126 default: break;
2127 }
1ab5e74f
MI		 2128
2129 return 0;
e9c64a78
MI		 2130}
2131
2132
2133static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2134{
2135 unsigned int idx;
2136 const struct pvr2_string_table *cm;
2137 const struct pvr2_device_client_table *ct;
1ab5e74f 2138 int okFl = !0;
e9c64a78
MI		 2139
2140 cm = &hdw->hdw_desc->client_modules;
2141 for (idx = 0; idx < cm->cnt; idx++) {
2142 request_module(cm->lst[idx]);
2143 }
2144
2145 ct = &hdw->hdw_desc->client_table;
2146 for (idx = 0; idx < ct->cnt; idx++) {
bd14d4f8 2147 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
e9c64a78 2148 }
27108147
MI		 2149 if (!okFl) {
2150 hdw->flag_modulefail = !0;
2151 pvr2_hdw_render_useless(hdw);
2152 }
e9c64a78
MI		 2153}
2154
2155
d855497e
MI		 2156static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2157{
2158 int ret;
2159 unsigned int idx;
2160 struct pvr2_ctrl *cptr;
2161 int reloadFl = 0;
989eb154 2162 if (hdw->hdw_desc->fx2_firmware.cnt) {
1d643a37
MI		 2163 if (!reloadFl) {
2164 reloadFl =
2165 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2166 == 0);
2167 if (reloadFl) {
2168 pvr2_trace(PVR2_TRACE_INIT,
2169 "USB endpoint config looks strange"
2170 "; possibly firmware needs to be"
2171 " loaded");
2172 }
d855497e 2173 }
1d643a37
MI		 2174 if (!reloadFl) {
2175 reloadFl = !pvr2_hdw_check_firmware(hdw);
2176 if (reloadFl) {
2177 pvr2_trace(PVR2_TRACE_INIT,
2178 "Check for FX2 firmware failed"
2179 "; possibly firmware needs to be"
2180 " loaded");
2181 }
d855497e 2182 }
1d643a37
MI		 2183 if (reloadFl) {
2184 if (pvr2_upload_firmware1(hdw) != 0) {
2185 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2186 "Failure uploading firmware1");
2187 }
2188 return;
d855497e 2189 }
d855497e
MI		 2190 }
2191 hdw->fw1_state = FW1_STATE_OK;
2192
d855497e
MI		 2193 if (!pvr2_hdw_dev_ok(hdw)) return;
2194
27764726
MI		 2195 hdw->force_dirty = !0;
2196
989eb154 2197 if (!hdw->hdw_desc->flag_no_powerup) {
1d643a37
MI		 2198 pvr2_hdw_cmd_powerup(hdw);
2199 if (!pvr2_hdw_dev_ok(hdw)) return;
d855497e
MI		 2200 }
2201
31335b13 2202 /* Take the IR chip out of reset, if appropriate */
27eab384 2203 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
31335b13
MI		 2204 pvr2_issue_simple_cmd(hdw,
2205 FX2CMD_HCW_ZILOG_RESET |
2206 (1 << 8) |
2207 ((0) << 16));
2208 }
2209
d855497e
MI		 2210 // This step MUST happen after the earlier powerup step.
2211 pvr2_i2c_core_init(hdw);
2212 if (!pvr2_hdw_dev_ok(hdw)) return;
2213
e9c64a78 2214 pvr2_hdw_load_modules(hdw);
1ab5e74f 2215 if (!pvr2_hdw_dev_ok(hdw)) return;
e9c64a78 2216
cc26b076 2217 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
5c6cb4e2 2218
c05c0462 2219 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e
MI		 2220 cptr = hdw->controls + idx;
2221 if (cptr->info->skip_init) continue;
2222 if (!cptr->info->set_value) continue;
2223 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2224 }
2225
e17d787c
MI		 2226 pvr2_hdw_cx25840_vbi_hack(hdw);
2227
1bde0289
MI		 2228 /* Set up special default values for the television and radio
2229 frequencies here. It's not really important what these defaults
2230 are, but I set them to something usable in the Chicago area just
2231 to make driver testing a little easier. */
2232
5a4f5da6
MK		 2233 hdw->freqValTelevision = default_tv_freq;
2234 hdw->freqValRadio = default_radio_freq;
1bde0289 2235
d855497e
MI		 2236 // Do not use pvr2_reset_ctl_endpoints() here. It is not
2237 // thread-safe against the normal pvr2_send_request() mechanism.
2238 // (We should make it thread safe).
2239
aaf7884d
MI		 2240 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2241 ret = pvr2_hdw_get_eeprom_addr(hdw);
d855497e 2242 if (!pvr2_hdw_dev_ok(hdw)) return;
aaf7884d
MI		 2243 if (ret < 0) {
2244 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2245 "Unable to determine location of eeprom,"
2246 " skipping");
2247 } else {
2248 hdw->eeprom_addr = ret;
2249 pvr2_eeprom_analyze(hdw);
2250 if (!pvr2_hdw_dev_ok(hdw)) return;
2251 }
2252 } else {
2253 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2254 hdw->tuner_updated = !0;
2255 hdw->std_mask_eeprom = V4L2_STD_ALL;
d855497e
MI		 2256 }
2257
13a88797
MI		 2258 if (hdw->serial_number) {
2259 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2260 "sn-%lu", hdw->serial_number);
2261 } else if (hdw->unit_number >= 0) {
2262 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2263 "unit-%c",
2264 hdw->unit_number + 'a');
2265 } else {
2266 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2267 "unit-??");
2268 }
2269 hdw->identifier[idx] = 0;
2270
d855497e
MI		 2271 pvr2_hdw_setup_std(hdw);
2272
2273 if (!get_default_tuner_type(hdw)) {
2274 pvr2_trace(PVR2_TRACE_INIT,
2275 "pvr2_hdw_setup: Tuner type overridden to %d",
2276 hdw->tuner_type);
2277 }
2278
d855497e
MI		 2279
2280 if (!pvr2_hdw_dev_ok(hdw)) return;
2281
1df59f0b
MI		 2282 if (hdw->hdw_desc->signal_routing_scheme ==
2283 PVR2_ROUTING_SCHEME_GOTVIEW) {
2284 /* Ensure that GPIO 11 is set to output for GOTVIEW
2285 hardware. */
2286 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2287 }
2288
681c7399 2289 pvr2_hdw_commit_setup(hdw);
d855497e
MI		 2290
2291 hdw->vid_stream = pvr2_stream_create();
2292 if (!pvr2_hdw_dev_ok(hdw)) return;
2293 pvr2_trace(PVR2_TRACE_INIT,
2294 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2295 if (hdw->vid_stream) {
2296 idx = get_default_error_tolerance(hdw);
2297 if (idx) {
2298 pvr2_trace(PVR2_TRACE_INIT,
2299 "pvr2_hdw_setup: video stream %p"
2300 " setting tolerance %u",
2301 hdw->vid_stream,idx);
2302 }
2303 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2304 PVR2_VID_ENDPOINT,idx);
2305 }
2306
2307 if (!pvr2_hdw_dev_ok(hdw)) return;
2308
d855497e 2309 hdw->flag_init_ok = !0;
681c7399
MI		 2310
2311 pvr2_hdw_state_sched(hdw);
d855497e
MI		 2312}
2313
2314
681c7399
MI		 2315/* Set up the structure and attempt to put the device into a usable state.
2316 This can be a time-consuming operation, which is why it is not done
2317 internally as part of the create() step. */
2318static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
d855497e
MI		 2319{
2320 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
681c7399 2321 do {
d855497e
MI		 2322 pvr2_hdw_setup_low(hdw);
2323 pvr2_trace(PVR2_TRACE_INIT,
2324 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
681c7399 2325 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
d855497e 2326 if (pvr2_hdw_dev_ok(hdw)) {
681c7399 2327 if (hdw->flag_init_ok) {
d855497e
MI		 2328 pvr2_trace(
2329 PVR2_TRACE_INFO,
2330 "Device initialization"
2331 " completed successfully.");
2332 break;
2333 }
2334 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2335 pvr2_trace(
2336 PVR2_TRACE_INFO,
2337 "Device microcontroller firmware"
2338 " (re)loaded; it should now reset"
2339 " and reconnect.");
2340 break;
2341 }
2342 pvr2_trace(
2343 PVR2_TRACE_ERROR_LEGS,
2344 "Device initialization was not successful.");
2345 if (hdw->fw1_state == FW1_STATE_MISSING) {
2346 pvr2_trace(
2347 PVR2_TRACE_ERROR_LEGS,
2348 "Giving up since device"
2349 " microcontroller firmware"
2350 " appears to be missing.");
2351 break;
2352 }
2353 }
27108147
MI		 2354 if (hdw->flag_modulefail) {
2355 pvr2_trace(
2356 PVR2_TRACE_ERROR_LEGS,
2357 "***WARNING*** pvrusb2 driver initialization"
2358 " failed due to the failure of one or more"
2359 " sub-device kernel modules.");
2360 pvr2_trace(
2361 PVR2_TRACE_ERROR_LEGS,
2362 "You need to resolve the failing condition"
2363 " before this driver can function. There"
2364 " should be some earlier messages giving more"
2365 " information about the problem.");
515ebf79 2366 break;
27108147 2367 }
d855497e
MI		 2368 if (procreload) {
2369 pvr2_trace(
2370 PVR2_TRACE_ERROR_LEGS,
2371 "Attempting pvrusb2 recovery by reloading"
2372 " primary firmware.");
2373 pvr2_trace(
2374 PVR2_TRACE_ERROR_LEGS,
2375 "If this works, device should disconnect"
2376 " and reconnect in a sane state.");
2377 hdw->fw1_state = FW1_STATE_UNKNOWN;
2378 pvr2_upload_firmware1(hdw);
2379 } else {
2380 pvr2_trace(
2381 PVR2_TRACE_ERROR_LEGS,
2382 "***WARNING*** pvrusb2 device hardware"
2383 " appears to be jammed"
2384 " and I can't clear it.");
2385 pvr2_trace(
2386 PVR2_TRACE_ERROR_LEGS,
2387 "You might need to power cycle"
2388 " the pvrusb2 device"
2389 " in order to recover.");
2390 }
681c7399 2391 } while (0);
d855497e 2392 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
d855497e
MI		 2393}
2394
2395
c4a8828d
MI		 2396/* Perform second stage initialization. Set callback pointer first so that
2397 we can avoid a possible initialization race (if the kernel thread runs
2398 before the callback has been set). */
794b1607
MI		 2399int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2400 void (*callback_func)(void *),
2401 void *callback_data)
c4a8828d
MI		 2402{
2403 LOCK_TAKE(hdw->big_lock); do {
97f26ff6
MI		 2404 if (hdw->flag_disconnected) {
2405 /* Handle a race here: If we're already
2406 disconnected by this point, then give up. If we
2407 get past this then we'll remain connected for
2408 the duration of initialization since the entire
2409 initialization sequence is now protected by the
2410 big_lock. */
2411 break;
2412 }
c4a8828d
MI		 2413 hdw->state_data = callback_data;
2414 hdw->state_func = callback_func;
97f26ff6 2415 pvr2_hdw_setup(hdw);
c4a8828d 2416 } while (0); LOCK_GIVE(hdw->big_lock);
794b1607 2417 return hdw->flag_init_ok;
c4a8828d
MI		 2418}
2419
2420
2421/* Create, set up, and return a structure for interacting with the
2422 underlying hardware. */
d855497e
MI		 2423struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2424 const struct usb_device_id *devid)
2425{
7fb20fa3 2426 unsigned int idx,cnt1,cnt2,m;
fe15f136 2427 struct pvr2_hdw *hdw = NULL;
d855497e
MI		 2428 int valid_std_mask;
2429 struct pvr2_ctrl *cptr;
b72b7bf5 2430 struct usb_device *usb_dev;
989eb154 2431 const struct pvr2_device_desc *hdw_desc;
d855497e 2432 __u8 ifnum;
b30d2441
MI		 2433 struct v4l2_queryctrl qctrl;
2434 struct pvr2_ctl_info *ciptr;
d855497e 2435
b72b7bf5
MI		 2436 usb_dev = interface_to_usbdev(intf);
2437
d130fa8a 2438 hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
d855497e 2439
fe15f136
MI		 2440 if (hdw_desc == NULL) {
2441 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2442 " No device description pointer,"
2443 " unable to continue.");
2444 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2445 " please contact Mike Isely <isely@pobox.com>"
2446 " to get it included in the driver\n");
2447 goto fail;
2448 }
2449
ca545f7c 2450 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
d855497e 2451 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
989eb154 2452 hdw,hdw_desc->description);
e67e376b 2453 pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
00970beb 2454 hdw_desc->description);
8fd04448
MI		 2455 if (hdw_desc->flag_is_experimental) {
2456 pvr2_trace(PVR2_TRACE_INFO, "**********");
2457 pvr2_trace(PVR2_TRACE_INFO,
2458 "WARNING: Support for this device (%s) is"
2459 " experimental.", hdw_desc->description);
2460 pvr2_trace(PVR2_TRACE_INFO,
2461 "Important functionality might not be"
2462 " entirely working.");
2463 pvr2_trace(PVR2_TRACE_INFO,
2464 "Please consider contacting the driver author to"
2465 " help with further stabilization of the driver.");
2466 pvr2_trace(PVR2_TRACE_INFO, "**********");
2467 }
d855497e 2468 if (!hdw) goto fail;
681c7399
MI		 2469
2470 init_timer(&hdw->quiescent_timer);
2471 hdw->quiescent_timer.data = (unsigned long)hdw;
2472 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2473
6e931375
MI		 2474 init_timer(&hdw->decoder_stabilization_timer);
2475 hdw->decoder_stabilization_timer.data = (unsigned long)hdw;
2476 hdw->decoder_stabilization_timer.function =
2477 pvr2_hdw_decoder_stabilization_timeout;
2478
681c7399
MI		 2479 init_timer(&hdw->encoder_wait_timer);
2480 hdw->encoder_wait_timer.data = (unsigned long)hdw;
2481 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2482
d913d630
MI		 2483 init_timer(&hdw->encoder_run_timer);
2484 hdw->encoder_run_timer.data = (unsigned long)hdw;
2485 hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2486
681c7399
MI		 2487 hdw->master_state = PVR2_STATE_DEAD;
2488
2489 init_waitqueue_head(&hdw->state_wait_data);
2490
18103c57 2491 hdw->tuner_signal_stale = !0;
b30d2441 2492 cx2341x_fill_defaults(&hdw->enc_ctl_state);
d855497e 2493
7fb20fa3
MI		 2494 /* Calculate which inputs are OK */
2495 m = 0;
2496 if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
e8f5bacf
MI		 2497 if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2498 m |= 1 << PVR2_CVAL_INPUT_DTV;
2499 }
7fb20fa3
MI		 2500 if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2501 if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2502 if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2503 hdw->input_avail_mask = m;
1cb03b76 2504 hdw->input_allowed_mask = hdw->input_avail_mask;
7fb20fa3 2505
62433e31
MI		 2506 /* If not a hybrid device, pathway_state never changes. So
2507 initialize it here to what it should forever be. */
2508 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2509 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2510 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2511 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2512 }
2513
c05c0462 2514 hdw->control_cnt = CTRLDEF_COUNT;
b30d2441 2515 hdw->control_cnt += MPEGDEF_COUNT;
ca545f7c 2516 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
d855497e
MI		 2517 GFP_KERNEL);
2518 if (!hdw->controls) goto fail;
989eb154 2519 hdw->hdw_desc = hdw_desc;
27eab384 2520 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
c05c0462
MI		 2521 for (idx = 0; idx < hdw->control_cnt; idx++) {
2522 cptr = hdw->controls + idx;
2523 cptr->hdw = hdw;
2524 }
d855497e
MI		 2525 for (idx = 0; idx < 32; idx++) {
2526 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2527 }
c05c0462 2528 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
d855497e 2529 cptr = hdw->controls + idx;
d855497e
MI		 2530 cptr->info = control_defs+idx;
2531 }
dbc40a0e
MI		 2532
2533 /* Ensure that default input choice is a valid one. */
2534 m = hdw->input_avail_mask;
2535 if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2536 if (!((1 << idx) & m)) continue;
2537 hdw->input_val = idx;
2538 break;
2539 }
2540
b30d2441 2541 /* Define and configure additional controls from cx2341x module. */
ca545f7c 2542 hdw->mpeg_ctrl_info = kzalloc(
b30d2441
MI		 2543 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2544 if (!hdw->mpeg_ctrl_info) goto fail;
b30d2441
MI		 2545 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2546 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2547 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2548 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2549 ciptr->name = mpeg_ids[idx].strid;
2550 ciptr->v4l_id = mpeg_ids[idx].id;
2551 ciptr->skip_init = !0;
2552 ciptr->get_value = ctrl_cx2341x_get;
2553 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2554 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2555 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2556 qctrl.id = ciptr->v4l_id;
2557 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2558 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2559 ciptr->set_value = ctrl_cx2341x_set;
2560 }
2561 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2562 PVR2_CTLD_INFO_DESC_SIZE);
2563 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2564 ciptr->default_value = qctrl.default_value;
2565 switch (qctrl.type) {
2566 default:
2567 case V4L2_CTRL_TYPE_INTEGER:
2568 ciptr->type = pvr2_ctl_int;
2569 ciptr->def.type_int.min_value = qctrl.minimum;
2570 ciptr->def.type_int.max_value = qctrl.maximum;
2571 break;
2572 case V4L2_CTRL_TYPE_BOOLEAN:
2573 ciptr->type = pvr2_ctl_bool;
2574 break;
2575 case V4L2_CTRL_TYPE_MENU:
2576 ciptr->type = pvr2_ctl_enum;
2577 ciptr->def.type_enum.value_names =
e0e31cdb
HV		 2578 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2579 ciptr->v4l_id);
b30d2441
MI		 2580 for (cnt1 = 0;
2581 ciptr->def.type_enum.value_names[cnt1] != NULL;
2582 cnt1++) { }
2583 ciptr->def.type_enum.count = cnt1;
2584 break;
2585 }
2586 cptr->info = ciptr;
2587 }
d855497e
MI		 2588
2589 // Initialize video standard enum dynamic control
2590 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2591 if (cptr) {
2592 memcpy(&hdw->std_info_enum,cptr->info,
2593 sizeof(hdw->std_info_enum));
2594 cptr->info = &hdw->std_info_enum;
2595
2596 }
2597 // Initialize control data regarding video standard masks
2598 valid_std_mask = pvr2_std_get_usable();
2599 for (idx = 0; idx < 32; idx++) {
2600 if (!(valid_std_mask & (1 << idx))) continue;
2601 cnt1 = pvr2_std_id_to_str(
2602 hdw->std_mask_names[idx],
2603 sizeof(hdw->std_mask_names[idx])-1,
2604 1 << idx);
2605 hdw->std_mask_names[idx][cnt1] = 0;
2606 }
2607 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2608 if (cptr) {
2609 memcpy(&hdw->std_info_avail,cptr->info,
2610 sizeof(hdw->std_info_avail));
2611 cptr->info = &hdw->std_info_avail;
2612 hdw->std_info_avail.def.type_bitmask.bit_names =
2613 hdw->std_mask_ptrs;
2614 hdw->std_info_avail.def.type_bitmask.valid_bits =
2615 valid_std_mask;
2616 }
2617 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2618 if (cptr) {
2619 memcpy(&hdw->std_info_cur,cptr->info,
2620 sizeof(hdw->std_info_cur));
2621 cptr->info = &hdw->std_info_cur;
2622 hdw->std_info_cur.def.type_bitmask.bit_names =
2623 hdw->std_mask_ptrs;
2624 hdw->std_info_avail.def.type_bitmask.valid_bits =
2625 valid_std_mask;
2626 }
2627
432907f7 2628 hdw->cropcap_stale = !0;
d855497e
MI		 2629 hdw->eeprom_addr = -1;
2630 hdw->unit_number = -1;
8079384e
MI		 2631 hdw->v4l_minor_number_video = -1;
2632 hdw->v4l_minor_number_vbi = -1;
fd5a75fe 2633 hdw->v4l_minor_number_radio = -1;
d855497e
MI		 2634 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2635 if (!hdw->ctl_write_buffer) goto fail;
2636 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2637 if (!hdw->ctl_read_buffer) goto fail;
2638 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2639 if (!hdw->ctl_write_urb) goto fail;
2640 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2641 if (!hdw->ctl_read_urb) goto fail;
2642
70ad6383 2643 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
b72b7bf5
MI		 2644 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2645 "Error registering with v4l core, giving up");
2646 goto fail;
2647 }
8df0c87c 2648 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2649 for (idx = 0; idx < PVR_NUM; idx++) {
2650 if (unit_pointers[idx]) continue;
2651 hdw->unit_number = idx;
2652 unit_pointers[idx] = hdw;
2653 break;
2654 }
8df0c87c 2655 } while (0); mutex_unlock(&pvr2_unit_mtx);
d855497e
MI		 2656
2657 cnt1 = 0;
2658 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2659 cnt1 += cnt2;
2660 if (hdw->unit_number >= 0) {
2661 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2662 ('a' + hdw->unit_number));
2663 cnt1 += cnt2;
2664 }
2665 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2666 hdw->name[cnt1] = 0;
2667
681c7399
MI		 2668 hdw->workqueue = create_singlethread_workqueue(hdw->name);
2669 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
681c7399 2670
d855497e
MI		 2671 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2672 hdw->unit_number,hdw->name);
2673
2674 hdw->tuner_type = -1;
2675 hdw->flag_ok = !0;
d855497e
MI		 2676
2677 hdw->usb_intf = intf;
b72b7bf5 2678 hdw->usb_dev = usb_dev;
d855497e 2679
87e3495c 2680 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
31a18547 2681
d855497e
MI		 2682 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2683 usb_set_interface(hdw->usb_dev,ifnum,0);
2684
2685 mutex_init(&hdw->ctl_lock_mutex);
2686 mutex_init(&hdw->big_lock_mutex);
2687
2688 return hdw;
2689 fail:
2690 if (hdw) {
681c7399 2691 del_timer_sync(&hdw->quiescent_timer);
6e931375 2692 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2693 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 2694 del_timer_sync(&hdw->encoder_wait_timer);
2695 if (hdw->workqueue) {
2696 flush_workqueue(hdw->workqueue);
2697 destroy_workqueue(hdw->workqueue);
2698 hdw->workqueue = NULL;
2699 }
5e55d2ce
MK		 2700 usb_free_urb(hdw->ctl_read_urb);
2701 usb_free_urb(hdw->ctl_write_urb);
22071a42
MK		 2702 kfree(hdw->ctl_read_buffer);
2703 kfree(hdw->ctl_write_buffer);
2704 kfree(hdw->controls);
2705 kfree(hdw->mpeg_ctrl_info);
681c7399
MI		 2706 kfree(hdw->std_defs);
2707 kfree(hdw->std_enum_names);
d855497e
MI		 2708 kfree(hdw);
2709 }
a0fd1cb1 2710 return NULL;
d855497e
MI		 2711}
2712
2713
2714/* Remove _all_ associations between this driver and the underlying USB
2715 layer. */
07e337ee 2716static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
d855497e
MI		 2717{
2718 if (hdw->flag_disconnected) return;
2719 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2720 if (hdw->ctl_read_urb) {
2721 usb_kill_urb(hdw->ctl_read_urb);
2722 usb_free_urb(hdw->ctl_read_urb);
a0fd1cb1 2723 hdw->ctl_read_urb = NULL;
d855497e
MI		 2724 }
2725 if (hdw->ctl_write_urb) {
2726 usb_kill_urb(hdw->ctl_write_urb);
2727 usb_free_urb(hdw->ctl_write_urb);
a0fd1cb1 2728 hdw->ctl_write_urb = NULL;
d855497e
MI		 2729 }
2730 if (hdw->ctl_read_buffer) {
2731 kfree(hdw->ctl_read_buffer);
a0fd1cb1 2732 hdw->ctl_read_buffer = NULL;
d855497e
MI		 2733 }
2734 if (hdw->ctl_write_buffer) {
2735 kfree(hdw->ctl_write_buffer);
a0fd1cb1 2736 hdw->ctl_write_buffer = NULL;
d855497e 2737 }
d855497e 2738 hdw->flag_disconnected = !0;
b72b7bf5
MI		 2739 /* If we don't do this, then there will be a dangling struct device
2740 reference to our disappearing device persisting inside the V4L
2741 core... */
dc070bcc 2742 v4l2_device_disconnect(&hdw->v4l2_dev);
a0fd1cb1
MI		 2743 hdw->usb_dev = NULL;
2744 hdw->usb_intf = NULL;
681c7399 2745 pvr2_hdw_render_useless(hdw);
d855497e
MI		 2746}
2747
2748
2749/* Destroy hardware interaction structure */
2750void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2751{
401c27ce 2752 if (!hdw) return;
d855497e 2753 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
681c7399
MI		 2754 if (hdw->workqueue) {
2755 flush_workqueue(hdw->workqueue);
2756 destroy_workqueue(hdw->workqueue);
2757 hdw->workqueue = NULL;
2758 }
8f59100a 2759 del_timer_sync(&hdw->quiescent_timer);
6e931375 2760 del_timer_sync(&hdw->decoder_stabilization_timer);
d913d630 2761 del_timer_sync(&hdw->encoder_run_timer);
8f59100a 2762 del_timer_sync(&hdw->encoder_wait_timer);
d855497e
MI		 2763 if (hdw->fw_buffer) {
2764 kfree(hdw->fw_buffer);
a0fd1cb1 2765 hdw->fw_buffer = NULL;
d855497e
MI		 2766 }
2767 if (hdw->vid_stream) {
2768 pvr2_stream_destroy(hdw->vid_stream);
a0fd1cb1 2769 hdw->vid_stream = NULL;
d855497e 2770 }
d855497e 2771 pvr2_i2c_core_done(hdw);
b72b7bf5 2772 v4l2_device_unregister(&hdw->v4l2_dev);
d855497e 2773 pvr2_hdw_remove_usb_stuff(hdw);
8df0c87c 2774 mutex_lock(&pvr2_unit_mtx); do {
d855497e
MI		 2775 if ((hdw->unit_number >= 0) &&
2776 (hdw->unit_number < PVR_NUM) &&
2777 (unit_pointers[hdw->unit_number] == hdw)) {
a0fd1cb1 2778 unit_pointers[hdw->unit_number] = NULL;
d855497e 2779 }
8df0c87c 2780 } while (0); mutex_unlock(&pvr2_unit_mtx);
22071a42
MK		 2781 kfree(hdw->controls);
2782 kfree(hdw->mpeg_ctrl_info);
2783 kfree(hdw->std_defs);
2784 kfree(hdw->std_enum_names);
d855497e
MI		 2785 kfree(hdw);
2786}
2787
2788
d855497e
MI		 2789int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2790{
2791 return (hdw && hdw->flag_ok);
2792}
2793
2794
2795/* Called when hardware has been unplugged */
2796void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2797{
2798 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2799 LOCK_TAKE(hdw->big_lock);
2800 LOCK_TAKE(hdw->ctl_lock);
2801 pvr2_hdw_remove_usb_stuff(hdw);
2802 LOCK_GIVE(hdw->ctl_lock);
2803 LOCK_GIVE(hdw->big_lock);
2804}
2805
2806
2807// Attempt to autoselect an appropriate value for std_enum_cur given
2808// whatever is currently in std_mask_cur
07e337ee 2809static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
d855497e
MI		 2810{
2811 unsigned int idx;
2812 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2813 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2814 hdw->std_enum_cur = idx;
2815 return;
2816 }
2817 }
2818 hdw->std_enum_cur = 0;
2819}
2820
2821
2822// Calculate correct set of enumerated standards based on currently known
2823// set of available standards bits.
07e337ee 2824static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
d855497e
MI		 2825{
2826 struct v4l2_standard *newstd;
2827 unsigned int std_cnt;
2828 unsigned int idx;
2829
2830 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2831
2832 if (hdw->std_defs) {
2833 kfree(hdw->std_defs);
a0fd1cb1 2834 hdw->std_defs = NULL;
d855497e
MI		 2835 }
2836 hdw->std_enum_cnt = 0;
2837 if (hdw->std_enum_names) {
2838 kfree(hdw->std_enum_names);
a0fd1cb1 2839 hdw->std_enum_names = NULL;
d855497e
MI		 2840 }
2841
2842 if (!std_cnt) {
2843 pvr2_trace(
2844 PVR2_TRACE_ERROR_LEGS,
2845 "WARNING: Failed to identify any viable standards");
2846 }
2847 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2848 hdw->std_enum_names[0] = "none";
2849 for (idx = 0; idx < std_cnt; idx++) {
2850 hdw->std_enum_names[idx+1] =
2851 newstd[idx].name;
2852 }
2853 // Set up the dynamic control for this standard
2854 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2855 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2856 hdw->std_defs = newstd;
2857 hdw->std_enum_cnt = std_cnt+1;
2858 hdw->std_enum_cur = 0;
2859 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2860}
2861
2862
2863int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2864 struct v4l2_standard *std,
2865 unsigned int idx)
2866{
2867 int ret = -EINVAL;
2868 if (!idx) return ret;
2869 LOCK_TAKE(hdw->big_lock); do {
2870 if (idx >= hdw->std_enum_cnt) break;
2871 idx--;
2872 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2873 ret = 0;
2874 } while (0); LOCK_GIVE(hdw->big_lock);
2875 return ret;
2876}
2877
2878
2879/* Get the number of defined controls */
2880unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2881{
c05c0462 2882 return hdw->control_cnt;
d855497e
MI		 2883}
2884
2885
2886/* Retrieve a control handle given its index (0..count-1) */
2887struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2888 unsigned int idx)
2889{
a0fd1cb1 2890 if (idx >= hdw->control_cnt) return NULL;
d855497e
MI		 2891 return hdw->controls + idx;
2892}
2893
2894
2895/* Retrieve a control handle given its index (0..count-1) */
2896struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2897 unsigned int ctl_id)
2898{
2899 struct pvr2_ctrl *cptr;
2900 unsigned int idx;
2901 int i;
2902
2903 /* This could be made a lot more efficient, but for now... */
c05c0462 2904 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2905 cptr = hdw->controls + idx;
2906 i = cptr->info->internal_id;
2907 if (i && (i == ctl_id)) return cptr;
2908 }
a0fd1cb1 2909 return NULL;
d855497e
MI		 2910}
2911
2912
a761f431 2913/* Given a V4L ID, retrieve the control structure associated with it. */
d855497e
MI		 2914struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2915{
2916 struct pvr2_ctrl *cptr;
2917 unsigned int idx;
2918 int i;
2919
2920 /* This could be made a lot more efficient, but for now... */
c05c0462 2921 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e
MI		 2922 cptr = hdw->controls + idx;
2923 i = cptr->info->v4l_id;
2924 if (i && (i == ctl_id)) return cptr;
2925 }
a0fd1cb1 2926 return NULL;
d855497e
MI		 2927}
2928
2929
a761f431
MI		 2930/* Given a V4L ID for its immediate predecessor, retrieve the control
2931 structure associated with it. */
2932struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2933 unsigned int ctl_id)
2934{
2935 struct pvr2_ctrl *cptr,*cp2;
2936 unsigned int idx;
2937 int i;
2938
2939 /* This could be made a lot more efficient, but for now... */
a0fd1cb1 2940 cp2 = NULL;
a761f431
MI		 2941 for (idx = 0; idx < hdw->control_cnt; idx++) {
2942 cptr = hdw->controls + idx;
2943 i = cptr->info->v4l_id;
2944 if (!i) continue;
2945 if (i <= ctl_id) continue;
2946 if (cp2 && (cp2->info->v4l_id < i)) continue;
2947 cp2 = cptr;
2948 }
2949 return cp2;
a0fd1cb1 2950 return NULL;
a761f431
MI		 2951}
2952
2953
d855497e
MI		 2954static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2955{
2956 switch (tp) {
2957 case pvr2_ctl_int: return "integer";
2958 case pvr2_ctl_enum: return "enum";
33213963 2959 case pvr2_ctl_bool: return "boolean";
d855497e
MI		 2960 case pvr2_ctl_bitmask: return "bitmask";
2961 }
2962 return "";
2963}
2964
2965
2641df36
MI		 2966static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2967 const char *name, int val)
2968{
2969 struct v4l2_control ctrl;
2970 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2971 memset(&ctrl, 0, sizeof(ctrl));
2972 ctrl.id = id;
2973 ctrl.value = val;
2974 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2975}
2976
2977#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
27764726 2978 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2641df36
MI		 2979 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2980 }
2981
5ceaad14 2982/* Execute whatever commands are required to update the state of all the
2641df36 2983 sub-devices so that they match our current control values. */
5ceaad14
MI		 2984static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2985{
edb9dcb8
MI		 2986 struct v4l2_subdev *sd;
2987 unsigned int id;
2988 pvr2_subdev_update_func fp;
2989
75212a02
MI		 2990 pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2991
27764726 2992 if (hdw->tuner_updated || hdw->force_dirty) {
75212a02
MI		 2993 struct tuner_setup setup;
2994 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2995 hdw->tuner_type);
2996 if (((int)(hdw->tuner_type)) >= 0) {
fcd62cf7 2997 memset(&setup, 0, sizeof(setup));
75212a02
MI		 2998 setup.addr = ADDR_UNSET;
2999 setup.type = hdw->tuner_type;
3000 setup.mode_mask = T_RADIO | T_ANALOG_TV;
3001 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3002 tuner, s_type_addr, &setup);
3003 }
3004 }
3005
27764726 3006 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
b481880b 3007 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2641df36
MI		 3008 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3009 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3010 tuner, s_radio);
3011 } else {
3012 v4l2_std_id vs;
3013 vs = hdw->std_mask_cur;
3014 v4l2_device_call_all(&hdw->v4l2_dev, 0,
f41737ec 3015 core, s_std, vs);
a6862da2 3016 pvr2_hdw_cx25840_vbi_hack(hdw);
2641df36
MI		 3017 }
3018 hdw->tuner_signal_stale = !0;
3019 hdw->cropcap_stale = !0;
3020 }
3021
3022 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
3023 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
3024 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
3025 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
3026 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
3027 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
3028 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
3029 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
3030 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
3031
27764726 3032 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2641df36
MI		 3033 struct v4l2_tuner vt;
3034 memset(&vt, 0, sizeof(vt));
3035 vt.audmode = hdw->audiomode_val;
3036 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3037 }
3038
27764726 3039 if (hdw->freqDirty || hdw->force_dirty) {
2641df36
MI		 3040 unsigned long fv;
3041 struct v4l2_frequency freq;
3042 fv = pvr2_hdw_get_cur_freq(hdw);
3043 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3044 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3045 memset(&freq, 0, sizeof(freq));
3046 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3047 /* ((fv * 1000) / 62500) */
3048 freq.frequency = (fv * 2) / 125;
3049 } else {
3050 freq.frequency = fv / 62500;
3051 }
3052 /* tuner-core currently doesn't seem to care about this, but
3053 let's set it anyway for completeness. */
3054 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3055 freq.type = V4L2_TUNER_RADIO;
3056 } else {
3057 freq.type = V4L2_TUNER_ANALOG_TV;
3058 }
3059 freq.tuner = 0;
3060 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3061 s_frequency, &freq);
3062 }
3063
27764726 3064 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
fa190ee9 3065 struct v4l2_mbus_framefmt fmt;
2641df36 3066 memset(&fmt, 0, sizeof(fmt));
fa190ee9
HV		 3067 fmt.width = hdw->res_hor_val;
3068 fmt.height = hdw->res_ver_val;
3069 fmt.code = V4L2_MBUS_FMT_FIXED;
7dfdf1ee 3070 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
fa190ee9
HV		 3071 fmt.width, fmt.height);
3072 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_mbus_fmt, &fmt);
2641df36
MI		 3073 }
3074
27764726 3075 if (hdw->srate_dirty || hdw->force_dirty) {
01c59df8
MI		 3076 u32 val;
3077 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3078 hdw->srate_val);
3079 switch (hdw->srate_val) {
3080 default:
3081 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3082 val = 48000;
3083 break;
3084 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3085 val = 44100;
3086 break;
3087 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3088 val = 32000;
3089 break;
3090 }
3091 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3092 audio, s_clock_freq, val);
3093 }
3094
2641df36
MI		 3095 /* Unable to set crop parameters; there is apparently no equivalent
3096 for VIDIOC_S_CROP */
3097
edb9dcb8
MI		 3098 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3099 id = sd->grp_id;
3100 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3101 fp = pvr2_module_update_functions[id];
3102 if (!fp) continue;
3103 (*fp)(hdw, sd);
3104 }
2641df36 3105
27764726 3106 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2641df36
MI		 3107 pvr2_hdw_status_poll(hdw);
3108 }
5ceaad14
MI		 3109}
3110
3111
681c7399
MI		 3112/* Figure out if we need to commit control changes. If so, mark internal
3113 state flags to indicate this fact and return true. Otherwise do nothing
3114 else and return false. */
3115static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
d855497e 3116{
d855497e
MI		 3117 unsigned int idx;
3118 struct pvr2_ctrl *cptr;
3119 int value;
27764726 3120 int commit_flag = hdw->force_dirty;
d855497e
MI		 3121 char buf[100];
3122 unsigned int bcnt,ccnt;
3123
c05c0462 3124 for (idx = 0; idx < hdw->control_cnt; idx++) {
d855497e 3125 cptr = hdw->controls + idx;
5fa1247a 3126 if (!cptr->info->is_dirty) continue;
d855497e 3127 if (!cptr->info->is_dirty(cptr)) continue;
fe23a280 3128 commit_flag = !0;
d855497e 3129
fe23a280 3130 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
d855497e
MI		 3131 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3132 cptr->info->name);
3133 value = 0;
3134 cptr->info->get_value(cptr,&value);
3135 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3136 buf+bcnt,
3137 sizeof(buf)-bcnt,&ccnt);
3138 bcnt += ccnt;
3139 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3140 get_ctrl_typename(cptr->info->type));
3141 pvr2_trace(PVR2_TRACE_CTL,
3142 "/*--TRACE_COMMIT--*/ %.*s",
3143 bcnt,buf);
3144 }
3145
3146 if (!commit_flag) {
3147 /* Nothing has changed */
3148 return 0;
3149 }
3150
681c7399
MI		 3151 hdw->state_pipeline_config = 0;
3152 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3153 pvr2_hdw_state_sched(hdw);
3154
3155 return !0;
3156}
3157
3158
3159/* Perform all operations needed to commit all control changes. This must
3160 be performed in synchronization with the pipeline state and is thus
3161 expected to be called as part of the driver's worker thread. Return
3162 true if commit successful, otherwise return false to indicate that
3163 commit isn't possible at this time. */
3164static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3165{
3166 unsigned int idx;
3167 struct pvr2_ctrl *cptr;
3168 int disruptive_change;
3169
ab062fe3
MI		 3170 /* Handle some required side effects when the video standard is
3171 changed.... */
d855497e 3172 if (hdw->std_dirty) {
d855497e 3173 int nvres;
00528d9c 3174 int gop_size;
d855497e
MI		 3175 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3176 nvres = 480;
00528d9c 3177 gop_size = 15;
d855497e
MI		 3178 } else {
3179 nvres = 576;
00528d9c 3180 gop_size = 12;
d855497e 3181 }
00528d9c
MI		 3182 /* Rewrite the vertical resolution to be appropriate to the
3183 video standard that has been selected. */
d855497e
MI		 3184 if (nvres != hdw->res_ver_val) {
3185 hdw->res_ver_val = nvres;
3186 hdw->res_ver_dirty = !0;
3187 }
00528d9c
MI		 3188 /* Rewrite the GOP size to be appropriate to the video
3189 standard that has been selected. */
3190 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3191 struct v4l2_ext_controls cs;
3192 struct v4l2_ext_control c1;
3193 memset(&cs, 0, sizeof(cs));
3194 memset(&c1, 0, sizeof(c1));
3195 cs.controls = &c1;
3196 cs.count = 1;
3197 c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3198 c1.value = gop_size;
3199 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3200 VIDIOC_S_EXT_CTRLS);
3201 }
d855497e
MI		 3202 }
3203
38d9a2cf 3204 if (hdw->input_dirty && hdw->state_pathway_ok &&
62433e31
MI		 3205 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3206 PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3207 hdw->pathway_state)) {
3208 /* Change of mode being asked for... */
3209 hdw->state_pathway_ok = 0;
e9db1ff2 3210 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 3211 }
3212 if (!hdw->state_pathway_ok) {
3213 /* Can't commit anything until pathway is ok. */
3214 return 0;
3215 }
e784bfb9 3216 /* The broadcast decoder can only scale down, so if
3217 * res_*_dirty && crop window < output format ==> enlarge crop.
3218 *
3219 * The mpeg encoder receives fields of res_hor_val dots and
3220 * res_ver_val halflines. Limits: hor<=720, ver<=576.
3221 */
3222 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3223 hdw->cropw_val = hdw->res_hor_val;
3224 hdw->cropw_dirty = !0;
3225 } else if (hdw->cropw_dirty) {
3226 hdw->res_hor_dirty = !0; /* must rescale */
3227 hdw->res_hor_val = min(720, hdw->cropw_val);
3228 }
3229 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3230 hdw->croph_val = hdw->res_ver_val;
3231 hdw->croph_dirty = !0;
3232 } else if (hdw->croph_dirty) {
3233 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3234 hdw->res_ver_dirty = !0;
3235 hdw->res_ver_val = min(nvres, hdw->croph_val);
3236 }
3237
681c7399
MI		 3238 /* If any of the below has changed, then we can't do the update
3239 while the pipeline is running. Pipeline must be paused first
3240 and decoder -> encoder connection be made quiescent before we
3241 can proceed. */
3242 disruptive_change =
3243 (hdw->std_dirty ||
3244 hdw->enc_unsafe_stale ||
3245 hdw->srate_dirty ||
3246 hdw->res_ver_dirty ||
3247 hdw->res_hor_dirty ||
755879c6
MI		 3248 hdw->cropw_dirty ||
3249 hdw->croph_dirty ||
681c7399
MI		 3250 hdw->input_dirty ||
3251 (hdw->active_stream_type != hdw->desired_stream_type));
3252 if (disruptive_change && !hdw->state_pipeline_idle) {
3253 /* Pipeline is not idle; we can't proceed. Arrange to
3254 cause pipeline to stop so that we can try this again
3255 later.... */
3256 hdw->state_pipeline_pause = !0;
3257 return 0;
275b2e28
PK		 3258 }
3259
b30d2441
MI		 3260 if (hdw->srate_dirty) {
3261 /* Write new sample rate into control structure since
3262 * the master copy is stale. We must track srate
3263 * separate from the mpeg control structure because
3264 * other logic also uses this value. */
3265 struct v4l2_ext_controls cs;
3266 struct v4l2_ext_control c1;
3267 memset(&cs,0,sizeof(cs));
3268 memset(&c1,0,sizeof(c1));
3269 cs.controls = &c1;
3270 cs.count = 1;
3271 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3272 c1.value = hdw->srate_val;
01f1e44f 3273 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
b30d2441 3274 }
c05c0462 3275
681c7399
MI		 3276 if (hdw->active_stream_type != hdw->desired_stream_type) {
3277 /* Handle any side effects of stream config here */
3278 hdw->active_stream_type = hdw->desired_stream_type;
3279 }
3280
1df59f0b
MI		 3281 if (hdw->hdw_desc->signal_routing_scheme ==
3282 PVR2_ROUTING_SCHEME_GOTVIEW) {
3283 u32 b;
3284 /* Handle GOTVIEW audio switching */
3285 pvr2_hdw_gpio_get_out(hdw,&b);
3286 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3287 /* Set GPIO 11 */
3288 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3289 } else {
3290 /* Clear GPIO 11 */
3291 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3292 }
3293 }
3294
e68a619a
MI		 3295 /* Check and update state for all sub-devices. */
3296 pvr2_subdev_update(hdw);
3297
75212a02 3298 hdw->tuner_updated = 0;
27764726 3299 hdw->force_dirty = 0;
5ceaad14
MI		 3300 for (idx = 0; idx < hdw->control_cnt; idx++) {
3301 cptr = hdw->controls + idx;
3302 if (!cptr->info->clear_dirty) continue;
3303 cptr->info->clear_dirty(cptr);
3304 }
3305
62433e31
MI		 3306 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3307 hdw->state_encoder_run) {
3308 /* If encoder isn't running or it can't be touched, then
3309 this will get worked out later when we start the
3310 encoder. */
681c7399
MI		 3311 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3312 }
d855497e 3313
681c7399 3314 hdw->state_pipeline_config = !0;
432907f7
MI		 3315 /* Hardware state may have changed in a way to cause the cropping
3316 capabilities to have changed. So mark it stale, which will
3317 cause a later re-fetch. */
681c7399
MI		 3318 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3319 return !0;
d855497e
MI		 3320}
3321
3322
3323int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3324{
681c7399
MI		 3325 int fl;
3326 LOCK_TAKE(hdw->big_lock);
3327 fl = pvr2_hdw_commit_setup(hdw);
3328 LOCK_GIVE(hdw->big_lock);
3329 if (!fl) return 0;
3330 return pvr2_hdw_wait(hdw,0);
3331}
3332
3333
681c7399 3334static void pvr2_hdw_worker_poll(struct work_struct *work)
d855497e 3335{
681c7399
MI		 3336 int fl = 0;
3337 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
d855497e 3338 LOCK_TAKE(hdw->big_lock); do {
681c7399 3339 fl = pvr2_hdw_state_eval(hdw);
d855497e 3340 } while (0); LOCK_GIVE(hdw->big_lock);
681c7399
MI		 3341 if (fl && hdw->state_func) {
3342 hdw->state_func(hdw->state_data);
3343 }
d855497e
MI		 3344}
3345
3346
681c7399 3347static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
d855497e 3348{
681c7399
MI		 3349 return wait_event_interruptible(
3350 hdw->state_wait_data,
3351 (hdw->state_stale == 0) &&
3352 (!state || (hdw->master_state != state)));
3353}
3354
3355
d855497e
MI		 3356/* Return name for this driver instance */
3357const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3358{
3359 return hdw->name;
3360}
3361
3362
78a47101
MI		 3363const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3364{
3365 return hdw->hdw_desc->description;
3366}
3367
3368
3369const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3370{
3371 return hdw->hdw_desc->shortname;
3372}
3373
3374
d855497e
MI		 3375int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3376{
3377 int result;
3378 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 3379 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
d855497e
MI		 3380 result = pvr2_send_request(hdw,
3381 hdw->cmd_buffer,1,
3382 hdw->cmd_buffer,1);
3383 if (result < 0) break;
3384 result = (hdw->cmd_buffer[0] != 0);
3385 } while(0); LOCK_GIVE(hdw->ctl_lock);
3386 return result;
3387}
3388
3389
18103c57
MI		 3390/* Execute poll of tuner status */
3391void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
d855497e 3392{
d855497e 3393 LOCK_TAKE(hdw->big_lock); do {
a51f5000 3394 pvr2_hdw_status_poll(hdw);
d855497e 3395 } while (0); LOCK_GIVE(hdw->big_lock);
18103c57
MI		 3396}
3397
3398
432907f7
MI		 3399static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3400{
3401 if (!hdw->cropcap_stale) {
432907f7
MI		 3402 return 0;
3403 }
a51f5000 3404 pvr2_hdw_status_poll(hdw);
432907f7 3405 if (hdw->cropcap_stale) {
432907f7
MI		 3406 return -EIO;
3407 }
3408 return 0;
3409}
3410
3411
3412/* Return information about cropping capabilities */
3413int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3414{
3415 int stat = 0;
3416 LOCK_TAKE(hdw->big_lock);
3417 stat = pvr2_hdw_check_cropcap(hdw);
3418 if (!stat) {
432907f7
MI		 3419 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3420 }
3421 LOCK_GIVE(hdw->big_lock);
3422 return stat;
3423}
3424
3425
18103c57
MI		 3426/* Return information about the tuner */
3427int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3428{
3429 LOCK_TAKE(hdw->big_lock); do {
3430 if (hdw->tuner_signal_stale) {
a51f5000 3431 pvr2_hdw_status_poll(hdw);
18103c57
MI		 3432 }
3433 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3434 } while (0); LOCK_GIVE(hdw->big_lock);
3435 return 0;
d855497e
MI		 3436}
3437
3438
3439/* Get handle to video output stream */
3440struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3441{
3442 return hp->vid_stream;
3443}
3444
3445
3446void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3447{
4f1a3e5b 3448 int nr = pvr2_hdw_get_unit_number(hdw);
d855497e 3449 LOCK_TAKE(hdw->big_lock); do {
4f1a3e5b 3450 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
ed3261a8 3451 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
b30d2441 3452 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
99eb44fe 3453 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
681c7399 3454 pvr2_hdw_state_log_state(hdw);
4f1a3e5b 3455 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
d855497e
MI		 3456 } while (0); LOCK_GIVE(hdw->big_lock);
3457}
3458
4db666cc
MI		 3459
3460/* Grab EEPROM contents, needed for direct method. */
3461#define EEPROM_SIZE 8192
3462#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3463static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3464{
3465 struct i2c_msg msg[2];
3466 u8 *eeprom;
3467 u8 iadd[2];
3468 u8 addr;
3469 u16 eepromSize;
3470 unsigned int offs;
3471 int ret;
3472 int mode16 = 0;
3473 unsigned pcnt,tcnt;
3474 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3475 if (!eeprom) {
3476 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3477 "Failed to allocate memory"
3478 " required to read eeprom");
3479 return NULL;
3480 }
3481
3482 trace_eeprom("Value for eeprom addr from controller was 0x%x",
3483 hdw->eeprom_addr);
3484 addr = hdw->eeprom_addr;
3485 /* Seems that if the high bit is set, then the *real* eeprom
3486 address is shifted right now bit position (noticed this in
3487 newer PVR USB2 hardware) */
3488 if (addr & 0x80) addr >>= 1;
3489
3490 /* FX2 documentation states that a 16bit-addressed eeprom is
3491 expected if the I2C address is an odd number (yeah, this is
3492 strange but it's what they do) */
3493 mode16 = (addr & 1);
3494 eepromSize = (mode16 ? EEPROM_SIZE : 256);
3495 trace_eeprom("Examining %d byte eeprom at location 0x%x"
3496 " using %d bit addressing",eepromSize,addr,
3497 mode16 ? 16 : 8);
3498
3499 msg[0].addr = addr;
3500 msg[0].flags = 0;
3501 msg[0].len = mode16 ? 2 : 1;
3502 msg[0].buf = iadd;
3503 msg[1].addr = addr;
3504 msg[1].flags = I2C_M_RD;
3505
3506 /* We have to do the actual eeprom data fetch ourselves, because
3507 (1) we're only fetching part of the eeprom, and (2) if we were
3508 getting the whole thing our I2C driver can't grab it in one
3509 pass - which is what tveeprom is otherwise going to attempt */
3510 memset(eeprom,0,EEPROM_SIZE);
3511 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3512 pcnt = 16;
3513 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3514 offs = tcnt + (eepromSize - EEPROM_SIZE);
3515 if (mode16) {
3516 iadd[0] = offs >> 8;
3517 iadd[1] = offs;
3518 } else {
3519 iadd[0] = offs;
3520 }
3521 msg[1].len = pcnt;
3522 msg[1].buf = eeprom+tcnt;
3523 if ((ret = i2c_transfer(&hdw->i2c_adap,
3524 msg,ARRAY_SIZE(msg))) != 2) {
3525 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3526 "eeprom fetch set offs err=%d",ret);
3527 kfree(eeprom);
3528 return NULL;
3529 }
3530 }
3531 return eeprom;
3532}
3533
3534
3535void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
568efaa2 3536 int mode,
4db666cc 3537 int enable_flag)
d855497e
MI		 3538{
3539 int ret;
3540 u16 address;
3541 unsigned int pipe;
3542 LOCK_TAKE(hdw->big_lock); do {
5fa1247a 3543 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
d855497e
MI		 3544
3545 if (!enable_flag) {
3546 pvr2_trace(PVR2_TRACE_FIRMWARE,
3547 "Cleaning up after CPU firmware fetch");
3548 kfree(hdw->fw_buffer);
a0fd1cb1 3549 hdw->fw_buffer = NULL;
d855497e 3550 hdw->fw_size = 0;
4db666cc
MI		 3551 if (hdw->fw_cpu_flag) {
3552 /* Now release the CPU. It will disconnect
3553 and reconnect later. */
3554 pvr2_hdw_cpureset_assert(hdw,0);
3555 }
d855497e
MI		 3556 break;
3557 }
3558
568efaa2 3559 hdw->fw_cpu_flag = (mode != 2);
4db666cc 3560 if (hdw->fw_cpu_flag) {
568efaa2 3561 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
4db666cc 3562 pvr2_trace(PVR2_TRACE_FIRMWARE,
568efaa2
MI		 3563 "Preparing to suck out CPU firmware"
3564 " (size=%u)", hdw->fw_size);
4db666cc
MI		 3565 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3566 if (!hdw->fw_buffer) {
3567 hdw->fw_size = 0;
3568 break;
3569 }
d855497e 3570
4db666cc
MI		 3571 /* We have to hold the CPU during firmware upload. */
3572 pvr2_hdw_cpureset_assert(hdw,1);
d855497e 3573
4db666cc
MI		 3574 /* download the firmware from address 0000-1fff in 2048
3575 (=0x800) bytes chunk. */
d855497e 3576
4db666cc
MI		 3577 pvr2_trace(PVR2_TRACE_FIRMWARE,
3578 "Grabbing CPU firmware");
3579 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3580 for(address = 0; address < hdw->fw_size;
3581 address += 0x800) {
3582 ret = usb_control_msg(hdw->usb_dev,pipe,
3583 0xa0,0xc0,
3584 address,0,
3585 hdw->fw_buffer+address,
3586 0x800,HZ);
3587 if (ret < 0) break;
3588 }
d855497e 3589
4db666cc
MI		 3590 pvr2_trace(PVR2_TRACE_FIRMWARE,
3591 "Done grabbing CPU firmware");
3592 } else {
3593 pvr2_trace(PVR2_TRACE_FIRMWARE,
3594 "Sucking down EEPROM contents");
3595 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3596 if (!hdw->fw_buffer) {
3597 pvr2_trace(PVR2_TRACE_FIRMWARE,
3598 "EEPROM content suck failed.");
3599 break;
3600 }
3601 hdw->fw_size = EEPROM_SIZE;
3602 pvr2_trace(PVR2_TRACE_FIRMWARE,
3603 "Done sucking down EEPROM contents");
3604 }
d855497e
MI		 3605
3606 } while (0); LOCK_GIVE(hdw->big_lock);
3607}
3608
3609
3610/* Return true if we're in a mode for retrieval CPU firmware */
3611int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3612{
5fa1247a 3613 return hdw->fw_buffer != NULL;
d855497e
MI		 3614}
3615
3616
3617int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3618 char *buf,unsigned int cnt)
3619{
3620 int ret = -EINVAL;
3621 LOCK_TAKE(hdw->big_lock); do {
3622 if (!buf) break;
3623 if (!cnt) break;
3624
3625 if (!hdw->fw_buffer) {
3626 ret = -EIO;
3627 break;
3628 }
3629
3630 if (offs >= hdw->fw_size) {
3631 pvr2_trace(PVR2_TRACE_FIRMWARE,
3632 "Read firmware data offs=%d EOF",
3633 offs);
3634 ret = 0;
3635 break;
3636 }
3637
3638 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3639
3640 memcpy(buf,hdw->fw_buffer+offs,cnt);
3641
3642 pvr2_trace(PVR2_TRACE_FIRMWARE,
3643 "Read firmware data offs=%d cnt=%d",
3644 offs,cnt);
3645 ret = cnt;
3646 } while (0); LOCK_GIVE(hdw->big_lock);
3647
3648 return ret;
3649}
3650
3651
fd5a75fe 3652int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
8079384e 3653 enum pvr2_v4l_type index)
d855497e 3654{
fd5a75fe 3655 switch (index) {
8079384e
MI		 3656 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3657 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3658 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
fd5a75fe
MI		 3659 default: return -1;
3660 }
d855497e
MI		 3661}
3662
3663
2fdf3d9c 3664/* Store a v4l minor device number */
fd5a75fe 3665void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
8079384e 3666 enum pvr2_v4l_type index,int v)
d855497e 3667{
fd5a75fe 3668 switch (index) {
8079384e
MI		 3669 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3670 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3671 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
fd5a75fe
MI		 3672 default: break;
3673 }
d855497e
MI		 3674}
3675
3676
7d12e780 3677static void pvr2_ctl_write_complete(struct urb *urb)
d855497e
MI		 3678{
3679 struct pvr2_hdw *hdw = urb->context;
3680 hdw->ctl_write_pend_flag = 0;
3681 if (hdw->ctl_read_pend_flag) return;
3682 complete(&hdw->ctl_done);
3683}
3684
3685
7d12e780 3686static void pvr2_ctl_read_complete(struct urb *urb)
d855497e
MI		 3687{
3688 struct pvr2_hdw *hdw = urb->context;
3689 hdw->ctl_read_pend_flag = 0;
3690 if (hdw->ctl_write_pend_flag) return;
3691 complete(&hdw->ctl_done);
3692}
3693
3694
3695static void pvr2_ctl_timeout(unsigned long data)
3696{
3697 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3698 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3699 hdw->ctl_timeout_flag = !0;
5e55d2ce 3700 if (hdw->ctl_write_pend_flag)
d855497e 3701 usb_unlink_urb(hdw->ctl_write_urb);
5e55d2ce 3702 if (hdw->ctl_read_pend_flag)
d855497e 3703 usb_unlink_urb(hdw->ctl_read_urb);
d855497e
MI		 3704 }
3705}
3706
3707
e61b6fc5
MI		 3708/* Issue a command and get a response from the device. This extended
3709 version includes a probe flag (which if set means that device errors
3710 should not be logged or treated as fatal) and a timeout in jiffies.
3711 This can be used to non-lethally probe the health of endpoint 1. */
07e337ee
AB		 3712static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3713 unsigned int timeout,int probe_fl,
3714 void *write_data,unsigned int write_len,
3715 void *read_data,unsigned int read_len)
d855497e
MI		 3716{
3717 unsigned int idx;
3718 int status = 0;
3719 struct timer_list timer;
3720 if (!hdw->ctl_lock_held) {
3721 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3722 "Attempted to execute control transfer"
3723 " without lock!!");
3724 return -EDEADLK;
3725 }
681c7399 3726 if (!hdw->flag_ok && !probe_fl) {
d855497e
MI		 3727 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3728 "Attempted to execute control transfer"
3729 " when device not ok");
3730 return -EIO;
3731 }
3732 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3733 if (!probe_fl) {
3734 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3735 "Attempted to execute control transfer"
3736 " when USB is disconnected");
3737 }
3738 return -ENOTTY;
3739 }
3740
3741 /* Ensure that we have sane parameters */
3742 if (!write_data) write_len = 0;
3743 if (!read_data) read_len = 0;
3744 if (write_len > PVR2_CTL_BUFFSIZE) {
3745 pvr2_trace(
3746 PVR2_TRACE_ERROR_LEGS,
3747 "Attempted to execute %d byte"
3748 " control-write transfer (limit=%d)",
3749 write_len,PVR2_CTL_BUFFSIZE);
3750 return -EINVAL;
3751 }
3752 if (read_len > PVR2_CTL_BUFFSIZE) {
3753 pvr2_trace(
3754 PVR2_TRACE_ERROR_LEGS,
3755 "Attempted to execute %d byte"
3756 " control-read transfer (limit=%d)",
3757 write_len,PVR2_CTL_BUFFSIZE);
3758 return -EINVAL;
3759 }
3760 if ((!write_len) && (!read_len)) {
3761 pvr2_trace(
3762 PVR2_TRACE_ERROR_LEGS,
3763 "Attempted to execute null control transfer?");
3764 return -EINVAL;
3765 }
3766
3767
3768 hdw->cmd_debug_state = 1;
3769 if (write_len) {
3770 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3771 } else {
3772 hdw->cmd_debug_code = 0;
3773 }
3774 hdw->cmd_debug_write_len = write_len;
3775 hdw->cmd_debug_read_len = read_len;
3776
3777 /* Initialize common stuff */
3778 init_completion(&hdw->ctl_done);
3779 hdw->ctl_timeout_flag = 0;
3780 hdw->ctl_write_pend_flag = 0;
3781 hdw->ctl_read_pend_flag = 0;
3782 init_timer(&timer);
3783 timer.expires = jiffies + timeout;
3784 timer.data = (unsigned long)hdw;
3785 timer.function = pvr2_ctl_timeout;
3786
3787 if (write_len) {
3788 hdw->cmd_debug_state = 2;
3789 /* Transfer write data to internal buffer */
3790 for (idx = 0; idx < write_len; idx++) {
3791 hdw->ctl_write_buffer[idx] =
3792 ((unsigned char *)write_data)[idx];
3793 }
3794 /* Initiate a write request */
3795 usb_fill_bulk_urb(hdw->ctl_write_urb,
3796 hdw->usb_dev,
3797 usb_sndbulkpipe(hdw->usb_dev,
3798 PVR2_CTL_WRITE_ENDPOINT),
3799 hdw->ctl_write_buffer,
3800 write_len,
3801 pvr2_ctl_write_complete,
3802 hdw);
3803 hdw->ctl_write_urb->actual_length = 0;
3804 hdw->ctl_write_pend_flag = !0;
3805 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3806 if (status < 0) {
3807 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3808 "Failed to submit write-control"
3809 " URB status=%d",status);
3810 hdw->ctl_write_pend_flag = 0;
3811 goto done;
3812 }
3813 }
3814
3815 if (read_len) {
3816 hdw->cmd_debug_state = 3;
3817 memset(hdw->ctl_read_buffer,0x43,read_len);
3818 /* Initiate a read request */
3819 usb_fill_bulk_urb(hdw->ctl_read_urb,
3820 hdw->usb_dev,
3821 usb_rcvbulkpipe(hdw->usb_dev,
3822 PVR2_CTL_READ_ENDPOINT),
3823 hdw->ctl_read_buffer,
3824 read_len,
3825 pvr2_ctl_read_complete,
3826 hdw);
3827 hdw->ctl_read_urb->actual_length = 0;
3828 hdw->ctl_read_pend_flag = !0;
3829 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3830 if (status < 0) {
3831 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3832 "Failed to submit read-control"
3833 " URB status=%d",status);
3834 hdw->ctl_read_pend_flag = 0;
3835 goto done;
3836 }
3837 }
3838
3839 /* Start timer */
3840 add_timer(&timer);
3841
3842 /* Now wait for all I/O to complete */
3843 hdw->cmd_debug_state = 4;
3844 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3845 wait_for_completion(&hdw->ctl_done);
3846 }
3847 hdw->cmd_debug_state = 5;
3848
3849 /* Stop timer */
3850 del_timer_sync(&timer);
3851
3852 hdw->cmd_debug_state = 6;
3853 status = 0;
3854
3855 if (hdw->ctl_timeout_flag) {
3856 status = -ETIMEDOUT;
3857 if (!probe_fl) {
3858 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3859 "Timed out control-write");
3860 }
3861 goto done;
3862 }
3863
3864 if (write_len) {
3865 /* Validate results of write request */
3866 if ((hdw->ctl_write_urb->status != 0) &&
3867 (hdw->ctl_write_urb->status != -ENOENT) &&
3868 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3869 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3870 /* USB subsystem is reporting some kind of failure
3871 on the write */
3872 status = hdw->ctl_write_urb->status;
3873 if (!probe_fl) {
3874 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3875 "control-write URB failure,"
3876 " status=%d",
3877 status);
3878 }
3879 goto done;
3880 }
3881 if (hdw->ctl_write_urb->actual_length < write_len) {
3882 /* Failed to write enough data */
3883 status = -EIO;
3884 if (!probe_fl) {
3885 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3886 "control-write URB short,"
3887 " expected=%d got=%d",
3888 write_len,
3889 hdw->ctl_write_urb->actual_length);
3890 }
3891 goto done;
3892 }
3893 }
3894 if (read_len) {
3895 /* Validate results of read request */
3896 if ((hdw->ctl_read_urb->status != 0) &&
3897 (hdw->ctl_read_urb->status != -ENOENT) &&
3898 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3899 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3900 /* USB subsystem is reporting some kind of failure
3901 on the read */
3902 status = hdw->ctl_read_urb->status;
3903 if (!probe_fl) {
3904 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3905 "control-read URB failure,"
3906 " status=%d",
3907 status);
3908 }
3909 goto done;
3910 }
3911 if (hdw->ctl_read_urb->actual_length < read_len) {
3912 /* Failed to read enough data */
3913 status = -EIO;
3914 if (!probe_fl) {
3915 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3916 "control-read URB short,"
3917 " expected=%d got=%d",
3918 read_len,
3919 hdw->ctl_read_urb->actual_length);
3920 }
3921 goto done;
3922 }
3923 /* Transfer retrieved data out from internal buffer */
3924 for (idx = 0; idx < read_len; idx++) {
3925 ((unsigned char *)read_data)[idx] =
3926 hdw->ctl_read_buffer[idx];
3927 }
3928 }
3929
3930 done:
3931
3932 hdw->cmd_debug_state = 0;
3933 if ((status < 0) && (!probe_fl)) {
681c7399 3934 pvr2_hdw_render_useless(hdw);
d855497e
MI		 3935 }
3936 return status;
3937}
3938
3939
3940int pvr2_send_request(struct pvr2_hdw *hdw,
3941 void *write_data,unsigned int write_len,
3942 void *read_data,unsigned int read_len)
3943{
3944 return pvr2_send_request_ex(hdw,HZ*4,0,
3945 write_data,write_len,
3946 read_data,read_len);
3947}
3948
1c9d10d4
MI		 3949
3950static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3951{
3952 int ret;
3953 unsigned int cnt = 1;
3954 unsigned int args = 0;
3955 LOCK_TAKE(hdw->ctl_lock);
3956 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3957 args = (cmdcode >> 8) & 0xffu;
3958 args = (args > 2) ? 2 : args;
3959 if (args) {
3960 cnt += args;
3961 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3962 if (args > 1) {
3963 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3964 }
3965 }
3966 if (pvrusb2_debug & PVR2_TRACE_INIT) {
3967 unsigned int idx;
3968 unsigned int ccnt,bcnt;
3969 char tbuf[50];
3970 cmdcode &= 0xffu;
3971 bcnt = 0;
3972 ccnt = scnprintf(tbuf+bcnt,
3973 sizeof(tbuf)-bcnt,
3974 "Sending FX2 command 0x%x",cmdcode);
3975 bcnt += ccnt;
3976 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3977 if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3978 ccnt = scnprintf(tbuf+bcnt,
3979 sizeof(tbuf)-bcnt,
3980 " \"%s\"",
3981 pvr2_fx2cmd_desc[idx].desc);
3982 bcnt += ccnt;
3983 break;
3984 }
3985 }
3986 if (args) {
3987 ccnt = scnprintf(tbuf+bcnt,
3988 sizeof(tbuf)-bcnt,
3989 " (%u",hdw->cmd_buffer[1]);
3990 bcnt += ccnt;
3991 if (args > 1) {
3992 ccnt = scnprintf(tbuf+bcnt,
3993 sizeof(tbuf)-bcnt,
3994 ",%u",hdw->cmd_buffer[2]);
3995 bcnt += ccnt;
3996 }
3997 ccnt = scnprintf(tbuf+bcnt,
3998 sizeof(tbuf)-bcnt,
3999 ")");
4000 bcnt += ccnt;
4001 }
4002 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
4003 }
4004 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
4005 LOCK_GIVE(hdw->ctl_lock);
4006 return ret;
4007}
4008
4009
d855497e
MI		 4010int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
4011{
4012 int ret;
4013
4014 LOCK_TAKE(hdw->ctl_lock);
4015
8d364363 4016 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
d855497e
MI		 4017 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
4018 hdw->cmd_buffer[5] = 0;
4019 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4020 hdw->cmd_buffer[7] = reg & 0xff;
4021
4022
4023 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4024
4025 LOCK_GIVE(hdw->ctl_lock);
4026
4027 return ret;
4028}
4029
4030
07e337ee 4031static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
d855497e
MI		 4032{
4033 int ret = 0;
4034
4035 LOCK_TAKE(hdw->ctl_lock);
4036
8d364363 4037 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
d855497e
MI		 4038 hdw->cmd_buffer[1] = 0;
4039 hdw->cmd_buffer[2] = 0;
4040 hdw->cmd_buffer[3] = 0;
4041 hdw->cmd_buffer[4] = 0;
4042 hdw->cmd_buffer[5] = 0;
4043 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4044 hdw->cmd_buffer[7] = reg & 0xff;
4045
4046 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4047 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4048
4049 LOCK_GIVE(hdw->ctl_lock);
4050
4051 return ret;
4052}
4053
4054
681c7399 4055void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
d855497e
MI		 4056{
4057 if (!hdw->flag_ok) return;
681c7399
MI		 4058 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4059 "Device being rendered inoperable");
d855497e 4060 if (hdw->vid_stream) {
a0fd1cb1 4061 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
d855497e 4062 }
681c7399
MI		 4063 hdw->flag_ok = 0;
4064 trace_stbit("flag_ok",hdw->flag_ok);
4065 pvr2_hdw_state_sched(hdw);
d855497e
MI		 4066}
4067
4068
4069void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4070{
4071 int ret;
4072 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
a0fd1cb1 4073 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
011b15df 4074 if (ret == 0) {
d855497e
MI		 4075 ret = usb_reset_device(hdw->usb_dev);
4076 usb_unlock_device(hdw->usb_dev);
4077 } else {
4078 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4079 "Failed to lock USB device ret=%d",ret);
4080 }
4081 if (init_pause_msec) {
4082 pvr2_trace(PVR2_TRACE_INFO,
4083 "Waiting %u msec for hardware to settle",
4084 init_pause_msec);
4085 msleep(init_pause_msec);
4086 }
4087
4088}
4089
4090
4091void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4092{
6861800c 4093 char *da;
d855497e
MI		 4094 unsigned int pipe;
4095 int ret;
4096
4097 if (!hdw->usb_dev) return;
4098
6861800c
MI		 4099 da = kmalloc(16, GFP_KERNEL);
4100
4101 if (da == NULL) {
4102 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4103 "Unable to allocate memory to control CPU reset");
4104 return;
4105 }
4106
d855497e
MI		 4107 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4108
4109 da[0] = val ? 0x01 : 0x00;
4110
4111 /* Write the CPUCS register on the 8051. The lsb of the register
4112 is the reset bit; a 1 asserts reset while a 0 clears it. */
4113 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4114 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4115 if (ret < 0) {
4116 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4117 "cpureset_assert(%d) error=%d",val,ret);
4118 pvr2_hdw_render_useless(hdw);
4119 }
6861800c
MI		 4120
4121 kfree(da);
d855497e
MI		 4122}
4123
4124
4125int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4126{
1c9d10d4 4127 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
d855497e
MI		 4128}
4129
4130
e1edb19a
MK		 4131int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4132{
1c9d10d4 4133 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
e1edb19a
MK		 4134}
4135
1c9d10d4 4136
e1edb19a
MK		 4137int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4138{
1c9d10d4 4139 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
e1edb19a
MK		 4140}
4141
d855497e
MI		 4142
4143int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4144{
af78e16b
MI		 4145 pvr2_trace(PVR2_TRACE_INIT,
4146 "Requesting decoder reset");
af78e16b
MI		 4147 if (hdw->decoder_client_id) {
4148 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4149 core, reset, 0);
e17d787c 4150 pvr2_hdw_cx25840_vbi_hack(hdw);
af78e16b 4151 return 0;
d855497e 4152 }
d855497e 4153 pvr2_trace(PVR2_TRACE_INIT,
af78e16b
MI		 4154 "Unable to reset decoder: nothing attached");
4155 return -ENOTTY;
d855497e
MI		 4156}
4157
4158
62433e31 4159static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
84147f3d 4160{
1c9d10d4
MI		 4161 hdw->flag_ok = !0;
4162 return pvr2_issue_simple_cmd(hdw,
4163 FX2CMD_HCW_DEMOD_RESETIN |
4164 (1 << 8) |
4165 ((onoff ? 1 : 0) << 16));
84147f3d
MI		 4166}
4167
84147f3d 4168
62433e31 4169static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
84147f3d 4170{
1c9d10d4
MI		 4171 hdw->flag_ok = !0;
4172 return pvr2_issue_simple_cmd(hdw,(onoff ?
4173 FX2CMD_ONAIR_DTV_POWER_ON :
4174 FX2CMD_ONAIR_DTV_POWER_OFF));
84147f3d
MI		 4175}
4176
62433e31
MI		 4177
4178static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4179 int onoff)
84147f3d 4180{
1c9d10d4
MI		 4181 return pvr2_issue_simple_cmd(hdw,(onoff ?
4182 FX2CMD_ONAIR_DTV_STREAMING_ON :
4183 FX2CMD_ONAIR_DTV_STREAMING_OFF));
84147f3d
MI		 4184}
4185
62433e31
MI		 4186
4187static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4188{
4189 int cmode;
4190 /* Compare digital/analog desired setting with current setting. If
4191 they don't match, fix it... */
4192 cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4193 if (cmode == hdw->pathway_state) {
4194 /* They match; nothing to do */
4195 return;
4196 }
4197
4198 switch (hdw->hdw_desc->digital_control_scheme) {
4199 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4200 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4201 if (cmode == PVR2_PATHWAY_ANALOG) {
4202 /* If moving to analog mode, also force the decoder
4203 to reset. If no decoder is attached, then it's
4204 ok to ignore this because if/when the decoder
4205 attaches, it will reset itself at that time. */
4206 pvr2_hdw_cmd_decoder_reset(hdw);
4207 }
4208 break;
4209 case PVR2_DIGITAL_SCHEME_ONAIR:
4210 /* Supposedly we should always have the power on whether in
4211 digital or analog mode. But for now do what appears to
4212 work... */
bb0c2fe0 4213 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
62433e31
MI		 4214 break;
4215 default: break;
4216 }
4217
1b9c18c5 4218 pvr2_hdw_untrip_unlocked(hdw);
62433e31
MI		 4219 hdw->pathway_state = cmode;
4220}
4221
4222
e9b59f6e 4223static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
c55a97d7
MI		 4224{
4225 /* change some GPIO data
4226 *
4227 * note: bit d7 of dir appears to control the LED,
4228 * so we shut it off here.
4229 *
c55a97d7 4230 */
40381cb0 4231 if (onoff) {
c55a97d7 4232 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
40381cb0 4233 } else {
c55a97d7 4234 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
40381cb0 4235 }
c55a97d7 4236 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
40381cb0 4237}
c55a97d7 4238
40381cb0
MI		 4239
4240typedef void (*led_method_func)(struct pvr2_hdw *,int);
4241
4242static led_method_func led_methods[] = {
4243 [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4244};
4245
4246
4247/* Toggle LED */
4248static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4249{
4250 unsigned int scheme_id;
4251 led_method_func fp;
4252
4253 if ((!onoff) == (!hdw->led_on)) return;
4254
4255 hdw->led_on = onoff != 0;
4256
4257 scheme_id = hdw->hdw_desc->led_scheme;
4258 if (scheme_id < ARRAY_SIZE(led_methods)) {
4259 fp = led_methods[scheme_id];
4260 } else {
4261 fp = NULL;
4262 }
4263
4264 if (fp) (*fp)(hdw,onoff);
c55a97d7
MI		 4265}
4266
4267
e61b6fc5 4268/* Stop / start video stream transport */
07e337ee 4269static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
d855497e 4270{
bb0c2fe0
MI		 4271 int ret;
4272
4273 /* If we're in analog mode, then just issue the usual analog
4274 command. */
4275 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4276 return pvr2_issue_simple_cmd(hdw,
4277 (runFl ?
4278 FX2CMD_STREAMING_ON :
4279 FX2CMD_STREAMING_OFF));
4280 /*Note: Not reached */
4281 }
4282
4283 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4284 /* Whoops, we don't know what mode we're in... */
4285 return -EINVAL;
4286 }
4287
4288 /* To get here we have to be in digital mode. The mechanism here
4289 is unfortunately different for different vendors. So we switch
4290 on the device's digital scheme attribute in order to figure out
4291 what to do. */
4292 switch (hdw->hdw_desc->digital_control_scheme) {
4293 case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4294 return pvr2_issue_simple_cmd(hdw,
4295 (runFl ?
4296 FX2CMD_HCW_DTV_STREAMING_ON :
4297 FX2CMD_HCW_DTV_STREAMING_OFF));
4298 case PVR2_DIGITAL_SCHEME_ONAIR:
4299 ret = pvr2_issue_simple_cmd(hdw,
4300 (runFl ?
4301 FX2CMD_STREAMING_ON :
4302 FX2CMD_STREAMING_OFF));
4303 if (ret) return ret;
4304 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4305 default:
4306 return -EINVAL;
62433e31 4307 }
d855497e
MI		 4308}
4309
4310
62433e31
MI		 4311/* Evaluate whether or not state_pathway_ok can change */
4312static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4313{
4314 if (hdw->state_pathway_ok) {
4315 /* Nothing to do if pathway is already ok */
4316 return 0;
4317 }
4318 if (!hdw->state_pipeline_idle) {
4319 /* Not allowed to change anything if pipeline is not idle */
4320 return 0;
4321 }
4322 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4323 hdw->state_pathway_ok = !0;
e9db1ff2 4324 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
62433e31
MI		 4325 return !0;
4326}
4327
4328
681c7399
MI		 4329/* Evaluate whether or not state_encoder_ok can change */
4330static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4331{
4332 if (hdw->state_encoder_ok) return 0;
4333 if (hdw->flag_tripped) return 0;
4334 if (hdw->state_encoder_run) return 0;
4335 if (hdw->state_encoder_config) return 0;
4336 if (hdw->state_decoder_run) return 0;
4337 if (hdw->state_usbstream_run) return 0;
72998b71
MI		 4338 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4339 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4340 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4341 return 0;
4342 }
4343
681c7399
MI		 4344 if (pvr2_upload_firmware2(hdw) < 0) {
4345 hdw->flag_tripped = !0;
4346 trace_stbit("flag_tripped",hdw->flag_tripped);
4347 return !0;
4348 }
4349 hdw->state_encoder_ok = !0;
4350 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4351 return !0;
4352}
4353
4354
4355/* Evaluate whether or not state_encoder_config can change */
4356static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4357{
4358 if (hdw->state_encoder_config) {
4359 if (hdw->state_encoder_ok) {
4360 if (hdw->state_pipeline_req &&
4361 !hdw->state_pipeline_pause) return 0;
4362 }
4363 hdw->state_encoder_config = 0;
4364 hdw->state_encoder_waitok = 0;
4365 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4366 /* paranoia - solve race if timer just completed */
4367 del_timer_sync(&hdw->encoder_wait_timer);
4368 } else {
62433e31
MI		 4369 if (!hdw->state_pathway_ok ||
4370 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4371 !hdw->state_encoder_ok ||
681c7399
MI		 4372 !hdw->state_pipeline_idle ||
4373 hdw->state_pipeline_pause ||
4374 !hdw->state_pipeline_req ||
4375 !hdw->state_pipeline_config) {
4376 /* We must reset the enforced wait interval if
4377 anything has happened that might have disturbed
4378 the encoder. This should be a rare case. */
4379 if (timer_pending(&hdw->encoder_wait_timer)) {
4380 del_timer_sync(&hdw->encoder_wait_timer);
4381 }
4382 if (hdw->state_encoder_waitok) {
4383 /* Must clear the state - therefore we did
4384 something to a state bit and must also
4385 return true. */
4386 hdw->state_encoder_waitok = 0;
4387 trace_stbit("state_encoder_waitok",
4388 hdw->state_encoder_waitok);
4389 return !0;
4390 }
4391 return 0;
4392 }
4393 if (!hdw->state_encoder_waitok) {
4394 if (!timer_pending(&hdw->encoder_wait_timer)) {
4395 /* waitok flag wasn't set and timer isn't
4396 running. Check flag once more to avoid
4397 a race then start the timer. This is
4398 the point when we measure out a minimal
4399 quiet interval before doing something to
4400 the encoder. */
4401 if (!hdw->state_encoder_waitok) {
4402 hdw->encoder_wait_timer.expires =
83ce57aa
MI		 4403 jiffies +
4404 (HZ * TIME_MSEC_ENCODER_WAIT
4405 / 1000);
681c7399
MI		 4406 add_timer(&hdw->encoder_wait_timer);
4407 }
4408 }
4409 /* We can't continue until we know we have been
4410 quiet for the interval measured by this
4411 timer. */
4412 return 0;
4413 }
4414 pvr2_encoder_configure(hdw);
4415 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4416 }
4417 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4418 return !0;
4419}
4420
4421
d913d630
MI		 4422/* Return true if the encoder should not be running. */
4423static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4424{
4425 if (!hdw->state_encoder_ok) {
4426 /* Encoder isn't healthy at the moment, so stop it. */
4427 return !0;
4428 }
4429 if (!hdw->state_pathway_ok) {
4430 /* Mode is not understood at the moment (i.e. it wants to
4431 change), so encoder must be stopped. */
4432 return !0;
4433 }
4434
4435 switch (hdw->pathway_state) {
4436 case PVR2_PATHWAY_ANALOG:
4437 if (!hdw->state_decoder_run) {
4438 /* We're in analog mode and the decoder is not
4439 running; thus the encoder should be stopped as
4440 well. */
4441 return !0;
4442 }
4443 break;
4444 case PVR2_PATHWAY_DIGITAL:
4445 if (hdw->state_encoder_runok) {
4446 /* This is a funny case. We're in digital mode so
4447 really the encoder should be stopped. However
4448 if it really is running, only kill it after
4449 runok has been set. This gives a chance for the
4450 onair quirk to function (encoder must run
4451 briefly first, at least once, before onair
4452 digital streaming can work). */
4453 return !0;
4454 }
4455 break;
4456 default:
4457 /* Unknown mode; so encoder should be stopped. */
4458 return !0;
4459 }
4460
4461 /* If we get here, we haven't found a reason to stop the
4462 encoder. */
4463 return 0;
4464}
4465
4466
4467/* Return true if the encoder should be running. */
4468static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4469{
4470 if (!hdw->state_encoder_ok) {
4471 /* Don't run the encoder if it isn't healthy... */
4472 return 0;
4473 }
4474 if (!hdw->state_pathway_ok) {
4475 /* Don't run the encoder if we don't (yet) know what mode
4476 we need to be in... */
4477 return 0;
4478 }
4479
4480 switch (hdw->pathway_state) {
4481 case PVR2_PATHWAY_ANALOG:
6e931375 4482 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
d913d630
MI		 4483 /* In analog mode, if the decoder is running, then
4484 run the encoder. */
4485 return !0;
4486 }
4487 break;
4488 case PVR2_PATHWAY_DIGITAL:
4489 if ((hdw->hdw_desc->digital_control_scheme ==
4490 PVR2_DIGITAL_SCHEME_ONAIR) &&
4491 !hdw->state_encoder_runok) {
4492 /* This is a quirk. OnAir hardware won't stream
4493 digital until the encoder has been run at least
4494 once, for a minimal period of time (empiricially
4495 measured to be 1/4 second). So if we're on
4496 OnAir hardware and the encoder has never been
4497 run at all, then start the encoder. Normal
4498 state machine logic in the driver will
4499 automatically handle the remaining bits. */
4500 return !0;
4501 }
4502 break;
4503 default:
4504 /* For completeness (unknown mode; encoder won't run ever) */
4505 break;
4506 }
4507 /* If we get here, then we haven't found any reason to run the
4508 encoder, so don't run it. */
4509 return 0;
4510}
4511
4512
681c7399
MI		 4513/* Evaluate whether or not state_encoder_run can change */
4514static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4515{
4516 if (hdw->state_encoder_run) {
d913d630 4517 if (!state_check_disable_encoder_run(hdw)) return 0;
681c7399 4518 if (hdw->state_encoder_ok) {
d913d630 4519 del_timer_sync(&hdw->encoder_run_timer);
681c7399
MI		 4520 if (pvr2_encoder_stop(hdw) < 0) return !0;
4521 }
4522 hdw->state_encoder_run = 0;
4523 } else {
d913d630 4524 if (!state_check_enable_encoder_run(hdw)) return 0;
681c7399
MI		 4525 if (pvr2_encoder_start(hdw) < 0) return !0;
4526 hdw->state_encoder_run = !0;
d913d630
MI		 4527 if (!hdw->state_encoder_runok) {
4528 hdw->encoder_run_timer.expires =
83ce57aa 4529 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
d913d630
MI		 4530 add_timer(&hdw->encoder_run_timer);
4531 }
681c7399
MI		 4532 }
4533 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4534 return !0;
4535}
4536
4537
4538/* Timeout function for quiescent timer. */
4539static void pvr2_hdw_quiescent_timeout(unsigned long data)
4540{
4541 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4542 hdw->state_decoder_quiescent = !0;
4543 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4544 hdw->state_stale = !0;
4545 queue_work(hdw->workqueue,&hdw->workpoll);
4546}
4547
4548
6e931375
MI		 4549/* Timeout function for decoder stabilization timer. */
4550static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4551{
4552 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4553 hdw->state_decoder_ready = !0;
4554 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4555 hdw->state_stale = !0;
4556 queue_work(hdw->workqueue, &hdw->workpoll);
4557}
4558
4559
681c7399
MI		 4560/* Timeout function for encoder wait timer. */
4561static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4562{
4563 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4564 hdw->state_encoder_waitok = !0;
4565 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4566 hdw->state_stale = !0;
4567 queue_work(hdw->workqueue,&hdw->workpoll);
4568}
4569
4570
d913d630
MI		 4571/* Timeout function for encoder run timer. */
4572static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4573{
4574 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4575 if (!hdw->state_encoder_runok) {
4576 hdw->state_encoder_runok = !0;
4577 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4578 hdw->state_stale = !0;
4579 queue_work(hdw->workqueue,&hdw->workpoll);
4580 }
4581}
4582
4583
681c7399
MI		 4584/* Evaluate whether or not state_decoder_run can change */
4585static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4586{
4587 if (hdw->state_decoder_run) {
4588 if (hdw->state_encoder_ok) {
4589 if (hdw->state_pipeline_req &&
62433e31
MI		 4590 !hdw->state_pipeline_pause &&
4591 hdw->state_pathway_ok) return 0;
681c7399
MI		 4592 }
4593 if (!hdw->flag_decoder_missed) {
4594 pvr2_decoder_enable(hdw,0);
4595 }
4596 hdw->state_decoder_quiescent = 0;
4597 hdw->state_decoder_run = 0;
6e931375 4598 /* paranoia - solve race if timer(s) just completed */
681c7399 4599 del_timer_sync(&hdw->quiescent_timer);
6e931375
MI		 4600 /* Kill the stabilization timer, in case we're killing the
4601 encoder before the previous stabilization interval has
4602 been properly timed. */
4603 del_timer_sync(&hdw->decoder_stabilization_timer);
4604 hdw->state_decoder_ready = 0;
681c7399
MI		 4605 } else {
4606 if (!hdw->state_decoder_quiescent) {
4607 if (!timer_pending(&hdw->quiescent_timer)) {
4608 /* We don't do something about the
4609 quiescent timer until right here because
4610 we also want to catch cases where the
4611 decoder was already not running (like
4612 after initialization) as opposed to
4613 knowing that we had just stopped it.
4614 The second flag check is here to cover a
4615 race - the timer could have run and set
4616 this flag just after the previous check
4617 but before we did the pending check. */
4618 if (!hdw->state_decoder_quiescent) {
4619 hdw->quiescent_timer.expires =
83ce57aa
MI		 4620 jiffies +
4621 (HZ * TIME_MSEC_DECODER_WAIT
4622 / 1000);
681c7399
MI		 4623 add_timer(&hdw->quiescent_timer);
4624 }
4625 }
4626 /* Don't allow decoder to start again until it has
4627 been quiesced first. This little detail should
4628 hopefully further stabilize the encoder. */
4629 return 0;
4630 }
62433e31
MI		 4631 if (!hdw->state_pathway_ok ||
4632 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4633 !hdw->state_pipeline_req ||
681c7399
MI		 4634 hdw->state_pipeline_pause ||
4635 !hdw->state_pipeline_config ||
4636 !hdw->state_encoder_config ||
4637 !hdw->state_encoder_ok) return 0;
4638 del_timer_sync(&hdw->quiescent_timer);
4639 if (hdw->flag_decoder_missed) return 0;
4640 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4641 hdw->state_decoder_quiescent = 0;
6e931375 4642 hdw->state_decoder_ready = 0;
681c7399 4643 hdw->state_decoder_run = !0;
fb640224
MI		 4644 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4645 hdw->decoder_stabilization_timer.expires =
4646 jiffies +
4647 (HZ * TIME_MSEC_DECODER_STABILIZATION_WAIT /
4648 1000);
4649 add_timer(&hdw->decoder_stabilization_timer);
4650 } else {
4651 hdw->state_decoder_ready = !0;
4652 }
681c7399
MI		 4653 }
4654 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4655 trace_stbit("state_decoder_run",hdw->state_decoder_run);
6e931375 4656 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
681c7399
MI		 4657 return !0;
4658}
4659
4660
4661/* Evaluate whether or not state_usbstream_run can change */
4662static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4663{
4664 if (hdw->state_usbstream_run) {
72998b71 4665 int fl = !0;
62433e31 4666 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
72998b71
MI		 4667 fl = (hdw->state_encoder_ok &&
4668 hdw->state_encoder_run);
4669 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4670 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4671 fl = hdw->state_encoder_ok;
4672 }
4673 if (fl &&
4674 hdw->state_pipeline_req &&
4675 !hdw->state_pipeline_pause &&
4676 hdw->state_pathway_ok) {
4677 return 0;
681c7399
MI		 4678 }
4679 pvr2_hdw_cmd_usbstream(hdw,0);
4680 hdw->state_usbstream_run = 0;
4681 } else {
62433e31
MI		 4682 if (!hdw->state_pipeline_req ||
4683 hdw->state_pipeline_pause ||
4684 !hdw->state_pathway_ok) return 0;
4685 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4686 if (!hdw->state_encoder_ok ||
4687 !hdw->state_encoder_run) return 0;
72998b71
MI		 4688 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4689 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4690 if (!hdw->state_encoder_ok) return 0;
d913d630
MI		 4691 if (hdw->state_encoder_run) return 0;
4692 if (hdw->hdw_desc->digital_control_scheme ==
4693 PVR2_DIGITAL_SCHEME_ONAIR) {
4694 /* OnAir digital receivers won't stream
4695 unless the analog encoder has run first.
4696 Why? I have no idea. But don't even
4697 try until we know the analog side is
4698 known to have run. */
4699 if (!hdw->state_encoder_runok) return 0;
4700 }
62433e31 4701 }
681c7399
MI		 4702 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4703 hdw->state_usbstream_run = !0;
4704 }
4705 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4706 return !0;
4707}
4708
4709
4710/* Attempt to configure pipeline, if needed */
4711static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4712{
4713 if (hdw->state_pipeline_config ||
4714 hdw->state_pipeline_pause) return 0;
4715 pvr2_hdw_commit_execute(hdw);
4716 return !0;
4717}
4718
4719
4720/* Update pipeline idle and pipeline pause tracking states based on other
4721 inputs. This must be called whenever the other relevant inputs have
4722 changed. */
4723static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4724{
4725 unsigned int st;
4726 int updatedFl = 0;
4727 /* Update pipeline state */
4728 st = !(hdw->state_encoder_run ||
4729 hdw->state_decoder_run ||
4730 hdw->state_usbstream_run ||
4731 (!hdw->state_decoder_quiescent));
4732 if (!st != !hdw->state_pipeline_idle) {
4733 hdw->state_pipeline_idle = st;
4734 updatedFl = !0;
4735 }
4736 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4737 hdw->state_pipeline_pause = 0;
4738 updatedFl = !0;
4739 }
4740 return updatedFl;
4741}
4742
4743
4744typedef int (*state_eval_func)(struct pvr2_hdw *);
4745
4746/* Set of functions to be run to evaluate various states in the driver. */
ebff0330 4747static const state_eval_func eval_funcs[] = {
62433e31 4748 state_eval_pathway_ok,
681c7399
MI		 4749 state_eval_pipeline_config,
4750 state_eval_encoder_ok,
4751 state_eval_encoder_config,
4752 state_eval_decoder_run,
4753 state_eval_encoder_run,
4754 state_eval_usbstream_run,
4755};
4756
4757
4758/* Process various states and return true if we did anything interesting. */
4759static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4760{
4761 unsigned int i;
4762 int state_updated = 0;
4763 int check_flag;
4764
4765 if (!hdw->state_stale) return 0;
4766 if ((hdw->fw1_state != FW1_STATE_OK) ||
4767 !hdw->flag_ok) {
4768 hdw->state_stale = 0;
4769 return !0;
4770 }
4771 /* This loop is the heart of the entire driver. It keeps trying to
4772 evaluate various bits of driver state until nothing changes for
4773 one full iteration. Each "bit of state" tracks some global
4774 aspect of the driver, e.g. whether decoder should run, if
4775 pipeline is configured, usb streaming is on, etc. We separately
4776 evaluate each of those questions based on other driver state to
4777 arrive at the correct running configuration. */
4778 do {
4779 check_flag = 0;
4780 state_update_pipeline_state(hdw);
4781 /* Iterate over each bit of state */
4782 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4783 if ((*eval_funcs[i])(hdw)) {
4784 check_flag = !0;
4785 state_updated = !0;
4786 state_update_pipeline_state(hdw);
4787 }
4788 }
4789 } while (check_flag && hdw->flag_ok);
4790 hdw->state_stale = 0;
4791 trace_stbit("state_stale",hdw->state_stale);
4792 return state_updated;
4793}
4794
4795
1cb03b76
MI		 4796static unsigned int print_input_mask(unsigned int msk,
4797 char *buf,unsigned int acnt)
4798{
4799 unsigned int idx,ccnt;
4800 unsigned int tcnt = 0;
4801 for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4802 if (!((1 << idx) & msk)) continue;
4803 ccnt = scnprintf(buf+tcnt,
4804 acnt-tcnt,
4805 "%s%s",
4806 (tcnt ? ", " : ""),
4807 control_values_input[idx]);
4808 tcnt += ccnt;
4809 }
4810 return tcnt;
4811}
4812
4813
62433e31
MI		 4814static const char *pvr2_pathway_state_name(int id)
4815{
4816 switch (id) {
4817 case PVR2_PATHWAY_ANALOG: return "analog";
4818 case PVR2_PATHWAY_DIGITAL: return "digital";
4819 default: return "unknown";
4820 }
4821}
4822
4823
681c7399
MI		 4824static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4825 char *buf,unsigned int acnt)
4826{
4827 switch (which) {
4828 case 0:
4829 return scnprintf(
4830 buf,acnt,
e9db1ff2 4831 "driver:%s%s%s%s%s <mode=%s>",
681c7399
MI		 4832 (hdw->flag_ok ? " <ok>" : " <fail>"),
4833 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4834 (hdw->flag_disconnected ? " <disconnected>" :
4835 " <connected>"),
4836 (hdw->flag_tripped ? " <tripped>" : ""),
62433e31
MI		 4837 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4838 pvr2_pathway_state_name(hdw->pathway_state));
4839
681c7399
MI		 4840 case 1:
4841 return scnprintf(
4842 buf,acnt,
4843 "pipeline:%s%s%s%s",
4844 (hdw->state_pipeline_idle ? " <idle>" : ""),
4845 (hdw->state_pipeline_config ?
4846 " <configok>" : " <stale>"),
4847 (hdw->state_pipeline_req ? " <req>" : ""),
4848 (hdw->state_pipeline_pause ? " <pause>" : ""));
4849 case 2:
4850 return scnprintf(
4851 buf,acnt,
62433e31 4852 "worker:%s%s%s%s%s%s%s",
681c7399 4853 (hdw->state_decoder_run ?
6e931375
MI		 4854 (hdw->state_decoder_ready ?
4855 "<decode:run>" : " <decode:start>") :
681c7399
MI		 4856 (hdw->state_decoder_quiescent ?
4857 "" : " <decode:stop>")),
4858 (hdw->state_decoder_quiescent ?
4859 " <decode:quiescent>" : ""),
4860 (hdw->state_encoder_ok ?
4861 "" : " <encode:init>"),
4862 (hdw->state_encoder_run ?
d913d630
MI		 4863 (hdw->state_encoder_runok ?
4864 " <encode:run>" :
4865 " <encode:firstrun>") :
4866 (hdw->state_encoder_runok ?
4867 " <encode:stop>" :
4868 " <encode:virgin>")),
681c7399
MI		 4869 (hdw->state_encoder_config ?
4870 " <encode:configok>" :
4871 (hdw->state_encoder_waitok ?
b9a37d91 4872 "" : " <encode:waitok>")),
681c7399 4873 (hdw->state_usbstream_run ?
62433e31
MI		 4874 " <usb:run>" : " <usb:stop>"),
4875 (hdw->state_pathway_ok ?
e9db1ff2 4876 " <pathway:ok>" : ""));
681c7399
MI		 4877 case 3:
4878 return scnprintf(
4879 buf,acnt,
4880 "state: %s",
4881 pvr2_get_state_name(hdw->master_state));
ad0992e9 4882 case 4: {
1cb03b76
MI		 4883 unsigned int tcnt = 0;
4884 unsigned int ccnt;
4885
4886 ccnt = scnprintf(buf,
4887 acnt,
4888 "Hardware supported inputs: ");
4889 tcnt += ccnt;
4890 tcnt += print_input_mask(hdw->input_avail_mask,
4891 buf+tcnt,
4892 acnt-tcnt);
4893 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4894 ccnt = scnprintf(buf+tcnt,
4895 acnt-tcnt,
4896 "; allowed inputs: ");
4897 tcnt += ccnt;
4898 tcnt += print_input_mask(hdw->input_allowed_mask,
4899 buf+tcnt,
4900 acnt-tcnt);
4901 }
4902 return tcnt;
4903 }
4904 case 5: {
ad0992e9
MI		 4905 struct pvr2_stream_stats stats;
4906 if (!hdw->vid_stream) break;
4907 pvr2_stream_get_stats(hdw->vid_stream,
4908 &stats,
4909 0);
4910 return scnprintf(
4911 buf,acnt,
4912 "Bytes streamed=%u"
4913 " URBs: queued=%u idle=%u ready=%u"
4914 " processed=%u failed=%u",
4915 stats.bytes_processed,
4916 stats.buffers_in_queue,
4917 stats.buffers_in_idle,
4918 stats.buffers_in_ready,
4919 stats.buffers_processed,
4920 stats.buffers_failed);
4921 }
27eab384
MI		 4922 case 6: {
4923 unsigned int id = hdw->ir_scheme_active;
4924 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4925 (id >= ARRAY_SIZE(ir_scheme_names) ?
4926 "?" : ir_scheme_names[id]));
4927 }
2eb563b7
MI		 4928 default: break;
4929 }
4930 return 0;
4931}
4932
4933
4934/* Generate report containing info about attached sub-devices and attached
4935 i2c clients, including an indication of which attached i2c clients are
4936 actually sub-devices. */
4937static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4938 char *buf, unsigned int acnt)
4939{
4940 struct v4l2_subdev *sd;
4941 unsigned int tcnt = 0;
4942 unsigned int ccnt;
4943 struct i2c_client *client;
2eb563b7
MI		 4944 const char *p;
4945 unsigned int id;
4946
fa7ce764 4947 ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
2eb563b7
MI		 4948 tcnt += ccnt;
4949 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4950 id = sd->grp_id;
4951 p = NULL;
4952 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4953 if (p) {
fa7ce764 4954 ccnt = scnprintf(buf + tcnt, acnt - tcnt, " %s:", p);
2eb563b7
MI		 4955 tcnt += ccnt;
4956 } else {
4957 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
fa7ce764 4958 " (unknown id=%u):", id);
2eb563b7
MI		 4959 tcnt += ccnt;
4960 }
fa7ce764
JD		 4961 client = v4l2_get_subdevdata(sd);
4962 if (client) {
4963 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4964 " %s @ %02x\n", client->name,
4965 client->addr);
4966 tcnt += ccnt;
4967 } else {
4968 ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4969 " no i2c client\n");
4970 tcnt += ccnt;
858f910e 4971 }
681c7399 4972 }
2eb563b7 4973 return tcnt;
681c7399
MI		 4974}
4975
4976
4977unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4978 char *buf,unsigned int acnt)
4979{
4980 unsigned int bcnt,ccnt,idx;
4981 bcnt = 0;
4982 LOCK_TAKE(hdw->big_lock);
4983 for (idx = 0; ; idx++) {
4984 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4985 if (!ccnt) break;
4986 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4987 if (!acnt) break;
4988 buf[0] = '\n'; ccnt = 1;
4989 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4990 }
2eb563b7
MI		 4991 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4992 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
681c7399
MI		 4993 LOCK_GIVE(hdw->big_lock);
4994 return bcnt;
4995}
4996
4997
4998static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4999{
2eb563b7
MI		 5000 char buf[256];
5001 unsigned int idx, ccnt;
5002 unsigned int lcnt, ucnt;
681c7399
MI		 5003
5004 for (idx = 0; ; idx++) {
5005 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
5006 if (!ccnt) break;
5007 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
5008 }
2eb563b7
MI		 5009 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
5010 ucnt = 0;
5011 while (ucnt < ccnt) {
5012 lcnt = 0;
5013 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
5014 lcnt++;
5015 }
5016 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
5017 ucnt += lcnt + 1;
5018 }
681c7399
MI		 5019}
5020
5021
5022/* Evaluate and update the driver's current state, taking various actions
5023 as appropriate for the update. */
5024static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
5025{
5026 unsigned int st;
5027 int state_updated = 0;
5028 int callback_flag = 0;
1b9c18c5 5029 int analog_mode;
681c7399
MI		 5030
5031 pvr2_trace(PVR2_TRACE_STBITS,
5032 "Drive state check START");
5033 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5034 pvr2_hdw_state_log_state(hdw);
5035 }
5036
5037 /* Process all state and get back over disposition */
5038 state_updated = pvr2_hdw_state_update(hdw);
5039
1b9c18c5
MI		 5040 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
5041
681c7399
MI		 5042 /* Update master state based upon all other states. */
5043 if (!hdw->flag_ok) {
5044 st = PVR2_STATE_DEAD;
5045 } else if (hdw->fw1_state != FW1_STATE_OK) {
5046 st = PVR2_STATE_COLD;
72998b71
MI		 5047 } else if ((analog_mode ||
5048 hdw->hdw_desc->flag_digital_requires_cx23416) &&
5049 !hdw->state_encoder_ok) {
681c7399 5050 st = PVR2_STATE_WARM;
1b9c18c5
MI		 5051 } else if (hdw->flag_tripped ||
5052 (analog_mode && hdw->flag_decoder_missed)) {
681c7399 5053 st = PVR2_STATE_ERROR;
62433e31 5054 } else if (hdw->state_usbstream_run &&
1b9c18c5 5055 (!analog_mode ||
62433e31 5056 (hdw->state_encoder_run && hdw->state_decoder_run))) {
681c7399
MI		 5057 st = PVR2_STATE_RUN;
5058 } else {
5059 st = PVR2_STATE_READY;
5060 }
5061 if (hdw->master_state != st) {
5062 pvr2_trace(PVR2_TRACE_STATE,
5063 "Device state change from %s to %s",
5064 pvr2_get_state_name(hdw->master_state),
5065 pvr2_get_state_name(st));
40381cb0 5066 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
681c7399
MI		 5067 hdw->master_state = st;
5068 state_updated = !0;
5069 callback_flag = !0;
5070 }
5071 if (state_updated) {
5072 /* Trigger anyone waiting on any state changes here. */
5073 wake_up(&hdw->state_wait_data);
5074 }
5075
5076 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5077 pvr2_hdw_state_log_state(hdw);
5078 }
5079 pvr2_trace(PVR2_TRACE_STBITS,
5080 "Drive state check DONE callback=%d",callback_flag);
5081
5082 return callback_flag;
5083}
5084
5085
5086/* Cause kernel thread to check / update driver state */
5087static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5088{
5089 if (hdw->state_stale) return;
5090 hdw->state_stale = !0;
5091 trace_stbit("state_stale",hdw->state_stale);
5092 queue_work(hdw->workqueue,&hdw->workpoll);
5093}
5094
5095
d855497e
MI		 5096int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5097{
5098 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5099}
5100
5101
5102int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5103{
5104 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5105}
5106
5107
5108int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5109{
5110 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5111}
5112
5113
5114int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5115{
5116 u32 cval,nval;
5117 int ret;
5118 if (~msk) {
5119 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5120 if (ret) return ret;
5121 nval = (cval & ~msk) | (val & msk);
5122 pvr2_trace(PVR2_TRACE_GPIO,
5123 "GPIO direction changing 0x%x:0x%x"
5124 " from 0x%x to 0x%x",
5125 msk,val,cval,nval);
5126 } else {
5127 nval = val;
5128 pvr2_trace(PVR2_TRACE_GPIO,
5129 "GPIO direction changing to 0x%x",nval);
5130 }
5131 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5132}
5133
5134
5135int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5136{
5137 u32 cval,nval;
5138 int ret;
5139 if (~msk) {
5140 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5141 if (ret) return ret;
5142 nval = (cval & ~msk) | (val & msk);
5143 pvr2_trace(PVR2_TRACE_GPIO,
5144 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5145 msk,val,cval,nval);
5146 } else {
5147 nval = val;
5148 pvr2_trace(PVR2_TRACE_GPIO,
5149 "GPIO output changing to 0x%x",nval);
5150 }
5151 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5152}
5153
5154
a51f5000
MI		 5155void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5156{
40f07111
MI		 5157 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5158 memset(vtp, 0, sizeof(*vtp));
2641df36 5159 hdw->tuner_signal_stale = 0;
40f07111
MI		 5160 /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5161 using v4l2-subdev - therefore we can't support that AT ALL right
5162 now. (Of course, no sub-drivers seem to implement it either.
5163 But now it's a a chicken and egg problem...) */
5164 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5165 &hdw->tuner_signal_info);
2641df36 5166 pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
40f07111
MI		 5167 " type=%u strength=%u audio=0x%x cap=0x%x"
5168 " low=%u hi=%u",
5169 vtp->type,
5170 vtp->signal, vtp->rxsubchans, vtp->capability,
5171 vtp->rangelow, vtp->rangehigh);
2641df36
MI		 5172
5173 /* We have to do this to avoid getting into constant polling if
5174 there's nobody to answer a poll of cropcap info. */
5175 hdw->cropcap_stale = 0;
a51f5000
MI		 5176}
5177
5178
7fb20fa3
MI		 5179unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5180{
5181 return hdw->input_avail_mask;
5182}
5183
5184
1cb03b76
MI		 5185unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5186{
5187 return hdw->input_allowed_mask;
5188}
5189
5190
5191static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5192{
5193 if (hdw->input_val != v) {
5194 hdw->input_val = v;
5195 hdw->input_dirty = !0;
5196 }
5197
5198 /* Handle side effects - if we switch to a mode that needs the RF
5199 tuner, then select the right frequency choice as well and mark
5200 it dirty. */
5201 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5202 hdw->freqSelector = 0;
5203 hdw->freqDirty = !0;
5204 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5205 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5206 hdw->freqSelector = 1;
5207 hdw->freqDirty = !0;
5208 }
5209 return 0;
5210}
5211
5212
5213int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5214 unsigned int change_mask,
5215 unsigned int change_val)
5216{
5217 int ret = 0;
5218 unsigned int nv,m,idx;
5219 LOCK_TAKE(hdw->big_lock);
5220 do {
5221 nv = hdw->input_allowed_mask & ~change_mask;
5222 nv |= (change_val & change_mask);
5223 nv &= hdw->input_avail_mask;
5224 if (!nv) {
5225 /* No legal modes left; return error instead. */
5226 ret = -EPERM;
5227 break;
5228 }
5229 hdw->input_allowed_mask = nv;
5230 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5231 /* Current mode is still in the allowed mask, so
5232 we're done. */
5233 break;
5234 }
5235 /* Select and switch to a mode that is still in the allowed
5236 mask */
5237 if (!hdw->input_allowed_mask) {
5238 /* Nothing legal; give up */
5239 break;
5240 }
5241 m = hdw->input_allowed_mask;
5242 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5243 if (!((1 << idx) & m)) continue;
5244 pvr2_hdw_set_input(hdw,idx);
5245 break;
5246 }
5247 } while (0);
5248 LOCK_GIVE(hdw->big_lock);
5249 return ret;
5250}
5251
5252
e61b6fc5 5253/* Find I2C address of eeprom */
07e337ee 5254static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
d855497e
MI		 5255{
5256 int result;
5257 LOCK_TAKE(hdw->ctl_lock); do {
8d364363 5258 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
d855497e
MI		 5259 result = pvr2_send_request(hdw,
5260 hdw->cmd_buffer,1,
5261 hdw->cmd_buffer,1);
5262 if (result < 0) break;
5263 result = hdw->cmd_buffer[0];
5264 } while(0); LOCK_GIVE(hdw->ctl_lock);
5265 return result;
5266}
5267
5268
32ffa9ae 5269int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
aecde8b5
HV		 5270 struct v4l2_dbg_match *match, u64 reg_id,
5271 int setFl, u64 *val_ptr)
32ffa9ae
MI		 5272{
5273#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 5274 struct v4l2_dbg_register req;
6d98816f
MI		 5275 int stat = 0;
5276 int okFl = 0;
32ffa9ae 5277
201f5c9c
MI		 5278 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5279
aecde8b5 5280 req.match = *match;
32ffa9ae
MI		 5281 req.reg = reg_id;
5282 if (setFl) req.val = *val_ptr;
d8f5b9ba
MI		 5283 /* It would be nice to know if a sub-device answered the request */
5284 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5285 if (!setFl) *val_ptr = req.val;
6d98816f
MI		 5286 if (okFl) {
5287 return stat;
5288 }
32ffa9ae
MI		 5289 return -EINVAL;
5290#else
5291 return -ENOSYS;
5292#endif
5293}
5294
5295
d855497e
MI		 5296/*
5297 Stuff for Emacs to see, in order to encourage consistent editing style:
5298 *** Local Variables: ***
5299 *** mode: c ***
5300 *** fill-column: 75 ***
5301 *** tab-width: 8 ***
5302 *** c-basic-offset: 8 ***
5303 *** End: ***
5304 */
Clone of davem's net-next-2.6 tree