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Merge branch 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...
[net-next-2.6.git] / drivers / media / video / mx1_camera.c
CommitLineData
6acc81c3
PZ		 1/*
2 * V4L2 Driver for i.MXL/i.MXL camera (CSI) host
3 *
4 * Copyright (C) 2008, Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
5 * Copyright (C) 2009, Darius Augulis <augulis.darius@gmail.com>
6 *
7 * Based on PXA SoC camera driver
8 * Copyright (C) 2006, Sascha Hauer, Pengutronix
9 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/device.h>
19#include <linux/dma-mapping.h>
20#include <linux/errno.h>
21#include <linux/fs.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/kernel.h>
26#include <linux/mm.h>
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/mutex.h>
30#include <linux/platform_device.h>
f39c1ab3 31#include <linux/sched.h>
5a0e3ad6 32#include <linux/slab.h>
6acc81c3
PZ		 33#include <linux/time.h>
34#include <linux/version.h>
35#include <linux/videodev2.h>
36
37#include <media/soc_camera.h>
38#include <media/v4l2-common.h>
39#include <media/v4l2-dev.h>
40#include <media/videobuf-dma-contig.h>
760697be 41#include <media/soc_mediabus.h>
6acc81c3
PZ		 42
43#include <asm/dma.h>
44#include <asm/fiq.h>
45#include <mach/dma-mx1-mx2.h>
46#include <mach/hardware.h>
47#include <mach/mx1_camera.h>
48
49/*
50 * CSI registers
51 */
6acc81c3
PZ		 52#define CSICR1 0x00 /* CSI Control Register 1 */
53#define CSISR 0x08 /* CSI Status Register */
54#define CSIRXR 0x10 /* CSI RxFIFO Register */
55
56#define CSICR1_RXFF_LEVEL(x) (((x) & 0x3) << 19)
57#define CSICR1_SOF_POL (1 << 17)
58#define CSICR1_SOF_INTEN (1 << 16)
59#define CSICR1_MCLKDIV(x) (((x) & 0xf) << 12)
60#define CSICR1_MCLKEN (1 << 9)
61#define CSICR1_FCC (1 << 8)
62#define CSICR1_BIG_ENDIAN (1 << 7)
63#define CSICR1_CLR_RXFIFO (1 << 5)
64#define CSICR1_GCLK_MODE (1 << 4)
65#define CSICR1_DATA_POL (1 << 2)
66#define CSICR1_REDGE (1 << 1)
67#define CSICR1_EN (1 << 0)
68
69#define CSISR_SFF_OR_INT (1 << 25)
70#define CSISR_RFF_OR_INT (1 << 24)
71#define CSISR_STATFF_INT (1 << 21)
72#define CSISR_RXFF_INT (1 << 18)
73#define CSISR_SOF_INT (1 << 16)
74#define CSISR_DRDY (1 << 0)
75
76#define VERSION_CODE KERNEL_VERSION(0, 0, 1)
77#define DRIVER_NAME "mx1-camera"
78
79#define CSI_IRQ_MASK (CSISR_SFF_OR_INT | CSISR_RFF_OR_INT | \
80 CSISR_STATFF_INT | CSISR_RXFF_INT | CSISR_SOF_INT)
81
82#define CSI_BUS_FLAGS (SOCAM_MASTER | SOCAM_HSYNC_ACTIVE_HIGH | \
83 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_VSYNC_ACTIVE_LOW | \
84 SOCAM_PCLK_SAMPLE_RISING | SOCAM_PCLK_SAMPLE_FALLING | \
85 SOCAM_DATA_ACTIVE_HIGH | SOCAM_DATA_ACTIVE_LOW | \
86 SOCAM_DATAWIDTH_8)
87
88#define MAX_VIDEO_MEM 16 /* Video memory limit in megabytes */
89
90/*
91 * Structures
92 */
93
94/* buffer for one video frame */
95struct mx1_buffer {
96 /* common v4l buffer stuff -- must be first */
760697be
GL		 97 struct videobuf_buffer vb;
98 enum v4l2_mbus_pixelcode code;
99 int inwork;
6acc81c3
PZ		 100};
101
5d28d525
GL		 102/*
103 * i.MX1/i.MXL is only supposed to handle one camera on its Camera Sensor
6acc81c3 104 * Interface. If anyone ever builds hardware to enable more than
5d28d525
GL		 105 * one camera, they will have to modify this driver too
106 */
6acc81c3 107struct mx1_camera_dev {
eb6c8558 108 struct soc_camera_host soc_host;
6acc81c3
PZ		 109 struct soc_camera_device *icd;
110 struct mx1_camera_pdata *pdata;
111 struct mx1_buffer *active;
6acc81c3
PZ		 112 struct resource *res;
113 struct clk *clk;
114 struct list_head capture;
115
116 void __iomem *base;
117 int dma_chan;
118 unsigned int irq;
119 unsigned long mclk;
120
121 spinlock_t lock;
122};
123
124/*
125 * Videobuf operations
126 */
127static int mx1_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
128 unsigned int *size)
129{
130 struct soc_camera_device *icd = vq->priv_data;
760697be
GL		 131 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
132 icd->current_fmt->host_fmt);
6acc81c3 133
760697be
GL		 134 if (bytes_per_line < 0)
135 return bytes_per_line;
136
137 *size = bytes_per_line * icd->user_height;
6acc81c3
PZ		 138
139 if (!*count)
140 *count = 32;
141
dab7e310
AB		 142 if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024)
143 *count = (MAX_VIDEO_MEM * 1024 * 1024) / *size;
6acc81c3 144
0166b743 145 dev_dbg(icd->dev.parent, "count=%d, size=%d\n", *count, *size);
6acc81c3
PZ		 146
147 return 0;
148}
149
150static void free_buffer(struct videobuf_queue *vq, struct mx1_buffer *buf)
151{
152 struct soc_camera_device *icd = vq->priv_data;
153 struct videobuf_buffer *vb = &buf->vb;
154
155 BUG_ON(in_interrupt());
156
0166b743 157 dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
6acc81c3
PZ		 158 vb, vb->baddr, vb->bsize);
159
5d28d525
GL		 160 /*
161 * This waits until this buffer is out of danger, i.e., until it is no
162 * longer in STATE_QUEUED or STATE_ACTIVE
163 */
0e0809a5 164 videobuf_waiton(vq, vb, 0, 0);
6acc81c3
PZ		 165 videobuf_dma_contig_free(vq, vb);
166
167 vb->state = VIDEOBUF_NEEDS_INIT;
168}
169
170static int mx1_videobuf_prepare(struct videobuf_queue *vq,
171 struct videobuf_buffer *vb, enum v4l2_field field)
172{
173 struct soc_camera_device *icd = vq->priv_data;
174 struct mx1_buffer *buf = container_of(vb, struct mx1_buffer, vb);
175 int ret;
760697be
GL		 176 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
177 icd->current_fmt->host_fmt);
178
179 if (bytes_per_line < 0)
180 return bytes_per_line;
6acc81c3 181
0166b743 182 dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
6acc81c3
PZ		 183 vb, vb->baddr, vb->bsize);
184
185 /* Added list head initialization on alloc */
186 WARN_ON(!list_empty(&vb->queue));
187
188 BUG_ON(NULL == icd->current_fmt);
189
5d28d525
GL		 190 /*
191 * I think, in buf_prepare you only have to protect global data,
192 * the actual buffer is yours
193 */
6acc81c3
PZ		 194 buf->inwork = 1;
195
760697be 196 if (buf->code != icd->current_fmt->code ||
6a6c8786
GL		 197 vb->width != icd->user_width ||
198 vb->height != icd->user_height ||
6acc81c3 199 vb->field != field) {
760697be 200 buf->code = icd->current_fmt->code;
6a6c8786
GL		 201 vb->width = icd->user_width;
202 vb->height = icd->user_height;
6acc81c3
PZ		 203 vb->field = field;
204 vb->state = VIDEOBUF_NEEDS_INIT;
205 }
206
760697be 207 vb->size = bytes_per_line * vb->height;
6acc81c3
PZ		 208 if (0 != vb->baddr && vb->bsize < vb->size) {
209 ret = -EINVAL;
210 goto out;
211 }
212
213 if (vb->state == VIDEOBUF_NEEDS_INIT) {
214 ret = videobuf_iolock(vq, vb, NULL);
215 if (ret)
216 goto fail;
217
218 vb->state = VIDEOBUF_PREPARED;
219 }
220
221 buf->inwork = 0;
222
223 return 0;
224
225fail:
226 free_buffer(vq, buf);
227out:
228 buf->inwork = 0;
229 return ret;
230}
231
232static int mx1_camera_setup_dma(struct mx1_camera_dev *pcdev)
233{
234 struct videobuf_buffer *vbuf = &pcdev->active->vb;
0166b743 235 struct device *dev = pcdev->icd->dev.parent;
6acc81c3
PZ		 236 int ret;
237
238 if (unlikely(!pcdev->active)) {
0166b743 239 dev_err(dev, "DMA End IRQ with no active buffer\n");
6acc81c3
PZ		 240 return -EFAULT;
241 }
242
243 /* setup sg list for future DMA */
244 ret = imx_dma_setup_single(pcdev->dma_chan,
245 videobuf_to_dma_contig(vbuf),
246 vbuf->size, pcdev->res->start +
247 CSIRXR, DMA_MODE_READ);
248 if (unlikely(ret))
0166b743 249 dev_err(dev, "Failed to setup DMA sg list\n");
6acc81c3
PZ		 250
251 return ret;
252}
253
2dd54a54 254/* Called under spinlock_irqsave(&pcdev->lock, ...) */
6acc81c3
PZ		 255static void mx1_videobuf_queue(struct videobuf_queue *vq,
256 struct videobuf_buffer *vb)
257{
258 struct soc_camera_device *icd = vq->priv_data;
259 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
260 struct mx1_camera_dev *pcdev = ici->priv;
261 struct mx1_buffer *buf = container_of(vb, struct mx1_buffer, vb);
6acc81c3 262
0166b743 263 dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
6acc81c3
PZ		 264 vb, vb->baddr, vb->bsize);
265
6acc81c3
PZ		 266 list_add_tail(&vb->queue, &pcdev->capture);
267
268 vb->state = VIDEOBUF_ACTIVE;
269
270 if (!pcdev->active) {
271 pcdev->active = buf;
272
273 /* setup sg list for future DMA */
274 if (!mx1_camera_setup_dma(pcdev)) {
275 unsigned int temp;
276 /* enable SOF irq */
277 temp = __raw_readl(pcdev->base + CSICR1) |
278 CSICR1_SOF_INTEN;
279 __raw_writel(temp, pcdev->base + CSICR1);
280 }
281 }
6acc81c3
PZ		 282}
283
284static void mx1_videobuf_release(struct videobuf_queue *vq,
285 struct videobuf_buffer *vb)
286{
287 struct mx1_buffer *buf = container_of(vb, struct mx1_buffer, vb);
288#ifdef DEBUG
289 struct soc_camera_device *icd = vq->priv_data;
0166b743 290 struct device *dev = icd->dev.parent;
6acc81c3 291
0166b743 292 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
6acc81c3
PZ		 293 vb, vb->baddr, vb->bsize);
294
295 switch (vb->state) {
296 case VIDEOBUF_ACTIVE:
0166b743 297 dev_dbg(dev, "%s (active)\n", __func__);
6acc81c3
PZ		 298 break;
299 case VIDEOBUF_QUEUED:
0166b743 300 dev_dbg(dev, "%s (queued)\n", __func__);
6acc81c3
PZ		 301 break;
302 case VIDEOBUF_PREPARED:
0166b743 303 dev_dbg(dev, "%s (prepared)\n", __func__);
6acc81c3
PZ		 304 break;
305 default:
0166b743 306 dev_dbg(dev, "%s (unknown)\n", __func__);
6acc81c3
PZ		 307 break;
308 }
309#endif
310
311 free_buffer(vq, buf);
312}
313
314static void mx1_camera_wakeup(struct mx1_camera_dev *pcdev,
315 struct videobuf_buffer *vb,
316 struct mx1_buffer *buf)
317{
318 /* _init is used to debug races, see comment in mx1_camera_reqbufs() */
319 list_del_init(&vb->queue);
320 vb->state = VIDEOBUF_DONE;
321 do_gettimeofday(&vb->ts);
322 vb->field_count++;
323 wake_up(&vb->done);
324
325 if (list_empty(&pcdev->capture)) {
326 pcdev->active = NULL;
327 return;
328 }
329
330 pcdev->active = list_entry(pcdev->capture.next,
331 struct mx1_buffer, vb.queue);
332
333 /* setup sg list for future DMA */
334 if (likely(!mx1_camera_setup_dma(pcdev))) {
335 unsigned int temp;
336
337 /* enable SOF irq */
338 temp = __raw_readl(pcdev->base + CSICR1) | CSICR1_SOF_INTEN;
339 __raw_writel(temp, pcdev->base + CSICR1);
340 }
341}
342
343static void mx1_camera_dma_irq(int channel, void *data)
344{
345 struct mx1_camera_dev *pcdev = data;
0166b743 346 struct device *dev = pcdev->icd->dev.parent;
6acc81c3
PZ		 347 struct mx1_buffer *buf;
348 struct videobuf_buffer *vb;
349 unsigned long flags;
350
351 spin_lock_irqsave(&pcdev->lock, flags);
352
353 imx_dma_disable(channel);
354
355 if (unlikely(!pcdev->active)) {
0166b743 356 dev_err(dev, "DMA End IRQ with no active buffer\n");
6acc81c3
PZ		 357 goto out;
358 }
359
360 vb = &pcdev->active->vb;
361 buf = container_of(vb, struct mx1_buffer, vb);
362 WARN_ON(buf->inwork || list_empty(&vb->queue));
0166b743 363 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
6acc81c3
PZ		 364 vb, vb->baddr, vb->bsize);
365
366 mx1_camera_wakeup(pcdev, vb, buf);
367out:
368 spin_unlock_irqrestore(&pcdev->lock, flags);
369}
370
371static struct videobuf_queue_ops mx1_videobuf_ops = {
372 .buf_setup = mx1_videobuf_setup,
373 .buf_prepare = mx1_videobuf_prepare,
374 .buf_queue = mx1_videobuf_queue,
375 .buf_release = mx1_videobuf_release,
376};
377
378static void mx1_camera_init_videobuf(struct videobuf_queue *q,
379 struct soc_camera_device *icd)
380{
381 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
382 struct mx1_camera_dev *pcdev = ici->priv;
383
979ea1dd 384 videobuf_queue_dma_contig_init(q, &mx1_videobuf_ops, icd->dev.parent,
6acc81c3
PZ		 385 &pcdev->lock,
386 V4L2_BUF_TYPE_VIDEO_CAPTURE,
387 V4L2_FIELD_NONE,
e3cfd447 388 sizeof(struct mx1_buffer), icd, NULL);
6acc81c3
PZ		 389}
390
391static int mclk_get_divisor(struct mx1_camera_dev *pcdev)
392{
393 unsigned int mclk = pcdev->mclk;
394 unsigned long div;
395 unsigned long lcdclk;
396
397 lcdclk = clk_get_rate(pcdev->clk);
398
5d28d525
GL		 399 /*
400 * We verify platform_mclk_10khz != 0, so if anyone breaks it, here
401 * they get a nice Oops
402 */
6acc81c3
PZ		 403 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
404
0166b743
GL		 405 dev_dbg(pcdev->icd->dev.parent,
406 "System clock %lukHz, target freq %dkHz, divisor %lu\n",
407 lcdclk / 1000, mclk / 1000, div);
6acc81c3
PZ		 408
409 return div;
410}
411
412static void mx1_camera_activate(struct mx1_camera_dev *pcdev)
413{
414 unsigned int csicr1 = CSICR1_EN;
415
979ea1dd 416 dev_dbg(pcdev->icd->dev.parent, "Activate device\n");
6acc81c3
PZ		 417
418 clk_enable(pcdev->clk);
419
420 /* enable CSI before doing anything else */
421 __raw_writel(csicr1, pcdev->base + CSICR1);
422
423 csicr1 |= CSICR1_MCLKEN | CSICR1_FCC | CSICR1_GCLK_MODE;
424 csicr1 |= CSICR1_MCLKDIV(mclk_get_divisor(pcdev));
425 csicr1 |= CSICR1_RXFF_LEVEL(2); /* 16 words */
426
427 __raw_writel(csicr1, pcdev->base + CSICR1);
428}
429
430static void mx1_camera_deactivate(struct mx1_camera_dev *pcdev)
431{
979ea1dd 432 dev_dbg(pcdev->icd->dev.parent, "Deactivate device\n");
6acc81c3
PZ		 433
434 /* Disable all CSI interface */
435 __raw_writel(0x00, pcdev->base + CSICR1);
436
437 clk_disable(pcdev->clk);
438}
439
5d28d525
GL		 440/*
441 * The following two functions absolutely depend on the fact, that
442 * there can be only one camera on i.MX1/i.MXL camera sensor interface
443 */
6acc81c3
PZ		 444static int mx1_camera_add_device(struct soc_camera_device *icd)
445{
446 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
447 struct mx1_camera_dev *pcdev = ici->priv;
448 int ret;
449
450 if (pcdev->icd) {
451 ret = -EBUSY;
452 goto ebusy;
453 }
454
0166b743 455 dev_info(icd->dev.parent, "MX1 Camera driver attached to camera %d\n",
6acc81c3
PZ		 456 icd->devnum);
457
458 mx1_camera_activate(pcdev);
6acc81c3 459
979ea1dd 460 pcdev->icd = icd;
6acc81c3
PZ		 461
462ebusy:
463 return ret;
464}
465
466static void mx1_camera_remove_device(struct soc_camera_device *icd)
467{
468 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
469 struct mx1_camera_dev *pcdev = ici->priv;
470 unsigned int csicr1;
471
472 BUG_ON(icd != pcdev->icd);
473
474 /* disable interrupts */
475 csicr1 = __raw_readl(pcdev->base + CSICR1) & ~CSI_IRQ_MASK;
476 __raw_writel(csicr1, pcdev->base + CSICR1);
477
478 /* Stop DMA engine */
479 imx_dma_disable(pcdev->dma_chan);
480
0166b743 481 dev_info(icd->dev.parent, "MX1 Camera driver detached from camera %d\n",
6acc81c3
PZ		 482 icd->devnum);
483
6acc81c3
PZ		 484 mx1_camera_deactivate(pcdev);
485
486 pcdev->icd = NULL;
487}
488
489static int mx1_camera_set_crop(struct soc_camera_device *icd,
08590b96 490 struct v4l2_crop *a)
6acc81c3 491{
c9c1f1c0 492 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
08590b96
GL		 493
494 return v4l2_subdev_call(sd, video, s_crop, a);
6acc81c3
PZ		 495}
496
497static int mx1_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
498{
499 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
500 struct mx1_camera_dev *pcdev = ici->priv;
501 unsigned long camera_flags, common_flags;
502 unsigned int csicr1;
503 int ret;
504
505 camera_flags = icd->ops->query_bus_param(icd);
506
507 /* MX1 supports only 8bit buswidth */
508 common_flags = soc_camera_bus_param_compatible(camera_flags,
760697be 509 CSI_BUS_FLAGS);
6acc81c3
PZ		 510 if (!common_flags)
511 return -EINVAL;
512
6acc81c3
PZ		 513 /* Make choises, based on platform choice */
514 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
515 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
516 if (!pcdev->pdata ||
517 pcdev->pdata->flags & MX1_CAMERA_VSYNC_HIGH)
518 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
519 else
520 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
521 }
522
523 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
524 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
525 if (!pcdev->pdata ||
526 pcdev->pdata->flags & MX1_CAMERA_PCLK_RISING)
527 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
528 else
529 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
530 }
531
532 if ((common_flags & SOCAM_DATA_ACTIVE_HIGH) &&
533 (common_flags & SOCAM_DATA_ACTIVE_LOW)) {
534 if (!pcdev->pdata ||
535 pcdev->pdata->flags & MX1_CAMERA_DATA_HIGH)
536 common_flags &= ~SOCAM_DATA_ACTIVE_LOW;
537 else
538 common_flags &= ~SOCAM_DATA_ACTIVE_HIGH;
539 }
540
541 ret = icd->ops->set_bus_param(icd, common_flags);
542 if (ret < 0)
543 return ret;
544
545 csicr1 = __raw_readl(pcdev->base + CSICR1);
546
547 if (common_flags & SOCAM_PCLK_SAMPLE_RISING)
548 csicr1 |= CSICR1_REDGE;
549 if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH)
550 csicr1 |= CSICR1_SOF_POL;
551 if (common_flags & SOCAM_DATA_ACTIVE_LOW)
552 csicr1 |= CSICR1_DATA_POL;
553
554 __raw_writel(csicr1, pcdev->base + CSICR1);
555
556 return 0;
557}
558
559static int mx1_camera_set_fmt(struct soc_camera_device *icd,
560 struct v4l2_format *f)
561{
c9c1f1c0 562 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
6acc81c3
PZ		 563 const struct soc_camera_format_xlate *xlate;
564 struct v4l2_pix_format *pix = &f->fmt.pix;
760697be
GL		 565 struct v4l2_mbus_framefmt mf;
566 int ret, buswidth;
6acc81c3
PZ		 567
568 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
569 if (!xlate) {
96c75399
GL		 570 dev_warn(icd->dev.parent, "Format %x not found\n",
571 pix->pixelformat);
6acc81c3
PZ		 572 return -EINVAL;
573 }
574
760697be
GL		 575 buswidth = xlate->host_fmt->bits_per_sample;
576 if (buswidth > 8) {
577 dev_warn(icd->dev.parent,
578 "bits-per-sample %d for format %x unsupported\n",
579 buswidth, pix->pixelformat);
580 return -EINVAL;
6acc81c3
PZ		 581 }
582
760697be
GL		 583 mf.width = pix->width;
584 mf.height = pix->height;
585 mf.field = pix->field;
586 mf.colorspace = pix->colorspace;
587 mf.code = xlate->code;
588
589 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
590 if (ret < 0)
591 return ret;
592
593 if (mf.code != xlate->code)
594 return -EINVAL;
595
596 pix->width = mf.width;
597 pix->height = mf.height;
598 pix->field = mf.field;
599 pix->colorspace = mf.colorspace;
600 icd->current_fmt = xlate;
601
6acc81c3
PZ		 602 return ret;
603}
604
605static int mx1_camera_try_fmt(struct soc_camera_device *icd,
606 struct v4l2_format *f)
607{
c9c1f1c0 608 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
760697be
GL		 609 const struct soc_camera_format_xlate *xlate;
610 struct v4l2_pix_format *pix = &f->fmt.pix;
611 struct v4l2_mbus_framefmt mf;
612 int ret;
6acc81c3
PZ		 613 /* TODO: limit to mx1 hardware capabilities */
614
760697be
GL		 615 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
616 if (!xlate) {
617 dev_warn(icd->dev.parent, "Format %x not found\n",
618 pix->pixelformat);
619 return -EINVAL;
620 }
621
622 mf.width = pix->width;
623 mf.height = pix->height;
624 mf.field = pix->field;
625 mf.colorspace = pix->colorspace;
626 mf.code = xlate->code;
627
6acc81c3 628 /* limit to sensor capabilities */
760697be
GL		 629 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
630 if (ret < 0)
631 return ret;
632
633 pix->width = mf.width;
634 pix->height = mf.height;
635 pix->field = mf.field;
636 pix->colorspace = mf.colorspace;
637
638 return 0;
6acc81c3
PZ		 639}
640
57bee29d 641static int mx1_camera_reqbufs(struct soc_camera_device *icd,
6acc81c3
PZ		 642 struct v4l2_requestbuffers *p)
643{
644 int i;
645
5d28d525
GL		 646 /*
647 * This is for locking debugging only. I removed spinlocks and now I
6acc81c3
PZ		 648 * check whether .prepare is ever called on a linked buffer, or whether
649 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
5d28d525
GL		 650 * it hadn't triggered
651 */
6acc81c3 652 for (i = 0; i < p->count; i++) {
57bee29d 653 struct mx1_buffer *buf = container_of(icd->vb_vidq.bufs[i],
6acc81c3
PZ		 654 struct mx1_buffer, vb);
655 buf->inwork = 0;
656 INIT_LIST_HEAD(&buf->vb.queue);
657 }
658
659 return 0;
660}
661
662static unsigned int mx1_camera_poll(struct file *file, poll_table *pt)
663{
57bee29d 664 struct soc_camera_device *icd = file->private_data;
6acc81c3
PZ		 665 struct mx1_buffer *buf;
666
57bee29d 667 buf = list_entry(icd->vb_vidq.stream.next, struct mx1_buffer,
6acc81c3
PZ		 668 vb.stream);
669
670 poll_wait(file, &buf->vb.done, pt);
671
672 if (buf->vb.state == VIDEOBUF_DONE ||
673 buf->vb.state == VIDEOBUF_ERROR)
674 return POLLIN | POLLRDNORM;
675
676 return 0;
677}
678
679static int mx1_camera_querycap(struct soc_camera_host *ici,
680 struct v4l2_capability *cap)
681{
682 /* cap->name is set by the friendly caller:-> */
683 strlcpy(cap->card, "i.MX1/i.MXL Camera", sizeof(cap->card));
684 cap->version = VERSION_CODE;
685 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
686
687 return 0;
688}
689
690static struct soc_camera_host_ops mx1_soc_camera_host_ops = {
691 .owner = THIS_MODULE,
692 .add = mx1_camera_add_device,
693 .remove = mx1_camera_remove_device,
694 .set_bus_param = mx1_camera_set_bus_param,
695 .set_crop = mx1_camera_set_crop,
696 .set_fmt = mx1_camera_set_fmt,
697 .try_fmt = mx1_camera_try_fmt,
698 .init_videobuf = mx1_camera_init_videobuf,
699 .reqbufs = mx1_camera_reqbufs,
700 .poll = mx1_camera_poll,
701 .querycap = mx1_camera_querycap,
702};
703
6acc81c3
PZ		 704static struct fiq_handler fh = {
705 .name = "csi_sof"
706};
707
708static int __init mx1_camera_probe(struct platform_device *pdev)
709{
710 struct mx1_camera_dev *pcdev;
711 struct resource *res;
712 struct pt_regs regs;
713 struct clk *clk;
714 void __iomem *base;
715 unsigned int irq;
716 int err = 0;
717
718 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
719 irq = platform_get_irq(pdev, 0);
30883ea8 720 if (!res || (int)irq <= 0) {
6acc81c3
PZ		 721 err = -ENODEV;
722 goto exit;
723 }
724
725 clk = clk_get(&pdev->dev, "csi_clk");
726 if (IS_ERR(clk)) {
727 err = PTR_ERR(clk);
728 goto exit;
729 }
730
731 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
732 if (!pcdev) {
733 dev_err(&pdev->dev, "Could not allocate pcdev\n");
734 err = -ENOMEM;
735 goto exit_put_clk;
736 }
737
6acc81c3
PZ		 738 pcdev->res = res;
739 pcdev->clk = clk;
740
741 pcdev->pdata = pdev->dev.platform_data;
742
743 if (pcdev->pdata)
744 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
745
746 if (!pcdev->mclk) {
747 dev_warn(&pdev->dev,
748 "mclk_10khz == 0! Please, fix your platform data. "
749 "Using default 20MHz\n");
750 pcdev->mclk = 20000000;
751 }
752
753 INIT_LIST_HEAD(&pcdev->capture);
754 spin_lock_init(&pcdev->lock);
755
756 /*
757 * Request the regions.
758 */
759 if (!request_mem_region(res->start, resource_size(res), DRIVER_NAME)) {
760 err = -EBUSY;
761 goto exit_kfree;
762 }
763
764 base = ioremap(res->start, resource_size(res));
765 if (!base) {
766 err = -ENOMEM;
767 goto exit_release;
768 }
769 pcdev->irq = irq;
770 pcdev->base = base;
6acc81c3
PZ		 771
772 /* request dma */
773 pcdev->dma_chan = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_HIGH);
774 if (pcdev->dma_chan < 0) {
eff505fa 775 dev_err(&pdev->dev, "Can't request DMA for MX1 CSI\n");
6acc81c3
PZ		 776 err = -EBUSY;
777 goto exit_iounmap;
778 }
eff505fa 779 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chan);
6acc81c3
PZ		 780
781 imx_dma_setup_handlers(pcdev->dma_chan, mx1_camera_dma_irq, NULL,
782 pcdev);
783
784 imx_dma_config_channel(pcdev->dma_chan, IMX_DMA_TYPE_FIFO,
b7d41d6d 785 IMX_DMA_MEMSIZE_32, MX1_DMA_REQ_CSI_R, 0);
6acc81c3
PZ		 786 /* burst length : 16 words = 64 bytes */
787 imx_dma_config_burstlen(pcdev->dma_chan, 0);
788
789 /* request irq */
790 err = claim_fiq(&fh);
791 if (err) {
eff505fa 792 dev_err(&pdev->dev, "Camera interrupt register failed \n");
6acc81c3
PZ		 793 goto exit_free_dma;
794 }
795
796 set_fiq_handler(&mx1_camera_sof_fiq_start, &mx1_camera_sof_fiq_end -
797 &mx1_camera_sof_fiq_start);
798
b7d41d6d
UKK		 799 regs.ARM_r8 = (long)MX1_DMA_DIMR;
800 regs.ARM_r9 = (long)MX1_DMA_CCR(pcdev->dma_chan);
6acc81c3
PZ		 801 regs.ARM_r10 = (long)pcdev->base + CSICR1;
802 regs.ARM_fp = (long)pcdev->base + CSISR;
803 regs.ARM_sp = 1 << pcdev->dma_chan;
804 set_fiq_regs(&regs);
805
806 mxc_set_irq_fiq(irq, 1);
807 enable_fiq(irq);
808
eb6c8558
GL		 809 pcdev->soc_host.drv_name = DRIVER_NAME;
810 pcdev->soc_host.ops = &mx1_soc_camera_host_ops;
811 pcdev->soc_host.priv = pcdev;
979ea1dd 812 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
eb6c8558
GL		 813 pcdev->soc_host.nr = pdev->id;
814 err = soc_camera_host_register(&pcdev->soc_host);
6acc81c3
PZ		 815 if (err)
816 goto exit_free_irq;
817
818 dev_info(&pdev->dev, "MX1 Camera driver loaded\n");
819
820 return 0;
821
822exit_free_irq:
823 disable_fiq(irq);
824 mxc_set_irq_fiq(irq, 0);
825 release_fiq(&fh);
826exit_free_dma:
827 imx_dma_free(pcdev->dma_chan);
828exit_iounmap:
829 iounmap(base);
830exit_release:
831 release_mem_region(res->start, resource_size(res));
832exit_kfree:
833 kfree(pcdev);
834exit_put_clk:
835 clk_put(clk);
836exit:
837 return err;
838}
839
840static int __exit mx1_camera_remove(struct platform_device *pdev)
841{
eff505fa
GL		 842 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
843 struct mx1_camera_dev *pcdev = container_of(soc_host,
844 struct mx1_camera_dev, soc_host);
6acc81c3
PZ		 845 struct resource *res;
846
847 imx_dma_free(pcdev->dma_chan);
848 disable_fiq(pcdev->irq);
849 mxc_set_irq_fiq(pcdev->irq, 0);
850 release_fiq(&fh);
851
852 clk_put(pcdev->clk);
853
eff505fa 854 soc_camera_host_unregister(soc_host);
6acc81c3
PZ		 855
856 iounmap(pcdev->base);
857
858 res = pcdev->res;
859 release_mem_region(res->start, resource_size(res));
860
861 kfree(pcdev);
862
863 dev_info(&pdev->dev, "MX1 Camera driver unloaded\n");
864
865 return 0;
866}
867
868static struct platform_driver mx1_camera_driver = {
869 .driver = {
870 .name = DRIVER_NAME,
871 },
872 .remove = __exit_p(mx1_camera_remove),
873};
874
875static int __init mx1_camera_init(void)
876{
877 return platform_driver_probe(&mx1_camera_driver, mx1_camera_probe);
878}
879
880static void __exit mx1_camera_exit(void)
881{
882 return platform_driver_unregister(&mx1_camera_driver);
883}
884
885module_init(mx1_camera_init);
886module_exit(mx1_camera_exit);
887
888MODULE_DESCRIPTION("i.MX1/i.MXL SoC Camera Host driver");
889MODULE_AUTHOR("Paulius Zaleckas <paulius.zaleckas@teltonika.lt>");
890MODULE_LICENSE("GPL v2");
891MODULE_ALIAS("platform:" DRIVER_NAME);
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