]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/media/video/em28xx/em28xx-core.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
V4L/DVB (12411): em28xx: Fix artifacts with Silvercrest webcam
[net-next-2.6.git] / drivers / media / video / em28xx / em28xx-core.c
CommitLineData
a6c2ba28 1/*
3acf2809 2 em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
a6c2ba28 3
f7abcd38
MCC		 4 Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
5 Markus Rechberger <mrechberger@gmail.com>
2e7c6dc3 6 Mauro Carvalho Chehab <mchehab@infradead.org>
f7abcd38 7 Sascha Sommer <saschasommer@freenet.de>
a6c2ba28
AM		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/module.h>
a6c2ba28
AM		 27#include <linux/usb.h>
28#include <linux/vmalloc.h>
1a23f81b 29#include <media/v4l2-common.h>
a6c2ba28 30
f7abcd38 31#include "em28xx.h"
a6c2ba28
AM		 32
33/* #define ENABLE_DEBUG_ISOC_FRAMES */
34
ff699e6b 35static unsigned int core_debug;
a1a6ee74
NS		 36module_param(core_debug, int, 0644);
37MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
a6c2ba28 38
3acf2809 39#define em28xx_coredbg(fmt, arg...) do {\
4ac97914
MCC		 40 if (core_debug) \
41 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 42 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 43
ff699e6b 44static unsigned int reg_debug;
a1a6ee74
NS		 45module_param(reg_debug, int, 0644);
46MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
a6c2ba28 47
3acf2809 48#define em28xx_regdbg(fmt, arg...) do {\
4ac97914
MCC		 49 if (reg_debug) \
50 printk(KERN_INFO "%s %s :"fmt, \
d80e134d 51 dev->name, __func__ , ##arg); } while (0)
a6c2ba28 52
3acf2809 53static int alt = EM28XX_PINOUT;
a6c2ba28
AM		 54module_param(alt, int, 0644);
55MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
56
579f72e4
AT		 57/* FIXME */
58#define em28xx_isocdbg(fmt, arg...) do {\
59 if (core_debug) \
60 printk(KERN_INFO "%s %s :"fmt, \
61 dev->name, __func__ , ##arg); } while (0)
62
a6c2ba28 63/*
3acf2809 64 * em28xx_read_reg_req()
a6c2ba28
AM		 65 * reads data from the usb device specifying bRequest
66 */
3acf2809 67int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
a6c2ba28
AM		 68 char *buf, int len)
69{
9e5d6760
MCC		 70 int ret;
71 int pipe = usb_rcvctrlpipe(dev->udev, 0);
a6c2ba28 72
9f38724a 73 if (dev->state & DEV_DISCONNECTED)
c4a98793
MCC		 74 return -ENODEV;
75
76 if (len > URB_MAX_CTRL_SIZE)
77 return -EINVAL;
9f38724a 78
9e5d6760 79 if (reg_debug) {
a1a6ee74 80 printk(KERN_DEBUG "(pipe 0x%08x): "
9e5d6760
MCC		 81 "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
82 pipe,
83 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
84 req, 0, 0,
85 reg & 0xff, reg >> 8,
86 len & 0xff, len >> 8);
87 }
a6c2ba28 88
f2a2e491 89 mutex_lock(&dev->ctrl_urb_lock);
9e5d6760 90 ret = usb_control_msg(dev->udev, pipe, req,
a6c2ba28 91 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793
MCC		 92 0x0000, reg, dev->urb_buf, len, HZ);
93 if (ret < 0) {
94 if (reg_debug)
95 printk(" failed!\n");
f2a2e491 96 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793
MCC		 97 return ret;
98 }
99
100 if (len)
101 memcpy(buf, dev->urb_buf, len);
a6c2ba28 102
f2a2e491
MCC		 103 mutex_unlock(&dev->ctrl_urb_lock);
104
6ea54d93 105 if (reg_debug) {
9e5d6760
MCC		 106 int byte;
107
108 printk("<<<");
6ea54d93 109 for (byte = 0; byte < len; byte++)
82ac4f87 110 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 111 printk("\n");
a6c2ba28
AM		 112 }
113
114 return ret;
115}
116
117/*
3acf2809 118 * em28xx_read_reg_req()
a6c2ba28
AM		 119 * reads data from the usb device specifying bRequest
120 */
3acf2809 121int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
a6c2ba28 122{
a6c2ba28 123 int ret;
9e5d6760 124 u8 val;
a6c2ba28 125
9e5d6760
MCC		 126 ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
127 if (ret < 0)
c4a98793 128 return ret;
a6c2ba28
AM		 129
130 return val;
131}
132
3acf2809 133int em28xx_read_reg(struct em28xx *dev, u16 reg)
a6c2ba28 134{
3acf2809 135 return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
a6c2ba28
AM		 136}
137
138/*
3acf2809 139 * em28xx_write_regs_req()
a6c2ba28
AM		 140 * sends data to the usb device, specifying bRequest
141 */
3acf2809 142int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
a6c2ba28
AM		 143 int len)
144{
145 int ret;
9e5d6760 146 int pipe = usb_sndctrlpipe(dev->udev, 0);
a6c2ba28 147
9f38724a 148 if (dev->state & DEV_DISCONNECTED)
c67ec53f
MCC		 149 return -ENODEV;
150
c4a98793 151 if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
c67ec53f 152 return -EINVAL;
9f38724a 153
a6c2ba28 154 if (reg_debug) {
9e5d6760
MCC		 155 int byte;
156
a1a6ee74 157 printk(KERN_DEBUG "(pipe 0x%08x): "
9e5d6760
MCC		 158 "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
159 pipe,
160 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
161 req, 0, 0,
162 reg & 0xff, reg >> 8,
163 len & 0xff, len >> 8);
164
165 for (byte = 0; byte < len; byte++)
166 printk(" %02x", (unsigned char)buf[byte]);
82ac4f87 167 printk("\n");
a6c2ba28
AM		 168 }
169
f2a2e491 170 mutex_lock(&dev->ctrl_urb_lock);
c4a98793 171 memcpy(dev->urb_buf, buf, len);
9e5d6760 172 ret = usb_control_msg(dev->udev, pipe, req,
a6c2ba28 173 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
c4a98793 174 0x0000, reg, dev->urb_buf, len, HZ);
f2a2e491 175 mutex_unlock(&dev->ctrl_urb_lock);
c4a98793 176
89b329ef
MCC		 177 if (dev->wait_after_write)
178 msleep(dev->wait_after_write);
179
a6c2ba28
AM		 180 return ret;
181}
182
3acf2809 183int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
a6c2ba28 184{
c67ec53f
MCC		 185 int rc;
186
187 rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
188
189 /* Stores GPO/GPIO values at the cache, if changed
190 Only write values should be stored, since input on a GPIO
191 register will return the input bits.
192 Not sure what happens on reading GPO register.
193 */
194 if (rc >= 0) {
6a1acc3b 195 if (reg == dev->reg_gpo_num)
c67ec53f 196 dev->reg_gpo = buf[0];
6a1acc3b 197 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 198 dev->reg_gpio = buf[0];
199 }
200
201 return rc;
a6c2ba28
AM		 202}
203
b6972489
DH		 204/* Write a single register */
205int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
206{
207 return em28xx_write_regs(dev, reg, &val, 1);
208}
209
a6c2ba28 210/*
3acf2809 211 * em28xx_write_reg_bits()
a6c2ba28
AM		 212 * sets only some bits (specified by bitmask) of a register, by first reading
213 * the actual value
214 */
532fe652 215static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
a6c2ba28
AM		 216 u8 bitmask)
217{
218 int oldval;
219 u8 newval;
6ea54d93 220
c67ec53f 221 /* Uses cache for gpo/gpio registers */
6a1acc3b 222 if (reg == dev->reg_gpo_num)
c67ec53f 223 oldval = dev->reg_gpo;
6a1acc3b 224 else if (reg == dev->reg_gpio_num)
c67ec53f
MCC		 225 oldval = dev->reg_gpio;
226 else
227 oldval = em28xx_read_reg(dev, reg);
6ea54d93
DSL		 228
229 if (oldval < 0)
a6c2ba28 230 return oldval;
6ea54d93 231
a6c2ba28 232 newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
c67ec53f 233
3acf2809 234 return em28xx_write_regs(dev, reg, &newval, 1);
a6c2ba28
AM		 235}
236
35643943
MCC		 237/*
238 * em28xx_is_ac97_ready()
239 * Checks if ac97 is ready
240 */
241static int em28xx_is_ac97_ready(struct em28xx *dev)
242{
243 int ret, i;
244
245 /* Wait up to 50 ms for AC97 command to complete */
246 for (i = 0; i < 10; i++, msleep(5)) {
247 ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
248 if (ret < 0)
249 return ret;
250
251 if (!(ret & 0x01))
252 return 0;
253 }
254
255 em28xx_warn("AC97 command still being executed: not handled properly!\n");
256 return -EBUSY;
257}
258
259/*
260 * em28xx_read_ac97()
261 * write a 16 bit value to the specified AC97 address (LSB first!)
262 */
531c98e7 263int em28xx_read_ac97(struct em28xx *dev, u8 reg)
35643943
MCC		 264{
265 int ret;
266 u8 addr = (reg & 0x7f) | 0x80;
267 u16 val;
268
269 ret = em28xx_is_ac97_ready(dev);
270 if (ret < 0)
271 return ret;
272
273 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
274 if (ret < 0)
275 return ret;
276
277 ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
278 (u8 *)&val, sizeof(val));
279
280 if (ret < 0)
281 return ret;
282 return le16_to_cpu(val);
283}
284
a6c2ba28 285/*
3acf2809 286 * em28xx_write_ac97()
a6c2ba28
AM		 287 * write a 16 bit value to the specified AC97 address (LSB first!)
288 */
531c98e7 289int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
a6c2ba28 290{
35643943 291 int ret;
a6c2ba28 292 u8 addr = reg & 0x7f;
35643943
MCC		 293 __le16 value;
294
295 value = cpu_to_le16(val);
296
297 ret = em28xx_is_ac97_ready(dev);
298 if (ret < 0)
299 return ret;
6ea54d93 300
35643943 301 ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
6ea54d93 302 if (ret < 0)
a6c2ba28 303 return ret;
6ea54d93 304
41facaa4 305 ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
6ea54d93 306 if (ret < 0)
a6c2ba28 307 return ret;
00b8730f 308
35643943
MCC		 309 return 0;
310}
6ea54d93 311
e879b8eb
MCC		 312struct em28xx_vol_table {
313 enum em28xx_amux mux;
5faff789
MCC		 314 u8 reg;
315};
316
e879b8eb 317static struct em28xx_vol_table inputs[] = {
5faff789
MCC		 318 { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
319 { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
320 { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
321 { EM28XX_AMUX_MIC, AC97_MIC_VOL },
322 { EM28XX_AMUX_CD, AC97_CD_VOL },
323 { EM28XX_AMUX_AUX, AC97_AUX_VOL },
324 { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
325};
326
327static int set_ac97_input(struct em28xx *dev)
35643943 328{
5faff789
MCC		 329 int ret, i;
330 enum em28xx_amux amux = dev->ctl_ainput;
35643943 331
5faff789
MCC		 332 /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
333 em28xx should point to LINE IN, while AC97 should use VIDEO
334 */
335 if (amux == EM28XX_AMUX_VIDEO2)
f1990a9c 336 amux = EM28XX_AMUX_VIDEO;
35643943 337
5faff789
MCC		 338 /* Mute all entres but the one that were selected */
339 for (i = 0; i < ARRAY_SIZE(inputs); i++) {
e879b8eb 340 if (amux == inputs[i].mux)
5faff789
MCC		 341 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
342 else
343 ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
35643943 344
5faff789
MCC		 345 if (ret < 0)
346 em28xx_warn("couldn't setup AC97 register %d\n",
347 inputs[i].reg);
348 }
349 return 0;
a6c2ba28
AM		 350}
351
00b8730f 352static int em28xx_set_audio_source(struct em28xx *dev)
539c96d0 353{
1685a6fe 354 int ret;
539c96d0
MCC		 355 u8 input;
356
505b6d0b 357 if (dev->board.is_em2800) {
5faff789 358 if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
539c96d0 359 input = EM2800_AUDIO_SRC_TUNER;
5faff789
MCC		 360 else
361 input = EM2800_AUDIO_SRC_LINE;
539c96d0 362
41facaa4 363 ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
539c96d0
MCC		 364 if (ret < 0)
365 return ret;
366 }
367
505b6d0b 368 if (dev->board.has_msp34xx)
539c96d0
MCC		 369 input = EM28XX_AUDIO_SRC_TUNER;
370 else {
371 switch (dev->ctl_ainput) {
372 case EM28XX_AMUX_VIDEO:
373 input = EM28XX_AUDIO_SRC_TUNER;
539c96d0 374 break;
35643943 375 default:
539c96d0 376 input = EM28XX_AUDIO_SRC_LINE;
539c96d0
MCC		 377 break;
378 }
379 }
380
2bd1d9eb
VW		 381 if (dev->board.mute_gpio && dev->mute)
382 em28xx_gpio_set(dev, dev->board.mute_gpio);
383 else
384 em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
385
41facaa4 386 ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
539c96d0
MCC		 387 if (ret < 0)
388 return ret;
00b8730f 389 msleep(5);
539c96d0 390
35643943
MCC		 391 switch (dev->audio_mode.ac97) {
392 case EM28XX_NO_AC97:
393 break;
5faff789
MCC		 394 default:
395 ret = set_ac97_input(dev);
35643943 396 }
539c96d0 397
5faff789 398 return ret;
539c96d0
MCC		 399}
400
26cdc76b 401static const struct em28xx_vol_table outputs[] = {
e879b8eb
MCC		 402 { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
403 { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
404 { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
405 { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
406 { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
35ae6f04
MCC		 407};
408
3acf2809 409int em28xx_audio_analog_set(struct em28xx *dev)
a6c2ba28 410{
35ae6f04 411 int ret, i;
a2070c66 412 u8 xclk;
539c96d0 413
35643943
MCC		 414 if (!dev->audio_mode.has_audio)
415 return 0;
539c96d0 416
5faff789
MCC		 417 /* It is assumed that all devices use master volume for output.
418 It would be possible to use also line output.
419 */
35643943 420 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
35ae6f04
MCC		 421 /* Mute all outputs */
422 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
e879b8eb 423 ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
35ae6f04
MCC		 424 if (ret < 0)
425 em28xx_warn("couldn't setup AC97 register %d\n",
e879b8eb 426 outputs[i].reg);
35ae6f04 427 }
35643943 428 }
539c96d0 429
505b6d0b 430 xclk = dev->board.xclk & 0x7f;
3abee53e 431 if (!dev->mute)
8ed06fd4 432 xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
3abee53e 433
a2070c66 434 ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
539c96d0
MCC		 435 if (ret < 0)
436 return ret;
3abee53e 437 msleep(10);
539c96d0
MCC		 438
439 /* Selects the proper audio input */
440 ret = em28xx_set_audio_source(dev);
a6c2ba28 441
35643943
MCC		 442 /* Sets volume */
443 if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
444 int vol;
445
7e4b15e4
RK		 446 em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
447 em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
448 em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
449
35643943
MCC		 450 /* LSB: left channel - both channels with the same level */
451 vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
452
453 /* Mute device, if needed */
454 if (dev->mute)
455 vol |= 0x8000;
456
457 /* Sets volume */
e879b8eb
MCC		 458 for (i = 0; i < ARRAY_SIZE(outputs); i++) {
459 if (dev->ctl_aoutput & outputs[i].mux)
460 ret = em28xx_write_ac97(dev, outputs[i].reg,
461 vol);
462 if (ret < 0)
463 em28xx_warn("couldn't setup AC97 register %d\n",
464 outputs[i].reg);
465 }
8866f9cf
MCC		 466
467 if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
468 int sel = ac97_return_record_select(dev->ctl_aoutput);
469
a1a6ee74
NS		 470 /* Use the same input for both left and right
471 channels */
8866f9cf
MCC		 472 sel |= (sel << 8);
473
474 em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
475 }
35643943 476 }
00b8730f 477
539c96d0
MCC		 478 return ret;
479}
480EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
a6c2ba28 481
35643943
MCC		 482int em28xx_audio_setup(struct em28xx *dev)
483{
484 int vid1, vid2, feat, cfg;
16c7bcad 485 u32 vid;
35643943 486
62f3e69b 487 if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874) {
35643943
MCC		 488 /* Digital only device - don't load any alsa module */
489 dev->audio_mode.has_audio = 0;
490 dev->has_audio_class = 0;
491 dev->has_alsa_audio = 0;
492 return 0;
493 }
494
495 /* If device doesn't support Usb Audio Class, use vendor class */
496 if (!dev->has_audio_class)
497 dev->has_alsa_audio = 1;
498
499 dev->audio_mode.has_audio = 1;
500
501 /* See how this device is configured */
502 cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
1cdc6392
DH		 503 em28xx_info("Config register raw data: 0x%02x\n", cfg);
504 if (cfg < 0) {
505 /* Register read error? */
35643943 506 cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
1cdc6392
DH		 507 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) == 0x00) {
508 /* The device doesn't have vendor audio at all */
509 dev->has_alsa_audio = 0;
510 dev->audio_mode.has_audio = 0;
511 return 0;
512 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
513 EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
35643943
MCC		 514 em28xx_info("I2S Audio (3 sample rates)\n");
515 dev->audio_mode.i2s_3rates = 1;
1cdc6392
DH		 516 } else if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
517 EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
35643943
MCC		 518 em28xx_info("I2S Audio (5 sample rates)\n");
519 dev->audio_mode.i2s_5rates = 1;
520 }
521
de84830e
DH		 522 if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
523 /* Skip the code that does AC97 vendor detection */
35643943
MCC		 524 dev->audio_mode.ac97 = EM28XX_NO_AC97;
525 goto init_audio;
526 }
527
528 dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
529
530 vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
531 if (vid1 < 0) {
532 /* Device likely doesn't support AC97 */
533 em28xx_warn("AC97 chip type couldn't be determined\n");
534 goto init_audio;
535 }
536
537 vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
538 if (vid2 < 0)
539 goto init_audio;
540
16c7bcad
MCC		 541 vid = vid1 << 16 | vid2;
542
543 dev->audio_mode.ac97_vendor_id = vid;
544 em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
35643943
MCC		 545
546 feat = em28xx_read_ac97(dev, AC97_RESET);
547 if (feat < 0)
548 goto init_audio;
549
550 dev->audio_mode.ac97_feat = feat;
551 em28xx_warn("AC97 features = 0x%04x\n", feat);
552
16c7bcad
MCC		 553 /* Try to identify what audio processor we have */
554 if ((vid == 0xffffffff) && (feat == 0x6a90))
35643943 555 dev->audio_mode.ac97 = EM28XX_AC97_EM202;
209acc02
MCC		 556 else if ((vid >> 8) == 0x838476)
557 dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
35643943
MCC		 558
559init_audio:
560 /* Reports detected AC97 processor */
561 switch (dev->audio_mode.ac97) {
562 case EM28XX_NO_AC97:
563 em28xx_info("No AC97 audio processor\n");
564 break;
565 case EM28XX_AC97_EM202:
566 em28xx_info("Empia 202 AC97 audio processor detected\n");
567 break;
209acc02
MCC		 568 case EM28XX_AC97_SIGMATEL:
569 em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
570 dev->audio_mode.ac97_vendor_id & 0xff);
571 break;
35643943
MCC		 572 case EM28XX_AC97_OTHER:
573 em28xx_warn("Unknown AC97 audio processor detected!\n");
574 break;
575 default:
576 break;
577 }
578
579 return em28xx_audio_analog_set(dev);
580}
581EXPORT_SYMBOL_GPL(em28xx_audio_setup);
582
3acf2809 583int em28xx_colorlevels_set_default(struct em28xx *dev)
a6c2ba28 584{
2a29a0d7
MCC		 585 em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
586 em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
587 em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
588 em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
589 em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
590 em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
591
592 em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
593 em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
594 em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
595 em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
596 em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
597 em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
598 return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
a6c2ba28
AM		 599}
600
3acf2809 601int em28xx_capture_start(struct em28xx *dev, int start)
a6c2ba28 602{
ee6e3a86 603 int rc;
ebef13d4
DH		 604
605 if (dev->chip_id == CHIP_ID_EM2874) {
606 /* The Transport Stream Enable Register moved in em2874 */
607 if (!start) {
608 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
609 0x00,
610 EM2874_TS1_CAPTURE_ENABLE);
611 return rc;
612 }
613
614 /* Enable Transport Stream */
615 rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
616 EM2874_TS1_CAPTURE_ENABLE,
617 EM2874_TS1_CAPTURE_ENABLE);
618 return rc;
619 }
620
621
a6c2ba28
AM		 622 /* FIXME: which is the best order? */
623 /* video registers are sampled by VREF */
41facaa4 624 rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
ee6e3a86
MCC		 625 start ? 0x10 : 0x00, 0x10);
626 if (rc < 0)
627 return rc;
628
629 if (!start) {
630 /* disable video capture */
2a29a0d7 631 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
102a0b08 632 return rc;
ee6e3a86
MCC		 633 }
634
a6c2ba28 635 /* enable video capture */
2a29a0d7 636 rc = em28xx_write_reg(dev, 0x48, 0x00);
102a0b08 637
ee6e3a86 638 if (dev->mode == EM28XX_ANALOG_MODE)
2a29a0d7 639 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
ee6e3a86 640 else
2a29a0d7 641 rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
ee6e3a86 642
6ea54d93 643 msleep(6);
ee6e3a86
MCC		 644
645 return rc;
a6c2ba28
AM		 646}
647
bddcf633 648int em28xx_set_outfmt(struct em28xx *dev)
a6c2ba28 649{
bddcf633
MCC		 650 int ret;
651
652 ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
579d3152 653 dev->format->reg | 0x20, 0xff);
bddcf633 654 if (ret < 0)
02e7804b 655 return ret;
bddcf633 656
579d3152 657 ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
bddcf633
MCC		 658 if (ret < 0)
659 return ret;
660
579d3152 661 return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, dev->vinctl);
a6c2ba28
AM		 662}
663
adcb0fa2
AB		 664static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
665 u8 ymin, u8 ymax)
a6c2ba28 666{
6ea54d93
DSL		 667 em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
668 xmin, ymin, xmax, ymax);
a6c2ba28 669
41facaa4
MCC		 670 em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
671 em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
672 em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
673 return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
a6c2ba28
AM		 674}
675
adcb0fa2 676static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
a6c2ba28
AM		 677 u16 width, u16 height)
678{
679 u8 cwidth = width;
680 u8 cheight = height;
681 u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
682
6ea54d93
DSL		 683 em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
684 (width | (overflow & 2) << 7),
a6c2ba28
AM		 685 (height | (overflow & 1) << 8));
686
41facaa4
MCC		 687 em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
688 em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
689 em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
690 em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
691 return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
a6c2ba28
AM		 692}
693
adcb0fa2 694static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
a6c2ba28 695{
52c02fcd
SS		 696 u8 mode;
697 /* the em2800 scaler only supports scaling down to 50% */
02e7804b 698
55699964 699 if (dev->board.is_em2800) {
52c02fcd 700 mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
02e7804b 701 } else {
52c02fcd 702 u8 buf[2];
02e7804b 703
52c02fcd
SS		 704 buf[0] = h;
705 buf[1] = h >> 8;
41facaa4 706 em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
02e7804b 707
52c02fcd
SS		 708 buf[0] = v;
709 buf[1] = v >> 8;
41facaa4 710 em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
6ea54d93
DSL		 711 /* it seems that both H and V scalers must be active
712 to work correctly */
a1a6ee74 713 mode = (h || v) ? 0x30 : 0x00;
74458e6c 714 }
41facaa4 715 return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
a6c2ba28
AM		 716}
717
718/* FIXME: this only function read values from dev */
3acf2809 719int em28xx_resolution_set(struct em28xx *dev)
a6c2ba28
AM		 720{
721 int width, height;
722 width = norm_maxw(dev);
c2a6b54a
MCC		 723 height = norm_maxh(dev);
724
725 if (!dev->progressive)
726 height >>= norm_maxh(dev);
a6c2ba28 727
bddcf633 728 em28xx_set_outfmt(dev);
02e7804b
MCC		 729
730
3acf2809
MCC		 731 em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
732 em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
02e7804b 733
3acf2809 734 return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
a6c2ba28
AM		 735}
736
3acf2809 737int em28xx_set_alternate(struct em28xx *dev)
a6c2ba28
AM		 738{
739 int errCode, prev_alt = dev->alt;
3687e1e6 740 int i;
44dc733c 741 unsigned int min_pkt_size = dev->width * 2 + 4;
3687e1e6 742
2c4a07b2 743 /* When image size is bigger than a certain value,
3687e1e6
MCC		 744 the frame size should be increased, otherwise, only
745 green screen will be received.
746 */
44dc733c 747 if (dev->width * 2 * dev->height > 720 * 240 * 2)
3687e1e6
MCC		 748 min_pkt_size *= 2;
749
2c4a07b2
SS		 750 for (i = 0; i < dev->num_alt; i++) {
751 /* stop when the selected alt setting offers enough bandwidth */
752 if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
753 dev->alt = i;
3687e1e6 754 break;
2c4a07b2
SS		 755 /* otherwise make sure that we end up with the maximum bandwidth
756 because the min_pkt_size equation might be wrong...
757 */
758 } else if (dev->alt_max_pkt_size[i] >
759 dev->alt_max_pkt_size[dev->alt])
760 dev->alt = i;
761 }
a6c2ba28
AM		 762
763 if (dev->alt != prev_alt) {
3687e1e6
MCC		 764 em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
765 min_pkt_size, dev->alt);
a6c2ba28 766 dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
3687e1e6
MCC		 767 em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
768 dev->alt, dev->max_pkt_size);
a6c2ba28
AM		 769 errCode = usb_set_interface(dev->udev, 0, dev->alt);
770 if (errCode < 0) {
6ea54d93 771 em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
3687e1e6 772 dev->alt, errCode);
a6c2ba28
AM		 773 return errCode;
774 }
775 }
776 return 0;
777}
579f72e4 778
c67ec53f
MCC		 779int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
780{
781 int rc = 0;
782
783 if (!gpio)
784 return rc;
785
2fe3e2ee
MCC		 786 if (dev->mode != EM28XX_SUSPEND) {
787 em28xx_write_reg(dev, 0x48, 0x00);
788 if (dev->mode == EM28XX_ANALOG_MODE)
789 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
790 else
791 em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
792 msleep(6);
793 }
c67ec53f
MCC		 794
795 /* Send GPIO reset sequences specified at board entry */
796 while (gpio->sleep >= 0) {
797 if (gpio->reg >= 0) {
798 rc = em28xx_write_reg_bits(dev,
799 gpio->reg,
800 gpio->val,
801 gpio->mask);
802 if (rc < 0)
803 return rc;
804 }
805 if (gpio->sleep > 0)
806 msleep(gpio->sleep);
807
808 gpio++;
809 }
810 return rc;
811}
812
813int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
814{
815 if (dev->mode == set_mode)
816 return 0;
817
2fe3e2ee 818 if (set_mode == EM28XX_SUSPEND) {
c67ec53f 819 dev->mode = set_mode;
2fe3e2ee
MCC		 820
821 /* FIXME: add suspend support for ac97 */
822
823 return em28xx_gpio_set(dev, dev->board.suspend_gpio);
c67ec53f
MCC		 824 }
825
826 dev->mode = set_mode;
827
828 if (dev->mode == EM28XX_DIGITAL_MODE)
f502e861 829 return em28xx_gpio_set(dev, dev->board.dvb_gpio);
c67ec53f 830 else
f502e861 831 return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
c67ec53f
MCC		 832}
833EXPORT_SYMBOL_GPL(em28xx_set_mode);
834
579f72e4
AT		 835/* ------------------------------------------------------------------
836 URB control
837 ------------------------------------------------------------------*/
838
839/*
840 * IRQ callback, called by URB callback
841 */
842static void em28xx_irq_callback(struct urb *urb)
843{
844 struct em28xx_dmaqueue *dma_q = urb->context;
845 struct em28xx *dev = container_of(dma_q, struct em28xx, vidq);
846 int rc, i;
847
aa5a1821
RK		 848 switch (urb->status) {
849 case 0: /* success */
850 case -ETIMEDOUT: /* NAK */
851 break;
852 case -ECONNRESET: /* kill */
853 case -ENOENT:
854 case -ESHUTDOWN:
855 return;
856 default: /* error */
857 em28xx_isocdbg("urb completition error %d.\n", urb->status);
858 break;
859 }
860
579f72e4
AT		 861 /* Copy data from URB */
862 spin_lock(&dev->slock);
863 rc = dev->isoc_ctl.isoc_copy(dev, urb);
864 spin_unlock(&dev->slock);
865
866 /* Reset urb buffers */
867 for (i = 0; i < urb->number_of_packets; i++) {
868 urb->iso_frame_desc[i].status = 0;
869 urb->iso_frame_desc[i].actual_length = 0;
870 }
871 urb->status = 0;
872
873 urb->status = usb_submit_urb(urb, GFP_ATOMIC);
874 if (urb->status) {
4269a8ee
DH		 875 em28xx_isocdbg("urb resubmit failed (error=%i)\n",
876 urb->status);
579f72e4
AT		 877 }
878}
879
880/*
881 * Stop and Deallocate URBs
882 */
883void em28xx_uninit_isoc(struct em28xx *dev)
884{
885 struct urb *urb;
886 int i;
887
888 em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
889
890 dev->isoc_ctl.nfields = -1;
891 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
892 urb = dev->isoc_ctl.urb[i];
893 if (urb) {
9c06210b
RK		 894 if (!irqs_disabled())
895 usb_kill_urb(urb);
896 else
897 usb_unlink_urb(urb);
898
579f72e4
AT		 899 if (dev->isoc_ctl.transfer_buffer[i]) {
900 usb_buffer_free(dev->udev,
6ea54d93
DSL		 901 urb->transfer_buffer_length,
902 dev->isoc_ctl.transfer_buffer[i],
903 urb->transfer_dma);
579f72e4
AT		 904 }
905 usb_free_urb(urb);
906 dev->isoc_ctl.urb[i] = NULL;
907 }
908 dev->isoc_ctl.transfer_buffer[i] = NULL;
909 }
910
911 kfree(dev->isoc_ctl.urb);
912 kfree(dev->isoc_ctl.transfer_buffer);
913
914 dev->isoc_ctl.urb = NULL;
915 dev->isoc_ctl.transfer_buffer = NULL;
916 dev->isoc_ctl.num_bufs = 0;
917
918 em28xx_capture_start(dev, 0);
919}
920EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
921
922/*
923 * Allocate URBs and start IRQ
924 */
925int em28xx_init_isoc(struct em28xx *dev, int max_packets,
926 int num_bufs, int max_pkt_size,
c67ec53f 927 int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
579f72e4
AT		 928{
929 struct em28xx_dmaqueue *dma_q = &dev->vidq;
930 int i;
931 int sb_size, pipe;
932 struct urb *urb;
933 int j, k;
934 int rc;
935
936 em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
937
938 /* De-allocates all pending stuff */
939 em28xx_uninit_isoc(dev);
940
941 dev->isoc_ctl.isoc_copy = isoc_copy;
942 dev->isoc_ctl.num_bufs = num_bufs;
943
944 dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
945 if (!dev->isoc_ctl.urb) {
946 em28xx_errdev("cannot alloc memory for usb buffers\n");
947 return -ENOMEM;
948 }
949
950 dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
951 GFP_KERNEL);
094f9b4b 952 if (!dev->isoc_ctl.transfer_buffer) {
42ef4632 953 em28xx_errdev("cannot allocate memory for usb transfer\n");
579f72e4
AT		 954 kfree(dev->isoc_ctl.urb);
955 return -ENOMEM;
956 }
957
958 dev->isoc_ctl.max_pkt_size = max_pkt_size;
959 dev->isoc_ctl.buf = NULL;
960
961 sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
962
963 /* allocate urbs and transfer buffers */
964 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
965 urb = usb_alloc_urb(max_packets, GFP_KERNEL);
966 if (!urb) {
967 em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
968 em28xx_uninit_isoc(dev);
969 return -ENOMEM;
970 }
971 dev->isoc_ctl.urb[i] = urb;
972
973 dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev,
974 sb_size, GFP_KERNEL, &urb->transfer_dma);
975 if (!dev->isoc_ctl.transfer_buffer[i]) {
976 em28xx_err("unable to allocate %i bytes for transfer"
977 " buffer %i%s\n",
978 sb_size, i,
a1a6ee74 979 in_interrupt() ? " while in int" : "");
579f72e4
AT		 980 em28xx_uninit_isoc(dev);
981 return -ENOMEM;
982 }
983 memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
984
985 /* FIXME: this is a hack - should be
986 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
987 should also be using 'desc.bInterval'
988 */
6ea54d93 989 pipe = usb_rcvisocpipe(dev->udev,
c67ec53f 990 dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
6ea54d93 991
579f72e4
AT		 992 usb_fill_int_urb(urb, dev->udev, pipe,
993 dev->isoc_ctl.transfer_buffer[i], sb_size,
994 em28xx_irq_callback, dma_q, 1);
995
996 urb->number_of_packets = max_packets;
9a4f8201 997 urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
579f72e4
AT		 998
999 k = 0;
1000 for (j = 0; j < max_packets; j++) {
1001 urb->iso_frame_desc[j].offset = k;
1002 urb->iso_frame_desc[j].length =
1003 dev->isoc_ctl.max_pkt_size;
1004 k += dev->isoc_ctl.max_pkt_size;
1005 }
1006 }
1007
1008 init_waitqueue_head(&dma_q->wq);
1009
c67ec53f 1010 em28xx_capture_start(dev, 1);
579f72e4
AT		 1011
1012 /* submit urbs and enables IRQ */
1013 for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
1014 rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
1015 if (rc) {
1016 em28xx_err("submit of urb %i failed (error=%i)\n", i,
1017 rc);
1018 em28xx_uninit_isoc(dev);
1019 return rc;
1020 }
1021 }
1022
1023 return 0;
1024}
1025EXPORT_SYMBOL_GPL(em28xx_init_isoc);
1a23f81b 1026
d18e2fda
DH		 1027/* Determine the packet size for the DVB stream for the given device
1028 (underlying value programmed into the eeprom) */
1029int em28xx_isoc_dvb_max_packetsize(struct em28xx *dev)
1030{
1031 unsigned int chip_cfg2;
1032 unsigned int packet_size = 564;
1033
1034 if (dev->chip_id == CHIP_ID_EM2874) {
1035 /* FIXME - for now assume 564 like it was before, but the
1036 em2874 code should be added to return the proper value... */
1037 packet_size = 564;
1038 } else {
1039 /* TS max packet size stored in bits 1-0 of R01 */
1040 chip_cfg2 = em28xx_read_reg(dev, EM28XX_R01_CHIPCFG2);
1041 switch (chip_cfg2 & EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK) {
1042 case EM28XX_CHIPCFG2_TS_PACKETSIZE_188:
1043 packet_size = 188;
1044 break;
1045 case EM28XX_CHIPCFG2_TS_PACKETSIZE_376:
1046 packet_size = 376;
1047 break;
1048 case EM28XX_CHIPCFG2_TS_PACKETSIZE_564:
1049 packet_size = 564;
1050 break;
1051 case EM28XX_CHIPCFG2_TS_PACKETSIZE_752:
1052 packet_size = 752;
1053 break;
1054 }
1055 }
1056
1057 em28xx_coredbg("dvb max packet size=%d\n", packet_size);
1058 return packet_size;
1059}
1060EXPORT_SYMBOL_GPL(em28xx_isoc_dvb_max_packetsize);
1061
1a23f81b
MCC		 1062/*
1063 * em28xx_wake_i2c()
1064 * configure i2c attached devices
1065 */
1066void em28xx_wake_i2c(struct em28xx *dev)
1067{
5325b427
HV		 1068 v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
1069 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
1070 INPUT(dev->ctl_input)->vmux, 0, 0);
f2cf250a 1071 v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
1a23f81b
MCC		 1072}
1073
1074/*
1075 * Device control list
1076 */
1077
1078static LIST_HEAD(em28xx_devlist);
1079static DEFINE_MUTEX(em28xx_devlist_mutex);
1080
bec43661 1081struct em28xx *em28xx_get_device(int minor,
1a23f81b
MCC		 1082 enum v4l2_buf_type *fh_type,
1083 int *has_radio)
1084{
1085 struct em28xx *h, *dev = NULL;
1a23f81b
MCC		 1086
1087 *fh_type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1088 *has_radio = 0;
1089
1090 mutex_lock(&em28xx_devlist_mutex);
1091 list_for_each_entry(h, &em28xx_devlist, devlist) {
1092 if (h->vdev->minor == minor)
1093 dev = h;
1094 if (h->vbi_dev->minor == minor) {
1095 dev = h;
1096 *fh_type = V4L2_BUF_TYPE_VBI_CAPTURE;
1097 }
1098 if (h->radio_dev &&
1099 h->radio_dev->minor == minor) {
1100 dev = h;
1101 *has_radio = 1;
1102 }
1103 }
1104 mutex_unlock(&em28xx_devlist_mutex);
1105
1106 return dev;
1107}
1108
1109/*
1110 * em28xx_realease_resources()
1111 * unregisters the v4l2,i2c and usb devices
1112 * called when the device gets disconected or at module unload
1113*/
1114void em28xx_remove_from_devlist(struct em28xx *dev)
1115{
1116 mutex_lock(&em28xx_devlist_mutex);
1117 list_del(&dev->devlist);
1118 mutex_unlock(&em28xx_devlist_mutex);
1119};
1120
1121void em28xx_add_into_devlist(struct em28xx *dev)
1122{
1123 mutex_lock(&em28xx_devlist_mutex);
1124 list_add_tail(&dev->devlist, &em28xx_devlist);
1125 mutex_unlock(&em28xx_devlist_mutex);
1126};
1127
1128/*
1129 * Extension interface
1130 */
1131
1132static LIST_HEAD(em28xx_extension_devlist);
1133static DEFINE_MUTEX(em28xx_extension_devlist_lock);
1134
1135int em28xx_register_extension(struct em28xx_ops *ops)
1136{
1137 struct em28xx *dev = NULL;
1138
1139 mutex_lock(&em28xx_devlist_mutex);
1140 mutex_lock(&em28xx_extension_devlist_lock);
1141 list_add_tail(&ops->next, &em28xx_extension_devlist);
1142 list_for_each_entry(dev, &em28xx_devlist, devlist) {
1143 if (dev)
1144 ops->init(dev);
1145 }
1146 printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
1147 mutex_unlock(&em28xx_extension_devlist_lock);
1148 mutex_unlock(&em28xx_devlist_mutex);
1149 return 0;
1150}
1151EXPORT_SYMBOL(em28xx_register_extension);
1152
1153void em28xx_unregister_extension(struct em28xx_ops *ops)
1154{
1155 struct em28xx *dev = NULL;
1156
1157 mutex_lock(&em28xx_devlist_mutex);
1158 list_for_each_entry(dev, &em28xx_devlist, devlist) {
1159 if (dev)
1160 ops->fini(dev);
1161 }
1162
1163 mutex_lock(&em28xx_extension_devlist_lock);
1164 printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
1165 list_del(&ops->next);
1166 mutex_unlock(&em28xx_extension_devlist_lock);
1167 mutex_unlock(&em28xx_devlist_mutex);
1168}
1169EXPORT_SYMBOL(em28xx_unregister_extension);
1170
1171void em28xx_init_extension(struct em28xx *dev)
1172{
1173 struct em28xx_ops *ops = NULL;
1174
1175 mutex_lock(&em28xx_extension_devlist_lock);
1176 if (!list_empty(&em28xx_extension_devlist)) {
1177 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1178 if (ops->init)
1179 ops->init(dev);
1180 }
1181 }
1182 mutex_unlock(&em28xx_extension_devlist_lock);
1183}
1184
1185void em28xx_close_extension(struct em28xx *dev)
1186{
1187 struct em28xx_ops *ops = NULL;
1188
1189 mutex_lock(&em28xx_extension_devlist_lock);
1190 if (!list_empty(&em28xx_extension_devlist)) {
1191 list_for_each_entry(ops, &em28xx_extension_devlist, next) {
1192 if (ops->fini)
1193 ops->fini(dev);
1194 }
1195 }
1196 mutex_unlock(&em28xx_extension_devlist_lock);
1197}
Clone of davem's net-next-2.6 tree