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[net-next-2.6.git] / drivers / media / video / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
ST		 31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
d1987d55 40#include "xc5000.h"
b3ea0166 41#include "tda10048.h"
07b4a835 42#include "tuner-xc2028.h"
827855d3 43#include "tuner-simple.h"
66762373
ST		 44#include "dib7000p.h"
45#include "dibx000_common.h"
aef2d186 46#include "zl10353.h"
5a23b076 47#include "stv0900.h"
f867c3f4 48#include "stv0900_reg.h"
5a23b076
IL		 49#include "stv6110.h"
50#include "lnbh24.h"
96318d0c 51#include "cx24116.h"
5a23b076 52#include "cimax2.h"
493b7127 53#include "lgs8gxx.h"
5a23b076
IL		 54#include "netup-eeprom.h"
55#include "netup-init.h"
a5dbf457 56#include "lgdt3305.h"
d19770e5 57
4513fc69 58static unsigned int debug;
d19770e5 59
4513fc69
ST		 60#define dprintk(level, fmt, arg...)\
61 do { if (debug >= level)\
62 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
63 } while (0)
d19770e5
ST		 64
65/* ------------------------------------------------------------------ */
66
3ba71d21
MK		 67static unsigned int alt_tuner;
68module_param(alt_tuner, int, 0644);
69MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
70
78e92006
JG		 71DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
72
3ba71d21
MK		 73/* ------------------------------------------------------------------ */
74
d19770e5
ST		 75static int dvb_buf_setup(struct videobuf_queue *q,
76 unsigned int *count, unsigned int *size)
77{
78 struct cx23885_tsport *port = q->priv_data;
79
80 port->ts_packet_size = 188 * 4;
81 port->ts_packet_count = 32;
82
83 *size = port->ts_packet_size * port->ts_packet_count;
84 *count = 32;
85 return 0;
86}
87
44a6481d
MK		 88static int dvb_buf_prepare(struct videobuf_queue *q,
89 struct videobuf_buffer *vb, enum v4l2_field field)
d19770e5
ST		 90{
91 struct cx23885_tsport *port = q->priv_data;
9c8ced51 92 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
d19770e5
ST		 93}
94
95static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
96{
97 struct cx23885_tsport *port = q->priv_data;
9c8ced51 98 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
d19770e5
ST		 99}
100
44a6481d
MK		 101static void dvb_buf_release(struct videobuf_queue *q,
102 struct videobuf_buffer *vb)
d19770e5 103{
9c8ced51 104 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
d19770e5
ST		 105}
106
107static struct videobuf_queue_ops dvb_qops = {
108 .buf_setup = dvb_buf_setup,
109 .buf_prepare = dvb_buf_prepare,
110 .buf_queue = dvb_buf_queue,
111 .buf_release = dvb_buf_release,
112};
113
86184e06 114static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST		 115 .demod_address = 0x32 >> 1,
116 .output_mode = S5H1409_SERIAL_OUTPUT,
117 .gpio = S5H1409_GPIO_ON,
2b03238a 118 .qam_if = 44000,
fc959bef 119 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 120 .status_mode = S5H1409_DEMODLOCKING,
121 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST		 122};
123
b3ea0166
ST		 124static struct tda10048_config hauppauge_hvr1200_config = {
125 .demod_address = 0x10 >> 1,
126 .output_mode = TDA10048_SERIAL_OUTPUT,
127 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 128 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST		 129 .dtv6_if_freq_khz = TDA10048_IF_3300,
130 .dtv7_if_freq_khz = TDA10048_IF_3800,
131 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 132 .clk_freq_khz = TDA10048_CLK_16000,
b3ea0166
ST		 133};
134
6b926eca
MK		 135static struct tda10048_config hauppauge_hvr1210_config = {
136 .demod_address = 0x10 >> 1,
137 .output_mode = TDA10048_SERIAL_OUTPUT,
138 .fwbulkwritelen = TDA10048_BULKWRITE_200,
139 .inversion = TDA10048_INVERSION_ON,
c27586e4
MK		 140 .dtv6_if_freq_khz = TDA10048_IF_3300,
141 .dtv7_if_freq_khz = TDA10048_IF_3500,
142 .dtv8_if_freq_khz = TDA10048_IF_4000,
6b926eca
MK		 143 .clk_freq_khz = TDA10048_CLK_16000,
144};
145
3ba71d21
MK		 146static struct s5h1409_config hauppauge_ezqam_config = {
147 .demod_address = 0x32 >> 1,
148 .output_mode = S5H1409_SERIAL_OUTPUT,
149 .gpio = S5H1409_GPIO_OFF,
150 .qam_if = 4000,
151 .inversion = S5H1409_INVERSION_ON,
dfc1c08a
ST		 152 .status_mode = S5H1409_DEMODLOCKING,
153 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
3ba71d21
MK		 154};
155
fc959bef 156static struct s5h1409_config hauppauge_hvr1800lp_config = {
d19770e5
ST		 157 .demod_address = 0x32 >> 1,
158 .output_mode = S5H1409_SERIAL_OUTPUT,
159 .gpio = S5H1409_GPIO_OFF,
2b03238a 160 .qam_if = 44000,
fe475163 161 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 162 .status_mode = S5H1409_DEMODLOCKING,
163 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d19770e5
ST		 164};
165
07b4a835
MK		 166static struct s5h1409_config hauppauge_hvr1500_config = {
167 .demod_address = 0x32 >> 1,
168 .output_mode = S5H1409_SERIAL_OUTPUT,
169 .gpio = S5H1409_GPIO_OFF,
170 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 171 .status_mode = S5H1409_DEMODLOCKING,
172 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
07b4a835
MK		 173};
174
86184e06 175static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
ST		 176 0x61
177};
178
9bc37caa
MK		 179static struct lgdt330x_config fusionhdtv_5_express = {
180 .demod_address = 0x0e,
181 .demod_chip = LGDT3303,
182 .serial_mpeg = 0x40,
183};
184
d1987d55
ST		 185static struct s5h1409_config hauppauge_hvr1500q_config = {
186 .demod_address = 0x32 >> 1,
187 .output_mode = S5H1409_SERIAL_OUTPUT,
188 .gpio = S5H1409_GPIO_ON,
189 .qam_if = 44000,
190 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 191 .status_mode = S5H1409_DEMODLOCKING,
192 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
ST		 193};
194
335377b7
MK		 195static struct s5h1409_config dvico_s5h1409_config = {
196 .demod_address = 0x32 >> 1,
197 .output_mode = S5H1409_SERIAL_OUTPUT,
198 .gpio = S5H1409_GPIO_ON,
199 .qam_if = 44000,
200 .inversion = S5H1409_INVERSION_OFF,
201 .status_mode = S5H1409_DEMODLOCKING,
202 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
203};
204
52b50450
MK		 205static struct s5h1411_config dvico_s5h1411_config = {
206 .output_mode = S5H1411_SERIAL_OUTPUT,
207 .gpio = S5H1411_GPIO_ON,
208 .qam_if = S5H1411_IF_44000,
209 .vsb_if = S5H1411_IF_44000,
210 .inversion = S5H1411_INVERSION_OFF,
211 .status_mode = S5H1411_DEMODLOCKING,
212 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
213};
214
19bc5796
MK		 215static struct s5h1411_config hcw_s5h1411_config = {
216 .output_mode = S5H1411_SERIAL_OUTPUT,
217 .gpio = S5H1411_GPIO_OFF,
218 .vsb_if = S5H1411_IF_44000,
219 .qam_if = S5H1411_IF_4000,
220 .inversion = S5H1411_INVERSION_ON,
221 .status_mode = S5H1411_DEMODLOCKING,
222 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
223};
224
d1987d55 225static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST		 226 .i2c_address = 0x61,
227 .if_khz = 5380,
d1987d55
ST		 228};
229
335377b7
MK		 230static struct xc5000_config dvico_xc5000_tunerconfig = {
231 .i2c_address = 0x64,
232 .if_khz = 5380,
335377b7
MK		 233};
234
4041f1a5
MK		 235static struct tda829x_config tda829x_no_probe = {
236 .probe_tuner = TDA829X_DONT_PROBE,
237};
238
f21e0d7f 239static struct tda18271_std_map hauppauge_tda18271_std_map = {
c0dc0c11
MK		 240 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
241 .if_lvl = 6, .rfagc_top = 0x37 },
242 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
243 .if_lvl = 6, .rfagc_top = 0x37 },
f21e0d7f
MK		 244};
245
b34cdc36
MK		 246static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
247 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
248 .if_lvl = 1, .rfagc_top = 0x37, },
249 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
250 .if_lvl = 1, .rfagc_top = 0x37, },
251 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
252 .if_lvl = 1, .rfagc_top = 0x37, },
253};
254
f21e0d7f
MK		 255static struct tda18271_config hauppauge_tda18271_config = {
256 .std_map = &hauppauge_tda18271_std_map,
257 .gate = TDA18271_GATE_ANALOG,
04a68baa 258 .output_opt = TDA18271_OUTPUT_LT_OFF,
f21e0d7f
MK		 259};
260
b3ea0166 261static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 262 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 263 .gate = TDA18271_GATE_ANALOG,
04a68baa 264 .output_opt = TDA18271_OUTPUT_LT_OFF,
b3ea0166
ST		 265};
266
6b926eca
MK		 267static struct tda18271_config hauppauge_hvr1210_tuner_config = {
268 .gate = TDA18271_GATE_DIGITAL,
04a68baa 269 .output_opt = TDA18271_OUTPUT_LT_OFF,
6b926eca
MK		 270};
271
247bc540 272static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
MK		 273 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
274 .if_lvl = 1, .rfagc_top = 0x58 },
275 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
276 .if_lvl = 1, .rfagc_top = 0x58 },
277};
278
247bc540
MK		 279static struct tda18271_config hauppauge_hvr127x_config = {
280 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 281 .output_opt = TDA18271_OUTPUT_LT_OFF,
a5dbf457
MK		 282};
283
247bc540 284static struct lgdt3305_config hauppauge_lgdt3305_config = {
a5dbf457
MK		 285 .i2c_addr = 0x0e,
286 .mpeg_mode = LGDT3305_MPEG_SERIAL,
287 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
288 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
289 .deny_i2c_rptr = 1,
290 .spectral_inversion = 1,
291 .qam_if_khz = 4000,
292 .vsb_if_khz = 3250,
293};
294
b1721d0d 295static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST		 296 BAND_VHF | BAND_UHF, /* band_caps */
297
298 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
299 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
300 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
301 * P_agc_nb_est=2, P_agc_write=0
302 */
303 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
304 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
305
306 712, /* inv_gain */
307 21, /* time_stabiliz */
308
309 0, /* alpha_level */
310 118, /* thlock */
311
312 0, /* wbd_inv */
313 2867, /* wbd_ref */
314 0, /* wbd_sel */
315 2, /* wbd_alpha */
316
317 0, /* agc1_max */
318 0, /* agc1_min */
319 39718, /* agc2_max */
320 9930, /* agc2_min */
321 0, /* agc1_pt1 */
322 0, /* agc1_pt2 */
323 0, /* agc1_pt3 */
324 0, /* agc1_slope1 */
325 0, /* agc1_slope2 */
326 0, /* agc2_pt1 */
327 128, /* agc2_pt2 */
328 29, /* agc2_slope1 */
329 29, /* agc2_slope2 */
330
331 17, /* alpha_mant */
332 27, /* alpha_exp */
333 23, /* beta_mant */
334 51, /* beta_exp */
335
336 1, /* perform_agc_softsplit */
337};
338
339/* PLL Configuration for COFDM BW_MHz = 8.000000
340 * With external clock = 30.000000 */
b1721d0d 341static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST		 342 60000, /* internal */
343 30000, /* sampling */
344 1, /* pll_cfg: prediv */
345 8, /* pll_cfg: ratio */
346 3, /* pll_cfg: range */
347 1, /* pll_cfg: reset */
348 0, /* pll_cfg: bypass */
349 0, /* misc: refdiv */
350 0, /* misc: bypclk_div */
351 1, /* misc: IO_CLK_en_core */
352 1, /* misc: ADClkSrc */
353 0, /* misc: modulo */
354 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
355 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
356 20452225, /* timf */
357 30000000 /* xtal_hz */
358};
359
360static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
361 .output_mpeg2_in_188_bytes = 1,
362 .hostbus_diversity = 1,
363 .tuner_is_baseband = 0,
364 .update_lna = NULL,
365
366 .agc_config_count = 1,
367 .agc = &xc3028_agc_config,
368 .bw = &xc3028_bw_config,
369
370 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
371 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
372 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
373
374 .pwm_freq_div = 0,
375 .agc_control = NULL,
376 .spur_protect = 0,
377
378 .output_mode = OUTMODE_MPEG2_SERIAL,
379};
380
aef2d186
ST		 381static struct zl10353_config dvico_fusionhdtv_xc3028 = {
382 .demod_address = 0x0f,
383 .if2 = 45600,
384 .no_tuner = 1,
d4dc673d 385 .disable_i2c_gate_ctrl = 1,
aef2d186
ST		 386};
387
f867c3f4
IL		 388static struct stv0900_reg stv0900_ts_regs[] = {
389 { R0900_TSGENERAL, 0x00 },
390 { R0900_P1_TSSPEED, 0x40 },
391 { R0900_P2_TSSPEED, 0x40 },
392 { R0900_P1_TSCFGM, 0xc0 },
393 { R0900_P2_TSCFGM, 0xc0 },
394 { R0900_P1_TSCFGH, 0xe0 },
395 { R0900_P2_TSCFGH, 0xe0 },
396 { R0900_P1_TSCFGL, 0x20 },
397 { R0900_P2_TSCFGL, 0x20 },
398 { 0xffff, 0xff }, /* terminate */
399};
400
5a23b076
IL		 401static struct stv0900_config netup_stv0900_config = {
402 .demod_address = 0x68,
644c7ef0 403 .xtal = 8000000,
5a23b076
IL		 404 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
405 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 406 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL		 407 .tun1_maddress = 0,/* 0x60 */
408 .tun2_maddress = 3,/* 0x63 */
409 .tun1_adc = 1,/* 1 Vpp */
410 .tun2_adc = 1,/* 1 Vpp */
411};
412
413static struct stv6110_config netup_stv6110_tunerconfig_a = {
414 .i2c_address = 0x60,
644c7ef0
AO		 415 .mclk = 16000000,
416 .clk_div = 1,
5a23b076
IL		 417};
418
419static struct stv6110_config netup_stv6110_tunerconfig_b = {
420 .i2c_address = 0x63,
644c7ef0
AO		 421 .mclk = 16000000,
422 .clk_div = 1,
5a23b076
IL		 423};
424
96318d0c
IL		 425static int tbs_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
426{
427 struct cx23885_tsport *port = fe->dvb->priv;
428 struct cx23885_dev *dev = port->dev;
429
430 if (voltage == SEC_VOLTAGE_18)
431 cx_write(MC417_RWD, 0x00001e00);/* GPIO-13 high */
432 else if (voltage == SEC_VOLTAGE_13)
433 cx_write(MC417_RWD, 0x00001a00);/* GPIO-13 low */
434 else
435 cx_write(MC417_RWD, 0x00001800);/* GPIO-12 low */
436 return 0;
437}
438
439static struct cx24116_config tbs_cx24116_config = {
440 .demod_address = 0x05,
441};
442
579943f5
IL		 443static struct cx24116_config tevii_cx24116_config = {
444 .demod_address = 0x55,
445};
446
c9b8b04b
IL		 447static struct cx24116_config dvbworld_cx24116_config = {
448 .demod_address = 0x05,
449};
450
493b7127
DW		 451static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
452 .prod = LGS8GXX_PROD_LGS8GL5,
453 .demod_address = 0x19,
454 .serial_ts = 0,
455 .ts_clk_pol = 1,
456 .ts_clk_gated = 1,
457 .if_clk_freq = 30400, /* 30.4 MHz */
458 .if_freq = 5380, /* 5.38 MHz */
459 .if_neg_center = 1,
460 .ext_adc = 0,
461 .adc_signed = 0,
462 .if_neg_edge = 0,
463};
464
465static struct xc5000_config mygica_x8506_xc5000_config = {
466 .i2c_address = 0x61,
467 .if_khz = 5380,
468};
469
f35b9e80
MK		 470static int cx23885_dvb_set_frontend(struct dvb_frontend *fe,
471 struct dvb_frontend_parameters *param)
472{
473 struct cx23885_tsport *port = fe->dvb->priv;
474 struct cx23885_dev *dev = port->dev;
475
476 switch (dev->board) {
477 case CX23885_BOARD_HAUPPAUGE_HVR1275:
478 switch (param->u.vsb.modulation) {
479 case VSB_8:
480 cx23885_gpio_clear(dev, GPIO_5);
481 break;
482 case QAM_64:
483 case QAM_256:
484 default:
485 cx23885_gpio_set(dev, GPIO_5);
486 break;
487 }
488 break;
489 }
490 return (port->set_frontend_save) ?
491 port->set_frontend_save(fe, param) : -ENODEV;
492}
493
2365b2d3
DW		 494static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
495 .prod = LGS8GXX_PROD_LGS8G75,
496 .demod_address = 0x19,
497 .serial_ts = 0,
498 .ts_clk_pol = 1,
499 .ts_clk_gated = 1,
500 .if_clk_freq = 30400, /* 30.4 MHz */
501 .if_freq = 6500, /* 6.50 MHz */
502 .if_neg_center = 1,
503 .ext_adc = 0,
504 .adc_signed = 1,
505 .adc_vpp = 2, /* 1.6 Vpp */
506 .if_neg_edge = 1,
507};
508
509static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
510 .i2c_address = 0x61,
511 .if_khz = 6500,
512};
513
d19770e5
ST		 514static int dvb_register(struct cx23885_tsport *port)
515{
516 struct cx23885_dev *dev = port->dev;
493b7127 517 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
363c35fc 518 struct videobuf_dvb_frontend *fe0;
5a23b076 519 int ret;
363c35fc 520
f972e0bd 521 /* Get the first frontend */
92abe9ee 522 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST		 523 if (!fe0)
524 return -EINVAL;
d19770e5
ST		 525
526 /* init struct videobuf_dvb */
363c35fc 527 fe0->dvb.name = dev->name;
d19770e5
ST		 528
529 /* init frontend */
530 switch (dev->board) {
a77743bc 531 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 532 i2c_bus = &dev->i2c_bus[0];
363c35fc 533 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 534 &hauppauge_generic_config,
f139fa71 535 &i2c_bus->i2c_adap);
363c35fc
ST		 536 if (fe0->dvb.frontend != NULL) {
537 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 538 &i2c_bus->i2c_adap,
86184e06 539 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST		 540 }
541 break;
a5dbf457 542 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 543 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK		 544 i2c_bus = &dev->i2c_bus[0];
545 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 546 &hauppauge_lgdt3305_config,
a5dbf457
MK		 547 &i2c_bus->i2c_adap);
548 if (fe0->dvb.frontend != NULL) {
549 dvb_attach(tda18271_attach, fe0->dvb.frontend,
550 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 551 &hauppauge_hvr127x_config);
a5dbf457 552 }
f35b9e80 553
b179bc45 554 /* FIXME: temporary hack */
f35b9e80
MK		 555 /* define bridge override to set_frontend */
556 port->set_frontend_save = fe0->dvb.frontend->ops.set_frontend;
557 fe0->dvb.frontend->ops.set_frontend = cx23885_dvb_set_frontend;
558
a5dbf457 559 break;
19bc5796
MK		 560 case CX23885_BOARD_HAUPPAUGE_HVR1255:
561 i2c_bus = &dev->i2c_bus[0];
562 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
563 &hcw_s5h1411_config,
564 &i2c_bus->i2c_adap);
565 if (fe0->dvb.frontend != NULL) {
566 dvb_attach(tda18271_attach, fe0->dvb.frontend,
567 0x60, &dev->i2c_bus[1].i2c_adap,
568 &hauppauge_tda18271_config);
569 }
570 break;
3ba71d21
MK		 571 case CX23885_BOARD_HAUPPAUGE_HVR1800:
572 i2c_bus = &dev->i2c_bus[0];
92abe9ee 573 switch (alt_tuner) {
3ba71d21 574 case 1:
363c35fc 575 fe0->dvb.frontend =
3ba71d21
MK		 576 dvb_attach(s5h1409_attach,
577 &hauppauge_ezqam_config,
578 &i2c_bus->i2c_adap);
363c35fc
ST		 579 if (fe0->dvb.frontend != NULL) {
580 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 581 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 582 &tda829x_no_probe);
363c35fc 583 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 584 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 585 &hauppauge_tda18271_config);
3ba71d21
MK		 586 }
587 break;
588 case 0:
589 default:
363c35fc 590 fe0->dvb.frontend =
3ba71d21
MK		 591 dvb_attach(s5h1409_attach,
592 &hauppauge_generic_config,
593 &i2c_bus->i2c_adap);
363c35fc
ST		 594 if (fe0->dvb.frontend != NULL)
595 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK		 596 &i2c_bus->i2c_adap,
597 &hauppauge_generic_tunerconfig, 0);
598 break;
599 }
600 break;
fc959bef 601 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 602 i2c_bus = &dev->i2c_bus[0];
363c35fc 603 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 604 &hauppauge_hvr1800lp_config,
f139fa71 605 &i2c_bus->i2c_adap);
363c35fc
ST		 606 if (fe0->dvb.frontend != NULL) {
607 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 608 &i2c_bus->i2c_adap,
fc959bef
ST		 609 &hauppauge_generic_tunerconfig, 0);
610 }
611 break;
9bc37caa 612 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 613 i2c_bus = &dev->i2c_bus[0];
363c35fc 614 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 615 &fusionhdtv_5_express,
f139fa71 616 &i2c_bus->i2c_adap);
363c35fc
ST		 617 if (fe0->dvb.frontend != NULL) {
618 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK		 619 &i2c_bus->i2c_adap, 0x61,
620 TUNER_LG_TDVS_H06XF);
9bc37caa
MK		 621 }
622 break;
d1987d55
ST		 623 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
624 i2c_bus = &dev->i2c_bus[1];
363c35fc 625 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST		 626 &hauppauge_hvr1500q_config,
627 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST		 628 if (fe0->dvb.frontend != NULL)
629 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 630 &i2c_bus->i2c_adap,
631 &hauppauge_hvr1500q_tunerconfig);
d1987d55 632 break;
07b4a835
MK		 633 case CX23885_BOARD_HAUPPAUGE_HVR1500:
634 i2c_bus = &dev->i2c_bus[1];
363c35fc 635 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK		 636 &hauppauge_hvr1500_config,
637 &dev->i2c_bus[0].i2c_adap);
363c35fc 638 if (fe0->dvb.frontend != NULL) {
07b4a835
MK		 639 struct dvb_frontend *fe;
640 struct xc2028_config cfg = {
641 .i2c_adap = &i2c_bus->i2c_adap,
642 .i2c_addr = 0x61,
07b4a835
MK		 643 };
644 static struct xc2028_ctrl ctl = {
ef80bfeb 645 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 646 .max_len = 64,
52c3d29c 647 .demod = XC3028_FE_OREN538,
07b4a835
MK		 648 };
649
650 fe = dvb_attach(xc2028_attach,
363c35fc 651 fe0->dvb.frontend, &cfg);
07b4a835
MK		 652 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
653 fe->ops.tuner_ops.set_config(fe, &ctl);
654 }
655 break;
b3ea0166 656 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 657 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 658 i2c_bus = &dev->i2c_bus[0];
363c35fc 659 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST		 660 &hauppauge_hvr1200_config,
661 &i2c_bus->i2c_adap);
363c35fc
ST		 662 if (fe0->dvb.frontend != NULL) {
663 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST		 664 &dev->i2c_bus[1].i2c_adap, 0x42,
665 &tda829x_no_probe);
363c35fc 666 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST		 667 0x60, &dev->i2c_bus[1].i2c_adap,
668 &hauppauge_hvr1200_tuner_config);
6b926eca
MK		 669 }
670 break;
671 case CX23885_BOARD_HAUPPAUGE_HVR1210:
672 i2c_bus = &dev->i2c_bus[0];
673 fe0->dvb.frontend = dvb_attach(tda10048_attach,
674 &hauppauge_hvr1210_config,
675 &i2c_bus->i2c_adap);
676 if (fe0->dvb.frontend != NULL) {
677 dvb_attach(tda18271_attach, fe0->dvb.frontend,
678 0x60, &dev->i2c_bus[1].i2c_adap,
679 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST		 680 }
681 break;
66762373
ST		 682 case CX23885_BOARD_HAUPPAUGE_HVR1400:
683 i2c_bus = &dev->i2c_bus[0];
363c35fc 684 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST		 685 &i2c_bus->i2c_adap,
686 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 687 if (fe0->dvb.frontend != NULL) {
66762373
ST		 688 struct dvb_frontend *fe;
689 struct xc2028_config cfg = {
690 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
691 .i2c_addr = 0x64,
66762373
ST		 692 };
693 static struct xc2028_ctrl ctl = {
ef80bfeb 694 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373
ST		 695 .max_len = 64,
696 .demod = 5000,
9c8ced51
ST		 697 /* This is true for all demods with
698 v36 firmware? */
0975fc68 699 .type = XC2028_D2633,
66762373
ST		 700 };
701
702 fe = dvb_attach(xc2028_attach,
363c35fc 703 fe0->dvb.frontend, &cfg);
66762373
ST		 704 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
705 fe->ops.tuner_ops.set_config(fe, &ctl);
706 }
707 break;
335377b7
MK		 708 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
709 i2c_bus = &dev->i2c_bus[port->nr - 1];
710
363c35fc 711 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK		 712 &dvico_s5h1409_config,
713 &i2c_bus->i2c_adap);
363c35fc
ST		 714 if (fe0->dvb.frontend == NULL)
715 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK		 716 &dvico_s5h1411_config,
717 &i2c_bus->i2c_adap);
363c35fc
ST		 718 if (fe0->dvb.frontend != NULL)
719 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 720 &i2c_bus->i2c_adap,
721 &dvico_xc5000_tunerconfig);
335377b7 722 break;
aef2d186
ST		 723 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
724 i2c_bus = &dev->i2c_bus[port->nr - 1];
725
363c35fc 726 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST		 727 &dvico_fusionhdtv_xc3028,
728 &i2c_bus->i2c_adap);
363c35fc 729 if (fe0->dvb.frontend != NULL) {
aef2d186
ST		 730 struct dvb_frontend *fe;
731 struct xc2028_config cfg = {
732 .i2c_adap = &i2c_bus->i2c_adap,
733 .i2c_addr = 0x61,
aef2d186
ST		 734 };
735 static struct xc2028_ctrl ctl = {
ef80bfeb 736 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST		 737 .max_len = 64,
738 .demod = XC3028_FE_ZARLINK456,
739 };
740
363c35fc 741 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST		 742 &cfg);
743 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
744 fe->ops.tuner_ops.set_config(fe, &ctl);
745 }
746 break;
747 }
4c56b04a 748 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 749 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 750 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST		 751 i2c_bus = &dev->i2c_bus[0];
752
363c35fc 753 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST		 754 &dvico_fusionhdtv_xc3028,
755 &i2c_bus->i2c_adap);
363c35fc 756 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST		 757 struct dvb_frontend *fe;
758 struct xc2028_config cfg = {
759 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
760 .i2c_addr = 0x61,
4c56b04a
ST		 761 };
762 static struct xc2028_ctrl ctl = {
ef80bfeb 763 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST		 764 .max_len = 64,
765 .demod = XC3028_FE_ZARLINK456,
766 };
767
363c35fc 768 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST		 769 &cfg);
770 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
771 fe->ops.tuner_ops.set_config(fe, &ctl);
772 }
96318d0c
IL		 773 break;
774 case CX23885_BOARD_TBS_6920:
775 i2c_bus = &dev->i2c_bus[0];
776
777 fe0->dvb.frontend = dvb_attach(cx24116_attach,
778 &tbs_cx24116_config,
779 &i2c_bus->i2c_adap);
780 if (fe0->dvb.frontend != NULL)
781 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
782
579943f5
IL		 783 break;
784 case CX23885_BOARD_TEVII_S470:
785 i2c_bus = &dev->i2c_bus[1];
786
787 fe0->dvb.frontend = dvb_attach(cx24116_attach,
788 &tevii_cx24116_config,
789 &i2c_bus->i2c_adap);
790 if (fe0->dvb.frontend != NULL)
791 fe0->dvb.frontend->ops.set_voltage = tbs_set_voltage;
792
4c56b04a 793 break;
c9b8b04b
IL		 794 case CX23885_BOARD_DVBWORLD_2005:
795 i2c_bus = &dev->i2c_bus[1];
796
797 fe0->dvb.frontend = dvb_attach(cx24116_attach,
798 &dvbworld_cx24116_config,
799 &i2c_bus->i2c_adap);
800 break;
5a23b076
IL		 801 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
802 i2c_bus = &dev->i2c_bus[0];
803 switch (port->nr) {
804 /* port B */
805 case 1:
806 fe0->dvb.frontend = dvb_attach(stv0900_attach,
807 &netup_stv0900_config,
808 &i2c_bus->i2c_adap, 0);
809 if (fe0->dvb.frontend != NULL) {
810 if (dvb_attach(stv6110_attach,
811 fe0->dvb.frontend,
812 &netup_stv6110_tunerconfig_a,
813 &i2c_bus->i2c_adap)) {
814 if (!dvb_attach(lnbh24_attach,
815 fe0->dvb.frontend,
816 &i2c_bus->i2c_adap,
0cde9b25
IL		 817 LNBH24_PCL,
818 LNBH24_TTX, 0x09))
5a23b076
IL		 819 printk(KERN_ERR
820 "No LNBH24 found!\n");
821
822 }
823 }
824 break;
825 /* port C */
826 case 2:
827 fe0->dvb.frontend = dvb_attach(stv0900_attach,
828 &netup_stv0900_config,
829 &i2c_bus->i2c_adap, 1);
830 if (fe0->dvb.frontend != NULL) {
831 if (dvb_attach(stv6110_attach,
832 fe0->dvb.frontend,
833 &netup_stv6110_tunerconfig_b,
834 &i2c_bus->i2c_adap)) {
835 if (!dvb_attach(lnbh24_attach,
836 fe0->dvb.frontend,
837 &i2c_bus->i2c_adap,
0cde9b25
IL		 838 LNBH24_PCL,
839 LNBH24_TTX, 0x0a))
5a23b076
IL		 840 printk(KERN_ERR
841 "No LNBH24 found!\n");
842
843 }
844 }
845 break;
846 }
847 break;
493b7127
DW		 848 case CX23885_BOARD_MYGICA_X8506:
849 i2c_bus = &dev->i2c_bus[0];
850 i2c_bus2 = &dev->i2c_bus[1];
851 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
852 &mygica_x8506_lgs8gl5_config,
853 &i2c_bus->i2c_adap);
854 if (fe0->dvb.frontend != NULL) {
855 dvb_attach(xc5000_attach,
856 fe0->dvb.frontend,
857 &i2c_bus2->i2c_adap,
858 &mygica_x8506_xc5000_config);
859 }
860 break;
2365b2d3
DW		 861 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
862 i2c_bus = &dev->i2c_bus[0];
863 i2c_bus2 = &dev->i2c_bus[1];
864 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
865 &magicpro_prohdtve2_lgs8g75_config,
866 &i2c_bus->i2c_adap);
867 if (fe0->dvb.frontend != NULL) {
868 dvb_attach(xc5000_attach,
869 fe0->dvb.frontend,
870 &i2c_bus2->i2c_adap,
871 &magicpro_prohdtve2_xc5000_config);
872 }
873 break;
13697380
ST		 874 case CX23885_BOARD_HAUPPAUGE_HVR1850:
875 i2c_bus = &dev->i2c_bus[0];
876 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
877 &hcw_s5h1411_config,
878 &i2c_bus->i2c_adap);
879 if (fe0->dvb.frontend != NULL)
880 dvb_attach(tda18271_attach, fe0->dvb.frontend,
881 0x60, &dev->i2c_bus[0].i2c_adap,
882 &hauppauge_tda18271_config);
883 break;
884
d19770e5 885 default:
9c8ced51
ST		 886 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
887 " isn't supported yet\n",
d19770e5
ST		 888 dev->name);
889 break;
890 }
363c35fc 891 if (NULL == fe0->dvb.frontend) {
9c8ced51
ST		 892 printk(KERN_ERR "%s: frontend initialization failed\n",
893 dev->name);
d19770e5
ST		 894 return -1;
895 }
d7cba043 896 /* define general-purpose callback pointer */
363c35fc 897 fe0->dvb.frontend->callback = cx23885_tuner_callback;
d19770e5
ST		 898
899 /* Put the analog decoder in standby to keep it quiet */
7c9fc9d5 900 call_all(dev, tuner, s_standby);
d19770e5 901
363c35fc
ST		 902 if (fe0->dvb.frontend->ops.analog_ops.standby)
903 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 904
d19770e5 905 /* register everything */
5a23b076 906 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
59b1842d 907 &dev->pci->dev, adapter_nr, 0);
363c35fc 908
5a23b076
IL		 909 /* init CI & MAC */
910 switch (dev->board) {
911 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
912 static struct netup_card_info cinfo;
913
914 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
915 memcpy(port->frontends.adapter.proposed_mac,
916 cinfo.port[port->nr - 1].mac, 6);
917 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC="
918 "%02X:%02X:%02X:%02X:%02X:%02X\n",
919 port->nr,
920 port->frontends.adapter.proposed_mac[0],
921 port->frontends.adapter.proposed_mac[1],
922 port->frontends.adapter.proposed_mac[2],
923 port->frontends.adapter.proposed_mac[3],
924 port->frontends.adapter.proposed_mac[4],
925 port->frontends.adapter.proposed_mac[5]);
926
927 netup_ci_init(port);
928 break;
929 }
930 }
931
932 return ret;
d19770e5
ST		 933}
934
935int cx23885_dvb_register(struct cx23885_tsport *port)
936{
363c35fc
ST		 937
938 struct videobuf_dvb_frontend *fe0;
d19770e5 939 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST		 940 int err, i;
941
942 /* Here we need to allocate the correct number of frontends,
af901ca1 943 * as reflected in the cards struct. The reality is that currently
eb0c58bb
ST		 944 * no cx23885 boards support this - yet. But, if we don't modify this
945 * code then the second frontend would never be allocated (later)
946 * and fail with error before the attach in dvb_register().
947 * Without these changes we risk an OOPS later. The changes here
948 * are for safety, and should provide a good foundation for the
949 * future addition of any multi-frontend cx23885 based boards.
950 */
951 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
952 port->num_frontends);
d19770e5 953
eb0c58bb 954 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 955 if (videobuf_dvb_alloc_frontend(
9c8ced51 956 &port->frontends, i) == NULL) {
eb0c58bb
ST		 957 printk(KERN_ERR "%s() failed to alloc\n", __func__);
958 return -ENOMEM;
959 }
960
961 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
962 if (!fe0)
963 err = -EINVAL;
363c35fc 964
eb0c58bb 965 dprintk(1, "%s\n", __func__);
9c8ced51 966 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST		 967 dev->board,
968 dev->name,
969 dev->pci_bus,
970 dev->pci_slot);
d19770e5 971
eb0c58bb 972 err = -ENODEV;
d19770e5 973
eb0c58bb
ST		 974 /* dvb stuff */
975 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST		 976 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
977 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
978 &dev->pci->dev, &port->slock,
44a6481d
MK		 979 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
980 sizeof(struct cx23885_buffer), port);
eb0c58bb 981 }
d19770e5
ST		 982 err = dvb_register(port);
983 if (err != 0)
9c8ced51
ST		 984 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
985 __func__, err);
d19770e5 986
d19770e5
ST		 987 return err;
988}
989
990int cx23885_dvb_unregister(struct cx23885_tsport *port)
991{
363c35fc
ST		 992 struct videobuf_dvb_frontend *fe0;
993
eb0c58bb
ST		 994 /* FIXME: in an error condition where the we have
995 * an expected number of frontends (attach problem)
996 * then this might not clean up correctly, if 1
997 * is invalid.
998 * This comment only applies to future boards IF they
999 * implement MFE support.
1000 */
92abe9ee 1001 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
9c8ced51 1002 if (fe0->dvb.frontend)
363c35fc 1003 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 1004
afd96668
HV		 1005 switch (port->dev->board) {
1006 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1007 netup_ci_exit(port);
1008 break;
1009 }
5a23b076 1010
d19770e5
ST		 1011 return 0;
1012}
44a6481d 1013
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