]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/media/video/cx18/cx18-streams.c
Merge branch 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[net-next-2.6.git] / drivers / media / video / cx18 / cx18-streams.c
CommitLineData
1c1e45d1
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1/*
2 * cx18 init/start/stop/exit stream functions
3 *
4 * Derived from ivtv-streams.c
5 *
6 * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
6afdeaf8 7 * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
1c1e45d1
HV
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
22 * 02111-1307 USA
23 */
24
25#include "cx18-driver.h"
b1526421 26#include "cx18-io.h"
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27#include "cx18-fileops.h"
28#include "cx18-mailbox.h"
29#include "cx18-i2c.h"
30#include "cx18-queue.h"
31#include "cx18-ioctl.h"
32#include "cx18-streams.h"
33#include "cx18-cards.h"
34#include "cx18-scb.h"
1c1e45d1
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35#include "cx18-dvb.h"
36
37#define CX18_DSP0_INTERRUPT_MASK 0xd0004C
38
bec43661 39static struct v4l2_file_operations cx18_v4l2_enc_fops = {
daf20d95
HV
40 .owner = THIS_MODULE,
41 .read = cx18_v4l2_read,
42 .open = cx18_v4l2_open,
3b6fe58f 43 /* FIXME change to video_ioctl2 if serialization lock can be removed */
daf20d95 44 .ioctl = cx18_v4l2_ioctl,
daf20d95
HV
45 .release = cx18_v4l2_close,
46 .poll = cx18_v4l2_enc_poll,
1c1e45d1
HV
47};
48
49/* offset from 0 to register ts v4l2 minors on */
50#define CX18_V4L2_ENC_TS_OFFSET 16
51/* offset from 0 to register pcm v4l2 minors on */
52#define CX18_V4L2_ENC_PCM_OFFSET 24
53/* offset from 0 to register yuv v4l2 minors on */
54#define CX18_V4L2_ENC_YUV_OFFSET 32
55
56static struct {
57 const char *name;
58 int vfl_type;
dd89601d 59 int num_offset;
1c1e45d1
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60 int dma;
61 enum v4l2_buf_type buf_type;
1c1e45d1
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62} cx18_stream_info[] = {
63 { /* CX18_ENC_STREAM_TYPE_MPG */
64 "encoder MPEG",
65 VFL_TYPE_GRABBER, 0,
66 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
1c1e45d1
HV
67 },
68 { /* CX18_ENC_STREAM_TYPE_TS */
69 "TS",
70 VFL_TYPE_GRABBER, -1,
71 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
1c1e45d1
HV
72 },
73 { /* CX18_ENC_STREAM_TYPE_YUV */
74 "encoder YUV",
75 VFL_TYPE_GRABBER, CX18_V4L2_ENC_YUV_OFFSET,
76 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
1c1e45d1
HV
77 },
78 { /* CX18_ENC_STREAM_TYPE_VBI */
79 "encoder VBI",
80 VFL_TYPE_VBI, 0,
81 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VBI_CAPTURE,
1c1e45d1
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82 },
83 { /* CX18_ENC_STREAM_TYPE_PCM */
84 "encoder PCM audio",
85 VFL_TYPE_GRABBER, CX18_V4L2_ENC_PCM_OFFSET,
86 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_PRIVATE,
1c1e45d1
HV
87 },
88 { /* CX18_ENC_STREAM_TYPE_IDX */
89 "encoder IDX",
90 VFL_TYPE_GRABBER, -1,
91 PCI_DMA_FROMDEVICE, V4L2_BUF_TYPE_VIDEO_CAPTURE,
1c1e45d1
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92 },
93 { /* CX18_ENC_STREAM_TYPE_RAD */
94 "encoder radio",
95 VFL_TYPE_RADIO, 0,
96 PCI_DMA_NONE, V4L2_BUF_TYPE_PRIVATE,
1c1e45d1
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97 },
98};
99
100static void cx18_stream_init(struct cx18 *cx, int type)
101{
102 struct cx18_stream *s = &cx->streams[type];
3d05913d 103 struct video_device *video_dev = s->video_dev;
1c1e45d1 104
3d05913d 105 /* we need to keep video_dev, so restore it afterwards */
1c1e45d1 106 memset(s, 0, sizeof(*s));
3d05913d 107 s->video_dev = video_dev;
1c1e45d1
HV
108
109 /* initialize cx18_stream fields */
110 s->cx = cx;
111 s->type = type;
112 s->name = cx18_stream_info[type].name;
d3c5e707 113 s->handle = CX18_INVALID_TASK_HANDLE;
1c1e45d1
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114
115 s->dma = cx18_stream_info[type].dma;
6ecd86dc 116 s->buffers = cx->stream_buffers[type];
1c1e45d1 117 s->buf_size = cx->stream_buf_size[type];
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118 INIT_LIST_HEAD(&s->buf_pool);
119 s->bufs_per_mdl = 1;
120 s->mdl_size = s->buf_size * s->bufs_per_mdl;
6ecd86dc 121
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122 init_waitqueue_head(&s->waitq);
123 s->id = -1;
40c5520f 124 spin_lock_init(&s->q_free.lock);
1c1e45d1 125 cx18_queue_init(&s->q_free);
40c5520f 126 spin_lock_init(&s->q_busy.lock);
66c2a6b0 127 cx18_queue_init(&s->q_busy);
40c5520f 128 spin_lock_init(&s->q_full.lock);
1c1e45d1 129 cx18_queue_init(&s->q_full);
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130 spin_lock_init(&s->q_idle.lock);
131 cx18_queue_init(&s->q_idle);
21a278b8
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132
133 INIT_WORK(&s->out_work_order, cx18_out_work_handler);
1c1e45d1
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134}
135
136static int cx18_prep_dev(struct cx18 *cx, int type)
137{
138 struct cx18_stream *s = &cx->streams[type];
139 u32 cap = cx->v4l2_cap;
dd89601d 140 int num_offset = cx18_stream_info[type].num_offset;
5811cf99 141 int num = cx->instance + cx18_first_minor + num_offset;
1c1e45d1 142
3d05913d 143 /* These four fields are always initialized. If video_dev == NULL, then
1c1e45d1
HV
144 this stream is not in use. In that case no other fields but these
145 four can be used. */
3d05913d 146 s->video_dev = NULL;
1c1e45d1
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147 s->cx = cx;
148 s->type = type;
149 s->name = cx18_stream_info[type].name;
150
151 /* Check whether the radio is supported */
152 if (type == CX18_ENC_STREAM_TYPE_RAD && !(cap & V4L2_CAP_RADIO))
153 return 0;
154
155 /* Check whether VBI is supported */
156 if (type == CX18_ENC_STREAM_TYPE_VBI &&
157 !(cap & (V4L2_CAP_VBI_CAPTURE | V4L2_CAP_SLICED_VBI_CAPTURE)))
158 return 0;
159
1c1e45d1
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160 /* User explicitly selected 0 buffers for these streams, so don't
161 create them. */
162 if (cx18_stream_info[type].dma != PCI_DMA_NONE &&
6ecd86dc 163 cx->stream_buffers[type] == 0) {
1c1e45d1
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164 CX18_INFO("Disabled %s device\n", cx18_stream_info[type].name);
165 return 0;
166 }
167
168 cx18_stream_init(cx, type);
169
dd89601d 170 if (num_offset == -1)
1c1e45d1
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171 return 0;
172
173 /* allocate and initialize the v4l2 video device structure */
3d05913d
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174 s->video_dev = video_device_alloc();
175 if (s->video_dev == NULL) {
1c1e45d1
HV
176 CX18_ERR("Couldn't allocate v4l2 video_device for %s\n",
177 s->name);
178 return -ENOMEM;
179 }
180
5811cf99
AW
181 snprintf(s->video_dev->name, sizeof(s->video_dev->name), "%s %s",
182 cx->v4l2_dev.name, s->name);
1c1e45d1 183
3d05913d 184 s->video_dev->num = num;
5811cf99 185 s->video_dev->v4l2_dev = &cx->v4l2_dev;
3d05913d
AW
186 s->video_dev->fops = &cx18_v4l2_enc_fops;
187 s->video_dev->release = video_device_release;
188 s->video_dev->tvnorms = V4L2_STD_ALL;
189 cx18_set_funcs(s->video_dev);
1c1e45d1
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190 return 0;
191}
192
193/* Initialize v4l2 variables and register v4l2 devices */
194int cx18_streams_setup(struct cx18 *cx)
195{
9b4a7c8a 196 int type, ret;
1c1e45d1
HV
197
198 /* Setup V4L2 Devices */
199 for (type = 0; type < CX18_MAX_STREAMS; type++) {
200 /* Prepare device */
9b4a7c8a
AW
201 ret = cx18_prep_dev(cx, type);
202 if (ret < 0)
1c1e45d1
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203 break;
204
205 /* Allocate Stream */
9b4a7c8a
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206 ret = cx18_stream_alloc(&cx->streams[type]);
207 if (ret < 0)
1c1e45d1
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208 break;
209 }
210 if (type == CX18_MAX_STREAMS)
211 return 0;
212
213 /* One or more streams could not be initialized. Clean 'em all up. */
3f98387e 214 cx18_streams_cleanup(cx, 0);
9b4a7c8a 215 return ret;
1c1e45d1
HV
216}
217
218static int cx18_reg_dev(struct cx18 *cx, int type)
219{
220 struct cx18_stream *s = &cx->streams[type];
221 int vfl_type = cx18_stream_info[type].vfl_type;
38c7c036 222 const char *name;
9b4a7c8a 223 int num, ret;
1c1e45d1
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224
225 /* TODO: Shouldn't this be a VFL_TYPE_TRANSPORT or something?
226 * We need a VFL_TYPE_TS defined.
227 */
228 if (strcmp("TS", s->name) == 0) {
229 /* just return if no DVB is supported */
230 if ((cx->card->hw_all & CX18_HW_DVB) == 0)
231 return 0;
9b4a7c8a
AW
232 ret = cx18_dvb_register(s);
233 if (ret < 0) {
1c1e45d1 234 CX18_ERR("DVB failed to register\n");
9b4a7c8a 235 return ret;
1c1e45d1
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236 }
237 }
238
3d05913d 239 if (s->video_dev == NULL)
1c1e45d1
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240 return 0;
241
3d05913d 242 num = s->video_dev->num;
dd89601d
HV
243 /* card number + user defined offset + device offset */
244 if (type != CX18_ENC_STREAM_TYPE_MPG) {
245 struct cx18_stream *s_mpg = &cx->streams[CX18_ENC_STREAM_TYPE_MPG];
246
3d05913d
AW
247 if (s_mpg->video_dev)
248 num = s_mpg->video_dev->num
249 + cx18_stream_info[type].num_offset;
dd89601d 250 }
5811cf99 251 video_set_drvdata(s->video_dev, s);
1c1e45d1
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252
253 /* Register device. First try the desired minor, then any free one. */
6b5270d2 254 ret = video_register_device_no_warn(s->video_dev, vfl_type, num);
9b4a7c8a 255 if (ret < 0) {
581644d9 256 CX18_ERR("Couldn't register v4l2 device for %s (device node number %d)\n",
dd89601d 257 s->name, num);
3d05913d
AW
258 video_device_release(s->video_dev);
259 s->video_dev = NULL;
9b4a7c8a 260 return ret;
1c1e45d1 261 }
38c7c036
LP
262
263 name = video_device_node_name(s->video_dev);
1c1e45d1
HV
264
265 switch (vfl_type) {
266 case VFL_TYPE_GRABBER:
38c7c036
LP
267 CX18_INFO("Registered device %s for %s (%d x %d.%02d kB)\n",
268 name, s->name, cx->stream_buffers[type],
22dce188
AW
269 cx->stream_buf_size[type] / 1024,
270 (cx->stream_buf_size[type] * 100 / 1024) % 100);
1c1e45d1
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271 break;
272
273 case VFL_TYPE_RADIO:
38c7c036 274 CX18_INFO("Registered device %s for %s\n", name, s->name);
1c1e45d1
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275 break;
276
277 case VFL_TYPE_VBI:
6ecd86dc 278 if (cx->stream_buffers[type])
38c7c036 279 CX18_INFO("Registered device %s for %s "
6ecd86dc 280 "(%d x %d bytes)\n",
38c7c036 281 name, s->name, cx->stream_buffers[type],
6ecd86dc 282 cx->stream_buf_size[type]);
1c1e45d1 283 else
38c7c036
LP
284 CX18_INFO("Registered device %s for %s\n",
285 name, s->name);
1c1e45d1
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286 break;
287 }
288
289 return 0;
290}
291
292/* Register v4l2 devices */
293int cx18_streams_register(struct cx18 *cx)
294{
295 int type;
9b4a7c8a
AW
296 int err;
297 int ret = 0;
1c1e45d1
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298
299 /* Register V4L2 devices */
9b4a7c8a
AW
300 for (type = 0; type < CX18_MAX_STREAMS; type++) {
301 err = cx18_reg_dev(cx, type);
302 if (err && ret == 0)
303 ret = err;
304 }
1c1e45d1 305
9b4a7c8a 306 if (ret == 0)
1c1e45d1
HV
307 return 0;
308
309 /* One or more streams could not be initialized. Clean 'em all up. */
3f98387e 310 cx18_streams_cleanup(cx, 1);
9b4a7c8a 311 return ret;
1c1e45d1
HV
312}
313
314/* Unregister v4l2 devices */
3f98387e 315void cx18_streams_cleanup(struct cx18 *cx, int unregister)
1c1e45d1
HV
316{
317 struct video_device *vdev;
318 int type;
319
320 /* Teardown all streams */
321 for (type = 0; type < CX18_MAX_STREAMS; type++) {
7b1dde03
AW
322
323 /* No struct video_device, but can have buffers allocated */
324 if (type == CX18_ENC_STREAM_TYPE_TS) {
325 if (cx->streams[type].dvb.enabled) {
326 cx18_dvb_unregister(&cx->streams[type]);
327 cx->streams[type].dvb.enabled = false;
328 cx18_stream_free(&cx->streams[type]);
329 }
330 continue;
331 }
332
333 /* No struct video_device, but can have buffers allocated */
334 if (type == CX18_ENC_STREAM_TYPE_IDX) {
335 if (cx->stream_buffers[type] != 0) {
336 cx->stream_buffers[type] = 0;
337 cx18_stream_free(&cx->streams[type]);
338 }
339 continue;
fac3639d 340 }
1c1e45d1 341
7b1dde03 342 /* If struct video_device exists, can have buffers allocated */
3d05913d 343 vdev = cx->streams[type].video_dev;
1c1e45d1 344
3d05913d 345 cx->streams[type].video_dev = NULL;
1c1e45d1
HV
346 if (vdev == NULL)
347 continue;
348
349 cx18_stream_free(&cx->streams[type]);
350
3f98387e
HV
351 /* Unregister or release device */
352 if (unregister)
353 video_unregister_device(vdev);
354 else
355 video_device_release(vdev);
1c1e45d1
HV
356 }
357}
358
359static void cx18_vbi_setup(struct cx18_stream *s)
360{
361 struct cx18 *cx = s->cx;
dd073434 362 int raw = cx18_raw_vbi(cx);
1c1e45d1
HV
363 u32 data[CX2341X_MBOX_MAX_DATA];
364 int lines;
365
366 if (cx->is_60hz) {
367 cx->vbi.count = 12;
368 cx->vbi.start[0] = 10;
369 cx->vbi.start[1] = 273;
370 } else { /* PAL/SECAM */
371 cx->vbi.count = 18;
372 cx->vbi.start[0] = 6;
373 cx->vbi.start[1] = 318;
374 }
375
376 /* setup VBI registers */
add632cd
HV
377 if (raw)
378 v4l2_subdev_call(cx->sd_av, vbi, s_raw_fmt, &cx->vbi.in.fmt.vbi);
379 else
380 v4l2_subdev_call(cx->sd_av, vbi, s_sliced_fmt, &cx->vbi.in.fmt.sliced);
1c1e45d1 381
dcc0ef88
AW
382 /*
383 * Send the CX18_CPU_SET_RAW_VBI_PARAM API command to setup Encoder Raw
384 * VBI when the first analog capture channel starts, as once it starts
385 * (e.g. MPEG), we can't effect any change in the Encoder Raw VBI setup
386 * (i.e. for the VBI capture channels). We also send it for each
387 * analog capture channel anyway just to make sure we get the proper
388 * behavior
389 */
1c1e45d1
HV
390 if (raw) {
391 lines = cx->vbi.count * 2;
392 } else {
812b1f9d
AW
393 /*
394 * For 525/60 systems, according to the VIP 2 & BT.656 std:
395 * The EAV RP code's Field bit toggles on line 4, a few lines
396 * after the Vertcal Blank bit has already toggled.
397 * Tell the encoder to capture 21-4+1=18 lines per field,
398 * since we want lines 10 through 21.
399 *
5ab74052
AW
400 * For 625/50 systems, according to the VIP 2 & BT.656 std:
401 * The EAV RP code's Field bit toggles on line 1, a few lines
402 * after the Vertcal Blank bit has already toggled.
929a3ad1
AW
403 * (We've actually set the digitizer so that the Field bit
404 * toggles on line 2.) Tell the encoder to capture 23-2+1=22
405 * lines per field, since we want lines 6 through 23.
812b1f9d 406 */
929a3ad1 407 lines = cx->is_60hz ? (21 - 4 + 1) * 2 : (23 - 2 + 1) * 2;
1c1e45d1
HV
408 }
409
1c1e45d1
HV
410 data[0] = s->handle;
411 /* Lines per field */
412 data[1] = (lines / 2) | ((lines / 2) << 16);
413 /* bytes per line */
302df970
AW
414 data[2] = (raw ? vbi_active_samples
415 : (cx->is_60hz ? vbi_hblank_samples_60Hz
416 : vbi_hblank_samples_50Hz));
1c1e45d1
HV
417 /* Every X number of frames a VBI interrupt arrives
418 (frames as in 25 or 30 fps) */
419 data[3] = 1;
302df970
AW
420 /*
421 * Set the SAV/EAV RP codes to look for as start/stop points
422 * when in VIP-1.1 mode
423 */
1c1e45d1 424 if (raw) {
302df970
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425 /*
426 * Start codes for beginning of "active" line in vertical blank
427 * 0x20 ( VerticalBlank )
428 * 0x60 ( EvenField VerticalBlank )
429 */
1c1e45d1 430 data[4] = 0x20602060;
302df970
AW
431 /*
432 * End codes for end of "active" raw lines and regular lines
433 * 0x30 ( VerticalBlank HorizontalBlank)
434 * 0x70 ( EvenField VerticalBlank HorizontalBlank)
435 * 0x90 (Task HorizontalBlank)
436 * 0xd0 (Task EvenField HorizontalBlank)
437 */
af009cf6 438 data[5] = 0x307090d0;
1c1e45d1 439 } else {
302df970
AW
440 /*
441 * End codes for active video, we want data in the hblank region
442 * 0xb0 (Task 0 VerticalBlank HorizontalBlank)
443 * 0xf0 (Task EvenField VerticalBlank HorizontalBlank)
444 *
445 * Since the V bit is only allowed to toggle in the EAV RP code,
446 * just before the first active region line, these two
812b1f9d 447 * are problematic:
302df970
AW
448 * 0x90 (Task HorizontalBlank)
449 * 0xd0 (Task EvenField HorizontalBlank)
812b1f9d 450 *
af7c58b1
AW
451 * We have set the digitzer such that we don't have to worry
452 * about these problem codes.
302df970 453 */
1c1e45d1 454 data[4] = 0xB0F0B0F0;
302df970
AW
455 /*
456 * Start codes for beginning of active line in vertical blank
457 * 0xa0 (Task VerticalBlank )
458 * 0xe0 (Task EvenField VerticalBlank )
459 */
1c1e45d1
HV
460 data[5] = 0xA0E0A0E0;
461 }
462
463 CX18_DEBUG_INFO("Setup VBI h: %d lines %x bpl %d fr %d %x %x\n",
464 data[0], data[1], data[2], data[3], data[4], data[5]);
465
dcc0ef88 466 cx18_api(cx, CX18_CPU_SET_RAW_VBI_PARAM, 6, data);
1c1e45d1
HV
467}
468
ef991797
AW
469void cx18_stream_rotate_idx_mdls(struct cx18 *cx)
470{
471 struct cx18_stream *s = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
472 struct cx18_mdl *mdl;
473
474 if (!cx18_stream_enabled(s))
475 return;
476
477 /* Return if the firmware is not running low on MDLs */
478 if ((atomic_read(&s->q_free.depth) + atomic_read(&s->q_busy.depth)) >=
479 CX18_ENC_STREAM_TYPE_IDX_FW_MDL_MIN)
480 return;
481
482 /* Return if there are no MDLs to rotate back to the firmware */
483 if (atomic_read(&s->q_full.depth) < 2)
484 return;
485
486 /*
487 * Take the oldest IDX MDL still holding data, and discard its index
488 * entries by scheduling the MDL to go back to the firmware
489 */
490 mdl = cx18_dequeue(s, &s->q_full);
491 if (mdl != NULL)
492 cx18_enqueue(s, mdl, &s->q_free);
493}
494
87116159 495static
52fcb3ec
AW
496struct cx18_queue *_cx18_stream_put_mdl_fw(struct cx18_stream *s,
497 struct cx18_mdl *mdl)
66c2a6b0
AW
498{
499 struct cx18 *cx = s->cx;
500 struct cx18_queue *q;
501
502 /* Don't give it to the firmware, if we're not running a capture */
503 if (s->handle == CX18_INVALID_TASK_HANDLE ||
87116159 504 test_bit(CX18_F_S_STOPPING, &s->s_flags) ||
66c2a6b0 505 !test_bit(CX18_F_S_STREAMING, &s->s_flags))
52fcb3ec 506 return cx18_enqueue(s, mdl, &s->q_free);
66c2a6b0 507
52fcb3ec 508 q = cx18_enqueue(s, mdl, &s->q_busy);
66c2a6b0 509 if (q != &s->q_busy)
52fcb3ec 510 return q; /* The firmware has the max MDLs it can handle */
66c2a6b0 511
52fcb3ec 512 cx18_mdl_sync_for_device(s, mdl);
66c2a6b0 513 cx18_vapi(cx, CX18_CPU_DE_SET_MDL, 5, s->handle,
52fcb3ec
AW
514 (void __iomem *) &cx->scb->cpu_mdl[mdl->id] - cx->enc_mem,
515 s->bufs_per_mdl, mdl->id, s->mdl_size);
66c2a6b0
AW
516 return q;
517}
518
87116159
AW
519static
520void _cx18_stream_load_fw_queue(struct cx18_stream *s)
66c2a6b0 521{
abb096de 522 struct cx18_queue *q;
52fcb3ec 523 struct cx18_mdl *mdl;
66c2a6b0 524
c37b11bf
AW
525 if (atomic_read(&s->q_free.depth) == 0 ||
526 atomic_read(&s->q_busy.depth) >= CX18_MAX_FW_MDLS_PER_STREAM)
abb096de
AW
527 return;
528
529 /* Move from q_free to q_busy notifying the firmware, until the limit */
530 do {
52fcb3ec
AW
531 mdl = cx18_dequeue(s, &s->q_free);
532 if (mdl == NULL)
abb096de 533 break;
52fcb3ec 534 q = _cx18_stream_put_mdl_fw(s, mdl);
c37b11bf 535 } while (atomic_read(&s->q_busy.depth) < CX18_MAX_FW_MDLS_PER_STREAM
0ef02892 536 && q == &s->q_busy);
66c2a6b0
AW
537}
538
87116159
AW
539void cx18_out_work_handler(struct work_struct *work)
540{
21a278b8
AW
541 struct cx18_stream *s =
542 container_of(work, struct cx18_stream, out_work_order);
87116159 543
21a278b8 544 _cx18_stream_load_fw_queue(s);
87116159
AW
545}
546
52fcb3ec
AW
547static void cx18_stream_configure_mdls(struct cx18_stream *s)
548{
549 cx18_unload_queues(s);
550
22dce188
AW
551 switch (s->type) {
552 case CX18_ENC_STREAM_TYPE_YUV:
553 /*
554 * Height should be a multiple of 32 lines.
555 * Set the MDL size to the exact size needed for one frame.
556 * Use enough buffers per MDL to cover the MDL size
557 */
558 s->mdl_size = 720 * s->cx->params.height * 3 / 2;
559 s->bufs_per_mdl = s->mdl_size / s->buf_size;
560 if (s->mdl_size % s->buf_size)
561 s->bufs_per_mdl++;
562 break;
127ce5f0
AW
563 case CX18_ENC_STREAM_TYPE_VBI:
564 s->bufs_per_mdl = 1;
565 if (cx18_raw_vbi(s->cx)) {
566 s->mdl_size = (s->cx->is_60hz ? 12 : 18)
567 * 2 * vbi_active_samples;
568 } else {
569 /*
570 * See comment in cx18_vbi_setup() below about the
571 * extra lines we capture in sliced VBI mode due to
572 * the lines on which EAV RP codes toggle.
573 */
574 s->mdl_size = s->cx->is_60hz
575 ? (21 - 4 + 1) * 2 * vbi_hblank_samples_60Hz
576 : (23 - 2 + 1) * 2 * vbi_hblank_samples_50Hz;
577 }
578 break;
22dce188
AW
579 default:
580 s->bufs_per_mdl = 1;
581 s->mdl_size = s->buf_size * s->bufs_per_mdl;
582 break;
583 }
52fcb3ec
AW
584
585 cx18_load_queues(s);
586}
587
1c1e45d1
HV
588int cx18_start_v4l2_encode_stream(struct cx18_stream *s)
589{
590 u32 data[MAX_MB_ARGUMENTS];
591 struct cx18 *cx = s->cx;
1c1e45d1 592 int captype = 0;
dcc0ef88 593 struct cx18_api_func_private priv;
e46c54a8 594 struct cx18_stream *s_idx;
1c1e45d1 595
540bab93 596 if (!cx18_stream_enabled(s))
1c1e45d1
HV
597 return -EINVAL;
598
599 CX18_DEBUG_INFO("Start encoder stream %s\n", s->name);
600
601 switch (s->type) {
602 case CX18_ENC_STREAM_TYPE_MPG:
603 captype = CAPTURE_CHANNEL_TYPE_MPEG;
604 cx->mpg_data_received = cx->vbi_data_inserted = 0;
605 cx->dualwatch_jiffies = jiffies;
606 cx->dualwatch_stereo_mode = cx->params.audio_properties & 0x300;
607 cx->search_pack_header = 0;
608 break;
609
e46c54a8
AW
610 case CX18_ENC_STREAM_TYPE_IDX:
611 captype = CAPTURE_CHANNEL_TYPE_INDEX;
612 break;
1c1e45d1
HV
613 case CX18_ENC_STREAM_TYPE_TS:
614 captype = CAPTURE_CHANNEL_TYPE_TS;
1c1e45d1
HV
615 break;
616 case CX18_ENC_STREAM_TYPE_YUV:
617 captype = CAPTURE_CHANNEL_TYPE_YUV;
618 break;
619 case CX18_ENC_STREAM_TYPE_PCM:
620 captype = CAPTURE_CHANNEL_TYPE_PCM;
621 break;
622 case CX18_ENC_STREAM_TYPE_VBI:
dcc0ef88 623#ifdef CX18_ENCODER_PARSES_SLICED
dd073434
AW
624 captype = cx18_raw_vbi(cx) ?
625 CAPTURE_CHANNEL_TYPE_VBI : CAPTURE_CHANNEL_TYPE_SLICED_VBI;
dcc0ef88
AW
626#else
627 /*
628 * Currently we set things up so that Sliced VBI from the
629 * digitizer is handled as Raw VBI by the encoder
630 */
631 captype = CAPTURE_CHANNEL_TYPE_VBI;
632#endif
1c1e45d1
HV
633 cx->vbi.frame = 0;
634 cx->vbi.inserted_frame = 0;
635 memset(cx->vbi.sliced_mpeg_size,
636 0, sizeof(cx->vbi.sliced_mpeg_size));
637 break;
638 default:
639 return -EINVAL;
640 }
1c1e45d1 641
1c1e45d1
HV
642 /* Clear Streamoff flags in case left from last capture */
643 clear_bit(CX18_F_S_STREAMOFF, &s->s_flags);
644
645 cx18_vapi_result(cx, data, CX18_CREATE_TASK, 1, CPU_CMD_MASK_CAPTURE);
646 s->handle = data[0];
647 cx18_vapi(cx, CX18_CPU_SET_CHANNEL_TYPE, 2, s->handle, captype);
648
dcc0ef88
AW
649 /*
650 * For everything but CAPTURE_CHANNEL_TYPE_TS, play it safe and
651 * set up all the parameters, as it is not obvious which parameters the
652 * firmware shares across capture channel types and which it does not.
653 *
654 * Some of the cx18_vapi() calls below apply to only certain capture
655 * channel types. We're hoping there's no harm in calling most of them
656 * anyway, as long as the values are all consistent. Setting some
657 * shared parameters will have no effect once an analog capture channel
658 * has started streaming.
659 */
660 if (captype != CAPTURE_CHANNEL_TYPE_TS) {
1c1e45d1
HV
661 cx18_vapi(cx, CX18_CPU_SET_VER_CROP_LINE, 2, s->handle, 0);
662 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 3, 1);
663 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 8, 0);
664 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 3, s->handle, 4, 1);
1c1e45d1 665
dcc0ef88
AW
666 /*
667 * Audio related reset according to
668 * Documentation/video4linux/cx2341x/fw-encoder-api.txt
669 */
670 if (atomic_read(&cx->ana_capturing) == 0)
671 cx18_vapi(cx, CX18_CPU_SET_MISC_PARAMETERS, 2,
672 s->handle, 12);
673
674 /*
675 * Number of lines for Field 1 & Field 2 according to
676 * Documentation/video4linux/cx2341x/fw-encoder-api.txt
f37aa511
AW
677 * Field 1 is 312 for 625 line systems in BT.656
678 * Field 2 is 313 for 625 line systems in BT.656
dcc0ef88 679 */
1c1e45d1 680 cx18_vapi(cx, CX18_CPU_SET_CAPTURE_LINE_NO, 3,
f37aa511 681 s->handle, 312, 313);
1c1e45d1 682
1c1e45d1
HV
683 if (cx->v4l2_cap & V4L2_CAP_VBI_CAPTURE)
684 cx18_vbi_setup(s);
685
dcc0ef88 686 /*
e46c54a8
AW
687 * Select to receive I, P, and B frame index entries, if the
688 * index stream is enabled. Otherwise disable index entry
689 * generation.
dcc0ef88 690 */
e46c54a8 691 s_idx = &cx->streams[CX18_ENC_STREAM_TYPE_IDX];
5ada5773
AW
692 cx18_vapi_result(cx, data, CX18_CPU_SET_INDEXTABLE, 2,
693 s->handle, cx18_stream_enabled(s_idx) ? 7 : 0);
1c1e45d1 694
dcc0ef88 695 /* Call out to the common CX2341x API setup for user controls */
50b86bac
AW
696 priv.cx = cx;
697 priv.s = s;
698 cx2341x_update(&priv, cx18_api_func, NULL, &cx->params);
dcc0ef88
AW
699
700 /*
701 * When starting a capture and we're set for radio,
702 * ensure the video is muted, despite the user control.
703 */
704 if (!cx->params.video_mute &&
705 test_bit(CX18_F_I_RADIO_USER, &cx->i_flags))
706 cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, s->handle,
707 (cx->params.video_mute_yuv << 8) | 1);
1c1e45d1
HV
708 }
709
31554ae5 710 if (atomic_read(&cx->tot_capturing) == 0) {
1c1e45d1 711 clear_bit(CX18_F_I_EOS, &cx->i_flags);
b1526421 712 cx18_write_reg(cx, 7, CX18_DSP0_INTERRUPT_MASK);
1c1e45d1
HV
713 }
714
715 cx18_vapi(cx, CX18_CPU_DE_SET_MDL_ACK, 3, s->handle,
990c81c8
AV
716 (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][0] - cx->enc_mem,
717 (void __iomem *)&cx->scb->cpu_mdl_ack[s->type][1] - cx->enc_mem);
1c1e45d1 718
66c2a6b0 719 /* Init all the cpu_mdls for this stream */
52fcb3ec 720 cx18_stream_configure_mdls(s);
87116159 721 _cx18_stream_load_fw_queue(s);
66c2a6b0 722
1c1e45d1
HV
723 /* begin_capture */
724 if (cx18_vapi(cx, CX18_CPU_CAPTURE_START, 1, s->handle)) {
725 CX18_DEBUG_WARN("Error starting capture!\n");
3b5df8ea 726 /* Ensure we're really not capturing before releasing MDLs */
87116159 727 set_bit(CX18_F_S_STOPPING, &s->s_flags);
3b5df8ea
AW
728 if (s->type == CX18_ENC_STREAM_TYPE_MPG)
729 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, 1);
730 else
731 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
66c2a6b0
AW
732 clear_bit(CX18_F_S_STREAMING, &s->s_flags);
733 /* FIXME - CX18_F_S_STREAMOFF as well? */
3b5df8ea 734 cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
1c1e45d1 735 cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
66c2a6b0 736 s->handle = CX18_INVALID_TASK_HANDLE;
87116159 737 clear_bit(CX18_F_S_STOPPING, &s->s_flags);
66c2a6b0
AW
738 if (atomic_read(&cx->tot_capturing) == 0) {
739 set_bit(CX18_F_I_EOS, &cx->i_flags);
740 cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
741 }
1c1e45d1
HV
742 return -EINVAL;
743 }
744
745 /* you're live! sit back and await interrupts :) */
dcc0ef88 746 if (captype != CAPTURE_CHANNEL_TYPE_TS)
31554ae5
HV
747 atomic_inc(&cx->ana_capturing);
748 atomic_inc(&cx->tot_capturing);
1c1e45d1
HV
749 return 0;
750}
0f4cf676 751EXPORT_SYMBOL(cx18_start_v4l2_encode_stream);
1c1e45d1
HV
752
753void cx18_stop_all_captures(struct cx18 *cx)
754{
755 int i;
756
757 for (i = CX18_MAX_STREAMS - 1; i >= 0; i--) {
758 struct cx18_stream *s = &cx->streams[i];
759
540bab93 760 if (!cx18_stream_enabled(s))
1c1e45d1
HV
761 continue;
762 if (test_bit(CX18_F_S_STREAMING, &s->s_flags))
763 cx18_stop_v4l2_encode_stream(s, 0);
764 }
765}
766
767int cx18_stop_v4l2_encode_stream(struct cx18_stream *s, int gop_end)
768{
769 struct cx18 *cx = s->cx;
770 unsigned long then;
771
540bab93 772 if (!cx18_stream_enabled(s))
1c1e45d1
HV
773 return -EINVAL;
774
775 /* This function assumes that you are allowed to stop the capture
776 and that we are actually capturing */
777
778 CX18_DEBUG_INFO("Stop Capture\n");
779
31554ae5 780 if (atomic_read(&cx->tot_capturing) == 0)
1c1e45d1
HV
781 return 0;
782
87116159 783 set_bit(CX18_F_S_STOPPING, &s->s_flags);
1c1e45d1
HV
784 if (s->type == CX18_ENC_STREAM_TYPE_MPG)
785 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 2, s->handle, !gop_end);
786 else
787 cx18_vapi(cx, CX18_CPU_CAPTURE_STOP, 1, s->handle);
788
789 then = jiffies;
790
791 if (s->type == CX18_ENC_STREAM_TYPE_MPG && gop_end) {
792 CX18_INFO("ignoring gop_end: not (yet?) supported by the firmware\n");
793 }
794
31554ae5
HV
795 if (s->type != CX18_ENC_STREAM_TYPE_TS)
796 atomic_dec(&cx->ana_capturing);
797 atomic_dec(&cx->tot_capturing);
1c1e45d1
HV
798
799 /* Clear capture and no-read bits */
800 clear_bit(CX18_F_S_STREAMING, &s->s_flags);
801
f68d0cf5
AW
802 /* Tell the CX23418 it can't use our buffers anymore */
803 cx18_vapi(cx, CX18_CPU_DE_RELEASE_MDL, 1, s->handle);
804
1c1e45d1 805 cx18_vapi(cx, CX18_DESTROY_TASK, 1, s->handle);
d3c5e707 806 s->handle = CX18_INVALID_TASK_HANDLE;
87116159 807 clear_bit(CX18_F_S_STOPPING, &s->s_flags);
1c1e45d1 808
31554ae5 809 if (atomic_read(&cx->tot_capturing) > 0)
1c1e45d1
HV
810 return 0;
811
b1526421 812 cx18_write_reg(cx, 5, CX18_DSP0_INTERRUPT_MASK);
1c1e45d1
HV
813 wake_up(&s->waitq);
814
815 return 0;
816}
0f4cf676 817EXPORT_SYMBOL(cx18_stop_v4l2_encode_stream);
1c1e45d1
HV
818
819u32 cx18_find_handle(struct cx18 *cx)
820{
821 int i;
822
823 /* find first available handle to be used for global settings */
824 for (i = 0; i < CX18_MAX_STREAMS; i++) {
825 struct cx18_stream *s = &cx->streams[i];
826
3d05913d 827 if (s->video_dev && (s->handle != CX18_INVALID_TASK_HANDLE))
1c1e45d1
HV
828 return s->handle;
829 }
d3c5e707 830 return CX18_INVALID_TASK_HANDLE;
1c1e45d1 831}
ee2d64f5
AW
832
833struct cx18_stream *cx18_handle_to_stream(struct cx18 *cx, u32 handle)
834{
835 int i;
836 struct cx18_stream *s;
837
838 if (handle == CX18_INVALID_TASK_HANDLE)
839 return NULL;
840
841 for (i = 0; i < CX18_MAX_STREAMS; i++) {
842 s = &cx->streams[i];
843 if (s->handle != handle)
844 continue;
540bab93 845 if (cx18_stream_enabled(s))
ee2d64f5
AW
846 return s;
847 }
848 return NULL;
849}