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Commit | Line | Data |
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9ea53b74 | 1 | /* |
11b64d31 | 2 | * driver for ENE KB3926 B/C/D/E/F CIR (pnp id: ENE0XXX) |
9ea53b74 ML |
3 | * |
4 | * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of the | |
9 | * License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 | |
19 | * USA | |
11b64d31 ML |
20 | * |
21 | * Special thanks to: | |
22 | * Sami R. <maesesami@gmail.com> for lot of help in debugging and therefore | |
23 | * bringing to life support for transmission & learning mode. | |
24 | * | |
25 | * Charlie Andrews <charliethepilot@googlemail.com> for lots of help in | |
26 | * bringing up the support of new firmware buffer that is popular | |
27 | * on latest notebooks | |
28 | * | |
29 | * ENE for partial device documentation | |
30 | * | |
9ea53b74 ML |
31 | */ |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pnp.h> | |
36 | #include <linux/io.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/sched.h> | |
931e39a1 ML |
39 | #include <linux/slab.h> |
40 | #include <linux/input.h> | |
41 | #include <media/ir-core.h> | |
42 | #include <media/ir-common.h> | |
43 | #include "ene_ir.h" | |
9ea53b74 | 44 | |
11b64d31 | 45 | static int sample_period; |
c29bc4d7 | 46 | static bool learning_mode_force; |
9ea53b74 | 47 | static int debug; |
11b64d31 | 48 | static bool txsim; |
9ea53b74 | 49 | |
11b64d31 ML |
50 | static void ene_set_reg_addr(struct ene_device *dev, u16 reg) |
51 | { | |
52 | outb(reg >> 8, dev->hw_io + ENE_ADDR_HI); | |
53 | outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO); | |
54 | } | |
9ea53b74 ML |
55 | |
56 | /* read a hardware register */ | |
11b64d31 | 57 | static u8 ene_read_reg(struct ene_device *dev, u16 reg) |
9ea53b74 ML |
58 | { |
59 | u8 retval; | |
11b64d31 | 60 | ene_set_reg_addr(dev, reg); |
9ea53b74 | 61 | retval = inb(dev->hw_io + ENE_IO); |
11b64d31 | 62 | dbg_regs("reg %04x == %02x", reg, retval); |
9ea53b74 ML |
63 | return retval; |
64 | } | |
65 | ||
66 | /* write a hardware register */ | |
11b64d31 | 67 | static void ene_write_reg(struct ene_device *dev, u16 reg, u8 value) |
9ea53b74 | 68 | { |
11b64d31 ML |
69 | dbg_regs("reg %04x <- %02x", reg, value); |
70 | ene_set_reg_addr(dev, reg); | |
9ea53b74 | 71 | outb(value, dev->hw_io + ENE_IO); |
9ea53b74 ML |
72 | } |
73 | ||
11b64d31 ML |
74 | /* Set bits in hardware register */ |
75 | static void ene_set_reg_mask(struct ene_device *dev, u16 reg, u8 mask) | |
9ea53b74 | 76 | { |
11b64d31 ML |
77 | dbg_regs("reg %04x |= %02x", reg, mask); |
78 | ene_set_reg_addr(dev, reg); | |
79 | outb(inb(dev->hw_io + ENE_IO) | mask, dev->hw_io + ENE_IO); | |
80 | } | |
9ea53b74 | 81 | |
11b64d31 ML |
82 | /* Clear bits in hardware register */ |
83 | static void ene_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask) | |
84 | { | |
85 | dbg_regs("reg %04x &= ~%02x ", reg, mask); | |
86 | ene_set_reg_addr(dev, reg); | |
87 | outb(inb(dev->hw_io + ENE_IO) & ~mask, dev->hw_io + ENE_IO); | |
88 | } | |
9ea53b74 | 89 | |
11b64d31 ML |
90 | /* A helper to set/clear a bit in register according to boolean variable */ |
91 | static void ene_set_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask, | |
92 | bool set) | |
93 | { | |
94 | if (set) | |
95 | ene_set_reg_mask(dev, reg, mask); | |
96 | else | |
97 | ene_clear_reg_mask(dev, reg, mask); | |
9ea53b74 ML |
98 | } |
99 | ||
100 | /* detect hardware features */ | |
101 | static int ene_hw_detect(struct ene_device *dev) | |
102 | { | |
103 | u8 chip_major, chip_minor; | |
104 | u8 hw_revision, old_ver; | |
11b64d31 | 105 | u8 fw_reg2, fw_reg1; |
9ea53b74 | 106 | |
11b64d31 ML |
107 | ene_clear_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD); |
108 | chip_major = ene_read_reg(dev, ENE_ECVER_MAJOR); | |
109 | chip_minor = ene_read_reg(dev, ENE_ECVER_MINOR); | |
110 | ene_set_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD); | |
9ea53b74 | 111 | |
11b64d31 ML |
112 | hw_revision = ene_read_reg(dev, ENE_ECHV); |
113 | old_ver = ene_read_reg(dev, ENE_HW_VER_OLD); | |
9ea53b74 | 114 | |
11b64d31 ML |
115 | dev->pll_freq = (ene_read_reg(dev, ENE_PLLFRH) << 4) + |
116 | (ene_read_reg(dev, ENE_PLLFRL) >> 4); | |
931e39a1 | 117 | |
11b64d31 ML |
118 | if (sample_period != ENE_DEFAULT_SAMPLE_PERIOD) |
119 | dev->rx_period_adjust = | |
120 | dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 2 : 4; | |
931e39a1 | 121 | |
9ea53b74 | 122 | if (hw_revision == 0xFF) { |
11b64d31 ML |
123 | ene_warn("device seems to be disabled"); |
124 | ene_warn("send a mail to lirc-list@lists.sourceforge.net"); | |
125 | ene_warn("please attach output of acpidump and dmidecode"); | |
9ea53b74 ML |
126 | return -ENODEV; |
127 | } | |
128 | ||
11b64d31 ML |
129 | ene_notice("chip is 0x%02x%02x - kbver = 0x%02x, rev = 0x%02x", |
130 | chip_major, chip_minor, old_ver, hw_revision); | |
131 | ||
132 | ene_notice("PLL freq = %d", dev->pll_freq); | |
133 | ||
9ea53b74 | 134 | if (chip_major == 0x33) { |
11b64d31 | 135 | ene_warn("chips 0x33xx aren't supported"); |
9ea53b74 ML |
136 | return -ENODEV; |
137 | } | |
138 | ||
139 | if (chip_major == 0x39 && chip_minor == 0x26 && hw_revision == 0xC0) { | |
140 | dev->hw_revision = ENE_HW_C; | |
11b64d31 | 141 | ene_notice("KB3926C detected"); |
9ea53b74 ML |
142 | } else if (old_ver == 0x24 && hw_revision == 0xC0) { |
143 | dev->hw_revision = ENE_HW_B; | |
11b64d31 | 144 | ene_notice("KB3926B detected"); |
9ea53b74 ML |
145 | } else { |
146 | dev->hw_revision = ENE_HW_D; | |
11b64d31 | 147 | ene_notice("KB3926D or higher detected"); |
9ea53b74 ML |
148 | } |
149 | ||
9ea53b74 ML |
150 | /* detect features hardware supports */ |
151 | if (dev->hw_revision < ENE_HW_C) | |
152 | return 0; | |
153 | ||
11b64d31 ML |
154 | fw_reg1 = ene_read_reg(dev, ENE_FW1); |
155 | fw_reg2 = ene_read_reg(dev, ENE_FW2); | |
9ea53b74 | 156 | |
11b64d31 | 157 | ene_notice("Firmware regs: %02x %02x", fw_reg1, fw_reg2); |
9ea53b74 | 158 | |
a06423c9 ML |
159 | dev->hw_use_gpio_0a = !!(fw_reg2 & ENE_FW2_GP0A); |
160 | dev->hw_learning_and_tx_capable = !!(fw_reg2 & ENE_FW2_LEARNING); | |
161 | dev->hw_extra_buffer = !!(fw_reg1 & ENE_FW1_HAS_EXTRA_BUF); | |
162 | ||
163 | if (dev->hw_learning_and_tx_capable) | |
164 | dev->hw_fan_input = !!(fw_reg2 & ENE_FW2_FAN_INPUT); | |
9ea53b74 | 165 | |
11b64d31 | 166 | ene_notice("Hardware features:"); |
9ea53b74 ML |
167 | |
168 | if (dev->hw_learning_and_tx_capable) { | |
11b64d31 ML |
169 | ene_notice("* Supports transmitting & learning mode"); |
170 | ene_notice(" This feature is rare and therefore,"); | |
171 | ene_notice(" you are welcome to test it,"); | |
172 | ene_notice(" and/or contact the author via:"); | |
173 | ene_notice(" lirc-list@lists.sourceforge.net"); | |
174 | ene_notice(" or maximlevitsky@gmail.com"); | |
175 | ||
176 | ene_notice("* Uses GPIO %s for IR raw input", | |
177 | dev->hw_use_gpio_0a ? "40" : "0A"); | |
178 | ||
179 | if (dev->hw_fan_input) | |
180 | ene_notice("* Uses unused fan feedback input as source" | |
181 | " of demodulated IR data"); | |
9ea53b74 | 182 | } |
11b64d31 ML |
183 | |
184 | if (!dev->hw_fan_input) | |
185 | ene_notice("* Uses GPIO %s for IR demodulated input", | |
186 | dev->hw_use_gpio_0a ? "0A" : "40"); | |
187 | ||
188 | if (dev->hw_extra_buffer) | |
189 | ene_notice("* Uses new style input buffer"); | |
9ea53b74 ML |
190 | return 0; |
191 | } | |
192 | ||
c29bc4d7 ML |
193 | /* Read properities of hw sample buffer */ |
194 | static void ene_rx_setup_hw_buffer(struct ene_device *dev) | |
195 | { | |
196 | u16 tmp; | |
197 | ||
198 | ene_rx_read_hw_pointer(dev); | |
199 | dev->r_pointer = dev->w_pointer; | |
200 | ||
201 | if (!dev->hw_extra_buffer) { | |
202 | dev->buffer_len = ENE_FW_PACKET_SIZE * 2; | |
203 | return; | |
204 | } | |
205 | ||
206 | tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER); | |
207 | tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER+1) << 8; | |
208 | dev->extra_buf1_address = tmp; | |
209 | ||
210 | dev->extra_buf1_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 2); | |
211 | ||
212 | tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 3); | |
213 | tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 4) << 8; | |
214 | dev->extra_buf2_address = tmp; | |
215 | ||
216 | dev->extra_buf2_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 5); | |
217 | ||
218 | dev->buffer_len = dev->extra_buf1_len + dev->extra_buf2_len + 8; | |
219 | ||
220 | ene_notice("Hardware uses 2 extended buffers:"); | |
221 | ene_notice(" 0x%04x - len : %d", dev->extra_buf1_address, | |
222 | dev->extra_buf1_len); | |
223 | ene_notice(" 0x%04x - len : %d", dev->extra_buf2_address, | |
224 | dev->extra_buf2_len); | |
225 | ||
226 | ene_notice("Total buffer len = %d", dev->buffer_len); | |
227 | ||
228 | if (dev->buffer_len > 64 || dev->buffer_len < 16) | |
229 | goto error; | |
230 | ||
231 | if (dev->extra_buf1_address > 0xFBFC || | |
232 | dev->extra_buf1_address < 0xEC00) | |
233 | goto error; | |
234 | ||
235 | if (dev->extra_buf2_address > 0xFBFC || | |
236 | dev->extra_buf2_address < 0xEC00) | |
237 | goto error; | |
238 | ||
239 | if (dev->r_pointer > dev->buffer_len) | |
240 | goto error; | |
241 | ||
242 | ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND); | |
243 | return; | |
244 | error: | |
245 | ene_warn("Error validating extra buffers, device probably won't work"); | |
246 | dev->hw_extra_buffer = false; | |
247 | ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND); | |
248 | } | |
249 | ||
250 | ||
251 | /* Restore the pointers to extra buffers - to make module reload work*/ | |
252 | static void ene_rx_restore_hw_buffer(struct ene_device *dev) | |
253 | { | |
254 | if (!dev->hw_extra_buffer) | |
255 | return; | |
256 | ||
257 | ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 0, | |
258 | dev->extra_buf1_address & 0xFF); | |
259 | ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 1, | |
260 | dev->extra_buf1_address >> 8); | |
261 | ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 2, dev->extra_buf1_len); | |
262 | ||
263 | ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 3, | |
264 | dev->extra_buf2_address & 0xFF); | |
265 | ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 4, | |
266 | dev->extra_buf2_address >> 8); | |
267 | ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 5, | |
268 | dev->extra_buf2_len); | |
269 | ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND); | |
270 | } | |
271 | ||
272 | /* Read hardware write pointer */ | |
273 | static void ene_rx_read_hw_pointer(struct ene_device *dev) | |
274 | { | |
275 | if (dev->hw_extra_buffer) | |
276 | dev->w_pointer = ene_read_reg(dev, ENE_FW_RX_POINTER); | |
277 | else | |
278 | dev->w_pointer = ene_read_reg(dev, ENE_FW2) | |
279 | & ENE_FW2_BUF_WPTR ? 0 : ENE_FW_PACKET_SIZE; | |
280 | ||
281 | dbg_verbose("RB: HW write pointer: %02x, driver read pointer: %02x", | |
282 | dev->w_pointer, dev->r_pointer); | |
283 | } | |
284 | ||
285 | /* Gets address of next sample from HW ring buffer */ | |
286 | static int ene_rx_get_sample_reg(struct ene_device *dev) | |
287 | { | |
288 | int r_pointer; | |
289 | ||
290 | if (dev->r_pointer == dev->w_pointer) { | |
291 | dbg_verbose("RB: hit end, try update w_pointer"); | |
292 | ene_rx_read_hw_pointer(dev); | |
293 | } | |
294 | ||
295 | if (dev->r_pointer == dev->w_pointer) { | |
296 | dbg_verbose("RB: end of data at %d", dev->r_pointer); | |
297 | return 0; | |
298 | } | |
299 | ||
300 | dbg_verbose("RB: reading at offset %d", dev->r_pointer); | |
301 | r_pointer = dev->r_pointer; | |
302 | ||
303 | dev->r_pointer++; | |
304 | if (dev->r_pointer == dev->buffer_len) | |
305 | dev->r_pointer = 0; | |
306 | ||
307 | dbg_verbose("RB: next read will be from offset %d", dev->r_pointer); | |
308 | ||
309 | if (r_pointer < 8) { | |
310 | dbg_verbose("RB: read at main buffer at %d", r_pointer); | |
311 | return ENE_FW_SAMPLE_BUFFER + r_pointer; | |
312 | } | |
313 | ||
314 | r_pointer -= 8; | |
315 | ||
316 | if (r_pointer < dev->extra_buf1_len) { | |
317 | dbg_verbose("RB: read at 1st extra buffer at %d", r_pointer); | |
318 | return dev->extra_buf1_address + r_pointer; | |
319 | } | |
320 | ||
321 | r_pointer -= dev->extra_buf1_len; | |
322 | ||
323 | if (r_pointer < dev->extra_buf2_len) { | |
324 | dbg_verbose("RB: read at 2nd extra buffer at %d", r_pointer); | |
325 | return dev->extra_buf2_address + r_pointer; | |
326 | } | |
327 | ||
328 | dbg("attempt to read beyong ring bufer end"); | |
329 | return 0; | |
330 | } | |
331 | ||
11b64d31 ML |
332 | /* Sense current received carrier */ |
333 | void ene_rx_sense_carrier(struct ene_device *dev) | |
9ea53b74 | 334 | { |
e1b1ddbe ML |
335 | DEFINE_IR_RAW_EVENT(ev); |
336 | ||
337 | int carrier, duty_cycle; | |
11b64d31 ML |
338 | int period = ene_read_reg(dev, ENE_CIRCAR_PRD); |
339 | int hperiod = ene_read_reg(dev, ENE_CIRCAR_HPRD); | |
11b64d31 ML |
340 | |
341 | if (!(period & ENE_CIRCAR_PRD_VALID)) | |
342 | return; | |
343 | ||
344 | period &= ~ENE_CIRCAR_PRD_VALID; | |
345 | ||
346 | if (!period) | |
347 | return; | |
348 | ||
349 | dbg("RX: hardware carrier period = %02x", period); | |
350 | dbg("RX: hardware carrier pulse period = %02x", hperiod); | |
351 | ||
11b64d31 ML |
352 | carrier = 2000000 / period; |
353 | duty_cycle = (hperiod * 100) / period; | |
354 | dbg("RX: sensed carrier = %d Hz, duty cycle %d%%", | |
e1b1ddbe ML |
355 | carrier, duty_cycle); |
356 | if (dev->carrier_detect_enabled) { | |
357 | ev.carrier_report = true; | |
358 | ev.carrier = carrier; | |
359 | ev.duty_cycle = duty_cycle; | |
360 | ir_raw_event_store(dev->idev, &ev); | |
361 | } | |
9ea53b74 ML |
362 | } |
363 | ||
11b64d31 | 364 | /* this enables/disables the CIR RX engine */ |
c29bc4d7 | 365 | static void ene_rx_enable_cir_engine(struct ene_device *dev, bool enable) |
9ea53b74 | 366 | { |
11b64d31 ML |
367 | ene_set_clear_reg_mask(dev, ENE_CIRCFG, |
368 | ENE_CIRCFG_RX_EN | ENE_CIRCFG_RX_IRQ, enable); | |
9ea53b74 ML |
369 | } |
370 | ||
11b64d31 | 371 | /* this selects input for CIR engine. Ether GPIO 0A or GPIO40*/ |
c29bc4d7 | 372 | static void ene_rx_select_input(struct ene_device *dev, bool gpio_0a) |
9ea53b74 | 373 | { |
11b64d31 | 374 | ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_GPIO0A, gpio_0a); |
9ea53b74 ML |
375 | } |
376 | ||
11b64d31 ML |
377 | /* |
378 | * this enables alternative input via fan tachometer sensor and bypasses | |
379 | * the hw CIR engine | |
380 | */ | |
c29bc4d7 | 381 | static void ene_rx_enable_fan_input(struct ene_device *dev, bool enable) |
9ea53b74 | 382 | { |
11b64d31 ML |
383 | if (!dev->hw_fan_input) |
384 | return; | |
9ea53b74 | 385 | |
11b64d31 ML |
386 | if (!enable) |
387 | ene_write_reg(dev, ENE_FAN_AS_IN1, 0); | |
388 | else { | |
389 | ene_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN); | |
390 | ene_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN); | |
391 | } | |
9ea53b74 ML |
392 | } |
393 | ||
11b64d31 ML |
394 | /* setup the receiver for RX*/ |
395 | static void ene_rx_setup(struct ene_device *dev) | |
9ea53b74 | 396 | { |
c29bc4d7 | 397 | bool learning_mode = dev->learning_mode_enabled || |
11b64d31 ML |
398 | dev->carrier_detect_enabled; |
399 | int sample_period_adjust = 0; | |
9ea53b74 | 400 | |
c29bc4d7 ML |
401 | dbg("RX: setup receiver, learning mode = %d", learning_mode); |
402 | ||
403 | ||
a06423c9 ML |
404 | /* This selects RLC input and clears CFG2 settings */ |
405 | ene_write_reg(dev, ENE_CIRCFG2, 0x00); | |
9ea53b74 | 406 | |
11b64d31 ML |
407 | /* set sample period*/ |
408 | if (sample_period == ENE_DEFAULT_SAMPLE_PERIOD) | |
409 | sample_period_adjust = | |
410 | dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 1 : 2; | |
9ea53b74 | 411 | |
11b64d31 ML |
412 | ene_write_reg(dev, ENE_CIRRLC_CFG, |
413 | (sample_period + sample_period_adjust) | | |
414 | ENE_CIRRLC_CFG_OVERFLOW); | |
415 | /* revB doesn't support inputs */ | |
416 | if (dev->hw_revision < ENE_HW_C) | |
417 | goto select_timeout; | |
9ea53b74 | 418 | |
a06423c9 ML |
419 | if (learning_mode) { |
420 | ||
421 | WARN_ON(!dev->hw_learning_and_tx_capable); | |
9ea53b74 | 422 | |
11b64d31 ML |
423 | /* Enable the opposite of the normal input |
424 | That means that if GPIO40 is normally used, use GPIO0A | |
425 | and vice versa. | |
426 | This input will carry non demodulated | |
427 | signal, and we will tell the hw to demodulate it itself */ | |
c29bc4d7 | 428 | ene_rx_select_input(dev, !dev->hw_use_gpio_0a); |
11b64d31 | 429 | dev->rx_fan_input_inuse = false; |
9ea53b74 | 430 | |
11b64d31 ML |
431 | /* Enable carrier demodulation */ |
432 | ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD); | |
9ea53b74 | 433 | |
11b64d31 | 434 | /* Enable carrier detection */ |
a06423c9 | 435 | ene_write_reg(dev, ENE_CIRCAR_PULS, 0x63); |
11b64d31 ML |
436 | ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT, |
437 | dev->carrier_detect_enabled || debug); | |
9ea53b74 | 438 | } else { |
11b64d31 ML |
439 | if (dev->hw_fan_input) |
440 | dev->rx_fan_input_inuse = true; | |
441 | else | |
c29bc4d7 | 442 | ene_rx_select_input(dev, dev->hw_use_gpio_0a); |
11b64d31 ML |
443 | |
444 | /* Disable carrier detection & demodulation */ | |
445 | ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD); | |
446 | ene_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT); | |
9ea53b74 ML |
447 | } |
448 | ||
11b64d31 | 449 | select_timeout: |
931e39a1 | 450 | if (dev->rx_fan_input_inuse) { |
11b64d31 | 451 | dev->props->rx_resolution = MS_TO_NS(ENE_FW_SAMPLE_PERIOD_FAN); |
931e39a1 | 452 | |
11b64d31 ML |
453 | /* Fan input doesn't support timeouts, it just ends the |
454 | input with a maximum sample */ | |
455 | dev->props->min_timeout = dev->props->max_timeout = | |
456 | MS_TO_NS(ENE_FW_SMPL_BUF_FAN_MSK * | |
457 | ENE_FW_SAMPLE_PERIOD_FAN); | |
931e39a1 | 458 | } else { |
11b64d31 ML |
459 | dev->props->rx_resolution = MS_TO_NS(sample_period); |
460 | ||
461 | /* Theoreticly timeout is unlimited, but we cap it | |
462 | * because it was seen that on one device, it | |
463 | * would stop sending spaces after around 250 msec. | |
464 | * Besides, this is close to 2^32 anyway and timeout is u32. | |
465 | */ | |
466 | dev->props->min_timeout = MS_TO_NS(127 * sample_period); | |
467 | dev->props->max_timeout = MS_TO_NS(200000); | |
931e39a1 | 468 | } |
11b64d31 ML |
469 | |
470 | if (dev->hw_learning_and_tx_capable) | |
471 | dev->props->tx_resolution = MS_TO_NS(sample_period); | |
472 | ||
473 | if (dev->props->timeout > dev->props->max_timeout) | |
474 | dev->props->timeout = dev->props->max_timeout; | |
475 | if (dev->props->timeout < dev->props->min_timeout) | |
476 | dev->props->timeout = dev->props->min_timeout; | |
9ea53b74 ML |
477 | } |
478 | ||
479 | /* Enable the device for receive */ | |
480 | static void ene_rx_enable(struct ene_device *dev) | |
481 | { | |
482 | u8 reg_value; | |
483 | ||
11b64d31 | 484 | /* Enable system interrupt */ |
9ea53b74 | 485 | if (dev->hw_revision < ENE_HW_C) { |
11b64d31 ML |
486 | ene_write_reg(dev, ENEB_IRQ, dev->irq << 1); |
487 | ene_write_reg(dev, ENEB_IRQ_UNK1, 0x01); | |
9ea53b74 | 488 | } else { |
11b64d31 ML |
489 | reg_value = ene_read_reg(dev, ENE_IRQ) & 0xF0; |
490 | reg_value |= ENE_IRQ_UNK_EN; | |
491 | reg_value &= ~ENE_IRQ_STATUS; | |
492 | reg_value |= (dev->irq & ENE_IRQ_MASK); | |
493 | ene_write_reg(dev, ENE_IRQ, reg_value); | |
9ea53b74 ML |
494 | } |
495 | ||
a06423c9 | 496 | /* Enable inputs */ |
c29bc4d7 ML |
497 | ene_rx_enable_fan_input(dev, dev->rx_fan_input_inuse); |
498 | ene_rx_enable_cir_engine(dev, !dev->rx_fan_input_inuse); | |
9ea53b74 ML |
499 | |
500 | /* ack any pending irqs - just in case */ | |
501 | ene_irq_status(dev); | |
502 | ||
9ea53b74 | 503 | /* enable firmware bits */ |
11b64d31 | 504 | ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ); |
931e39a1 ML |
505 | |
506 | /* enter idle mode */ | |
11b64d31 ML |
507 | ir_raw_event_set_idle(dev->idev, true); |
508 | dev->rx_enabled = true; | |
9ea53b74 ML |
509 | } |
510 | ||
931e39a1 | 511 | /* Disable the device receiver */ |
9ea53b74 ML |
512 | static void ene_rx_disable(struct ene_device *dev) |
513 | { | |
514 | /* disable inputs */ | |
c29bc4d7 ML |
515 | ene_rx_enable_cir_engine(dev, false); |
516 | ene_rx_enable_fan_input(dev, false); | |
9ea53b74 ML |
517 | |
518 | /* disable hardware IRQ and firmware flag */ | |
11b64d31 | 519 | ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ); |
9ea53b74 | 520 | |
11b64d31 ML |
521 | ir_raw_event_set_idle(dev->idev, true); |
522 | dev->rx_enabled = false; | |
9ea53b74 ML |
523 | } |
524 | ||
c29bc4d7 ML |
525 | /* This resets the receiver. Usefull to stop stream of spaces at end of |
526 | * transmission | |
527 | */ | |
528 | static void ene_rx_reset(struct ene_device *dev) | |
529 | { | |
530 | ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN); | |
531 | ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN); | |
532 | } | |
533 | ||
534 | /* Set up the TX carrier frequency and duty cycle */ | |
535 | static void ene_tx_set_carrier(struct ene_device *dev) | |
536 | { | |
537 | u8 tx_puls_width; | |
538 | unsigned long flags; | |
539 | ||
540 | spin_lock_irqsave(&dev->hw_lock, flags); | |
541 | ||
542 | ene_set_clear_reg_mask(dev, ENE_CIRCFG, | |
543 | ENE_CIRCFG_TX_CARR, dev->tx_period > 0); | |
544 | ||
545 | if (!dev->tx_period) | |
546 | goto unlock; | |
547 | ||
548 | BUG_ON(dev->tx_duty_cycle >= 100 || dev->tx_duty_cycle <= 0); | |
549 | ||
550 | tx_puls_width = dev->tx_period / (100 / dev->tx_duty_cycle); | |
551 | ||
552 | if (!tx_puls_width) | |
553 | tx_puls_width = 1; | |
554 | ||
555 | dbg("TX: pulse distance = %d * 500 ns", dev->tx_period); | |
556 | dbg("TX: pulse width = %d * 500 ns", tx_puls_width); | |
557 | ||
558 | ene_write_reg(dev, ENE_CIRMOD_PRD, dev->tx_period | ENE_CIRMOD_PRD_POL); | |
559 | ene_write_reg(dev, ENE_CIRMOD_HPRD, tx_puls_width); | |
560 | unlock: | |
561 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
562 | } | |
563 | ||
564 | /* Enable/disable transmitters */ | |
565 | static void ene_tx_set_transmitters(struct ene_device *dev) | |
566 | { | |
567 | unsigned long flags; | |
568 | ||
569 | spin_lock_irqsave(&dev->hw_lock, flags); | |
570 | ene_set_clear_reg_mask(dev, ENE_GPIOFS8, ENE_GPIOFS8_GPIO41, | |
571 | !!(dev->transmitter_mask & 0x01)); | |
572 | ene_set_clear_reg_mask(dev, ENE_GPIOFS1, ENE_GPIOFS1_GPIO0D, | |
573 | !!(dev->transmitter_mask & 0x02)); | |
574 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
575 | } | |
576 | ||
9ea53b74 | 577 | /* prepare transmission */ |
c29bc4d7 | 578 | static void ene_tx_enable(struct ene_device *dev) |
9ea53b74 | 579 | { |
11b64d31 ML |
580 | u8 conf1 = ene_read_reg(dev, ENE_CIRCFG); |
581 | u8 fwreg2 = ene_read_reg(dev, ENE_FW2); | |
9ea53b74 | 582 | |
9ea53b74 ML |
583 | dev->saved_conf1 = conf1; |
584 | ||
11b64d31 ML |
585 | /* Show information about currently connected transmitter jacks */ |
586 | if (fwreg2 & ENE_FW2_EMMITER1_CONN) | |
587 | dbg("TX: Transmitter #1 is connected"); | |
9ea53b74 | 588 | |
11b64d31 ML |
589 | if (fwreg2 & ENE_FW2_EMMITER2_CONN) |
590 | dbg("TX: Transmitter #2 is connected"); | |
9ea53b74 | 591 | |
11b64d31 ML |
592 | if (!(fwreg2 & (ENE_FW2_EMMITER1_CONN | ENE_FW2_EMMITER2_CONN))) |
593 | ene_warn("TX: transmitter cable isn't connected!"); | |
594 | ||
11b64d31 ML |
595 | /* disable receive on revc */ |
596 | if (dev->hw_revision == ENE_HW_C) | |
597 | conf1 &= ~ENE_CIRCFG_RX_EN; | |
9ea53b74 | 598 | |
11b64d31 ML |
599 | /* Enable TX engine */ |
600 | conf1 |= ENE_CIRCFG_TX_EN | ENE_CIRCFG_TX_IRQ; | |
601 | ene_write_reg(dev, ENE_CIRCFG, conf1); | |
9ea53b74 ML |
602 | } |
603 | ||
604 | /* end transmission */ | |
c29bc4d7 | 605 | static void ene_tx_disable(struct ene_device *dev) |
9ea53b74 | 606 | { |
11b64d31 | 607 | ene_write_reg(dev, ENE_CIRCFG, dev->saved_conf1); |
931e39a1 | 608 | dev->tx_buffer = NULL; |
9ea53b74 ML |
609 | } |
610 | ||
9ea53b74 ML |
611 | |
612 | /* TX one sample - must be called with dev->hw_lock*/ | |
613 | static void ene_tx_sample(struct ene_device *dev) | |
614 | { | |
615 | u8 raw_tx; | |
616 | u32 sample; | |
11b64d31 | 617 | bool pulse = dev->tx_sample_pulse; |
9ea53b74 | 618 | |
931e39a1 | 619 | if (!dev->tx_buffer) { |
11b64d31 | 620 | ene_warn("TX: BUG: attempt to transmit NULL buffer"); |
9ea53b74 ML |
621 | return; |
622 | } | |
623 | ||
624 | /* Grab next TX sample */ | |
625 | if (!dev->tx_sample) { | |
11b64d31 ML |
626 | |
627 | if (dev->tx_pos == dev->tx_len) { | |
9ea53b74 | 628 | if (!dev->tx_done) { |
11b64d31 ML |
629 | dbg("TX: no more data to send"); |
630 | dev->tx_done = true; | |
9ea53b74 ML |
631 | goto exit; |
632 | } else { | |
11b64d31 | 633 | dbg("TX: last sample sent by hardware"); |
c29bc4d7 | 634 | ene_tx_disable(dev); |
9ea53b74 ML |
635 | complete(&dev->tx_complete); |
636 | return; | |
637 | } | |
638 | } | |
639 | ||
640 | sample = dev->tx_buffer[dev->tx_pos++]; | |
641 | dev->tx_sample_pulse = !dev->tx_sample_pulse; | |
642 | ||
11b64d31 | 643 | dev->tx_sample = DIV_ROUND_CLOSEST(sample, sample_period); |
9ea53b74 | 644 | |
9ea53b74 | 645 | if (!dev->tx_sample) |
11b64d31 | 646 | dev->tx_sample = 1; |
9ea53b74 ML |
647 | } |
648 | ||
11b64d31 | 649 | raw_tx = min(dev->tx_sample , (unsigned int)ENE_CIRRLC_OUT_MASK); |
9ea53b74 ML |
650 | dev->tx_sample -= raw_tx; |
651 | ||
11b64d31 ML |
652 | dbg("TX: sample %8d (%s)", raw_tx * sample_period, |
653 | pulse ? "pulse" : "space"); | |
654 | if (pulse) | |
655 | raw_tx |= ENE_CIRRLC_OUT_PULSE; | |
656 | ||
657 | ene_write_reg(dev, | |
658 | dev->tx_reg ? ENE_CIRRLC_OUT1 : ENE_CIRRLC_OUT0, raw_tx); | |
9ea53b74 | 659 | |
9ea53b74 ML |
660 | dev->tx_reg = !dev->tx_reg; |
661 | exit: | |
662 | /* simulate TX done interrupt */ | |
663 | if (txsim) | |
664 | mod_timer(&dev->tx_sim_timer, jiffies + HZ / 500); | |
665 | } | |
666 | ||
667 | /* timer to simulate tx done interrupt */ | |
668 | static void ene_tx_irqsim(unsigned long data) | |
669 | { | |
670 | struct ene_device *dev = (struct ene_device *)data; | |
671 | unsigned long flags; | |
672 | ||
673 | spin_lock_irqsave(&dev->hw_lock, flags); | |
674 | ene_tx_sample(dev); | |
675 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
676 | } | |
677 | ||
678 | ||
679 | /* read irq status and ack it */ | |
680 | static int ene_irq_status(struct ene_device *dev) | |
681 | { | |
682 | u8 irq_status; | |
683 | u8 fw_flags1, fw_flags2; | |
9ea53b74 ML |
684 | int retval = 0; |
685 | ||
11b64d31 | 686 | fw_flags2 = ene_read_reg(dev, ENE_FW2); |
9ea53b74 ML |
687 | |
688 | if (dev->hw_revision < ENE_HW_C) { | |
11b64d31 | 689 | irq_status = ene_read_reg(dev, ENEB_IRQ_STATUS); |
9ea53b74 ML |
690 | |
691 | if (!(irq_status & ENEB_IRQ_STATUS_IR)) | |
692 | return 0; | |
693 | ||
11b64d31 | 694 | ene_clear_reg_mask(dev, ENEB_IRQ_STATUS, ENEB_IRQ_STATUS_IR); |
9ea53b74 ML |
695 | return ENE_IRQ_RX; |
696 | } | |
697 | ||
11b64d31 ML |
698 | irq_status = ene_read_reg(dev, ENE_IRQ); |
699 | if (!(irq_status & ENE_IRQ_STATUS)) | |
9ea53b74 ML |
700 | return 0; |
701 | ||
702 | /* original driver does that twice - a workaround ? */ | |
11b64d31 ML |
703 | ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS); |
704 | ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS); | |
9ea53b74 | 705 | |
11b64d31 ML |
706 | /* check RX interrupt */ |
707 | if (fw_flags2 & ENE_FW2_RXIRQ) { | |
708 | retval |= ENE_IRQ_RX; | |
709 | ene_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_RXIRQ); | |
710 | } | |
9ea53b74 | 711 | |
11b64d31 ML |
712 | /* check TX interrupt */ |
713 | fw_flags1 = ene_read_reg(dev, ENE_FW1); | |
9ea53b74 | 714 | if (fw_flags1 & ENE_FW1_TXIRQ) { |
11b64d31 | 715 | ene_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ); |
9ea53b74 ML |
716 | retval |= ENE_IRQ_TX; |
717 | } | |
718 | ||
11b64d31 ML |
719 | return retval; |
720 | } | |
9ea53b74 | 721 | |
9ea53b74 ML |
722 | /* interrupt handler */ |
723 | static irqreturn_t ene_isr(int irq, void *data) | |
724 | { | |
11b64d31 ML |
725 | u16 hw_value, reg; |
726 | int hw_sample, irq_status; | |
727 | bool pulse; | |
9ea53b74 | 728 | unsigned long flags; |
9ea53b74 ML |
729 | irqreturn_t retval = IRQ_NONE; |
730 | struct ene_device *dev = (struct ene_device *)data; | |
4651918a | 731 | DEFINE_IR_RAW_EVENT(ev); |
9ea53b74 | 732 | |
9ea53b74 | 733 | spin_lock_irqsave(&dev->hw_lock, flags); |
11b64d31 ML |
734 | |
735 | dbg_verbose("ISR called"); | |
c29bc4d7 | 736 | ene_rx_read_hw_pointer(dev); |
9ea53b74 ML |
737 | irq_status = ene_irq_status(dev); |
738 | ||
739 | if (!irq_status) | |
740 | goto unlock; | |
741 | ||
742 | retval = IRQ_HANDLED; | |
743 | ||
744 | if (irq_status & ENE_IRQ_TX) { | |
11b64d31 | 745 | dbg_verbose("TX interrupt"); |
9ea53b74 | 746 | if (!dev->hw_learning_and_tx_capable) { |
11b64d31 | 747 | dbg("TX interrupt on unsupported device!"); |
9ea53b74 ML |
748 | goto unlock; |
749 | } | |
750 | ene_tx_sample(dev); | |
751 | } | |
752 | ||
753 | if (!(irq_status & ENE_IRQ_RX)) | |
754 | goto unlock; | |
755 | ||
11b64d31 | 756 | dbg_verbose("RX interrupt"); |
9ea53b74 | 757 | |
e1b1ddbe | 758 | if (dev->hw_learning_and_tx_capable) |
11b64d31 ML |
759 | ene_rx_sense_carrier(dev); |
760 | ||
761 | /* On hardware that don't support extra buffer we need to trust | |
762 | the interrupt and not track the read pointer */ | |
763 | if (!dev->hw_extra_buffer) | |
764 | dev->r_pointer = dev->w_pointer == 0 ? ENE_FW_PACKET_SIZE : 0; | |
765 | ||
766 | while (1) { | |
9ea53b74 | 767 | |
c29bc4d7 | 768 | reg = ene_rx_get_sample_reg(dev); |
11b64d31 ML |
769 | |
770 | dbg_verbose("next sample to read at: %04x", reg); | |
771 | if (!reg) | |
772 | break; | |
773 | ||
774 | hw_value = ene_read_reg(dev, reg); | |
9ea53b74 ML |
775 | |
776 | if (dev->rx_fan_input_inuse) { | |
11b64d31 ML |
777 | |
778 | int offset = ENE_FW_SMPL_BUF_FAN - ENE_FW_SAMPLE_BUFFER; | |
779 | ||
9ea53b74 | 780 | /* read high part of the sample */ |
11b64d31 ML |
781 | hw_value |= ene_read_reg(dev, reg + offset) << 8; |
782 | pulse = hw_value & ENE_FW_SMPL_BUF_FAN_PLS; | |
9ea53b74 ML |
783 | |
784 | /* clear space bit, and other unused bits */ | |
11b64d31 ML |
785 | hw_value &= ENE_FW_SMPL_BUF_FAN_MSK; |
786 | hw_sample = hw_value * ENE_FW_SAMPLE_PERIOD_FAN; | |
9ea53b74 ML |
787 | |
788 | } else { | |
11b64d31 ML |
789 | pulse = !(hw_value & ENE_FW_SAMPLE_SPACE); |
790 | hw_value &= ~ENE_FW_SAMPLE_SPACE; | |
9ea53b74 | 791 | hw_sample = hw_value * sample_period; |
931e39a1 ML |
792 | |
793 | if (dev->rx_period_adjust) { | |
11b64d31 ML |
794 | hw_sample *= 100; |
795 | hw_sample /= (100 + dev->rx_period_adjust); | |
931e39a1 | 796 | } |
9ea53b74 | 797 | } |
9ea53b74 | 798 | |
11b64d31 ML |
799 | if (!dev->hw_extra_buffer && !hw_sample) { |
800 | dev->r_pointer = dev->w_pointer; | |
801 | continue; | |
802 | } | |
931e39a1 | 803 | |
11b64d31 | 804 | dbg("RX: %d (%s)", hw_sample, pulse ? "pulse" : "space"); |
931e39a1 | 805 | |
11b64d31 | 806 | ev.duration = MS_TO_NS(hw_sample); |
931e39a1 ML |
807 | ev.pulse = pulse; |
808 | ir_raw_event_store_with_filter(dev->idev, &ev); | |
9ea53b74 | 809 | } |
931e39a1 ML |
810 | |
811 | ir_raw_event_handle(dev->idev); | |
9ea53b74 ML |
812 | unlock: |
813 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
814 | return retval; | |
815 | } | |
816 | ||
817 | /* Initialize default settings */ | |
c29bc4d7 | 818 | static void ene_setup_default_settings(struct ene_device *dev) |
9ea53b74 | 819 | { |
9ea53b74 | 820 | dev->tx_period = 32; |
11b64d31 ML |
821 | dev->tx_duty_cycle = 50; /*%*/ |
822 | dev->transmitter_mask = 0x03; | |
c29bc4d7 | 823 | dev->learning_mode_enabled = learning_mode_force; |
9ea53b74 | 824 | |
11b64d31 | 825 | /* Set reasonable default timeout */ |
a06423c9 | 826 | dev->props->timeout = MS_TO_NS(150000); |
9ea53b74 ML |
827 | } |
828 | ||
c29bc4d7 ML |
829 | /* Upload all hardware settings at once. Used at load and resume time */ |
830 | static void ene_setup_hw_settings(struct ene_device *dev) | |
831 | { | |
832 | if (dev->hw_learning_and_tx_capable) { | |
833 | ene_tx_set_carrier(dev); | |
834 | ene_tx_set_transmitters(dev); | |
835 | } | |
836 | ||
837 | ene_rx_setup(dev); | |
838 | } | |
839 | ||
9ea53b74 ML |
840 | /* outside interface: called on first open*/ |
841 | static int ene_open(void *data) | |
842 | { | |
843 | struct ene_device *dev = (struct ene_device *)data; | |
844 | unsigned long flags; | |
845 | ||
846 | spin_lock_irqsave(&dev->hw_lock, flags); | |
9ea53b74 ML |
847 | ene_rx_enable(dev); |
848 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
849 | return 0; | |
850 | } | |
851 | ||
852 | /* outside interface: called on device close*/ | |
853 | static void ene_close(void *data) | |
854 | { | |
855 | struct ene_device *dev = (struct ene_device *)data; | |
856 | unsigned long flags; | |
857 | spin_lock_irqsave(&dev->hw_lock, flags); | |
858 | ||
859 | ene_rx_disable(dev); | |
9ea53b74 ML |
860 | spin_unlock_irqrestore(&dev->hw_lock, flags); |
861 | } | |
862 | ||
931e39a1 ML |
863 | /* outside interface: set transmitter mask */ |
864 | static int ene_set_tx_mask(void *data, u32 tx_mask) | |
9ea53b74 | 865 | { |
931e39a1 | 866 | struct ene_device *dev = (struct ene_device *)data; |
11b64d31 | 867 | dbg("TX: attempt to set transmitter mask %02x", tx_mask); |
931e39a1 ML |
868 | |
869 | /* invalid txmask */ | |
11b64d31 ML |
870 | if (!tx_mask || tx_mask & ~0x03) { |
871 | dbg("TX: invalid mask"); | |
931e39a1 ML |
872 | /* return count of transmitters */ |
873 | return 2; | |
9ea53b74 ML |
874 | } |
875 | ||
931e39a1 | 876 | dev->transmitter_mask = tx_mask; |
c29bc4d7 | 877 | ene_tx_set_transmitters(dev); |
931e39a1 ML |
878 | return 0; |
879 | } | |
9ea53b74 | 880 | |
931e39a1 ML |
881 | /* outside interface : set tx carrier */ |
882 | static int ene_set_tx_carrier(void *data, u32 carrier) | |
883 | { | |
884 | struct ene_device *dev = (struct ene_device *)data; | |
11b64d31 | 885 | u32 period = 2000000 / carrier; |
9ea53b74 | 886 | |
11b64d31 | 887 | dbg("TX: attempt to set tx carrier to %d kHz", carrier); |
9ea53b74 | 888 | |
11b64d31 ML |
889 | if (period && (period > ENE_CIRMOD_PRD_MAX || |
890 | period < ENE_CIRMOD_PRD_MIN)) { | |
9ea53b74 | 891 | |
11b64d31 | 892 | dbg("TX: out of range %d-%d kHz carrier", |
c29bc4d7 | 893 | 2000 / ENE_CIRMOD_PRD_MIN, 2000 / ENE_CIRMOD_PRD_MAX); |
11b64d31 | 894 | return -1; |
9ea53b74 ML |
895 | } |
896 | ||
931e39a1 | 897 | dev->tx_period = period; |
c29bc4d7 | 898 | ene_tx_set_carrier(dev); |
931e39a1 | 899 | return 0; |
9ea53b74 ML |
900 | } |
901 | ||
11b64d31 ML |
902 | /*outside interface : set tx duty cycle */ |
903 | static int ene_set_tx_duty_cycle(void *data, u32 duty_cycle) | |
904 | { | |
905 | struct ene_device *dev = (struct ene_device *)data; | |
11b64d31 | 906 | dbg("TX: setting duty cycle to %d%%", duty_cycle); |
11b64d31 | 907 | dev->tx_duty_cycle = duty_cycle; |
c29bc4d7 | 908 | ene_tx_set_carrier(dev); |
11b64d31 ML |
909 | return 0; |
910 | } | |
931e39a1 ML |
911 | |
912 | /* outside interface: enable learning mode */ | |
913 | static int ene_set_learning_mode(void *data, int enable) | |
9ea53b74 | 914 | { |
931e39a1 | 915 | struct ene_device *dev = (struct ene_device *)data; |
9ea53b74 | 916 | unsigned long flags; |
c29bc4d7 | 917 | if (enable == dev->learning_mode_enabled) |
931e39a1 | 918 | return 0; |
9ea53b74 | 919 | |
931e39a1 | 920 | spin_lock_irqsave(&dev->hw_lock, flags); |
c29bc4d7 | 921 | dev->learning_mode_enabled = enable; |
11b64d31 ML |
922 | ene_rx_disable(dev); |
923 | ene_rx_setup(dev); | |
924 | ene_rx_enable(dev); | |
931e39a1 ML |
925 | spin_unlock_irqrestore(&dev->hw_lock, flags); |
926 | return 0; | |
927 | } | |
9ea53b74 | 928 | |
e1b1ddbe ML |
929 | static int ene_set_carrier_report(void *data, int enable) |
930 | { | |
931 | struct ene_device *dev = (struct ene_device *)data; | |
932 | unsigned long flags; | |
933 | ||
934 | if (enable == dev->carrier_detect_enabled) | |
935 | return 0; | |
936 | ||
937 | spin_lock_irqsave(&dev->hw_lock, flags); | |
938 | dev->carrier_detect_enabled = enable; | |
939 | ene_rx_disable(dev); | |
940 | ene_rx_setup(dev); | |
941 | ene_rx_enable(dev); | |
942 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
943 | return 0; | |
944 | } | |
945 | ||
931e39a1 | 946 | /* outside interface: enable or disable idle mode */ |
c29bc4d7 | 947 | static void ene_set_idle(void *data, bool idle) |
931e39a1 | 948 | { |
c29bc4d7 ML |
949 | if (idle) { |
950 | ene_rx_reset((struct ene_device *)data); | |
951 | dbg("RX: end of data"); | |
952 | } | |
11b64d31 | 953 | } |
9ea53b74 | 954 | |
931e39a1 ML |
955 | /* outside interface: transmit */ |
956 | static int ene_transmit(void *data, int *buf, u32 n) | |
957 | { | |
958 | struct ene_device *dev = (struct ene_device *)data; | |
959 | unsigned long flags; | |
960 | ||
961 | dev->tx_buffer = buf; | |
9ea53b74 ML |
962 | dev->tx_len = n / sizeof(int); |
963 | dev->tx_pos = 0; | |
964 | dev->tx_reg = 0; | |
965 | dev->tx_done = 0; | |
966 | dev->tx_sample = 0; | |
967 | dev->tx_sample_pulse = 0; | |
968 | ||
11b64d31 | 969 | dbg("TX: %d samples", dev->tx_len); |
9ea53b74 ML |
970 | |
971 | spin_lock_irqsave(&dev->hw_lock, flags); | |
972 | ||
c29bc4d7 | 973 | ene_tx_enable(dev); |
9ea53b74 ML |
974 | |
975 | /* Transmit first two samples */ | |
976 | ene_tx_sample(dev); | |
977 | ene_tx_sample(dev); | |
978 | ||
979 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
980 | ||
981 | if (wait_for_completion_timeout(&dev->tx_complete, 2 * HZ) == 0) { | |
11b64d31 | 982 | dbg("TX: timeout"); |
9ea53b74 | 983 | spin_lock_irqsave(&dev->hw_lock, flags); |
c29bc4d7 | 984 | ene_tx_disable(dev); |
9ea53b74 ML |
985 | spin_unlock_irqrestore(&dev->hw_lock, flags); |
986 | } else | |
11b64d31 | 987 | dbg("TX: done"); |
9ea53b74 ML |
988 | return n; |
989 | } | |
990 | ||
931e39a1 ML |
991 | /* probe entry */ |
992 | static int ene_probe(struct pnp_dev *pnp_dev, const struct pnp_device_id *id) | |
9ea53b74 | 993 | { |
9ea53b74 | 994 | int error = -ENOMEM; |
931e39a1 ML |
995 | struct ir_dev_props *ir_props; |
996 | struct input_dev *input_dev; | |
997 | struct ene_device *dev; | |
9ea53b74 | 998 | |
931e39a1 ML |
999 | /* allocate memory */ |
1000 | input_dev = input_allocate_device(); | |
1001 | ir_props = kzalloc(sizeof(struct ir_dev_props), GFP_KERNEL); | |
9ea53b74 ML |
1002 | dev = kzalloc(sizeof(struct ene_device), GFP_KERNEL); |
1003 | ||
931e39a1 | 1004 | if (!input_dev || !ir_props || !dev) |
2e75bcea | 1005 | goto error1; |
9ea53b74 ML |
1006 | |
1007 | /* validate resources */ | |
931e39a1 ML |
1008 | error = -ENODEV; |
1009 | ||
9ea53b74 | 1010 | if (!pnp_port_valid(pnp_dev, 0) || |
11b64d31 | 1011 | pnp_port_len(pnp_dev, 0) < ENE_IO_SIZE) |
931e39a1 | 1012 | goto error; |
9ea53b74 ML |
1013 | |
1014 | if (!pnp_irq_valid(pnp_dev, 0)) | |
931e39a1 | 1015 | goto error; |
9ea53b74 | 1016 | |
9ea53b74 ML |
1017 | spin_lock_init(&dev->hw_lock); |
1018 | ||
1019 | /* claim the resources */ | |
1020 | error = -EBUSY; | |
11b64d31 ML |
1021 | dev->hw_io = pnp_port_start(pnp_dev, 0); |
1022 | if (!request_region(dev->hw_io, ENE_IO_SIZE, ENE_DRIVER_NAME)) { | |
1023 | dev->hw_io = -1; | |
1024 | dev->irq = -1; | |
931e39a1 | 1025 | goto error; |
11b64d31 | 1026 | } |
9ea53b74 | 1027 | |
11b64d31 | 1028 | dev->irq = pnp_irq(pnp_dev, 0); |
9ea53b74 | 1029 | if (request_irq(dev->irq, ene_isr, |
11b64d31 ML |
1030 | IRQF_SHARED, ENE_DRIVER_NAME, (void *)dev)) { |
1031 | dev->irq = -1; | |
931e39a1 | 1032 | goto error; |
11b64d31 | 1033 | } |
931e39a1 ML |
1034 | |
1035 | pnp_set_drvdata(pnp_dev, dev); | |
1036 | dev->pnp_dev = pnp_dev; | |
9ea53b74 | 1037 | |
11b64d31 ML |
1038 | /* don't allow too short/long sample periods */ |
1039 | if (sample_period < 5 || sample_period > 0x7F) | |
1040 | sample_period = ENE_DEFAULT_SAMPLE_PERIOD; | |
1041 | ||
9ea53b74 ML |
1042 | /* detect hardware version and features */ |
1043 | error = ene_hw_detect(dev); | |
1044 | if (error) | |
931e39a1 | 1045 | goto error; |
9ea53b74 | 1046 | |
9ea53b74 | 1047 | if (!dev->hw_learning_and_tx_capable && txsim) { |
11b64d31 | 1048 | dev->hw_learning_and_tx_capable = true; |
9ea53b74 ML |
1049 | setup_timer(&dev->tx_sim_timer, ene_tx_irqsim, |
1050 | (long unsigned int)dev); | |
11b64d31 | 1051 | ene_warn("Simulation of TX activated"); |
9ea53b74 ML |
1052 | } |
1053 | ||
a06423c9 | 1054 | if (!dev->hw_learning_and_tx_capable) |
c29bc4d7 | 1055 | learning_mode_force = false; |
a06423c9 | 1056 | |
931e39a1 ML |
1057 | ir_props->driver_type = RC_DRIVER_IR_RAW; |
1058 | ir_props->allowed_protos = IR_TYPE_ALL; | |
1059 | ir_props->priv = dev; | |
1060 | ir_props->open = ene_open; | |
1061 | ir_props->close = ene_close; | |
c29bc4d7 | 1062 | ir_props->s_idle = ene_set_idle; |
9ea53b74 | 1063 | |
931e39a1 ML |
1064 | dev->props = ir_props; |
1065 | dev->idev = input_dev; | |
9ea53b74 | 1066 | |
931e39a1 | 1067 | if (dev->hw_learning_and_tx_capable) { |
931e39a1 | 1068 | ir_props->s_learning_mode = ene_set_learning_mode; |
931e39a1 ML |
1069 | init_completion(&dev->tx_complete); |
1070 | ir_props->tx_ir = ene_transmit; | |
1071 | ir_props->s_tx_mask = ene_set_tx_mask; | |
1072 | ir_props->s_tx_carrier = ene_set_tx_carrier; | |
11b64d31 | 1073 | ir_props->s_tx_duty_cycle = ene_set_tx_duty_cycle; |
e1b1ddbe | 1074 | ir_props->s_carrier_report = ene_set_carrier_report; |
931e39a1 ML |
1075 | } |
1076 | ||
c29bc4d7 ML |
1077 | ene_rx_setup_hw_buffer(dev); |
1078 | ene_setup_default_settings(dev); | |
1079 | ene_setup_hw_settings(dev); | |
931e39a1 | 1080 | |
11b64d31 ML |
1081 | device_set_wakeup_capable(&pnp_dev->dev, true); |
1082 | device_set_wakeup_enable(&pnp_dev->dev, true); | |
9ea53b74 | 1083 | |
931e39a1 ML |
1084 | if (dev->hw_learning_and_tx_capable) |
1085 | input_dev->name = "ENE eHome Infrared Remote Transceiver"; | |
1086 | else | |
1087 | input_dev->name = "ENE eHome Infrared Remote Receiver"; | |
1088 | ||
9ea53b74 | 1089 | error = -ENODEV; |
931e39a1 ML |
1090 | if (ir_input_register(input_dev, RC_MAP_RC6_MCE, ir_props, |
1091 | ENE_DRIVER_NAME)) | |
1092 | goto error; | |
1093 | ||
11b64d31 | 1094 | ene_notice("driver has been succesfully loaded"); |
9ea53b74 | 1095 | return 0; |
931e39a1 | 1096 | error: |
11b64d31 | 1097 | if (dev && dev->irq >= 0) |
931e39a1 | 1098 | free_irq(dev->irq, dev); |
11b64d31 ML |
1099 | if (dev && dev->hw_io >= 0) |
1100 | release_region(dev->hw_io, ENE_IO_SIZE); | |
2e75bcea | 1101 | error1: |
931e39a1 ML |
1102 | input_free_device(input_dev); |
1103 | kfree(ir_props); | |
9ea53b74 | 1104 | kfree(dev); |
9ea53b74 ML |
1105 | return error; |
1106 | } | |
1107 | ||
1108 | /* main unload function */ | |
1109 | static void ene_remove(struct pnp_dev *pnp_dev) | |
1110 | { | |
1111 | struct ene_device *dev = pnp_get_drvdata(pnp_dev); | |
1112 | unsigned long flags; | |
1113 | ||
1114 | spin_lock_irqsave(&dev->hw_lock, flags); | |
1115 | ene_rx_disable(dev); | |
c29bc4d7 | 1116 | ene_rx_restore_hw_buffer(dev); |
9ea53b74 ML |
1117 | spin_unlock_irqrestore(&dev->hw_lock, flags); |
1118 | ||
1119 | free_irq(dev->irq, dev); | |
11b64d31 | 1120 | release_region(dev->hw_io, ENE_IO_SIZE); |
931e39a1 ML |
1121 | ir_input_unregister(dev->idev); |
1122 | kfree(dev->props); | |
9ea53b74 ML |
1123 | kfree(dev); |
1124 | } | |
1125 | ||
1126 | /* enable wake on IR (wakes on specific button on original remote) */ | |
1127 | static void ene_enable_wake(struct ene_device *dev, int enable) | |
1128 | { | |
1129 | enable = enable && device_may_wakeup(&dev->pnp_dev->dev); | |
11b64d31 ML |
1130 | dbg("wake on IR %s", enable ? "enabled" : "disabled"); |
1131 | ene_set_clear_reg_mask(dev, ENE_FW1, ENE_FW1_WAKE, enable); | |
9ea53b74 ML |
1132 | } |
1133 | ||
1134 | #ifdef CONFIG_PM | |
1135 | static int ene_suspend(struct pnp_dev *pnp_dev, pm_message_t state) | |
1136 | { | |
1137 | struct ene_device *dev = pnp_get_drvdata(pnp_dev); | |
11b64d31 ML |
1138 | ene_enable_wake(dev, true); |
1139 | ||
1140 | /* TODO: add support for wake pattern */ | |
9ea53b74 ML |
1141 | return 0; |
1142 | } | |
1143 | ||
1144 | static int ene_resume(struct pnp_dev *pnp_dev) | |
1145 | { | |
1146 | struct ene_device *dev = pnp_get_drvdata(pnp_dev); | |
c29bc4d7 ML |
1147 | ene_setup_hw_settings(dev); |
1148 | ||
1149 | if (dev->rx_enabled) | |
9ea53b74 | 1150 | ene_rx_enable(dev); |
c29bc4d7 | 1151 | |
11b64d31 | 1152 | ene_enable_wake(dev, false); |
9ea53b74 ML |
1153 | return 0; |
1154 | } | |
1155 | #endif | |
1156 | ||
1157 | static void ene_shutdown(struct pnp_dev *pnp_dev) | |
1158 | { | |
1159 | struct ene_device *dev = pnp_get_drvdata(pnp_dev); | |
11b64d31 | 1160 | ene_enable_wake(dev, true); |
9ea53b74 ML |
1161 | } |
1162 | ||
1163 | static const struct pnp_device_id ene_ids[] = { | |
1164 | {.id = "ENE0100",}, | |
1165 | {.id = "ENE0200",}, | |
1166 | {.id = "ENE0201",}, | |
931e39a1 | 1167 | {.id = "ENE0202",}, |
9ea53b74 ML |
1168 | {}, |
1169 | }; | |
1170 | ||
1171 | static struct pnp_driver ene_driver = { | |
1172 | .name = ENE_DRIVER_NAME, | |
1173 | .id_table = ene_ids, | |
1174 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
1175 | ||
1176 | .probe = ene_probe, | |
1177 | .remove = __devexit_p(ene_remove), | |
1178 | #ifdef CONFIG_PM | |
1179 | .suspend = ene_suspend, | |
1180 | .resume = ene_resume, | |
1181 | #endif | |
1182 | .shutdown = ene_shutdown, | |
1183 | }; | |
1184 | ||
1185 | static int __init ene_init(void) | |
1186 | { | |
1187 | return pnp_register_driver(&ene_driver); | |
1188 | } | |
1189 | ||
1190 | static void ene_exit(void) | |
1191 | { | |
1192 | pnp_unregister_driver(&ene_driver); | |
1193 | } | |
1194 | ||
1195 | module_param(sample_period, int, S_IRUGO); | |
1196 | MODULE_PARM_DESC(sample_period, "Hardware sample period (50 us default)"); | |
1197 | ||
c29bc4d7 ML |
1198 | module_param(learning_mode_force, bool, S_IRUGO); |
1199 | MODULE_PARM_DESC(learning_mode_force, "Enable learning mode by default"); | |
9ea53b74 ML |
1200 | |
1201 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
11b64d31 | 1202 | MODULE_PARM_DESC(debug, "Debug level"); |
9ea53b74 ML |
1203 | |
1204 | module_param(txsim, bool, S_IRUGO); | |
1205 | MODULE_PARM_DESC(txsim, | |
1206 | "Simulate TX features on unsupported hardware (dangerous)"); | |
1207 | ||
9ea53b74 ML |
1208 | MODULE_DEVICE_TABLE(pnp, ene_ids); |
1209 | MODULE_DESCRIPTION | |
11b64d31 ML |
1210 | ("Infrared input driver for KB3926B/C/D/E/F " |
1211 | "(aka ENE0100/ENE0200/ENE0201/ENE0202) CIR port"); | |
9ea53b74 ML |
1212 | |
1213 | MODULE_AUTHOR("Maxim Levitsky"); | |
1214 | MODULE_LICENSE("GPL"); | |
1215 | ||
1216 | module_init(ene_init); | |
1217 | module_exit(ene_exit); |