]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/infiniband/hw/mthca/mthca_main.c
dma-mapping: replace all DMA_32BIT_MASK macro with DMA_BIT_MASK(32)
[net-next-2.6.git] / drivers / infiniband / hw / mthca / mthca_main.c
CommitLineData
1da177e4
LT
1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
cd4e8fb4 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
2a1d9b7f 4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
1da177e4
LT
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
1da177e4
LT
33 */
34
1da177e4
LT
35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/interrupt.h>
40
41#include "mthca_dev.h"
42#include "mthca_config_reg.h"
43#include "mthca_cmd.h"
44#include "mthca_profile.h"
45#include "mthca_memfree.h"
12103dca 46#include "mthca_wqe.h"
1da177e4
LT
47
48MODULE_AUTHOR("Roland Dreier");
49MODULE_DESCRIPTION("Mellanox InfiniBand HCA low-level driver");
50MODULE_LICENSE("Dual BSD/GPL");
51MODULE_VERSION(DRV_VERSION);
52
227c939b
RD
53#ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
54
55int mthca_debug_level = 0;
56module_param_named(debug_level, mthca_debug_level, int, 0644);
57MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
58
59#endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
60
1da177e4
LT
61#ifdef CONFIG_PCI_MSI
62
017aadc4 63static int msi_x = 1;
1da177e4
LT
64module_param(msi_x, int, 0444);
65MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
66
1da177e4
LT
67#else /* CONFIG_PCI_MSI */
68
69#define msi_x (0)
1da177e4
LT
70
71#endif /* CONFIG_PCI_MSI */
72
abf45dbb
MT
73static int tune_pci = 0;
74module_param(tune_pci, int, 0444);
75MODULE_PARM_DESC(tune_pci, "increase PCI burst from the default set by BIOS if nonzero");
76
0b0df6f2 77DEFINE_MUTEX(mthca_device_mutex);
b3b30f5e 78
82da703e
LA
79#define MTHCA_DEFAULT_NUM_QP (1 << 16)
80#define MTHCA_DEFAULT_RDB_PER_QP (1 << 2)
81#define MTHCA_DEFAULT_NUM_CQ (1 << 16)
82#define MTHCA_DEFAULT_NUM_MCG (1 << 13)
83#define MTHCA_DEFAULT_NUM_MPT (1 << 17)
84#define MTHCA_DEFAULT_NUM_MTT (1 << 20)
85#define MTHCA_DEFAULT_NUM_UDAV (1 << 15)
86#define MTHCA_DEFAULT_NUM_RESERVED_MTTS (1 << 18)
87#define MTHCA_DEFAULT_NUM_UARC_SIZE (1 << 18)
88
89static struct mthca_profile hca_profile = {
90 .num_qp = MTHCA_DEFAULT_NUM_QP,
91 .rdb_per_qp = MTHCA_DEFAULT_RDB_PER_QP,
92 .num_cq = MTHCA_DEFAULT_NUM_CQ,
93 .num_mcg = MTHCA_DEFAULT_NUM_MCG,
94 .num_mpt = MTHCA_DEFAULT_NUM_MPT,
95 .num_mtt = MTHCA_DEFAULT_NUM_MTT,
96 .num_udav = MTHCA_DEFAULT_NUM_UDAV, /* Tavor only */
97 .fmr_reserved_mtts = MTHCA_DEFAULT_NUM_RESERVED_MTTS, /* Tavor only */
98 .uarc_size = MTHCA_DEFAULT_NUM_UARC_SIZE, /* Arbel only */
99};
100
101module_param_named(num_qp, hca_profile.num_qp, int, 0444);
102MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA");
103
104module_param_named(rdb_per_qp, hca_profile.rdb_per_qp, int, 0444);
105MODULE_PARM_DESC(rdb_per_qp, "number of RDB buffers per QP");
106
107module_param_named(num_cq, hca_profile.num_cq, int, 0444);
108MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA");
109
110module_param_named(num_mcg, hca_profile.num_mcg, int, 0444);
111MODULE_PARM_DESC(num_mcg, "maximum number of multicast groups per HCA");
112
113module_param_named(num_mpt, hca_profile.num_mpt, int, 0444);
114MODULE_PARM_DESC(num_mpt,
115 "maximum number of memory protection table entries per HCA");
116
117module_param_named(num_mtt, hca_profile.num_mtt, int, 0444);
118MODULE_PARM_DESC(num_mtt,
119 "maximum number of memory translation table segments per HCA");
120
121module_param_named(num_udav, hca_profile.num_udav, int, 0444);
122MODULE_PARM_DESC(num_udav, "maximum number of UD address vectors per HCA");
123
124module_param_named(fmr_reserved_mtts, hca_profile.fmr_reserved_mtts, int, 0444);
125MODULE_PARM_DESC(fmr_reserved_mtts,
126 "number of memory translation table segments reserved for FMR");
127
f33afc26 128static char mthca_version[] __devinitdata =
177214af 129 DRV_NAME ": Mellanox InfiniBand HCA driver v"
1da177e4
LT
130 DRV_VERSION " (" DRV_RELDATE ")\n";
131
f4f3d0f0 132static int mthca_tune_pci(struct mthca_dev *mdev)
1da177e4 133{
abf45dbb
MT
134 if (!tune_pci)
135 return 0;
136
1da177e4 137 /* First try to max out Read Byte Count */
a855b1a7
PO
138 if (pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX)) {
139 if (pcix_set_mmrbc(mdev->pdev, pcix_get_max_mmrbc(mdev->pdev))) {
140 mthca_err(mdev, "Couldn't set PCI-X max read count, "
141 "aborting.\n");
1da177e4
LT
142 return -ENODEV;
143 }
68a3c212 144 } else if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE))
1da177e4
LT
145 mthca_info(mdev, "No PCI-X capability, not setting RBC.\n");
146
a855b1a7
PO
147 if (pci_find_capability(mdev->pdev, PCI_CAP_ID_EXP)) {
148 if (pcie_set_readrq(mdev->pdev, 4096)) {
149 mthca_err(mdev, "Couldn't write PCI Express read request, "
150 "aborting.\n");
1da177e4
LT
151 return -ENODEV;
152 }
68a3c212 153 } else if (mdev->mthca_flags & MTHCA_FLAG_PCIE)
1da177e4
LT
154 mthca_info(mdev, "No PCI Express capability, "
155 "not setting Max Read Request Size.\n");
156
157 return 0;
158}
159
f4f3d0f0 160static int mthca_dev_lim(struct mthca_dev *mdev, struct mthca_dev_lim *dev_lim)
1da177e4
LT
161{
162 int err;
163 u8 status;
164
165 err = mthca_QUERY_DEV_LIM(mdev, dev_lim, &status);
166 if (err) {
167 mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
168 return err;
169 }
170 if (status) {
171 mthca_err(mdev, "QUERY_DEV_LIM returned status 0x%02x, "
172 "aborting.\n", status);
173 return -EINVAL;
174 }
175 if (dev_lim->min_page_sz > PAGE_SIZE) {
176 mthca_err(mdev, "HCA minimum page size of %d bigger than "
177 "kernel PAGE_SIZE of %ld, aborting.\n",
178 dev_lim->min_page_sz, PAGE_SIZE);
179 return -ENODEV;
180 }
181 if (dev_lim->num_ports > MTHCA_MAX_PORTS) {
182 mthca_err(mdev, "HCA has %d ports, but we only support %d, "
183 "aborting.\n",
184 dev_lim->num_ports, MTHCA_MAX_PORTS);
185 return -ENODEV;
186 }
187
cbd2981a
MT
188 if (dev_lim->uar_size > pci_resource_len(mdev->pdev, 2)) {
189 mthca_err(mdev, "HCA reported UAR size of 0x%x bigger than "
e29419ff
GKH
190 "PCI resource 2 size of 0x%llx, aborting.\n",
191 dev_lim->uar_size,
192 (unsigned long long)pci_resource_len(mdev->pdev, 2));
cbd2981a
MT
193 return -ENODEV;
194 }
195
1da177e4
LT
196 mdev->limits.num_ports = dev_lim->num_ports;
197 mdev->limits.vl_cap = dev_lim->max_vl;
198 mdev->limits.mtu_cap = dev_lim->max_mtu;
199 mdev->limits.gid_table_len = dev_lim->max_gids;
200 mdev->limits.pkey_table_len = dev_lim->max_pkeys;
201 mdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay;
12103dca
RD
202 /*
203 * Need to allow for worst case send WQE overhead and check
204 * whether max_desc_sz imposes a lower limit than max_sg; UD
205 * send has the biggest overhead.
206 */
207 mdev->limits.max_sg = min_t(int, dev_lim->max_sg,
208 (dev_lim->max_desc_sz -
209 sizeof (struct mthca_next_seg) -
210 (mthca_is_memfree(mdev) ?
211 sizeof (struct mthca_arbel_ud_seg) :
212 sizeof (struct mthca_tavor_ud_seg))) /
213 sizeof (struct mthca_data_seg));
efaae8f7
JM
214 mdev->limits.max_wqes = dev_lim->max_qp_sz;
215 mdev->limits.max_qp_init_rdma = dev_lim->max_requester_per_qp;
1da177e4 216 mdev->limits.reserved_qps = dev_lim->reserved_qps;
efaae8f7 217 mdev->limits.max_srq_wqes = dev_lim->max_srq_sz;
1da177e4
LT
218 mdev->limits.reserved_srqs = dev_lim->reserved_srqs;
219 mdev->limits.reserved_eecs = dev_lim->reserved_eecs;
77369ed3 220 mdev->limits.max_desc_sz = dev_lim->max_desc_sz;
59fef3b1 221 mdev->limits.max_srq_sge = mthca_max_srq_sge(mdev);
efaae8f7
JM
222 /*
223 * Subtract 1 from the limit because we need to allocate a
224 * spare CQE so the HCA HW can tell the difference between an
225 * empty CQ and a full CQ.
226 */
227 mdev->limits.max_cqes = dev_lim->max_cq_sz - 1;
1da177e4
LT
228 mdev->limits.reserved_cqs = dev_lim->reserved_cqs;
229 mdev->limits.reserved_eqs = dev_lim->reserved_eqs;
230 mdev->limits.reserved_mtts = dev_lim->reserved_mtts;
231 mdev->limits.reserved_mrws = dev_lim->reserved_mrws;
232 mdev->limits.reserved_uars = dev_lim->reserved_uars;
233 mdev->limits.reserved_pds = dev_lim->reserved_pds;
da6561c2 234 mdev->limits.port_width_cap = dev_lim->max_port_width;
0f69ce1e 235 mdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1);
33033b79 236 mdev->limits.flags = dev_lim->flags;
bf6a9e31
JM
237 /*
238 * For old FW that doesn't return static rate support, use a
239 * value of 0x3 (only static rate values of 0 or 1 are handled),
240 * except on Sinai, where even old FW can handle static rate
241 * values of 2 and 3.
242 */
243 if (dev_lim->stat_rate_support)
244 mdev->limits.stat_rate_support = dev_lim->stat_rate_support;
245 else if (mdev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
246 mdev->limits.stat_rate_support = 0xf;
247 else
248 mdev->limits.stat_rate_support = 0x3;
1da177e4
LT
249
250 /* IB_DEVICE_RESIZE_MAX_WR not supported by driver.
251 May be doable since hardware supports it for SRQ.
252
253 IB_DEVICE_N_NOTIFY_CQ is supported by hardware but not by driver.
254
255 IB_DEVICE_SRQ_RESIZE is supported by hardware but SRQ is not
256 supported by driver. */
257 mdev->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
258 IB_DEVICE_PORT_ACTIVE_EVENT |
259 IB_DEVICE_SYS_IMAGE_GUID |
260 IB_DEVICE_RC_RNR_NAK_GEN;
261
262 if (dev_lim->flags & DEV_LIM_FLAG_BAD_PKEY_CNTR)
263 mdev->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
264
265 if (dev_lim->flags & DEV_LIM_FLAG_BAD_QKEY_CNTR)
266 mdev->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
267
268 if (dev_lim->flags & DEV_LIM_FLAG_RAW_MULTI)
269 mdev->device_cap_flags |= IB_DEVICE_RAW_MULTI;
270
271 if (dev_lim->flags & DEV_LIM_FLAG_AUTO_PATH_MIG)
272 mdev->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
273
274 if (dev_lim->flags & DEV_LIM_FLAG_UD_AV_PORT_ENFORCE)
275 mdev->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
276
277 if (dev_lim->flags & DEV_LIM_FLAG_SRQ)
278 mdev->mthca_flags |= MTHCA_FLAG_SRQ;
279
680b575f
EC
280 if (mthca_is_memfree(mdev))
281 if (dev_lim->flags & DEV_LIM_FLAG_IPOIB_CSUM)
282 mdev->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
283
1da177e4
LT
284 return 0;
285}
286
f4f3d0f0 287static int mthca_init_tavor(struct mthca_dev *mdev)
1da177e4 288{
19773539 289 s64 size;
1da177e4
LT
290 u8 status;
291 int err;
292 struct mthca_dev_lim dev_lim;
293 struct mthca_profile profile;
294 struct mthca_init_hca_param init_hca;
1da177e4
LT
295
296 err = mthca_SYS_EN(mdev, &status);
297 if (err) {
298 mthca_err(mdev, "SYS_EN command failed, aborting.\n");
299 return err;
300 }
301 if (status) {
302 mthca_err(mdev, "SYS_EN returned status 0x%02x, "
303 "aborting.\n", status);
304 return -EINVAL;
305 }
306
307 err = mthca_QUERY_FW(mdev, &status);
308 if (err) {
309 mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
310 goto err_disable;
311 }
312 if (status) {
313 mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
314 "aborting.\n", status);
315 err = -EINVAL;
316 goto err_disable;
317 }
318 err = mthca_QUERY_DDR(mdev, &status);
319 if (err) {
320 mthca_err(mdev, "QUERY_DDR command failed, aborting.\n");
321 goto err_disable;
322 }
323 if (status) {
324 mthca_err(mdev, "QUERY_DDR returned status 0x%02x, "
325 "aborting.\n", status);
326 err = -EINVAL;
327 goto err_disable;
328 }
329
330 err = mthca_dev_lim(mdev, &dev_lim);
aa2f9367
JM
331 if (err) {
332 mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
333 goto err_disable;
334 }
1da177e4 335
82da703e 336 profile = hca_profile;
1da177e4
LT
337 profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
338 profile.uarc_size = 0;
ec34a922
RD
339 if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
340 profile.num_srq = dev_lim.max_srqs;
1da177e4 341
19773539
RD
342 size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
343 if (size < 0) {
344 err = size;
1da177e4 345 goto err_disable;
19773539 346 }
1da177e4
LT
347
348 err = mthca_INIT_HCA(mdev, &init_hca, &status);
349 if (err) {
350 mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
351 goto err_disable;
352 }
353 if (status) {
354 mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
355 "aborting.\n", status);
356 err = -EINVAL;
357 goto err_disable;
358 }
359
1da177e4
LT
360 return 0;
361
1da177e4
LT
362err_disable:
363 mthca_SYS_DIS(mdev, &status);
364
365 return err;
366}
367
f4f3d0f0 368static int mthca_load_fw(struct mthca_dev *mdev)
1da177e4
LT
369{
370 u8 status;
371 int err;
372
373 /* FIXME: use HCA-attached memory for FW if present */
374
375 mdev->fw.arbel.fw_icm =
376 mthca_alloc_icm(mdev, mdev->fw.arbel.fw_pages,
391e4dea 377 GFP_HIGHUSER | __GFP_NOWARN, 0);
1da177e4
LT
378 if (!mdev->fw.arbel.fw_icm) {
379 mthca_err(mdev, "Couldn't allocate FW area, aborting.\n");
380 return -ENOMEM;
381 }
382
383 err = mthca_MAP_FA(mdev, mdev->fw.arbel.fw_icm, &status);
384 if (err) {
385 mthca_err(mdev, "MAP_FA command failed, aborting.\n");
386 goto err_free;
387 }
388 if (status) {
389 mthca_err(mdev, "MAP_FA returned status 0x%02x, aborting.\n", status);
390 err = -EINVAL;
391 goto err_free;
392 }
393 err = mthca_RUN_FW(mdev, &status);
394 if (err) {
395 mthca_err(mdev, "RUN_FW command failed, aborting.\n");
396 goto err_unmap_fa;
397 }
398 if (status) {
399 mthca_err(mdev, "RUN_FW returned status 0x%02x, aborting.\n", status);
400 err = -EINVAL;
401 goto err_unmap_fa;
402 }
403
404 return 0;
405
406err_unmap_fa:
407 mthca_UNMAP_FA(mdev, &status);
408
409err_free:
391e4dea 410 mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
1da177e4
LT
411 return err;
412}
413
f4f3d0f0
RD
414static int mthca_init_icm(struct mthca_dev *mdev,
415 struct mthca_dev_lim *dev_lim,
416 struct mthca_init_hca_param *init_hca,
417 u64 icm_size)
1da177e4
LT
418{
419 u64 aux_pages;
420 u8 status;
421 int err;
422
423 err = mthca_SET_ICM_SIZE(mdev, icm_size, &aux_pages, &status);
424 if (err) {
425 mthca_err(mdev, "SET_ICM_SIZE command failed, aborting.\n");
426 return err;
427 }
428 if (status) {
429 mthca_err(mdev, "SET_ICM_SIZE returned status 0x%02x, "
430 "aborting.\n", status);
431 return -EINVAL;
432 }
433
434 mthca_dbg(mdev, "%lld KB of HCA context requires %lld KB aux memory.\n",
435 (unsigned long long) icm_size >> 10,
436 (unsigned long long) aux_pages << 2);
437
438 mdev->fw.arbel.aux_icm = mthca_alloc_icm(mdev, aux_pages,
391e4dea 439 GFP_HIGHUSER | __GFP_NOWARN, 0);
1da177e4
LT
440 if (!mdev->fw.arbel.aux_icm) {
441 mthca_err(mdev, "Couldn't allocate aux memory, aborting.\n");
442 return -ENOMEM;
443 }
444
445 err = mthca_MAP_ICM_AUX(mdev, mdev->fw.arbel.aux_icm, &status);
446 if (err) {
447 mthca_err(mdev, "MAP_ICM_AUX command failed, aborting.\n");
448 goto err_free_aux;
449 }
450 if (status) {
451 mthca_err(mdev, "MAP_ICM_AUX returned status 0x%02x, aborting.\n", status);
452 err = -EINVAL;
453 goto err_free_aux;
454 }
455
456 err = mthca_map_eq_icm(mdev, init_hca->eqc_base);
457 if (err) {
458 mthca_err(mdev, "Failed to map EQ context memory, aborting.\n");
459 goto err_unmap_aux;
460 }
461
1d1f19cf
MT
462 /* CPU writes to non-reserved MTTs, while HCA might DMA to reserved mtts */
463 mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * MTHCA_MTT_SEG_SIZE,
464 dma_get_cache_alignment()) / MTHCA_MTT_SEG_SIZE;
465
1da177e4 466 mdev->mr_table.mtt_table = mthca_alloc_icm_table(mdev, init_hca->mtt_base,
44ea6687 467 MTHCA_MTT_SEG_SIZE,
1da177e4 468 mdev->limits.num_mtt_segs,
391e4dea
MT
469 mdev->limits.reserved_mtts,
470 1, 0);
1da177e4
LT
471 if (!mdev->mr_table.mtt_table) {
472 mthca_err(mdev, "Failed to map MTT context memory, aborting.\n");
473 err = -ENOMEM;
474 goto err_unmap_eq;
475 }
476
477 mdev->mr_table.mpt_table = mthca_alloc_icm_table(mdev, init_hca->mpt_base,
478 dev_lim->mpt_entry_sz,
479 mdev->limits.num_mpts,
391e4dea
MT
480 mdev->limits.reserved_mrws,
481 1, 1);
1da177e4
LT
482 if (!mdev->mr_table.mpt_table) {
483 mthca_err(mdev, "Failed to map MPT context memory, aborting.\n");
484 err = -ENOMEM;
485 goto err_unmap_mtt;
486 }
487
488 mdev->qp_table.qp_table = mthca_alloc_icm_table(mdev, init_hca->qpc_base,
489 dev_lim->qpc_entry_sz,
490 mdev->limits.num_qps,
391e4dea
MT
491 mdev->limits.reserved_qps,
492 0, 0);
1da177e4
LT
493 if (!mdev->qp_table.qp_table) {
494 mthca_err(mdev, "Failed to map QP context memory, aborting.\n");
495 err = -ENOMEM;
496 goto err_unmap_mpt;
497 }
498
499 mdev->qp_table.eqp_table = mthca_alloc_icm_table(mdev, init_hca->eqpc_base,
500 dev_lim->eqpc_entry_sz,
501 mdev->limits.num_qps,
391e4dea
MT
502 mdev->limits.reserved_qps,
503 0, 0);
1da177e4
LT
504 if (!mdev->qp_table.eqp_table) {
505 mthca_err(mdev, "Failed to map EQP context memory, aborting.\n");
506 err = -ENOMEM;
507 goto err_unmap_qp;
508 }
509
08aeb14e
RD
510 mdev->qp_table.rdb_table = mthca_alloc_icm_table(mdev, init_hca->rdb_base,
511 MTHCA_RDB_ENTRY_SIZE,
512 mdev->limits.num_qps <<
391e4dea 513 mdev->qp_table.rdb_shift, 0,
08aeb14e
RD
514 0, 0);
515 if (!mdev->qp_table.rdb_table) {
516 mthca_err(mdev, "Failed to map RDB context memory, aborting\n");
517 err = -ENOMEM;
19272d43 518 goto err_unmap_eqp;
08aeb14e
RD
519 }
520
521 mdev->cq_table.table = mthca_alloc_icm_table(mdev, init_hca->cqc_base,
ec34a922
RD
522 dev_lim->cqc_entry_sz,
523 mdev->limits.num_cqs,
391e4dea
MT
524 mdev->limits.reserved_cqs,
525 0, 0);
1da177e4
LT
526 if (!mdev->cq_table.table) {
527 mthca_err(mdev, "Failed to map CQ context memory, aborting.\n");
528 err = -ENOMEM;
08aeb14e 529 goto err_unmap_rdb;
1da177e4
LT
530 }
531
ec34a922
RD
532 if (mdev->mthca_flags & MTHCA_FLAG_SRQ) {
533 mdev->srq_table.table =
534 mthca_alloc_icm_table(mdev, init_hca->srqc_base,
535 dev_lim->srq_entry_sz,
536 mdev->limits.num_srqs,
391e4dea
MT
537 mdev->limits.reserved_srqs,
538 0, 0);
ec34a922
RD
539 if (!mdev->srq_table.table) {
540 mthca_err(mdev, "Failed to map SRQ context memory, "
541 "aborting.\n");
542 err = -ENOMEM;
543 goto err_unmap_cq;
544 }
545 }
546
1da177e4
LT
547 /*
548 * It's not strictly required, but for simplicity just map the
549 * whole multicast group table now. The table isn't very big
550 * and it's a lot easier than trying to track ref counts.
551 */
552 mdev->mcg_table.table = mthca_alloc_icm_table(mdev, init_hca->mc_base,
553 MTHCA_MGM_ENTRY_SIZE,
554 mdev->limits.num_mgms +
555 mdev->limits.num_amgms,
556 mdev->limits.num_mgms +
557 mdev->limits.num_amgms,
391e4dea 558 0, 0);
1da177e4
LT
559 if (!mdev->mcg_table.table) {
560 mthca_err(mdev, "Failed to map MCG context memory, aborting.\n");
561 err = -ENOMEM;
ec34a922 562 goto err_unmap_srq;
1da177e4
LT
563 }
564
565 return 0;
566
ec34a922
RD
567err_unmap_srq:
568 if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
569 mthca_free_icm_table(mdev, mdev->srq_table.table);
570
1da177e4
LT
571err_unmap_cq:
572 mthca_free_icm_table(mdev, mdev->cq_table.table);
573
08aeb14e
RD
574err_unmap_rdb:
575 mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
576
1da177e4
LT
577err_unmap_eqp:
578 mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
579
580err_unmap_qp:
581 mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
582
583err_unmap_mpt:
584 mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
585
586err_unmap_mtt:
587 mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
588
589err_unmap_eq:
590 mthca_unmap_eq_icm(mdev);
591
592err_unmap_aux:
593 mthca_UNMAP_ICM_AUX(mdev, &status);
594
595err_free_aux:
391e4dea 596 mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
1da177e4
LT
597
598 return err;
599}
600
aba7a22f
MT
601static void mthca_free_icms(struct mthca_dev *mdev)
602{
603 u8 status;
604
605 mthca_free_icm_table(mdev, mdev->mcg_table.table);
606 if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
607 mthca_free_icm_table(mdev, mdev->srq_table.table);
608 mthca_free_icm_table(mdev, mdev->cq_table.table);
609 mthca_free_icm_table(mdev, mdev->qp_table.rdb_table);
610 mthca_free_icm_table(mdev, mdev->qp_table.eqp_table);
611 mthca_free_icm_table(mdev, mdev->qp_table.qp_table);
612 mthca_free_icm_table(mdev, mdev->mr_table.mpt_table);
613 mthca_free_icm_table(mdev, mdev->mr_table.mtt_table);
614 mthca_unmap_eq_icm(mdev);
615
616 mthca_UNMAP_ICM_AUX(mdev, &status);
391e4dea 617 mthca_free_icm(mdev, mdev->fw.arbel.aux_icm, 0);
aba7a22f
MT
618}
619
f4f3d0f0 620static int mthca_init_arbel(struct mthca_dev *mdev)
1da177e4
LT
621{
622 struct mthca_dev_lim dev_lim;
623 struct mthca_profile profile;
624 struct mthca_init_hca_param init_hca;
19773539 625 s64 icm_size;
1da177e4
LT
626 u8 status;
627 int err;
628
629 err = mthca_QUERY_FW(mdev, &status);
630 if (err) {
631 mthca_err(mdev, "QUERY_FW command failed, aborting.\n");
632 return err;
633 }
634 if (status) {
635 mthca_err(mdev, "QUERY_FW returned status 0x%02x, "
636 "aborting.\n", status);
637 return -EINVAL;
638 }
639
640 err = mthca_ENABLE_LAM(mdev, &status);
641 if (err) {
642 mthca_err(mdev, "ENABLE_LAM command failed, aborting.\n");
643 return err;
644 }
645 if (status == MTHCA_CMD_STAT_LAM_NOT_PRE) {
646 mthca_dbg(mdev, "No HCA-attached memory (running in MemFree mode)\n");
647 mdev->mthca_flags |= MTHCA_FLAG_NO_LAM;
648 } else if (status) {
649 mthca_err(mdev, "ENABLE_LAM returned status 0x%02x, "
650 "aborting.\n", status);
651 return -EINVAL;
652 }
653
654 err = mthca_load_fw(mdev);
655 if (err) {
656 mthca_err(mdev, "Failed to start FW, aborting.\n");
657 goto err_disable;
658 }
659
660 err = mthca_dev_lim(mdev, &dev_lim);
661 if (err) {
662 mthca_err(mdev, "QUERY_DEV_LIM command failed, aborting.\n");
663 goto err_stop_fw;
664 }
665
82da703e 666 profile = hca_profile;
1da177e4
LT
667 profile.num_uar = dev_lim.uar_size / PAGE_SIZE;
668 profile.num_udav = 0;
ec34a922
RD
669 if (mdev->mthca_flags & MTHCA_FLAG_SRQ)
670 profile.num_srq = dev_lim.max_srqs;
1da177e4
LT
671
672 icm_size = mthca_make_profile(mdev, &profile, &dev_lim, &init_hca);
19773539 673 if (icm_size < 0) {
1da177e4
LT
674 err = icm_size;
675 goto err_stop_fw;
676 }
677
678 err = mthca_init_icm(mdev, &dev_lim, &init_hca, icm_size);
679 if (err)
680 goto err_stop_fw;
681
682 err = mthca_INIT_HCA(mdev, &init_hca, &status);
683 if (err) {
684 mthca_err(mdev, "INIT_HCA command failed, aborting.\n");
685 goto err_free_icm;
686 }
687 if (status) {
688 mthca_err(mdev, "INIT_HCA returned status 0x%02x, "
689 "aborting.\n", status);
690 err = -EINVAL;
691 goto err_free_icm;
692 }
693
1da177e4
LT
694 return 0;
695
696err_free_icm:
aba7a22f 697 mthca_free_icms(mdev);
1da177e4
LT
698
699err_stop_fw:
700 mthca_UNMAP_FA(mdev, &status);
391e4dea 701 mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
1da177e4
LT
702
703err_disable:
704 if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
705 mthca_DISABLE_LAM(mdev, &status);
706
707 return err;
708}
709
2e8b981c
MT
710static void mthca_close_hca(struct mthca_dev *mdev)
711{
712 u8 status;
713
714 mthca_CLOSE_HCA(mdev, 0, &status);
715
716 if (mthca_is_memfree(mdev)) {
aba7a22f 717 mthca_free_icms(mdev);
2e8b981c
MT
718
719 mthca_UNMAP_FA(mdev, &status);
391e4dea 720 mthca_free_icm(mdev, mdev->fw.arbel.fw_icm, 0);
2e8b981c
MT
721
722 if (!(mdev->mthca_flags & MTHCA_FLAG_NO_LAM))
723 mthca_DISABLE_LAM(mdev, &status);
724 } else
725 mthca_SYS_DIS(mdev, &status);
726}
727
f4f3d0f0 728static int mthca_init_hca(struct mthca_dev *mdev)
1da177e4 729{
2e8b981c
MT
730 u8 status;
731 int err;
732 struct mthca_adapter adapter;
733
d10ddbf6 734 if (mthca_is_memfree(mdev))
2e8b981c 735 err = mthca_init_arbel(mdev);
1da177e4 736 else
2e8b981c
MT
737 err = mthca_init_tavor(mdev);
738
739 if (err)
740 return err;
741
742 err = mthca_QUERY_ADAPTER(mdev, &adapter, &status);
743 if (err) {
744 mthca_err(mdev, "QUERY_ADAPTER command failed, aborting.\n");
745 goto err_close;
746 }
747 if (status) {
748 mthca_err(mdev, "QUERY_ADAPTER returned status 0x%02x, "
749 "aborting.\n", status);
750 err = -EINVAL;
751 goto err_close;
752 }
753
754 mdev->eq_table.inta_pin = adapter.inta_pin;
6ccef1de
JM
755 if (!mthca_is_memfree(mdev))
756 mdev->rev_id = adapter.revision_id;
2e8b981c
MT
757 memcpy(mdev->board_id, adapter.board_id, sizeof mdev->board_id);
758
759 return 0;
760
761err_close:
762 mthca_close_hca(mdev);
763 return err;
1da177e4
LT
764}
765
f4f3d0f0 766static int mthca_setup_hca(struct mthca_dev *dev)
1da177e4
LT
767{
768 int err;
769 u8 status;
770
771 MTHCA_INIT_DOORBELL_LOCK(&dev->doorbell_lock);
772
773 err = mthca_init_uar_table(dev);
774 if (err) {
775 mthca_err(dev, "Failed to initialize "
776 "user access region table, aborting.\n");
777 return err;
778 }
779
780 err = mthca_uar_alloc(dev, &dev->driver_uar);
781 if (err) {
782 mthca_err(dev, "Failed to allocate driver access region, "
783 "aborting.\n");
784 goto err_uar_table_free;
785 }
786
787 dev->kar = ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
788 if (!dev->kar) {
789 mthca_err(dev, "Couldn't map kernel access region, "
790 "aborting.\n");
791 err = -ENOMEM;
792 goto err_uar_free;
793 }
794
795 err = mthca_init_pd_table(dev);
796 if (err) {
797 mthca_err(dev, "Failed to initialize "
798 "protection domain table, aborting.\n");
799 goto err_kar_unmap;
800 }
801
802 err = mthca_init_mr_table(dev);
803 if (err) {
804 mthca_err(dev, "Failed to initialize "
805 "memory region table, aborting.\n");
806 goto err_pd_table_free;
807 }
808
99264c1e 809 err = mthca_pd_alloc(dev, 1, &dev->driver_pd);
1da177e4
LT
810 if (err) {
811 mthca_err(dev, "Failed to create driver PD, "
812 "aborting.\n");
813 goto err_mr_table_free;
814 }
815
816 err = mthca_init_eq_table(dev);
817 if (err) {
818 mthca_err(dev, "Failed to initialize "
819 "event queue table, aborting.\n");
820 goto err_pd_free;
821 }
822
823 err = mthca_cmd_use_events(dev);
824 if (err) {
825 mthca_err(dev, "Failed to switch to event-driven "
826 "firmware commands, aborting.\n");
827 goto err_eq_table_free;
828 }
829
830 err = mthca_NOP(dev, &status);
831 if (err || status) {
e57895d3 832 if (dev->mthca_flags & MTHCA_FLAG_MSI_X) {
017aadc4
MT
833 mthca_warn(dev, "NOP command failed to generate interrupt "
834 "(IRQ %d).\n",
e57895d3
AB
835 dev->eq_table.eq[MTHCA_EQ_CMD].msi_x_vector);
836 mthca_warn(dev, "Trying again with MSI-X disabled.\n");
017aadc4
MT
837 } else {
838 mthca_err(dev, "NOP command failed to generate interrupt "
839 "(IRQ %d), aborting.\n",
840 dev->pdev->irq);
1da177e4 841 mthca_err(dev, "BIOS or ACPI interrupt routing problem?\n");
017aadc4 842 }
1da177e4
LT
843
844 goto err_cmd_poll;
845 }
846
847 mthca_dbg(dev, "NOP command IRQ test passed\n");
848
849 err = mthca_init_cq_table(dev);
850 if (err) {
851 mthca_err(dev, "Failed to initialize "
852 "completion queue table, aborting.\n");
853 goto err_cmd_poll;
854 }
855
ec34a922
RD
856 err = mthca_init_srq_table(dev);
857 if (err) {
858 mthca_err(dev, "Failed to initialize "
859 "shared receive queue table, aborting.\n");
860 goto err_cq_table_free;
861 }
862
1da177e4
LT
863 err = mthca_init_qp_table(dev);
864 if (err) {
865 mthca_err(dev, "Failed to initialize "
866 "queue pair table, aborting.\n");
ec34a922 867 goto err_srq_table_free;
1da177e4
LT
868 }
869
870 err = mthca_init_av_table(dev);
871 if (err) {
872 mthca_err(dev, "Failed to initialize "
873 "address vector table, aborting.\n");
874 goto err_qp_table_free;
875 }
876
877 err = mthca_init_mcg_table(dev);
878 if (err) {
879 mthca_err(dev, "Failed to initialize "
880 "multicast group table, aborting.\n");
881 goto err_av_table_free;
882 }
883
884 return 0;
885
886err_av_table_free:
887 mthca_cleanup_av_table(dev);
888
889err_qp_table_free:
890 mthca_cleanup_qp_table(dev);
891
ec34a922
RD
892err_srq_table_free:
893 mthca_cleanup_srq_table(dev);
894
1da177e4
LT
895err_cq_table_free:
896 mthca_cleanup_cq_table(dev);
897
898err_cmd_poll:
899 mthca_cmd_use_polling(dev);
900
901err_eq_table_free:
902 mthca_cleanup_eq_table(dev);
903
904err_pd_free:
905 mthca_pd_free(dev, &dev->driver_pd);
906
907err_mr_table_free:
908 mthca_cleanup_mr_table(dev);
909
910err_pd_table_free:
911 mthca_cleanup_pd_table(dev);
912
913err_kar_unmap:
914 iounmap(dev->kar);
915
916err_uar_free:
917 mthca_uar_free(dev, &dev->driver_uar);
918
919err_uar_table_free:
920 mthca_cleanup_uar_table(dev);
921 return err;
922}
923
f4f3d0f0 924static int mthca_enable_msi_x(struct mthca_dev *mdev)
1da177e4
LT
925{
926 struct msix_entry entries[3];
927 int err;
928
929 entries[0].entry = 0;
930 entries[1].entry = 1;
931 entries[2].entry = 2;
932
933 err = pci_enable_msix(mdev->pdev, entries, ARRAY_SIZE(entries));
934 if (err) {
935 if (err > 0)
936 mthca_info(mdev, "Only %d MSI-X vectors available, "
937 "not using MSI-X\n", err);
938 return err;
939 }
940
941 mdev->eq_table.eq[MTHCA_EQ_COMP ].msi_x_vector = entries[0].vector;
942 mdev->eq_table.eq[MTHCA_EQ_ASYNC].msi_x_vector = entries[1].vector;
943 mdev->eq_table.eq[MTHCA_EQ_CMD ].msi_x_vector = entries[2].vector;
944
945 return 0;
946}
947
68a3c212
RD
948/* Types of supported HCA */
949enum {
950 TAVOR, /* MT23108 */
951 ARBEL_COMPAT, /* MT25208 in Tavor compat mode */
952 ARBEL_NATIVE, /* MT25208 with extended features */
953 SINAI /* MT25204 */
954};
955
956#define MTHCA_FW_VER(major, minor, subminor) \
957 (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor))
958
959static struct {
960 u64 latest_fw;
651eaac9 961 u32 flags;
68a3c212 962} mthca_hca_table[] = {
3f114853 963 [TAVOR] = { .latest_fw = MTHCA_FW_VER(3, 5, 0),
651eaac9 964 .flags = 0 },
3f114853 965 [ARBEL_COMPAT] = { .latest_fw = MTHCA_FW_VER(4, 8, 200),
651eaac9 966 .flags = MTHCA_FLAG_PCIE },
950529e5 967 [ARBEL_NATIVE] = { .latest_fw = MTHCA_FW_VER(5, 3, 0),
651eaac9
EC
968 .flags = MTHCA_FLAG_MEMFREE |
969 MTHCA_FLAG_PCIE },
3f114853 970 [SINAI] = { .latest_fw = MTHCA_FW_VER(1, 2, 0),
651eaac9
EC
971 .flags = MTHCA_FLAG_MEMFREE |
972 MTHCA_FLAG_PCIE |
973 MTHCA_FLAG_SINAI_OPT }
68a3c212
RD
974};
975
b3b30f5e 976static int __mthca_init_one(struct pci_dev *pdev, int hca_type)
1da177e4 977{
1da177e4
LT
978 int ddr_hidden = 0;
979 int err;
980 struct mthca_dev *mdev;
981
982245f0
AB
982 printk(KERN_INFO PFX "Initializing %s\n",
983 pci_name(pdev));
1da177e4
LT
984
985 err = pci_enable_device(pdev);
986 if (err) {
987 dev_err(&pdev->dev, "Cannot enable PCI device, "
988 "aborting.\n");
989 return err;
990 }
991
992 /*
993 * Check for BARs. We expect 0: 1MB, 2: 8MB, 4: DDR (may not
994 * be present)
995 */
996 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
997 pci_resource_len(pdev, 0) != 1 << 20) {
177214af 998 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1da177e4
LT
999 err = -ENODEV;
1000 goto err_disable_pdev;
1001 }
cbd2981a 1002 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
177214af 1003 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1da177e4
LT
1004 err = -ENODEV;
1005 goto err_disable_pdev;
1006 }
1007 if (!(pci_resource_flags(pdev, 4) & IORESOURCE_MEM))
1008 ddr_hidden = 1;
1009
208dde28 1010 err = pci_request_regions(pdev, DRV_NAME);
1da177e4
LT
1011 if (err) {
1012 dev_err(&pdev->dev, "Cannot obtain PCI resources, "
1013 "aborting.\n");
1014 goto err_disable_pdev;
1015 }
1016
1017 pci_set_master(pdev);
1018
6a35528a 1019 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4
LT
1020 if (err) {
1021 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
284901a9 1022 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4
LT
1023 if (err) {
1024 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1025 goto err_free_res;
1026 }
1027 }
6a35528a 1028 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4
LT
1029 if (err) {
1030 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1031 "consistent PCI DMA mask.\n");
284901a9 1032 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4
LT
1033 if (err) {
1034 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1035 "aborting.\n");
1036 goto err_free_res;
1037 }
1038 }
1039
1040 mdev = (struct mthca_dev *) ib_alloc_device(sizeof *mdev);
1041 if (!mdev) {
1042 dev_err(&pdev->dev, "Device struct alloc failed, "
1043 "aborting.\n");
1044 err = -ENOMEM;
1045 goto err_free_res;
1046 }
1047
68a3c212 1048 mdev->pdev = pdev;
1da177e4 1049
b3b30f5e 1050 mdev->mthca_flags = mthca_hca_table[hca_type].flags;
1da177e4
LT
1051 if (ddr_hidden)
1052 mdev->mthca_flags |= MTHCA_FLAG_DDR_HIDDEN;
1053
1054 /*
1055 * Now reset the HCA before we touch the PCI capabilities or
1056 * attempt a firmware command, since a boot ROM may have left
1057 * the HCA in an undefined state.
1058 */
1059 err = mthca_reset(mdev);
1060 if (err) {
1061 mthca_err(mdev, "Failed to reset HCA, aborting.\n");
1062 goto err_free_dev;
1063 }
1064
80fd8238
RD
1065 if (mthca_cmd_init(mdev)) {
1066 mthca_err(mdev, "Failed to init command interface, aborting.\n");
1da177e4
LT
1067 goto err_free_dev;
1068 }
1069
1070 err = mthca_tune_pci(mdev);
1071 if (err)
80fd8238 1072 goto err_cmd;
1da177e4
LT
1073
1074 err = mthca_init_hca(mdev);
1075 if (err)
80fd8238 1076 goto err_cmd;
1da177e4 1077
b3b30f5e 1078 if (mdev->fw_ver < mthca_hca_table[hca_type].latest_fw) {
e4daf738 1079 mthca_warn(mdev, "HCA FW version %d.%d.%03d is old (%d.%d.%03d is current).\n",
68a3c212
RD
1080 (int) (mdev->fw_ver >> 32), (int) (mdev->fw_ver >> 16) & 0xffff,
1081 (int) (mdev->fw_ver & 0xffff),
b3b30f5e
JM
1082 (int) (mthca_hca_table[hca_type].latest_fw >> 32),
1083 (int) (mthca_hca_table[hca_type].latest_fw >> 16) & 0xffff,
1084 (int) (mthca_hca_table[hca_type].latest_fw & 0xffff));
68a3c212
RD
1085 mthca_warn(mdev, "If you have problems, try updating your HCA FW.\n");
1086 }
1087
017aadc4
MT
1088 if (msi_x && !mthca_enable_msi_x(mdev))
1089 mdev->mthca_flags |= MTHCA_FLAG_MSI_X;
017aadc4 1090
1da177e4 1091 err = mthca_setup_hca(mdev);
e57895d3 1092 if (err == -EBUSY && (mdev->mthca_flags & MTHCA_FLAG_MSI_X)) {
017aadc4
MT
1093 if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
1094 pci_disable_msix(pdev);
e57895d3 1095 mdev->mthca_flags &= ~MTHCA_FLAG_MSI_X;
017aadc4
MT
1096
1097 err = mthca_setup_hca(mdev);
1098 }
1099
1da177e4
LT
1100 if (err)
1101 goto err_close;
1102
1103 err = mthca_register_device(mdev);
1104 if (err)
1105 goto err_cleanup;
1106
1107 err = mthca_create_agents(mdev);
1108 if (err)
1109 goto err_unregister;
1110
1111 pci_set_drvdata(pdev, mdev);
b3b30f5e 1112 mdev->hca_type = hca_type;
1da177e4
LT
1113
1114 return 0;
1115
1116err_unregister:
1117 mthca_unregister_device(mdev);
1118
1119err_cleanup:
1120 mthca_cleanup_mcg_table(mdev);
1121 mthca_cleanup_av_table(mdev);
1122 mthca_cleanup_qp_table(mdev);
ec34a922 1123 mthca_cleanup_srq_table(mdev);
1da177e4
LT
1124 mthca_cleanup_cq_table(mdev);
1125 mthca_cmd_use_polling(mdev);
1126 mthca_cleanup_eq_table(mdev);
1127
1128 mthca_pd_free(mdev, &mdev->driver_pd);
1129
1130 mthca_cleanup_mr_table(mdev);
1131 mthca_cleanup_pd_table(mdev);
1132 mthca_cleanup_uar_table(mdev);
1133
1134err_close:
017aadc4
MT
1135 if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
1136 pci_disable_msix(pdev);
017aadc4 1137
1da177e4
LT
1138 mthca_close_hca(mdev);
1139
80fd8238
RD
1140err_cmd:
1141 mthca_cmd_cleanup(mdev);
1da177e4
LT
1142
1143err_free_dev:
1da177e4
LT
1144 ib_dealloc_device(&mdev->ib_dev);
1145
1146err_free_res:
208dde28 1147 pci_release_regions(pdev);
1da177e4
LT
1148
1149err_disable_pdev:
1150 pci_disable_device(pdev);
1151 pci_set_drvdata(pdev, NULL);
1152 return err;
1153}
1154
b3b30f5e 1155static void __mthca_remove_one(struct pci_dev *pdev)
1da177e4
LT
1156{
1157 struct mthca_dev *mdev = pci_get_drvdata(pdev);
1158 u8 status;
1159 int p;
1160
1161 if (mdev) {
1162 mthca_free_agents(mdev);
1163 mthca_unregister_device(mdev);
1164
1165 for (p = 1; p <= mdev->limits.num_ports; ++p)
1166 mthca_CLOSE_IB(mdev, p, &status);
1167
1168 mthca_cleanup_mcg_table(mdev);
1169 mthca_cleanup_av_table(mdev);
1170 mthca_cleanup_qp_table(mdev);
ec34a922 1171 mthca_cleanup_srq_table(mdev);
1da177e4
LT
1172 mthca_cleanup_cq_table(mdev);
1173 mthca_cmd_use_polling(mdev);
1174 mthca_cleanup_eq_table(mdev);
1175
1176 mthca_pd_free(mdev, &mdev->driver_pd);
1177
1178 mthca_cleanup_mr_table(mdev);
1179 mthca_cleanup_pd_table(mdev);
1180
1181 iounmap(mdev->kar);
1182 mthca_uar_free(mdev, &mdev->driver_uar);
1183 mthca_cleanup_uar_table(mdev);
1da177e4 1184 mthca_close_hca(mdev);
80fd8238 1185 mthca_cmd_cleanup(mdev);
1da177e4
LT
1186
1187 if (mdev->mthca_flags & MTHCA_FLAG_MSI_X)
1188 pci_disable_msix(pdev);
1da177e4
LT
1189
1190 ib_dealloc_device(&mdev->ib_dev);
208dde28 1191 pci_release_regions(pdev);
1da177e4
LT
1192 pci_disable_device(pdev);
1193 pci_set_drvdata(pdev, NULL);
1194 }
1195}
1196
b3b30f5e
JM
1197int __mthca_restart_one(struct pci_dev *pdev)
1198{
1199 struct mthca_dev *mdev;
de57c9f1 1200 int hca_type;
b3b30f5e
JM
1201
1202 mdev = pci_get_drvdata(pdev);
1203 if (!mdev)
1204 return -ENODEV;
de57c9f1 1205 hca_type = mdev->hca_type;
b3b30f5e 1206 __mthca_remove_one(pdev);
de57c9f1 1207 return __mthca_init_one(pdev, hca_type);
b3b30f5e
JM
1208}
1209
1210static int __devinit mthca_init_one(struct pci_dev *pdev,
f4f3d0f0 1211 const struct pci_device_id *id)
b3b30f5e
JM
1212{
1213 static int mthca_version_printed = 0;
1214 int ret;
1215
1216 mutex_lock(&mthca_device_mutex);
1217
1218 if (!mthca_version_printed) {
1219 printk(KERN_INFO "%s", mthca_version);
1220 ++mthca_version_printed;
1221 }
1222
1223 if (id->driver_data >= ARRAY_SIZE(mthca_hca_table)) {
1224 printk(KERN_ERR PFX "%s has invalid driver data %lx\n",
1225 pci_name(pdev), id->driver_data);
1226 mutex_unlock(&mthca_device_mutex);
1227 return -ENODEV;
1228 }
1229
1230 ret = __mthca_init_one(pdev, id->driver_data);
1231
1232 mutex_unlock(&mthca_device_mutex);
1233
1234 return ret;
1235}
1236
1237static void __devexit mthca_remove_one(struct pci_dev *pdev)
1238{
1239 mutex_lock(&mthca_device_mutex);
1240 __mthca_remove_one(pdev);
1241 mutex_unlock(&mthca_device_mutex);
1242}
1243
1da177e4
LT
1244static struct pci_device_id mthca_pci_table[] = {
1245 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR),
1246 .driver_data = TAVOR },
1247 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_TAVOR),
1248 .driver_data = TAVOR },
1249 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
1250 .driver_data = ARBEL_COMPAT },
1251 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT),
1252 .driver_data = ARBEL_COMPAT },
1253 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_ARBEL),
1254 .driver_data = ARBEL_NATIVE },
1255 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_ARBEL),
1256 .driver_data = ARBEL_NATIVE },
68a3c212
RD
1257 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI),
1258 .driver_data = SINAI },
1259 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI),
1260 .driver_data = SINAI },
1261 { PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
1262 .driver_data = SINAI },
1263 { PCI_DEVICE(PCI_VENDOR_ID_TOPSPIN, PCI_DEVICE_ID_MELLANOX_SINAI_OLD),
1264 .driver_data = SINAI },
1da177e4
LT
1265 { 0, }
1266};
1267
1268MODULE_DEVICE_TABLE(pci, mthca_pci_table);
1269
1270static struct pci_driver mthca_driver = {
177214af 1271 .name = DRV_NAME,
1da177e4
LT
1272 .id_table = mthca_pci_table,
1273 .probe = mthca_init_one,
1274 .remove = __devexit_p(mthca_remove_one)
1275};
1276
82da703e
LA
1277static void __init __mthca_check_profile_val(const char *name, int *pval,
1278 int pval_default)
1279{
1280 /* value must be positive and power of 2 */
1281 int old_pval = *pval;
1282
1283 if (old_pval <= 0)
1284 *pval = pval_default;
1285 else
1286 *pval = roundup_pow_of_two(old_pval);
1287
1288 if (old_pval != *pval) {
1289 printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n",
1290 old_pval, name);
1291 printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval);
1292 }
1293}
1294
1295#define mthca_check_profile_val(name, default) \
1296 __mthca_check_profile_val(#name, &hca_profile.name, default)
1297
1298static void __init mthca_validate_profile(void)
1299{
1300 mthca_check_profile_val(num_qp, MTHCA_DEFAULT_NUM_QP);
1301 mthca_check_profile_val(rdb_per_qp, MTHCA_DEFAULT_RDB_PER_QP);
1302 mthca_check_profile_val(num_cq, MTHCA_DEFAULT_NUM_CQ);
1303 mthca_check_profile_val(num_mcg, MTHCA_DEFAULT_NUM_MCG);
1304 mthca_check_profile_val(num_mpt, MTHCA_DEFAULT_NUM_MPT);
1305 mthca_check_profile_val(num_mtt, MTHCA_DEFAULT_NUM_MTT);
1306 mthca_check_profile_val(num_udav, MTHCA_DEFAULT_NUM_UDAV);
1307 mthca_check_profile_val(fmr_reserved_mtts, MTHCA_DEFAULT_NUM_RESERVED_MTTS);
1308
1309 if (hca_profile.fmr_reserved_mtts >= hca_profile.num_mtt) {
1310 printk(KERN_WARNING PFX "Invalid fmr_reserved_mtts module parameter %d.\n",
1311 hca_profile.fmr_reserved_mtts);
1312 printk(KERN_WARNING PFX "(Must be smaller than num_mtt %d)\n",
1313 hca_profile.num_mtt);
1314 hca_profile.fmr_reserved_mtts = hca_profile.num_mtt / 2;
1315 printk(KERN_WARNING PFX "Corrected fmr_reserved_mtts to %d.\n",
1316 hca_profile.fmr_reserved_mtts);
1317 }
1318}
1319
1da177e4
LT
1320static int __init mthca_init(void)
1321{
1322 int ret;
1323
82da703e
LA
1324 mthca_validate_profile();
1325
b3b30f5e
JM
1326 ret = mthca_catas_init();
1327 if (ret)
1328 return ret;
1329
1da177e4 1330 ret = pci_register_driver(&mthca_driver);
b3b30f5e
JM
1331 if (ret < 0) {
1332 mthca_catas_cleanup();
1333 return ret;
1334 }
1335
1336 return 0;
1da177e4
LT
1337}
1338
1339static void __exit mthca_cleanup(void)
1340{
1341 pci_unregister_driver(&mthca_driver);
b3b30f5e 1342 mthca_catas_cleanup();
1da177e4
LT
1343}
1344
1345module_init(mthca_init);
1346module_exit(mthca_cleanup);