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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[net-next-2.6.git] / drivers / infiniband / hw / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
ea54b10c 34#include <linux/log2.h>
5a0e3ad6 35#include <linux/slab.h>
ea54b10c 36
225c7b1f
RD		 37#include <rdma/ib_cache.h>
38#include <rdma/ib_pack.h>
39
40#include <linux/mlx4/qp.h>
41
42#include "mlx4_ib.h"
43#include "user.h"
44
45enum {
46 MLX4_IB_ACK_REQ_FREQ = 8,
47};
48
49enum {
50 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
51 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
52};
53
54enum {
55 /*
56 * Largest possible UD header: send with GRH and immediate data.
57 */
417608c2
EC		 58 MLX4_IB_UD_HEADER_SIZE = 72,
59 MLX4_IB_LSO_HEADER_SPARE = 128,
225c7b1f
RD		 60};
61
62struct mlx4_ib_sqp {
63 struct mlx4_ib_qp qp;
64 int pkey_index;
65 u32 qkey;
66 u32 send_psn;
67 struct ib_ud_header ud_header;
68 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
69};
70
83904132 71enum {
417608c2
EC		 72 MLX4_IB_MIN_SQ_STRIDE = 6,
73 MLX4_IB_CACHE_LINE_SIZE = 64,
83904132
JM		 74};
75
225c7b1f 76static const __be32 mlx4_ib_opcode[] = {
9c3da099
HH		 77 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
78 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
79 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
80 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
81 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
82 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
83 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
84 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
85 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
86 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
87 [IB_WR_FAST_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
225c7b1f
RD		 88};
89
90static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
91{
92 return container_of(mqp, struct mlx4_ib_sqp, qp);
93}
94
95static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
96{
97 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
98 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
99}
100
101static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
102{
103 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
104 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
105}
106
107static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
108{
1c69fc2a 109 return mlx4_buf_offset(&qp->buf, offset);
225c7b1f
RD		 110}
111
112static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
113{
114 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
115}
116
117static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
118{
119 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
120}
121
0e6e7416
RD		 122/*
123 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
ea54b10c
JM		 124 * first four bytes of every 64 byte chunk with
125 * 0x7FFFFFF | (invalid_ownership_value << 31).
126 *
127 * When the max work request size is less than or equal to the WQE
128 * basic block size, as an optimization, we can stamp all WQEs with
129 * 0xffffffff, and skip the very first chunk of each WQE.
0e6e7416 130 */
ea54b10c 131static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
0e6e7416 132{
d2ae16d5 133 __be32 *wqe;
0e6e7416 134 int i;
ea54b10c
JM		 135 int s;
136 int ind;
137 void *buf;
138 __be32 stamp;
9670e553 139 struct mlx4_wqe_ctrl_seg *ctrl;
ea54b10c 140
ea54b10c 141 if (qp->sq_max_wqes_per_wr > 1) {
9670e553 142 s = roundup(size, 1U << qp->sq.wqe_shift);
ea54b10c
JM		 143 for (i = 0; i < s; i += 64) {
144 ind = (i >> qp->sq.wqe_shift) + n;
145 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
146 cpu_to_be32(0xffffffff);
147 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
148 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
149 *wqe = stamp;
150 }
151 } else {
9670e553
EC		 152 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
153 s = (ctrl->fence_size & 0x3f) << 4;
ea54b10c
JM		 154 for (i = 64; i < s; i += 64) {
155 wqe = buf + i;
d2ae16d5 156 *wqe = cpu_to_be32(0xffffffff);
ea54b10c
JM		 157 }
158 }
159}
160
161static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
162{
163 struct mlx4_wqe_ctrl_seg *ctrl;
164 struct mlx4_wqe_inline_seg *inl;
165 void *wqe;
166 int s;
167
168 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
169 s = sizeof(struct mlx4_wqe_ctrl_seg);
170
171 if (qp->ibqp.qp_type == IB_QPT_UD) {
172 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
173 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
174 memset(dgram, 0, sizeof *dgram);
175 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
176 s += sizeof(struct mlx4_wqe_datagram_seg);
177 }
178
179 /* Pad the remainder of the WQE with an inline data segment. */
180 if (size > s) {
181 inl = wqe + s;
182 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
183 }
184 ctrl->srcrb_flags = 0;
185 ctrl->fence_size = size / 16;
186 /*
187 * Make sure descriptor is fully written before setting ownership bit
188 * (because HW can start executing as soon as we do).
189 */
190 wmb();
191
192 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
193 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
0e6e7416 194
ea54b10c
JM		 195 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
196}
197
198/* Post NOP WQE to prevent wrap-around in the middle of WR */
199static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
200{
201 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
202 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
203 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
204 ind += s;
205 }
206 return ind;
0e6e7416
RD		 207}
208
225c7b1f
RD		 209static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
210{
211 struct ib_event event;
212 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
213
214 if (type == MLX4_EVENT_TYPE_PATH_MIG)
215 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
216
217 if (ibqp->event_handler) {
218 event.device = ibqp->device;
219 event.element.qp = ibqp;
220 switch (type) {
221 case MLX4_EVENT_TYPE_PATH_MIG:
222 event.event = IB_EVENT_PATH_MIG;
223 break;
224 case MLX4_EVENT_TYPE_COMM_EST:
225 event.event = IB_EVENT_COMM_EST;
226 break;
227 case MLX4_EVENT_TYPE_SQ_DRAINED:
228 event.event = IB_EVENT_SQ_DRAINED;
229 break;
230 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
231 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
232 break;
233 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
234 event.event = IB_EVENT_QP_FATAL;
235 break;
236 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
237 event.event = IB_EVENT_PATH_MIG_ERR;
238 break;
239 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
240 event.event = IB_EVENT_QP_REQ_ERR;
241 break;
242 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
243 event.event = IB_EVENT_QP_ACCESS_ERR;
244 break;
245 default:
246 printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
247 "on QP %06x\n", type, qp->qpn);
248 return;
249 }
250
251 ibqp->event_handler(&event, ibqp->qp_context);
252 }
253}
254
b832be1e 255static int send_wqe_overhead(enum ib_qp_type type, u32 flags)
225c7b1f
RD		 256{
257 /*
258 * UD WQEs must have a datagram segment.
259 * RC and UC WQEs might have a remote address segment.
260 * MLX WQEs need two extra inline data segments (for the UD
261 * header and space for the ICRC).
262 */
263 switch (type) {
264 case IB_QPT_UD:
265 return sizeof (struct mlx4_wqe_ctrl_seg) +
b832be1e 266 sizeof (struct mlx4_wqe_datagram_seg) +
417608c2 267 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
225c7b1f
RD		 268 case IB_QPT_UC:
269 return sizeof (struct mlx4_wqe_ctrl_seg) +
270 sizeof (struct mlx4_wqe_raddr_seg);
271 case IB_QPT_RC:
272 return sizeof (struct mlx4_wqe_ctrl_seg) +
273 sizeof (struct mlx4_wqe_atomic_seg) +
274 sizeof (struct mlx4_wqe_raddr_seg);
275 case IB_QPT_SMI:
276 case IB_QPT_GSI:
277 return sizeof (struct mlx4_wqe_ctrl_seg) +
278 ALIGN(MLX4_IB_UD_HEADER_SIZE +
e61ef241
RD		 279 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
280 MLX4_INLINE_ALIGN) *
225c7b1f
RD		 281 sizeof (struct mlx4_wqe_inline_seg),
282 sizeof (struct mlx4_wqe_data_seg)) +
283 ALIGN(4 +
284 sizeof (struct mlx4_wqe_inline_seg),
285 sizeof (struct mlx4_wqe_data_seg));
286 default:
287 return sizeof (struct mlx4_wqe_ctrl_seg);
288 }
289}
290
2446304d 291static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
a4cd7ed8 292 int is_user, int has_srq, struct mlx4_ib_qp *qp)
225c7b1f 293{
2446304d
EC		 294 /* Sanity check RQ size before proceeding */
295 if (cap->max_recv_wr > dev->dev->caps.max_wqes ||
296 cap->max_recv_sge > dev->dev->caps.max_rq_sg)
297 return -EINVAL;
298
a4cd7ed8
RD		 299 if (has_srq) {
300 /* QPs attached to an SRQ should have no RQ */
301 if (cap->max_recv_wr)
302 return -EINVAL;
2446304d 303
0e6e7416 304 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
a4cd7ed8
RD		 305 } else {
306 /* HW requires >= 1 RQ entry with >= 1 gather entry */
307 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
308 return -EINVAL;
309
0e6e7416 310 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
42c059ea 311 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
a4cd7ed8
RD		 312 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
313 }
2446304d 314
0e6e7416 315 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
2446304d
EC		 316 cap->max_recv_sge = qp->rq.max_gs;
317
318 return 0;
319}
320
321static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
322 enum ib_qp_type type, struct mlx4_ib_qp *qp)
323{
ea54b10c
JM		 324 int s;
325
2446304d 326 /* Sanity check SQ size before proceeding */
225c7b1f 327 if (cap->max_send_wr > dev->dev->caps.max_wqes ||
225c7b1f 328 cap->max_send_sge > dev->dev->caps.max_sq_sg ||
b832be1e 329 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
225c7b1f
RD		 330 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
331 return -EINVAL;
332
333 /*
334 * For MLX transport we need 2 extra S/G entries:
335 * one for the header and one for the checksum at the end
336 */
337 if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
338 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
339 return -EINVAL;
340
ea54b10c
JM		 341 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
342 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
b832be1e 343 send_wqe_overhead(type, qp->flags);
225c7b1f 344
cd155c1c
RD		 345 if (s > dev->dev->caps.max_sq_desc_sz)
346 return -EINVAL;
347
0e6e7416 348 /*
ea54b10c
JM		 349 * Hermon supports shrinking WQEs, such that a single work
350 * request can include multiple units of 1 << wqe_shift. This
351 * way, work requests can differ in size, and do not have to
352 * be a power of 2 in size, saving memory and speeding up send
353 * WR posting. Unfortunately, if we do this then the
354 * wqe_index field in CQEs can't be used to look up the WR ID
355 * anymore, so we do this only if selective signaling is off.
356 *
357 * Further, on 32-bit platforms, we can't use vmap() to make
af901ca1 358 * the QP buffer virtually contiguous. Thus we have to use
ea54b10c
JM		 359 * constant-sized WRs to make sure a WR is always fully within
360 * a single page-sized chunk.
361 *
362 * Finally, we use NOP work requests to pad the end of the
363 * work queue, to avoid wrap-around in the middle of WR. We
364 * set NEC bit to avoid getting completions with error for
365 * these NOP WRs, but since NEC is only supported starting
366 * with firmware 2.2.232, we use constant-sized WRs for older
367 * firmware.
368 *
369 * And, since MLX QPs only support SEND, we use constant-sized
370 * WRs in this case.
371 *
372 * We look for the smallest value of wqe_shift such that the
373 * resulting number of wqes does not exceed device
374 * capabilities.
375 *
376 * We set WQE size to at least 64 bytes, this way stamping
377 * invalidates each WQE.
0e6e7416 378 */
ea54b10c
JM		 379 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
380 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
381 type != IB_QPT_SMI && type != IB_QPT_GSI)
382 qp->sq.wqe_shift = ilog2(64);
383 else
384 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
385
386 for (;;) {
ea54b10c
JM		 387 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
388
389 /*
390 * We need to leave 2 KB + 1 WR of headroom in the SQ to
391 * allow HW to prefetch.
392 */
393 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
394 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
395 qp->sq_max_wqes_per_wr +
396 qp->sq_spare_wqes);
397
398 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
399 break;
400
401 if (qp->sq_max_wqes_per_wr <= 1)
402 return -EINVAL;
403
404 ++qp->sq.wqe_shift;
405 }
406
cd155c1c
RD		 407 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
408 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
b832be1e
EC		 409 send_wqe_overhead(type, qp->flags)) /
410 sizeof (struct mlx4_wqe_data_seg);
0e6e7416
RD		 411
412 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
413 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
225c7b1f
RD		 414 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
415 qp->rq.offset = 0;
0e6e7416 416 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
225c7b1f 417 } else {
0e6e7416 418 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
225c7b1f
RD		 419 qp->sq.offset = 0;
420 }
421
ea54b10c
JM		 422 cap->max_send_wr = qp->sq.max_post =
423 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cd155c1c
RD		 424 cap->max_send_sge = min(qp->sq.max_gs,
425 min(dev->dev->caps.max_sq_sg,
426 dev->dev->caps.max_rq_sg));
54e95f8d
RD		 427 /* We don't support inline sends for kernel QPs (yet) */
428 cap->max_inline_data = 0;
225c7b1f
RD		 429
430 return 0;
431}
432
83904132
JM		 433static int set_user_sq_size(struct mlx4_ib_dev *dev,
434 struct mlx4_ib_qp *qp,
2446304d
EC		 435 struct mlx4_ib_create_qp *ucmd)
436{
83904132
JM		 437 /* Sanity check SQ size before proceeding */
438 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
439 ucmd->log_sq_stride >
440 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
441 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
442 return -EINVAL;
443
0e6e7416 444 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
2446304d
EC		 445 qp->sq.wqe_shift = ucmd->log_sq_stride;
446
0e6e7416
RD		 447 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
448 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
2446304d
EC		 449
450 return 0;
451}
452
225c7b1f
RD		 453static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
454 struct ib_qp_init_attr *init_attr,
455 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
456{
a3cdcbfa 457 int qpn;
225c7b1f 458 int err;
225c7b1f
RD		 459
460 mutex_init(&qp->mutex);
461 spin_lock_init(&qp->sq.lock);
462 spin_lock_init(&qp->rq.lock);
463
464 qp->state = IB_QPS_RESET;
ea54b10c
JM		 465 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
466 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
225c7b1f 467
a4cd7ed8 468 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
225c7b1f
RD		 469 if (err)
470 goto err;
471
472 if (pd->uobject) {
473 struct mlx4_ib_create_qp ucmd;
474
475 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
476 err = -EFAULT;
477 goto err;
478 }
479
0e6e7416
RD		 480 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
481
83904132 482 err = set_user_sq_size(dev, qp, &ucmd);
2446304d
EC		 483 if (err)
484 goto err;
485
225c7b1f 486 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
cb9fbc5c 487 qp->buf_size, 0, 0);
225c7b1f
RD		 488 if (IS_ERR(qp->umem)) {
489 err = PTR_ERR(qp->umem);
490 goto err;
491 }
492
493 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
494 ilog2(qp->umem->page_size), &qp->mtt);
495 if (err)
496 goto err_buf;
497
498 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
499 if (err)
500 goto err_mtt;
501
02d89b87
RD		 502 if (!init_attr->srq) {
503 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
504 ucmd.db_addr, &qp->db);
505 if (err)
506 goto err_mtt;
507 }
225c7b1f 508 } else {
0e6e7416
RD		 509 qp->sq_no_prefetch = 0;
510
521e575b
RL		 511 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
512 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
513
b832be1e
EC		 514 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
515 qp->flags |= MLX4_IB_QP_LSO;
516
2446304d
EC		 517 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
518 if (err)
519 goto err;
520
02d89b87 521 if (!init_attr->srq) {
6296883c 522 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
02d89b87
RD		 523 if (err)
524 goto err;
225c7b1f 525
02d89b87
RD		 526 *qp->db.db = 0;
527 }
225c7b1f
RD		 528
529 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
530 err = -ENOMEM;
531 goto err_db;
532 }
533
534 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
535 &qp->mtt);
536 if (err)
537 goto err_buf;
538
539 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
540 if (err)
541 goto err_mtt;
542
0e6e7416
RD		 543 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
544 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
225c7b1f
RD		 545
546 if (!qp->sq.wrid || !qp->rq.wrid) {
547 err = -ENOMEM;
548 goto err_wrid;
549 }
225c7b1f
RD		 550 }
551
a3cdcbfa
YP		 552 if (sqpn) {
553 qpn = sqpn;
554 } else {
555 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn);
556 if (err)
557 goto err_wrid;
558 }
559
560 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
225c7b1f 561 if (err)
a3cdcbfa 562 goto err_qpn;
225c7b1f
RD		 563
564 /*
565 * Hardware wants QPN written in big-endian order (after
566 * shifting) for send doorbell. Precompute this value to save
567 * a little bit when posting sends.
568 */
569 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
570
225c7b1f
RD		 571 qp->mqp.event = mlx4_ib_qp_event;
572
573 return 0;
574
a3cdcbfa
YP		 575err_qpn:
576 if (!sqpn)
577 mlx4_qp_release_range(dev->dev, qpn, 1);
578
225c7b1f 579err_wrid:
23f1b384
RD		 580 if (pd->uobject) {
581 if (!init_attr->srq)
582 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context),
583 &qp->db);
584 } else {
225c7b1f
RD		 585 kfree(qp->sq.wrid);
586 kfree(qp->rq.wrid);
587 }
588
589err_mtt:
590 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
591
592err_buf:
593 if (pd->uobject)
594 ib_umem_release(qp->umem);
595 else
596 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
597
598err_db:
02d89b87 599 if (!pd->uobject && !init_attr->srq)
6296883c 600 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 601
602err:
603 return err;
604}
605
606static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
607{
608 switch (state) {
609 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
610 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
611 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
612 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
613 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
614 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
615 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
616 default: return -1;
617 }
618}
619
620static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 621 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
225c7b1f 622{
338a8fad 623 if (send_cq == recv_cq) {
225c7b1f 624 spin_lock_irq(&send_cq->lock);
338a8fad
RD		 625 __acquire(&recv_cq->lock);
626 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f
RD		 627 spin_lock_irq(&send_cq->lock);
628 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
629 } else {
630 spin_lock_irq(&recv_cq->lock);
631 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
632 }
633}
634
635static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
338a8fad 636 __releases(&send_cq->lock) __releases(&recv_cq->lock)
225c7b1f 637{
338a8fad
RD		 638 if (send_cq == recv_cq) {
639 __release(&recv_cq->lock);
225c7b1f 640 spin_unlock_irq(&send_cq->lock);
338a8fad 641 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
225c7b1f
RD		 642 spin_unlock(&recv_cq->lock);
643 spin_unlock_irq(&send_cq->lock);
644 } else {
645 spin_unlock(&send_cq->lock);
646 spin_unlock_irq(&recv_cq->lock);
647 }
648}
649
650static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
651 int is_user)
652{
653 struct mlx4_ib_cq *send_cq, *recv_cq;
654
655 if (qp->state != IB_QPS_RESET)
656 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
657 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
658 printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
659 qp->mqp.qpn);
660
661 send_cq = to_mcq(qp->ibqp.send_cq);
662 recv_cq = to_mcq(qp->ibqp.recv_cq);
663
664 mlx4_ib_lock_cqs(send_cq, recv_cq);
665
666 if (!is_user) {
667 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
668 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
669 if (send_cq != recv_cq)
670 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
671 }
672
673 mlx4_qp_remove(dev->dev, &qp->mqp);
674
675 mlx4_ib_unlock_cqs(send_cq, recv_cq);
676
677 mlx4_qp_free(dev->dev, &qp->mqp);
a3cdcbfa
YP		 678
679 if (!is_sqp(dev, qp))
680 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
681
225c7b1f
RD		 682 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
683
684 if (is_user) {
02d89b87
RD		 685 if (!qp->ibqp.srq)
686 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
687 &qp->db);
225c7b1f
RD		 688 ib_umem_release(qp->umem);
689 } else {
690 kfree(qp->sq.wrid);
691 kfree(qp->rq.wrid);
692 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
02d89b87 693 if (!qp->ibqp.srq)
6296883c 694 mlx4_db_free(dev->dev, &qp->db);
225c7b1f
RD		 695 }
696}
697
698struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
699 struct ib_qp_init_attr *init_attr,
700 struct ib_udata *udata)
701{
702 struct mlx4_ib_dev *dev = to_mdev(pd->device);
703 struct mlx4_ib_sqp *sqp;
704 struct mlx4_ib_qp *qp;
705 int err;
706
521e575b
RL		 707 /*
708 * We only support LSO and multicast loopback blocking, and
709 * only for kernel UD QPs.
710 */
711 if (init_attr->create_flags & ~(IB_QP_CREATE_IPOIB_UD_LSO |
712 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
b832be1e 713 return ERR_PTR(-EINVAL);
521e575b
RL		 714
715 if (init_attr->create_flags &&
b832be1e 716 (pd->uobject || init_attr->qp_type != IB_QPT_UD))
b846f25a
EC		 717 return ERR_PTR(-EINVAL);
718
225c7b1f
RD		 719 switch (init_attr->qp_type) {
720 case IB_QPT_RC:
721 case IB_QPT_UC:
722 case IB_QPT_UD:
723 {
f507d28b 724 qp = kzalloc(sizeof *qp, GFP_KERNEL);
225c7b1f
RD		 725 if (!qp)
726 return ERR_PTR(-ENOMEM);
727
728 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
729 if (err) {
730 kfree(qp);
731 return ERR_PTR(err);
732 }
733
734 qp->ibqp.qp_num = qp->mqp.qpn;
735
736 break;
737 }
738 case IB_QPT_SMI:
739 case IB_QPT_GSI:
740 {
741 /* Userspace is not allowed to create special QPs: */
742 if (pd->uobject)
743 return ERR_PTR(-EINVAL);
744
f507d28b 745 sqp = kzalloc(sizeof *sqp, GFP_KERNEL);
225c7b1f
RD		 746 if (!sqp)
747 return ERR_PTR(-ENOMEM);
748
749 qp = &sqp->qp;
750
751 err = create_qp_common(dev, pd, init_attr, udata,
752 dev->dev->caps.sqp_start +
753 (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
754 init_attr->port_num - 1,
755 qp);
756 if (err) {
757 kfree(sqp);
758 return ERR_PTR(err);
759 }
760
761 qp->port = init_attr->port_num;
762 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
763
764 break;
765 }
766 default:
767 /* Don't support raw QPs */
768 return ERR_PTR(-EINVAL);
769 }
770
771 return &qp->ibqp;
772}
773
774int mlx4_ib_destroy_qp(struct ib_qp *qp)
775{
776 struct mlx4_ib_dev *dev = to_mdev(qp->device);
777 struct mlx4_ib_qp *mqp = to_mqp(qp);
778
779 if (is_qp0(dev, mqp))
780 mlx4_CLOSE_PORT(dev->dev, mqp->port);
781
782 destroy_qp_common(dev, mqp, !!qp->pd->uobject);
783
784 if (is_sqp(dev, mqp))
785 kfree(to_msqp(mqp));
786 else
787 kfree(mqp);
788
789 return 0;
790}
791
225c7b1f
RD		 792static int to_mlx4_st(enum ib_qp_type type)
793{
794 switch (type) {
795 case IB_QPT_RC: return MLX4_QP_ST_RC;
796 case IB_QPT_UC: return MLX4_QP_ST_UC;
797 case IB_QPT_UD: return MLX4_QP_ST_UD;
798 case IB_QPT_SMI:
799 case IB_QPT_GSI: return MLX4_QP_ST_MLX;
800 default: return -1;
801 }
802}
803
65adfa91 804static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
225c7b1f
RD		 805 int attr_mask)
806{
807 u8 dest_rd_atomic;
808 u32 access_flags;
809 u32 hw_access_flags = 0;
810
811 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
812 dest_rd_atomic = attr->max_dest_rd_atomic;
813 else
814 dest_rd_atomic = qp->resp_depth;
815
816 if (attr_mask & IB_QP_ACCESS_FLAGS)
817 access_flags = attr->qp_access_flags;
818 else
819 access_flags = qp->atomic_rd_en;
820
821 if (!dest_rd_atomic)
822 access_flags &= IB_ACCESS_REMOTE_WRITE;
823
824 if (access_flags & IB_ACCESS_REMOTE_READ)
825 hw_access_flags |= MLX4_QP_BIT_RRE;
826 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
827 hw_access_flags |= MLX4_QP_BIT_RAE;
828 if (access_flags & IB_ACCESS_REMOTE_WRITE)
829 hw_access_flags |= MLX4_QP_BIT_RWE;
830
831 return cpu_to_be32(hw_access_flags);
832}
833
65adfa91 834static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
225c7b1f
RD		 835 int attr_mask)
836{
837 if (attr_mask & IB_QP_PKEY_INDEX)
838 sqp->pkey_index = attr->pkey_index;
839 if (attr_mask & IB_QP_QKEY)
840 sqp->qkey = attr->qkey;
841 if (attr_mask & IB_QP_SQ_PSN)
842 sqp->send_psn = attr->sq_psn;
843}
844
845static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
846{
847 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
848}
849
65adfa91 850static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
225c7b1f
RD		 851 struct mlx4_qp_path *path, u8 port)
852{
853 path->grh_mylmc = ah->src_path_bits & 0x7f;
854 path->rlid = cpu_to_be16(ah->dlid);
855 if (ah->static_rate) {
856 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
857 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
858 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
859 --path->static_rate;
860 } else
861 path->static_rate = 0;
862 path->counter_index = 0xff;
863
864 if (ah->ah_flags & IB_AH_GRH) {
5ae2a7a8 865 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
225c7b1f 866 printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
5ae2a7a8 867 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
225c7b1f
RD		 868 return -1;
869 }
870
871 path->grh_mylmc |= 1 << 7;
872 path->mgid_index = ah->grh.sgid_index;
873 path->hop_limit = ah->grh.hop_limit;
874 path->tclass_flowlabel =
875 cpu_to_be32((ah->grh.traffic_class << 20) |
876 (ah->grh.flow_label));
877 memcpy(path->rgid, ah->grh.dgid.raw, 16);
878 }
879
880 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
881 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
882
883 return 0;
884}
885
65adfa91
MT		 886static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
887 const struct ib_qp_attr *attr, int attr_mask,
888 enum ib_qp_state cur_state, enum ib_qp_state new_state)
225c7b1f
RD		 889{
890 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
891 struct mlx4_ib_qp *qp = to_mqp(ibqp);
892 struct mlx4_qp_context *context;
893 enum mlx4_qp_optpar optpar = 0;
225c7b1f
RD		 894 int sqd_event;
895 int err = -EINVAL;
896
897 context = kzalloc(sizeof *context, GFP_KERNEL);
898 if (!context)
899 return -ENOMEM;
900
225c7b1f
RD		 901 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
902 (to_mlx4_st(ibqp->qp_type) << 16));
225c7b1f
RD		 903
904 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
905 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
906 else {
907 optpar |= MLX4_QP_OPTPAR_PM_STATE;
908 switch (attr->path_mig_state) {
909 case IB_MIG_MIGRATED:
910 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
911 break;
912 case IB_MIG_REARM:
913 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
914 break;
915 case IB_MIG_ARMED:
916 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
917 break;
918 }
919 }
920
b832be1e 921 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
225c7b1f 922 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
b832be1e
EC		 923 else if (ibqp->qp_type == IB_QPT_UD) {
924 if (qp->flags & MLX4_IB_QP_LSO)
925 context->mtu_msgmax = (IB_MTU_4096 << 5) |
926 ilog2(dev->dev->caps.max_gso_sz);
927 else
6e0d733d 928 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
b832be1e 929 } else if (attr_mask & IB_QP_PATH_MTU) {
225c7b1f
RD		 930 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
931 printk(KERN_ERR "path MTU (%u) is invalid\n",
932 attr->path_mtu);
f5b40431 933 goto out;
225c7b1f 934 }
d1f2cd89
EC		 935 context->mtu_msgmax = (attr->path_mtu << 5) |
936 ilog2(dev->dev->caps.max_msg_sz);
225c7b1f
RD		 937 }
938
0e6e7416
RD		 939 if (qp->rq.wqe_cnt)
940 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
225c7b1f
RD		 941 context->rq_size_stride |= qp->rq.wqe_shift - 4;
942
0e6e7416
RD		 943 if (qp->sq.wqe_cnt)
944 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
225c7b1f
RD		 945 context->sq_size_stride |= qp->sq.wqe_shift - 4;
946
0e6e7416
RD		 947 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
948 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
949
225c7b1f
RD		 950 if (qp->ibqp.uobject)
951 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
952 else
953 context->usr_page = cpu_to_be32(dev->priv_uar.index);
954
955 if (attr_mask & IB_QP_DEST_QPN)
956 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
957
958 if (attr_mask & IB_QP_PORT) {
959 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
960 !(attr_mask & IB_QP_AV)) {
961 mlx4_set_sched(&context->pri_path, attr->port_num);
962 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
963 }
964 }
965
966 if (attr_mask & IB_QP_PKEY_INDEX) {
967 context->pri_path.pkey_index = attr->pkey_index;
968 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
969 }
970
225c7b1f
RD		 971 if (attr_mask & IB_QP_AV) {
972 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
f5b40431 973 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
225c7b1f 974 goto out;
225c7b1f
RD		 975
976 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
977 MLX4_QP_OPTPAR_SCHED_QUEUE);
978 }
979
980 if (attr_mask & IB_QP_TIMEOUT) {
981 context->pri_path.ackto = attr->timeout << 3;
982 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
983 }
984
985 if (attr_mask & IB_QP_ALT_PATH) {
225c7b1f
RD		 986 if (attr->alt_port_num == 0 ||
987 attr->alt_port_num > dev->dev->caps.num_ports)
f5b40431 988 goto out;
225c7b1f 989
5ae2a7a8
RD		 990 if (attr->alt_pkey_index >=
991 dev->dev->caps.pkey_table_len[attr->alt_port_num])
f5b40431 992 goto out;
5ae2a7a8 993
225c7b1f
RD		 994 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
995 attr->alt_port_num))
f5b40431 996 goto out;
225c7b1f
RD		 997
998 context->alt_path.pkey_index = attr->alt_pkey_index;
999 context->alt_path.ackto = attr->alt_timeout << 3;
1000 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1001 }
1002
1003 context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
1004 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
57f01b53 1005
95d04f07
RD		 1006 /* Set "fast registration enabled" for all kernel QPs */
1007 if (!qp->ibqp.uobject)
1008 context->params1 |= cpu_to_be32(1 << 11);
1009
57f01b53
JM		 1010 if (attr_mask & IB_QP_RNR_RETRY) {
1011 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1012 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1013 }
1014
225c7b1f
RD		 1015 if (attr_mask & IB_QP_RETRY_CNT) {
1016 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1017 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1018 }
1019
1020 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1021 if (attr->max_rd_atomic)
1022 context->params1 |=
1023 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1024 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1025 }
1026
1027 if (attr_mask & IB_QP_SQ_PSN)
1028 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1029
1030 context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
1031
1032 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1033 if (attr->max_dest_rd_atomic)
1034 context->params2 |=
1035 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1036 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1037 }
1038
1039 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1040 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1041 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1042 }
1043
1044 if (ibqp->srq)
1045 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1046
1047 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1048 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1049 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1050 }
1051 if (attr_mask & IB_QP_RQ_PSN)
1052 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1053
1054 context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
1055
1056 if (attr_mask & IB_QP_QKEY) {
1057 context->qkey = cpu_to_be32(attr->qkey);
1058 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1059 }
1060
1061 if (ibqp->srq)
1062 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1063
02d89b87 1064 if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
225c7b1f
RD		 1065 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1066
1067 if (cur_state == IB_QPS_INIT &&
1068 new_state == IB_QPS_RTR &&
1069 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1070 ibqp->qp_type == IB_QPT_UD)) {
1071 context->pri_path.sched_queue = (qp->port - 1) << 6;
1072 if (is_qp0(dev, qp))
1073 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1074 else
1075 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1076 }
1077
1078 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1079 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1080 sqd_event = 1;
1081 else
1082 sqd_event = 0;
1083
d57f5f72
VS		 1084 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1085 context->rlkey |= (1 << 4);
1086
c0be5fb5
EC		 1087 /*
1088 * Before passing a kernel QP to the HW, make sure that the
0e6e7416
RD		 1089 * ownership bits of the send queue are set and the SQ
1090 * headroom is stamped so that the hardware doesn't start
1091 * processing stale work requests.
c0be5fb5
EC		 1092 */
1093 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1094 struct mlx4_wqe_ctrl_seg *ctrl;
1095 int i;
1096
0e6e7416 1097 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
c0be5fb5
EC		 1098 ctrl = get_send_wqe(qp, i);
1099 ctrl->owner_opcode = cpu_to_be32(1 << 31);
9670e553
EC		 1100 if (qp->sq_max_wqes_per_wr == 1)
1101 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
0e6e7416 1102
ea54b10c 1103 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
c0be5fb5
EC		 1104 }
1105 }
1106
225c7b1f
RD		 1107 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1108 to_mlx4_state(new_state), context, optpar,
1109 sqd_event, &qp->mqp);
1110 if (err)
1111 goto out;
1112
1113 qp->state = new_state;
1114
1115 if (attr_mask & IB_QP_ACCESS_FLAGS)
1116 qp->atomic_rd_en = attr->qp_access_flags;
1117 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1118 qp->resp_depth = attr->max_dest_rd_atomic;
1119 if (attr_mask & IB_QP_PORT)
1120 qp->port = attr->port_num;
1121 if (attr_mask & IB_QP_ALT_PATH)
1122 qp->alt_port = attr->alt_port_num;
1123
1124 if (is_sqp(dev, qp))
1125 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1126
1127 /*
1128 * If we moved QP0 to RTR, bring the IB link up; if we moved
1129 * QP0 to RESET or ERROR, bring the link back down.
1130 */
1131 if (is_qp0(dev, qp)) {
1132 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
5ae2a7a8
RD		 1133 if (mlx4_INIT_PORT(dev->dev, qp->port))
1134 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
1135 qp->port);
225c7b1f
RD		 1136
1137 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1138 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1139 mlx4_CLOSE_PORT(dev->dev, qp->port);
1140 }
1141
1142 /*
1143 * If we moved a kernel QP to RESET, clean up all old CQ
1144 * entries and reinitialize the QP.
1145 */
1146 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1147 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
1148 ibqp->srq ? to_msrq(ibqp->srq): NULL);
1149 if (ibqp->send_cq != ibqp->recv_cq)
1150 mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
1151
1152 qp->rq.head = 0;
1153 qp->rq.tail = 0;
1154 qp->sq.head = 0;
1155 qp->sq.tail = 0;
ea54b10c 1156 qp->sq_next_wqe = 0;
02d89b87
RD		 1157 if (!ibqp->srq)
1158 *qp->db.db = 0;
225c7b1f
RD		 1159 }
1160
1161out:
225c7b1f
RD		 1162 kfree(context);
1163 return err;
1164}
1165
65adfa91
MT		 1166int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1167 int attr_mask, struct ib_udata *udata)
1168{
1169 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1170 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1171 enum ib_qp_state cur_state, new_state;
1172 int err = -EINVAL;
1173
1174 mutex_lock(&qp->mutex);
1175
1176 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1177 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1178
1179 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1180 goto out;
1181
65adfa91
MT		 1182 if ((attr_mask & IB_QP_PORT) &&
1183 (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1184 goto out;
1185 }
1186
5ae2a7a8
RD		 1187 if (attr_mask & IB_QP_PKEY_INDEX) {
1188 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1189 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1190 goto out;
1191 }
1192
65adfa91
MT		 1193 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1194 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1195 goto out;
1196 }
1197
1198 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1199 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1200 goto out;
1201 }
1202
1203 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1204 err = 0;
1205 goto out;
1206 }
1207
65adfa91
MT		 1208 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1209
1210out:
1211 mutex_unlock(&qp->mutex);
1212 return err;
1213}
1214
225c7b1f 1215static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
f438000f 1216 void *wqe, unsigned *mlx_seg_len)
225c7b1f 1217{
a478868a 1218 struct ib_device *ib_dev = sqp->qp.ibqp.device;
225c7b1f
RD		 1219 struct mlx4_wqe_mlx_seg *mlx = wqe;
1220 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1221 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1222 u16 pkey;
1223 int send_size;
1224 int header_size;
e61ef241 1225 int spc;
225c7b1f
RD		 1226 int i;
1227
1228 send_size = 0;
1229 for (i = 0; i < wr->num_sge; ++i)
1230 send_size += wr->sg_list[i].length;
1231
920d706c 1232 ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), 0, &sqp->ud_header);
225c7b1f
RD		 1233
1234 sqp->ud_header.lrh.service_level =
1235 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1236 sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1237 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.g_slid & 0x7f);
1238 if (mlx4_ib_ah_grh_present(ah)) {
1239 sqp->ud_header.grh.traffic_class =
1240 (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1241 sqp->ud_header.grh.flow_label =
1242 ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
15261303 1243 sqp->ud_header.grh.hop_limit = ah->av.hop_limit;
225c7b1f
RD		 1244 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1245 ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1246 memcpy(sqp->ud_header.grh.destination_gid.raw,
1247 ah->av.dgid, 16);
1248 }
1249
1250 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1251 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1252 (sqp->ud_header.lrh.destination_lid ==
1253 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1254 (sqp->ud_header.lrh.service_level << 8));
1255 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1256
1257 switch (wr->opcode) {
1258 case IB_WR_SEND:
1259 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1260 sqp->ud_header.immediate_present = 0;
1261 break;
1262 case IB_WR_SEND_WITH_IMM:
1263 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1264 sqp->ud_header.immediate_present = 1;
0f39cf3d 1265 sqp->ud_header.immediate_data = wr->ex.imm_data;
225c7b1f
RD		 1266 break;
1267 default:
1268 return -EINVAL;
1269 }
1270
1271 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1272 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1273 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1274 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1275 if (!sqp->qp.ibqp.qp_num)
1276 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1277 else
1278 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1279 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1280 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1281 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1282 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1283 sqp->qkey : wr->wr.ud.remote_qkey);
1284 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1285
1286 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1287
1288 if (0) {
1289 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1290 for (i = 0; i < header_size / 4; ++i) {
1291 if (i % 8 == 0)
1292 printk(" [%02x] ", i * 4);
1293 printk(" %08x",
1294 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1295 if ((i + 1) % 8 == 0)
1296 printk("\n");
1297 }
1298 printk("\n");
1299 }
1300
e61ef241
RD		 1301 /*
1302 * Inline data segments may not cross a 64 byte boundary. If
1303 * our UD header is bigger than the space available up to the
1304 * next 64 byte boundary in the WQE, use two inline data
1305 * segments to hold the UD header.
1306 */
1307 spc = MLX4_INLINE_ALIGN -
1308 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1309 if (header_size <= spc) {
1310 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1311 memcpy(inl + 1, sqp->header_buf, header_size);
1312 i = 1;
1313 } else {
1314 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1315 memcpy(inl + 1, sqp->header_buf, spc);
1316
1317 inl = (void *) (inl + 1) + spc;
1318 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1319 /*
1320 * Need a barrier here to make sure all the data is
1321 * visible before the byte_count field is set.
1322 * Otherwise the HCA prefetcher could grab the 64-byte
1323 * chunk with this inline segment and get a valid (!=
1324 * 0xffffffff) byte count but stale data, and end up
1325 * generating a packet with bad headers.
1326 *
1327 * The first inline segment's byte_count field doesn't
1328 * need a barrier, because it comes after a
1329 * control/MLX segment and therefore is at an offset
1330 * of 16 mod 64.
1331 */
1332 wmb();
1333 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1334 i = 2;
1335 }
225c7b1f 1336
f438000f
RD		 1337 *mlx_seg_len =
1338 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1339 return 0;
225c7b1f
RD		 1340}
1341
1342static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1343{
1344 unsigned cur;
1345 struct mlx4_ib_cq *cq;
1346
1347 cur = wq->head - wq->tail;
0e6e7416 1348 if (likely(cur + nreq < wq->max_post))
225c7b1f
RD		 1349 return 0;
1350
1351 cq = to_mcq(ib_cq);
1352 spin_lock(&cq->lock);
1353 cur = wq->head - wq->tail;
1354 spin_unlock(&cq->lock);
1355
0e6e7416 1356 return cur + nreq >= wq->max_post;
225c7b1f
RD		 1357}
1358
95d04f07
RD		 1359static __be32 convert_access(int acc)
1360{
1361 return (acc & IB_ACCESS_REMOTE_ATOMIC ? cpu_to_be32(MLX4_WQE_FMR_PERM_ATOMIC) : 0) |
1362 (acc & IB_ACCESS_REMOTE_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_WRITE) : 0) |
1363 (acc & IB_ACCESS_REMOTE_READ ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_READ) : 0) |
1364 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
1365 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
1366}
1367
1368static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
1369{
1370 struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
29bdc883
VS		 1371 int i;
1372
1373 for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
2b6b7d4b 1374 mfrpl->mapped_page_list[i] =
29bdc883
VS		 1375 cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
1376 MLX4_MTT_FLAG_PRESENT);
95d04f07
RD		 1377
1378 fseg->flags = convert_access(wr->wr.fast_reg.access_flags);
1379 fseg->mem_key = cpu_to_be32(wr->wr.fast_reg.rkey);
1380 fseg->buf_list = cpu_to_be64(mfrpl->map);
1381 fseg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1382 fseg->reg_len = cpu_to_be64(wr->wr.fast_reg.length);
1383 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
1384 fseg->page_size = cpu_to_be32(wr->wr.fast_reg.page_shift);
1385 fseg->reserved[0] = 0;
1386 fseg->reserved[1] = 0;
1387}
1388
1389static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
1390{
1391 iseg->flags = 0;
1392 iseg->mem_key = cpu_to_be32(rkey);
1393 iseg->guest_id = 0;
1394 iseg->pa = 0;
1395}
1396
0fbfa6a9
RD		 1397static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1398 u64 remote_addr, u32 rkey)
1399{
1400 rseg->raddr = cpu_to_be64(remote_addr);
1401 rseg->rkey = cpu_to_be32(rkey);
1402 rseg->reserved = 0;
1403}
1404
1405static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1406{
1407 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1408 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1409 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
1410 } else {
1411 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1412 aseg->compare = 0;
1413 }
1414
1415}
1416
1417static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1418 struct ib_send_wr *wr)
1419{
1420 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1421 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1422 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
0fbfa6a9
RD		 1423}
1424
6e694ea3
JM		 1425static void set_mlx_icrc_seg(void *dseg)
1426{
1427 u32 *t = dseg;
1428 struct mlx4_wqe_inline_seg *iseg = dseg;
1429
1430 t[1] = 0;
1431
1432 /*
1433 * Need a barrier here before writing the byte_count field to
1434 * make sure that all the data is visible before the
1435 * byte_count field is set. Otherwise, if the segment begins
1436 * a new cacheline, the HCA prefetcher could grab the 64-byte
1437 * chunk and get a valid (!= * 0xffffffff) byte count but
1438 * stale data, and end up sending the wrong data.
1439 */
1440 wmb();
1441
1442 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1443}
1444
1445static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
d420d9e3 1446{
d420d9e3
RD		 1447 dseg->lkey = cpu_to_be32(sg->lkey);
1448 dseg->addr = cpu_to_be64(sg->addr);
6e694ea3
JM		 1449
1450 /*
1451 * Need a barrier here before writing the byte_count field to
1452 * make sure that all the data is visible before the
1453 * byte_count field is set. Otherwise, if the segment begins
1454 * a new cacheline, the HCA prefetcher could grab the 64-byte
1455 * chunk and get a valid (!= * 0xffffffff) byte count but
1456 * stale data, and end up sending the wrong data.
1457 */
1458 wmb();
1459
1460 dseg->byte_count = cpu_to_be32(sg->length);
d420d9e3
RD		 1461}
1462
2242fa4f
RD		 1463static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1464{
1465 dseg->byte_count = cpu_to_be32(sg->length);
1466 dseg->lkey = cpu_to_be32(sg->lkey);
1467 dseg->addr = cpu_to_be64(sg->addr);
1468}
1469
47b37475 1470static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
0fd7e1d8 1471 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
417608c2 1472 __be32 *lso_hdr_sz, __be32 *blh)
b832be1e
EC		 1473{
1474 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
1475
417608c2
EC		 1476 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
1477 *blh = cpu_to_be32(1 << 6);
b832be1e
EC		 1478
1479 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
1480 wr->num_sge > qp->sq.max_gs - (halign >> 4)))
1481 return -EINVAL;
1482
1483 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
1484
0fd7e1d8
RD		 1485 *lso_hdr_sz = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
1486 wr->wr.ud.hlen);
b832be1e
EC		 1487 *lso_seg_len = halign;
1488 return 0;
1489}
1490
95d04f07
RD		 1491static __be32 send_ieth(struct ib_send_wr *wr)
1492{
1493 switch (wr->opcode) {
1494 case IB_WR_SEND_WITH_IMM:
1495 case IB_WR_RDMA_WRITE_WITH_IMM:
1496 return wr->ex.imm_data;
1497
1498 case IB_WR_SEND_WITH_INV:
1499 return cpu_to_be32(wr->ex.invalidate_rkey);
1500
1501 default:
1502 return 0;
1503 }
1504}
1505
225c7b1f
RD		 1506int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1507 struct ib_send_wr **bad_wr)
1508{
1509 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1510 void *wqe;
1511 struct mlx4_wqe_ctrl_seg *ctrl;
6e694ea3 1512 struct mlx4_wqe_data_seg *dseg;
225c7b1f
RD		 1513 unsigned long flags;
1514 int nreq;
1515 int err = 0;
ea54b10c
JM		 1516 unsigned ind;
1517 int uninitialized_var(stamp);
1518 int uninitialized_var(size);
a3d8e159 1519 unsigned uninitialized_var(seglen);
0fd7e1d8
RD		 1520 __be32 dummy;
1521 __be32 *lso_wqe;
1522 __be32 uninitialized_var(lso_hdr_sz);
417608c2 1523 __be32 blh;
225c7b1f
RD		 1524 int i;
1525
96db0e03 1526 spin_lock_irqsave(&qp->sq.lock, flags);
225c7b1f 1527
ea54b10c 1528 ind = qp->sq_next_wqe;
225c7b1f
RD		 1529
1530 for (nreq = 0; wr; ++nreq, wr = wr->next) {
0fd7e1d8 1531 lso_wqe = &dummy;
417608c2 1532 blh = 0;
0fd7e1d8 1533
225c7b1f
RD		 1534 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1535 err = -ENOMEM;
1536 *bad_wr = wr;
1537 goto out;
1538 }
1539
1540 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1541 err = -EINVAL;
1542 *bad_wr = wr;
1543 goto out;
1544 }
1545
0e6e7416 1546 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
ea54b10c 1547 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
225c7b1f
RD		 1548
1549 ctrl->srcrb_flags =
1550 (wr->send_flags & IB_SEND_SIGNALED ?
1551 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1552 (wr->send_flags & IB_SEND_SOLICITED ?
1553 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
8ff095ec
EC		 1554 ((wr->send_flags & IB_SEND_IP_CSUM) ?
1555 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
1556 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
225c7b1f
RD		 1557 qp->sq_signal_bits;
1558
95d04f07 1559 ctrl->imm = send_ieth(wr);
225c7b1f
RD		 1560
1561 wqe += sizeof *ctrl;
1562 size = sizeof *ctrl / 16;
1563
1564 switch (ibqp->qp_type) {
1565 case IB_QPT_RC:
1566 case IB_QPT_UC:
1567 switch (wr->opcode) {
1568 case IB_WR_ATOMIC_CMP_AND_SWP:
1569 case IB_WR_ATOMIC_FETCH_AND_ADD:
0fbfa6a9
RD		 1570 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1571 wr->wr.atomic.rkey);
225c7b1f
RD		 1572 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1573
0fbfa6a9 1574 set_atomic_seg(wqe, wr);
225c7b1f 1575 wqe += sizeof (struct mlx4_wqe_atomic_seg);
0fbfa6a9 1576
225c7b1f
RD		 1577 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1578 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1579
1580 break;
1581
1582 case IB_WR_RDMA_READ:
1583 case IB_WR_RDMA_WRITE:
1584 case IB_WR_RDMA_WRITE_WITH_IMM:
0fbfa6a9
RD		 1585 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1586 wr->wr.rdma.rkey);
225c7b1f
RD		 1587 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1588 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
225c7b1f 1589 break;
95d04f07
RD		 1590
1591 case IB_WR_LOCAL_INV:
2ac6bf4d
JM		 1592 ctrl->srcrb_flags |=
1593 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 1594 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
1595 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
1596 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
1597 break;
1598
1599 case IB_WR_FAST_REG_MR:
2ac6bf4d
JM		 1600 ctrl->srcrb_flags |=
1601 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
95d04f07
RD		 1602 set_fmr_seg(wqe, wr);
1603 wqe += sizeof (struct mlx4_wqe_fmr_seg);
1604 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
1605 break;
225c7b1f
RD		 1606
1607 default:
1608 /* No extra segments required for sends */
1609 break;
1610 }
1611 break;
1612
1613 case IB_QPT_UD:
0fbfa6a9 1614 set_datagram_seg(wqe, wr);
225c7b1f
RD		 1615 wqe += sizeof (struct mlx4_wqe_datagram_seg);
1616 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
b832be1e
EC		 1617
1618 if (wr->opcode == IB_WR_LSO) {
417608c2 1619 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz, &blh);
b832be1e
EC		 1620 if (unlikely(err)) {
1621 *bad_wr = wr;
1622 goto out;
1623 }
0fd7e1d8 1624 lso_wqe = (__be32 *) wqe;
b832be1e
EC		 1625 wqe += seglen;
1626 size += seglen / 16;
1627 }
225c7b1f
RD		 1628 break;
1629
1630 case IB_QPT_SMI:
1631 case IB_QPT_GSI:
f438000f
RD		 1632 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
1633 if (unlikely(err)) {
225c7b1f
RD		 1634 *bad_wr = wr;
1635 goto out;
1636 }
f438000f
RD		 1637 wqe += seglen;
1638 size += seglen / 16;
225c7b1f
RD		 1639 break;
1640
1641 default:
1642 break;
1643 }
1644
6e694ea3
JM		 1645 /*
1646 * Write data segments in reverse order, so as to
1647 * overwrite cacheline stamp last within each
1648 * cacheline. This avoids issues with WQE
1649 * prefetching.
1650 */
225c7b1f 1651
6e694ea3
JM		 1652 dseg = wqe;
1653 dseg += wr->num_sge - 1;
1654 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
225c7b1f
RD		 1655
1656 /* Add one more inline data segment for ICRC for MLX sends */
6e694ea3
JM		 1657 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1658 qp->ibqp.qp_type == IB_QPT_GSI)) {
1659 set_mlx_icrc_seg(dseg + 1);
225c7b1f
RD		 1660 size += sizeof (struct mlx4_wqe_data_seg) / 16;
1661 }
1662
6e694ea3
JM		 1663 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1664 set_data_seg(dseg, wr->sg_list + i);
1665
0fd7e1d8
RD		 1666 /*
1667 * Possibly overwrite stamping in cacheline with LSO
1668 * segment only after making sure all data segments
1669 * are written.
1670 */
1671 wmb();
1672 *lso_wqe = lso_hdr_sz;
1673
225c7b1f
RD		 1674 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1675 MLX4_WQE_CTRL_FENCE : 0) | size;
1676
1677 /*
1678 * Make sure descriptor is fully written before
1679 * setting ownership bit (because HW can start
1680 * executing as soon as we do).
1681 */
1682 wmb();
1683
59b0ed12 1684 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
225c7b1f
RD		 1685 err = -EINVAL;
1686 goto out;
1687 }
1688
1689 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
417608c2 1690 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
0e6e7416 1691
ea54b10c
JM		 1692 stamp = ind + qp->sq_spare_wqes;
1693 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
1694
0e6e7416
RD		 1695 /*
1696 * We can improve latency by not stamping the last
1697 * send queue WQE until after ringing the doorbell, so
1698 * only stamp here if there are still more WQEs to post.
ea54b10c
JM		 1699 *
1700 * Same optimization applies to padding with NOP wqe
1701 * in case of WQE shrinking (used to prevent wrap-around
1702 * in the middle of WR).
0e6e7416 1703 */
ea54b10c
JM		 1704 if (wr->next) {
1705 stamp_send_wqe(qp, stamp, size * 16);
1706 ind = pad_wraparound(qp, ind);
1707 }
225c7b1f
RD		 1708 }
1709
1710out:
1711 if (likely(nreq)) {
1712 qp->sq.head += nreq;
1713
1714 /*
1715 * Make sure that descriptors are written before
1716 * doorbell record.
1717 */
1718 wmb();
1719
1720 writel(qp->doorbell_qpn,
1721 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1722
1723 /*
1724 * Make sure doorbells don't leak out of SQ spinlock
1725 * and reach the HCA out of order.
1726 */
1727 mmiowb();
0e6e7416 1728
ea54b10c
JM		 1729 stamp_send_wqe(qp, stamp, size * 16);
1730
1731 ind = pad_wraparound(qp, ind);
1732 qp->sq_next_wqe = ind;
225c7b1f
RD		 1733 }
1734
96db0e03 1735 spin_unlock_irqrestore(&qp->sq.lock, flags);
225c7b1f
RD		 1736
1737 return err;
1738}
1739
1740int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1741 struct ib_recv_wr **bad_wr)
1742{
1743 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1744 struct mlx4_wqe_data_seg *scat;
1745 unsigned long flags;
1746 int err = 0;
1747 int nreq;
1748 int ind;
1749 int i;
1750
1751 spin_lock_irqsave(&qp->rq.lock, flags);
1752
0e6e7416 1753 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 1754
1755 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2b946077 1756 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
225c7b1f
RD		 1757 err = -ENOMEM;
1758 *bad_wr = wr;
1759 goto out;
1760 }
1761
1762 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1763 err = -EINVAL;
1764 *bad_wr = wr;
1765 goto out;
1766 }
1767
1768 scat = get_recv_wqe(qp, ind);
1769
2242fa4f
RD		 1770 for (i = 0; i < wr->num_sge; ++i)
1771 __set_data_seg(scat + i, wr->sg_list + i);
225c7b1f
RD		 1772
1773 if (i < qp->rq.max_gs) {
1774 scat[i].byte_count = 0;
1775 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
1776 scat[i].addr = 0;
1777 }
1778
1779 qp->rq.wrid[ind] = wr->wr_id;
1780
0e6e7416 1781 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
225c7b1f
RD		 1782 }
1783
1784out:
1785 if (likely(nreq)) {
1786 qp->rq.head += nreq;
1787
1788 /*
1789 * Make sure that descriptors are written before
1790 * doorbell record.
1791 */
1792 wmb();
1793
1794 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1795 }
1796
1797 spin_unlock_irqrestore(&qp->rq.lock, flags);
1798
1799 return err;
1800}
6a775e2b
JM		 1801
1802static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
1803{
1804 switch (mlx4_state) {
1805 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
1806 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
1807 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
1808 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
1809 case MLX4_QP_STATE_SQ_DRAINING:
1810 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
1811 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
1812 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
1813 default: return -1;
1814 }
1815}
1816
1817static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
1818{
1819 switch (mlx4_mig_state) {
1820 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
1821 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
1822 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
1823 default: return -1;
1824 }
1825}
1826
1827static int to_ib_qp_access_flags(int mlx4_flags)
1828{
1829 int ib_flags = 0;
1830
1831 if (mlx4_flags & MLX4_QP_BIT_RRE)
1832 ib_flags |= IB_ACCESS_REMOTE_READ;
1833 if (mlx4_flags & MLX4_QP_BIT_RWE)
1834 ib_flags |= IB_ACCESS_REMOTE_WRITE;
1835 if (mlx4_flags & MLX4_QP_BIT_RAE)
1836 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
1837
1838 return ib_flags;
1839}
1840
1841static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr,
1842 struct mlx4_qp_path *path)
1843{
8fcea95a 1844 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
6a775e2b
JM		 1845 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
1846
1847 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
1848 return;
1849
1850 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
1851 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
1852 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
1853 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
1854 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
1855 if (ib_ah_attr->ah_flags) {
1856 ib_ah_attr->grh.sgid_index = path->mgid_index;
1857 ib_ah_attr->grh.hop_limit = path->hop_limit;
1858 ib_ah_attr->grh.traffic_class =
1859 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
1860 ib_ah_attr->grh.flow_label =
586bb586 1861 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
6a775e2b
JM		 1862 memcpy(ib_ah_attr->grh.dgid.raw,
1863 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
1864 }
1865}
1866
1867int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1868 struct ib_qp_init_attr *qp_init_attr)
1869{
1870 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1871 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1872 struct mlx4_qp_context context;
1873 int mlx4_state;
0df67030
DB		 1874 int err = 0;
1875
1876 mutex_lock(&qp->mutex);
6a775e2b
JM		 1877
1878 if (qp->state == IB_QPS_RESET) {
1879 qp_attr->qp_state = IB_QPS_RESET;
1880 goto done;
1881 }
1882
1883 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
0df67030
DB		 1884 if (err) {
1885 err = -EINVAL;
1886 goto out;
1887 }
6a775e2b
JM		 1888
1889 mlx4_state = be32_to_cpu(context.flags) >> 28;
1890
0df67030
DB		 1891 qp->state = to_ib_qp_state(mlx4_state);
1892 qp_attr->qp_state = qp->state;
6a775e2b
JM		 1893 qp_attr->path_mtu = context.mtu_msgmax >> 5;
1894 qp_attr->path_mig_state =
1895 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
1896 qp_attr->qkey = be32_to_cpu(context.qkey);
1897 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
1898 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
1899 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
1900 qp_attr->qp_access_flags =
1901 to_ib_qp_access_flags(be32_to_cpu(context.params2));
1902
1903 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
1904 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path);
1905 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path);
1906 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
1907 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
1908 }
1909
1910 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1c27cb71
JM		 1911 if (qp_attr->qp_state == IB_QPS_INIT)
1912 qp_attr->port_num = qp->port;
1913 else
1914 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
6a775e2b
JM		 1915
1916 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1917 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
1918
1919 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
1920
1921 qp_attr->max_dest_rd_atomic =
1922 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
1923 qp_attr->min_rnr_timer =
1924 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
1925 qp_attr->timeout = context.pri_path.ackto >> 3;
1926 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
1927 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
1928 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
1929
1930done:
1931 qp_attr->cur_qp_state = qp_attr->qp_state;
7f5eb9bb
RD		 1932 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
1933 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
1934
6a775e2b 1935 if (!ibqp->uobject) {
7f5eb9bb
RD		 1936 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
1937 qp_attr->cap.max_send_sge = qp->sq.max_gs;
1938 } else {
1939 qp_attr->cap.max_send_wr = 0;
1940 qp_attr->cap.max_send_sge = 0;
6a775e2b
JM		 1941 }
1942
7f5eb9bb
RD		 1943 /*
1944 * We don't support inline sends for kernel QPs (yet), and we
1945 * don't know what userspace's value should be.
1946 */
1947 qp_attr->cap.max_inline_data = 0;
1948
1949 qp_init_attr->cap = qp_attr->cap;
1950
521e575b
RL		 1951 qp_init_attr->create_flags = 0;
1952 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1953 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
1954
1955 if (qp->flags & MLX4_IB_QP_LSO)
1956 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
1957
0df67030
DB		 1958out:
1959 mutex_unlock(&qp->mutex);
1960 return err;
6a775e2b
JM		 1961}
1962
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