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d41d3aeb BS |
1 | #ifndef _IPATH_KERNEL_H |
2 | #define _IPATH_KERNEL_H | |
3 | /* | |
87427da5 | 4 | * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved. |
d41d3aeb BS |
5 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
6 | * | |
7 | * This software is available to you under a choice of one of two | |
8 | * licenses. You may choose to be licensed under the terms of the GNU | |
9 | * General Public License (GPL) Version 2, available from the file | |
10 | * COPYING in the main directory of this source tree, or the | |
11 | * OpenIB.org BSD license below: | |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or | |
14 | * without modification, are permitted provided that the following | |
15 | * conditions are met: | |
16 | * | |
17 | * - Redistributions of source code must retain the above | |
18 | * copyright notice, this list of conditions and the following | |
19 | * disclaimer. | |
20 | * | |
21 | * - Redistributions in binary form must reproduce the above | |
22 | * copyright notice, this list of conditions and the following | |
23 | * disclaimer in the documentation and/or other materials | |
24 | * provided with the distribution. | |
25 | * | |
26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
27 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
28 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
29 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
30 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
31 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
32 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
33 | * SOFTWARE. | |
34 | */ | |
35 | ||
36 | /* | |
37 | * This header file is the base header file for infinipath kernel code | |
38 | * ipath_user.h serves a similar purpose for user code. | |
39 | */ | |
40 | ||
41 | #include <linux/interrupt.h> | |
1fd3b40f BS |
42 | #include <linux/pci.h> |
43 | #include <linux/dma-mapping.h> | |
2c45688f | 44 | #include <linux/mutex.h> |
d41d3aeb | 45 | #include <asm/io.h> |
49739b3e | 46 | #include <rdma/ib_verbs.h> |
d41d3aeb BS |
47 | |
48 | #include "ipath_common.h" | |
49 | #include "ipath_debug.h" | |
50 | #include "ipath_registers.h" | |
51 | ||
52 | /* only s/w major version of InfiniPath we can handle */ | |
53 | #define IPATH_CHIP_VERS_MAJ 2U | |
54 | ||
55 | /* don't care about this except printing */ | |
56 | #define IPATH_CHIP_VERS_MIN 0U | |
57 | ||
58 | /* temporary, maybe always */ | |
59 | extern struct infinipath_stats ipath_stats; | |
60 | ||
61 | #define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ | |
aecd3b5a MA |
62 | /* |
63 | * First-cut critierion for "device is active" is | |
64 | * two thousand dwords combined Tx, Rx traffic per | |
65 | * 5-second interval. SMA packets are 64 dwords, | |
66 | * and occur "a few per second", presumably each way. | |
67 | */ | |
68 | #define IPATH_TRAFFIC_ACTIVE_THRESHOLD (2000) | |
69 | /* | |
70 | * Struct used to indicate which errors are logged in each of the | |
71 | * error-counters that are logged to EEPROM. A counter is incremented | |
72 | * _once_ (saturating at 255) for each event with any bits set in | |
73 | * the error or hwerror register masks below. | |
74 | */ | |
75 | #define IPATH_EEP_LOG_CNT (4) | |
76 | struct ipath_eep_log_mask { | |
77 | u64 errs_to_log; | |
78 | u64 hwerrs_to_log; | |
79 | }; | |
d41d3aeb BS |
80 | |
81 | struct ipath_portdata { | |
82 | void **port_rcvegrbuf; | |
83 | dma_addr_t *port_rcvegrbuf_phys; | |
84 | /* rcvhdrq base, needs mmap before useful */ | |
85 | void *port_rcvhdrq; | |
86 | /* kernel virtual address where hdrqtail is updated */ | |
1fd3b40f | 87 | void *port_rcvhdrtail_kvaddr; |
d41d3aeb BS |
88 | /* |
89 | * temp buffer for expected send setup, allocated at open, instead | |
90 | * of each setup call | |
91 | */ | |
92 | void *port_tid_pg_list; | |
93 | /* when waiting for rcv or pioavail */ | |
94 | wait_queue_head_t port_wait; | |
95 | /* | |
96 | * rcvegr bufs base, physical, must fit | |
97 | * in 44 bits so 32 bit programs mmap64 44 bit works) | |
98 | */ | |
99 | dma_addr_t port_rcvegr_phys; | |
100 | /* mmap of hdrq, must fit in 44 bits */ | |
101 | dma_addr_t port_rcvhdrq_phys; | |
f37bda92 | 102 | dma_addr_t port_rcvhdrqtailaddr_phys; |
d41d3aeb | 103 | /* |
9929b0fb BS |
104 | * number of opens (including slave subports) on this instance |
105 | * (ignoring forks, dup, etc. for now) | |
d41d3aeb BS |
106 | */ |
107 | int port_cnt; | |
108 | /* | |
109 | * how much space to leave at start of eager TID entries for | |
110 | * protocol use, on each TID | |
111 | */ | |
112 | /* instead of calculating it */ | |
113 | unsigned port_port; | |
9929b0fb BS |
114 | /* non-zero if port is being shared. */ |
115 | u16 port_subport_cnt; | |
116 | /* non-zero if port is being shared. */ | |
117 | u16 port_subport_id; | |
d41d3aeb BS |
118 | /* chip offset of PIO buffers for this port */ |
119 | u32 port_piobufs; | |
120 | /* how many alloc_pages() chunks in port_rcvegrbuf_pages */ | |
121 | u32 port_rcvegrbuf_chunks; | |
122 | /* how many egrbufs per chunk */ | |
123 | u32 port_rcvegrbufs_perchunk; | |
124 | /* order for port_rcvegrbuf_pages */ | |
125 | size_t port_rcvegrbuf_size; | |
126 | /* rcvhdrq size (for freeing) */ | |
127 | size_t port_rcvhdrq_size; | |
128 | /* next expected TID to check when looking for free */ | |
129 | u32 port_tidcursor; | |
130 | /* next expected TID to check */ | |
131 | unsigned long port_flag; | |
f2d04231 RW |
132 | /* what happened */ |
133 | unsigned long int_flag; | |
d41d3aeb BS |
134 | /* WAIT_RCV that timed out, no interrupt */ |
135 | u32 port_rcvwait_to; | |
136 | /* WAIT_PIO that timed out, no interrupt */ | |
137 | u32 port_piowait_to; | |
138 | /* WAIT_RCV already happened, no wait */ | |
139 | u32 port_rcvnowait; | |
140 | /* WAIT_PIO already happened, no wait */ | |
141 | u32 port_pionowait; | |
142 | /* total number of rcvhdrqfull errors */ | |
143 | u32 port_hdrqfull; | |
755807a2 DO |
144 | /* |
145 | * Used to suppress multiple instances of same | |
146 | * port staying stuck at same point. | |
147 | */ | |
148 | u32 port_lastrcvhdrqtail; | |
70c51da2 AJ |
149 | /* saved total number of rcvhdrqfull errors for poll edge trigger */ |
150 | u32 port_hdrqfull_poll; | |
151 | /* total number of polled urgent packets */ | |
152 | u32 port_urgent; | |
153 | /* saved total number of polled urgent packets for poll edge trigger */ | |
154 | u32 port_urgent_poll; | |
d41d3aeb BS |
155 | /* pid of process using this port */ |
156 | pid_t port_pid; | |
755807a2 | 157 | pid_t port_subpid[INFINIPATH_MAX_SUBPORT]; |
d41d3aeb BS |
158 | /* same size as task_struct .comm[] */ |
159 | char port_comm[16]; | |
160 | /* pkeys set by this use of this port */ | |
161 | u16 port_pkeys[4]; | |
162 | /* so file ops can get at unit */ | |
163 | struct ipath_devdata *port_dd; | |
9929b0fb BS |
164 | /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */ |
165 | void *subport_uregbase; | |
166 | /* An array of pages for the eager receive buffers * N */ | |
167 | void *subport_rcvegrbuf; | |
168 | /* An array of pages for the eager header queue entries * N */ | |
169 | void *subport_rcvhdr_base; | |
170 | /* The version of the library which opened this port */ | |
171 | u32 userversion; | |
172 | /* Bitmask of active slaves */ | |
173 | u32 active_slaves; | |
f2d04231 RW |
174 | /* Type of packets or conditions we want to poll for */ |
175 | u16 poll_type; | |
c59a80ac RC |
176 | /* port rcvhdrq head offset */ |
177 | u32 port_head; | |
9355fb6a RC |
178 | /* receive packet sequence counter */ |
179 | u32 port_seq_cnt; | |
d41d3aeb BS |
180 | }; |
181 | ||
182 | struct sk_buff; | |
183 | ||
184 | /* | |
185 | * control information for layered drivers | |
186 | */ | |
187 | struct _ipath_layer { | |
188 | void *l_arg; | |
189 | }; | |
190 | ||
1fd3b40f BS |
191 | struct ipath_skbinfo { |
192 | struct sk_buff *skb; | |
193 | dma_addr_t phys; | |
194 | }; | |
195 | ||
c4b4d16e RC |
196 | /* max dwords in small buffer packet */ |
197 | #define IPATH_SMALLBUF_DWORDS (dd->ipath_piosize2k >> 2) | |
198 | ||
c4bce803 DO |
199 | /* |
200 | * Possible IB config parameters for ipath_f_get/set_ib_cfg() | |
201 | */ | |
202 | #define IPATH_IB_CFG_LIDLMC 0 /* Get/set LID (LS16b) and Mask (MS16b) */ | |
203 | #define IPATH_IB_CFG_HRTBT 1 /* Get/set Heartbeat off/enable/auto */ | |
204 | #define IPATH_IB_HRTBT_ON 3 /* Heartbeat enabled, sent every 100msec */ | |
205 | #define IPATH_IB_HRTBT_OFF 0 /* Heartbeat off */ | |
206 | #define IPATH_IB_CFG_LWID_ENB 2 /* Get/set allowed Link-width */ | |
207 | #define IPATH_IB_CFG_LWID 3 /* Get currently active Link-width */ | |
208 | #define IPATH_IB_CFG_SPD_ENB 4 /* Get/set allowed Link speeds */ | |
209 | #define IPATH_IB_CFG_SPD 5 /* Get current Link spd */ | |
210 | #define IPATH_IB_CFG_RXPOL_ENB 6 /* Get/set Auto-RX-polarity enable */ | |
211 | #define IPATH_IB_CFG_LREV_ENB 7 /* Get/set Auto-Lane-reversal enable */ | |
212 | #define IPATH_IB_CFG_LINKLATENCY 8 /* Get Auto-Lane-reversal enable */ | |
213 | ||
214 | ||
d41d3aeb BS |
215 | struct ipath_devdata { |
216 | struct list_head ipath_list; | |
217 | ||
218 | struct ipath_kregs const *ipath_kregs; | |
219 | struct ipath_cregs const *ipath_cregs; | |
220 | ||
221 | /* mem-mapped pointer to base of chip regs */ | |
222 | u64 __iomem *ipath_kregbase; | |
223 | /* end of mem-mapped chip space; range checking */ | |
224 | u64 __iomem *ipath_kregend; | |
225 | /* physical address of chip for io_remap, etc. */ | |
226 | unsigned long ipath_physaddr; | |
227 | /* base of memory alloced for ipath_kregbase, for free */ | |
228 | u64 *ipath_kregalloc; | |
d41d3aeb BS |
229 | /* ipath_cfgports pointers */ |
230 | struct ipath_portdata **ipath_pd; | |
231 | /* sk_buffs used by port 0 eager receive queue */ | |
1fd3b40f | 232 | struct ipath_skbinfo *ipath_port0_skbinfo; |
d41d3aeb BS |
233 | /* kvirt address of 1st 2k pio buffer */ |
234 | void __iomem *ipath_pio2kbase; | |
235 | /* kvirt address of 1st 4k pio buffer */ | |
236 | void __iomem *ipath_pio4kbase; | |
237 | /* | |
238 | * points to area where PIOavail registers will be DMA'ed. | |
239 | * Has to be on a page of it's own, because the page will be | |
240 | * mapped into user program space. This copy is *ONLY* ever | |
241 | * written by DMA, not by the driver! Need a copy per device | |
242 | * when we get to multiple devices | |
243 | */ | |
244 | volatile __le64 *ipath_pioavailregs_dma; | |
245 | /* physical address where updates occur */ | |
246 | dma_addr_t ipath_pioavailregs_phys; | |
247 | struct _ipath_layer ipath_layer; | |
248 | /* setup intr */ | |
249 | int (*ipath_f_intrsetup)(struct ipath_devdata *); | |
c4bce803 DO |
250 | /* fallback to alternate interrupt type if possible */ |
251 | int (*ipath_f_intr_fallback)(struct ipath_devdata *); | |
d41d3aeb BS |
252 | /* setup on-chip bus config */ |
253 | int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *); | |
254 | /* hard reset chip */ | |
255 | int (*ipath_f_reset)(struct ipath_devdata *); | |
256 | int (*ipath_f_get_boardname)(struct ipath_devdata *, char *, | |
257 | size_t); | |
258 | void (*ipath_f_init_hwerrors)(struct ipath_devdata *); | |
259 | void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *, | |
260 | size_t); | |
261 | void (*ipath_f_quiet_serdes)(struct ipath_devdata *); | |
262 | int (*ipath_f_bringup_serdes)(struct ipath_devdata *); | |
263 | int (*ipath_f_early_init)(struct ipath_devdata *); | |
264 | void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned); | |
265 | void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*, | |
266 | u32, unsigned long); | |
267 | void (*ipath_f_tidtemplate)(struct ipath_devdata *); | |
268 | void (*ipath_f_cleanup)(struct ipath_devdata *); | |
269 | void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64); | |
270 | /* fill out chip-specific fields */ | |
271 | int (*ipath_f_get_base_info)(struct ipath_portdata *, void *); | |
51f65ebc BS |
272 | /* free irq */ |
273 | void (*ipath_f_free_irq)(struct ipath_devdata *); | |
c4bce803 DO |
274 | struct ipath_message_header *(*ipath_f_get_msgheader) |
275 | (struct ipath_devdata *, __le32 *); | |
60948a41 | 276 | void (*ipath_f_config_ports)(struct ipath_devdata *, ushort); |
c4bce803 DO |
277 | int (*ipath_f_get_ib_cfg)(struct ipath_devdata *, int); |
278 | int (*ipath_f_set_ib_cfg)(struct ipath_devdata *, int, u32); | |
279 | void (*ipath_f_config_jint)(struct ipath_devdata *, u16 , u16); | |
3029fcc3 | 280 | void (*ipath_f_read_counters)(struct ipath_devdata *, |
c4bce803 DO |
281 | struct infinipath_counters *); |
282 | void (*ipath_f_xgxs_reset)(struct ipath_devdata *); | |
283 | /* per chip actions needed for IB Link up/down changes */ | |
284 | int (*ipath_f_ib_updown)(struct ipath_devdata *, int, u64); | |
285 | ||
9355fb6a | 286 | unsigned ipath_lastegr_idx; |
b1c1b6a3 BS |
287 | struct ipath_ibdev *verbs_dev; |
288 | struct timer_list verbs_timer; | |
d41d3aeb BS |
289 | /* total dwords sent (summed from counter) */ |
290 | u64 ipath_sword; | |
291 | /* total dwords rcvd (summed from counter) */ | |
292 | u64 ipath_rword; | |
293 | /* total packets sent (summed from counter) */ | |
294 | u64 ipath_spkts; | |
295 | /* total packets rcvd (summed from counter) */ | |
296 | u64 ipath_rpkts; | |
297 | /* ipath_statusp initially points to this. */ | |
298 | u64 _ipath_status; | |
299 | /* GUID for this interface, in network order */ | |
300 | __be64 ipath_guid; | |
301 | /* | |
302 | * aggregrate of error bits reported since last cleared, for | |
303 | * limiting of error reporting | |
304 | */ | |
305 | ipath_err_t ipath_lasterror; | |
306 | /* | |
307 | * aggregrate of error bits reported since last cleared, for | |
308 | * limiting of hwerror reporting | |
309 | */ | |
310 | ipath_err_t ipath_lasthwerror; | |
78d1e02f | 311 | /* errors masked because they occur too fast */ |
d41d3aeb | 312 | ipath_err_t ipath_maskederrs; |
72708a0a | 313 | u64 ipath_lastlinkrecov; /* link recoveries at last ACTIVE */ |
d41d3aeb BS |
314 | /* time in jiffies at which to re-enable maskederrs */ |
315 | unsigned long ipath_unmasktime; | |
d41d3aeb BS |
316 | /* count of egrfull errors, combined for all ports */ |
317 | u64 ipath_last_tidfull; | |
318 | /* for ipath_qcheck() */ | |
319 | u64 ipath_lastport0rcv_cnt; | |
320 | /* template for writing TIDs */ | |
321 | u64 ipath_tidtemplate; | |
322 | /* value to write to free TIDs */ | |
323 | u64 ipath_tidinvalid; | |
525d0ca1 | 324 | /* IBA6120 rcv interrupt setup */ |
d41d3aeb BS |
325 | u64 ipath_rhdrhead_intr_off; |
326 | ||
327 | /* size of memory at ipath_kregbase */ | |
328 | u32 ipath_kregsize; | |
329 | /* number of registers used for pioavail */ | |
330 | u32 ipath_pioavregs; | |
331 | /* IPATH_POLL, etc. */ | |
332 | u32 ipath_flags; | |
0fd41363 BS |
333 | /* ipath_flags driver is waiting for */ |
334 | u32 ipath_state_wanted; | |
d41d3aeb BS |
335 | /* last buffer for user use, first buf for kernel use is this |
336 | * index. */ | |
337 | u32 ipath_lastport_piobuf; | |
338 | /* is a stats timer active */ | |
339 | u32 ipath_stats_timer_active; | |
3588423f AJ |
340 | /* number of interrupts for this device -- saturates... */ |
341 | u32 ipath_int_counter; | |
d41d3aeb BS |
342 | /* dwords sent read from counter */ |
343 | u32 ipath_lastsword; | |
344 | /* dwords received read from counter */ | |
345 | u32 ipath_lastrword; | |
346 | /* sent packets read from counter */ | |
347 | u32 ipath_lastspkts; | |
348 | /* received packets read from counter */ | |
349 | u32 ipath_lastrpkts; | |
350 | /* pio bufs allocated per port */ | |
351 | u32 ipath_pbufsport; | |
1d7c2e52 | 352 | u32 ipath_pioupd_thresh; /* update threshold, some chips */ |
d41d3aeb BS |
353 | /* |
354 | * number of ports configured as max; zero is set to number chip | |
355 | * supports, less gives more pio bufs/port, etc. | |
356 | */ | |
357 | u32 ipath_cfgports; | |
d41d3aeb BS |
358 | /* count of port 0 hdrqfull errors */ |
359 | u32 ipath_p0_hdrqfull; | |
60948a41 RC |
360 | /* port 0 number of receive eager buffers */ |
361 | u32 ipath_p0_rcvegrcnt; | |
d41d3aeb | 362 | |
d41d3aeb BS |
363 | /* |
364 | * index of last piobuffer we used. Speeds up searching, by | |
365 | * starting at this point. Doesn't matter if multiple cpu's use and | |
366 | * update, last updater is only write that matters. Whenever it | |
367 | * wraps, we update shadow copies. Need a copy per device when we | |
368 | * get to multiple devices | |
369 | */ | |
370 | u32 ipath_lastpioindex; | |
c4b4d16e | 371 | u32 ipath_lastpioindexl; |
d41d3aeb BS |
372 | /* max length of freezemsg */ |
373 | u32 ipath_freezelen; | |
374 | /* | |
375 | * consecutive times we wanted a PIO buffer but were unable to | |
376 | * get one | |
377 | */ | |
378 | u32 ipath_consec_nopiobuf; | |
379 | /* | |
380 | * hint that we should update ipath_pioavailshadow before | |
381 | * looking for a PIO buffer | |
382 | */ | |
383 | u32 ipath_upd_pio_shadow; | |
384 | /* so we can rewrite it after a chip reset */ | |
385 | u32 ipath_pcibar0; | |
386 | /* so we can rewrite it after a chip reset */ | |
387 | u32 ipath_pcibar1; | |
d41d3aeb | 388 | |
51f65ebc BS |
389 | /* interrupt number */ |
390 | int ipath_irq; | |
d41d3aeb BS |
391 | /* HT/PCI Vendor ID (here for NodeInfo) */ |
392 | u16 ipath_vendorid; | |
393 | /* HT/PCI Device ID (here for NodeInfo) */ | |
394 | u16 ipath_deviceid; | |
395 | /* offset in HT config space of slave/primary interface block */ | |
396 | u8 ipath_ht_slave_off; | |
397 | /* for write combining settings */ | |
398 | unsigned long ipath_wc_cookie; | |
957670a5 BS |
399 | unsigned long ipath_wc_base; |
400 | unsigned long ipath_wc_len; | |
d41d3aeb BS |
401 | /* ref count for each pkey */ |
402 | atomic_t ipath_pkeyrefs[4]; | |
d41d3aeb BS |
403 | /* shadow copy of struct page *'s for exp tid pages */ |
404 | struct page **ipath_pageshadow; | |
1fd3b40f BS |
405 | /* shadow copy of dma handles for exp tid pages */ |
406 | dma_addr_t *ipath_physshadow; | |
c4bce803 | 407 | u64 __iomem *ipath_egrtidbase; |
ddb70c83 DO |
408 | /* lock to workaround chip bug 9437 and others */ |
409 | spinlock_t ipath_kernel_tid_lock; | |
d41d3aeb | 410 | spinlock_t ipath_tid_lock; |
e342c119 | 411 | spinlock_t ipath_sendctrl_lock; |
d41d3aeb BS |
412 | |
413 | /* | |
414 | * IPATH_STATUS_*, | |
415 | * this address is mapped readonly into user processes so they can | |
416 | * get status cheaply, whenever they want. | |
417 | */ | |
418 | u64 *ipath_statusp; | |
419 | /* freeze msg if hw error put chip in freeze */ | |
420 | char *ipath_freezemsg; | |
421 | /* pci access data structure */ | |
422 | struct pci_dev *pcidev; | |
a2acb2ff BS |
423 | struct cdev *user_cdev; |
424 | struct cdev *diag_cdev; | |
425 | struct class_device *user_class_dev; | |
426 | struct class_device *diag_class_dev; | |
d41d3aeb BS |
427 | /* timer used to prevent stats overflow, error throttling, etc. */ |
428 | struct timer_list ipath_stats_timer; | |
35783ec0 BS |
429 | void *ipath_dummy_hdrq; /* used after port close */ |
430 | dma_addr_t ipath_dummy_hdrq_phys; | |
d41d3aeb | 431 | |
a18e26ae RC |
432 | unsigned long ipath_ureg_align; /* user register alignment */ |
433 | ||
58411d1c JG |
434 | /* HoL blocking / user app forward-progress state */ |
435 | unsigned ipath_hol_state; | |
436 | unsigned ipath_hol_next; | |
437 | struct timer_list ipath_hol_timer; | |
438 | ||
d41d3aeb BS |
439 | /* |
440 | * Shadow copies of registers; size indicates read access size. | |
441 | * Most of them are readonly, but some are write-only register, | |
442 | * where we manipulate the bits in the shadow copy, and then write | |
443 | * the shadow copy to infinipath. | |
444 | * | |
445 | * We deliberately make most of these 32 bits, since they have | |
446 | * restricted range. For any that we read, we won't to generate 32 | |
447 | * bit accesses, since Opteron will generate 2 separate 32 bit HT | |
448 | * transactions for a 64 bit read, and we want to avoid unnecessary | |
449 | * HT transactions. | |
450 | */ | |
451 | ||
452 | /* This is the 64 bit group */ | |
453 | ||
454 | /* | |
455 | * shadow of pioavail, check to be sure it's large enough at | |
456 | * init time. | |
457 | */ | |
458 | unsigned long ipath_pioavailshadow[8]; | |
c4b4d16e RC |
459 | /* bitmap of send buffers available for the kernel to use with PIO. */ |
460 | unsigned long ipath_pioavailkernel[8]; | |
d41d3aeb BS |
461 | /* shadow of kr_gpio_out, for rmw ops */ |
462 | u64 ipath_gpio_out; | |
8f140b40 AJ |
463 | /* shadow the gpio mask register */ |
464 | u64 ipath_gpio_mask; | |
17b2eb9f MA |
465 | /* shadow the gpio output enable, etc... */ |
466 | u64 ipath_extctrl; | |
d41d3aeb BS |
467 | /* kr_revision shadow */ |
468 | u64 ipath_revision; | |
469 | /* | |
470 | * shadow of ibcctrl, for interrupt handling of link changes, | |
471 | * etc. | |
472 | */ | |
473 | u64 ipath_ibcctrl; | |
474 | /* | |
475 | * last ibcstatus, to suppress "duplicate" status change messages, | |
476 | * mostly from 2 to 3 | |
477 | */ | |
478 | u64 ipath_lastibcstat; | |
479 | /* hwerrmask shadow */ | |
480 | ipath_err_t ipath_hwerrmask; | |
78d1e02f | 481 | ipath_err_t ipath_errormask; /* errormask shadow */ |
d41d3aeb BS |
482 | /* interrupt config reg shadow */ |
483 | u64 ipath_intconfig; | |
484 | /* kr_sendpiobufbase value */ | |
485 | u64 ipath_piobufbase; | |
486 | ||
487 | /* these are the "32 bit" regs */ | |
488 | ||
489 | /* | |
490 | * number of GUIDs in the flash for this interface; may need some | |
491 | * rethinking for setting on other ifaces | |
492 | */ | |
493 | u32 ipath_nguid; | |
494 | /* | |
495 | * the following two are 32-bit bitmasks, but {test,clear,set}_bit | |
496 | * all expect bit fields to be "unsigned long" | |
497 | */ | |
498 | /* shadow kr_rcvctrl */ | |
499 | unsigned long ipath_rcvctrl; | |
500 | /* shadow kr_sendctrl */ | |
501 | unsigned long ipath_sendctrl; | |
89d1e09b | 502 | unsigned long ipath_lastcancel; /* to not count armlaunch after cancel */ |
d41d3aeb BS |
503 | |
504 | /* value we put in kr_rcvhdrcnt */ | |
505 | u32 ipath_rcvhdrcnt; | |
506 | /* value we put in kr_rcvhdrsize */ | |
507 | u32 ipath_rcvhdrsize; | |
508 | /* value we put in kr_rcvhdrentsize */ | |
509 | u32 ipath_rcvhdrentsize; | |
510 | /* offset of last entry in rcvhdrq */ | |
511 | u32 ipath_hdrqlast; | |
512 | /* kr_portcnt value */ | |
513 | u32 ipath_portcnt; | |
514 | /* kr_pagealign value */ | |
515 | u32 ipath_palign; | |
516 | /* number of "2KB" PIO buffers */ | |
517 | u32 ipath_piobcnt2k; | |
518 | /* size in bytes of "2KB" PIO buffers */ | |
519 | u32 ipath_piosize2k; | |
520 | /* number of "4KB" PIO buffers */ | |
521 | u32 ipath_piobcnt4k; | |
522 | /* size in bytes of "4KB" PIO buffers */ | |
523 | u32 ipath_piosize4k; | |
524 | /* kr_rcvegrbase value */ | |
525 | u32 ipath_rcvegrbase; | |
526 | /* kr_rcvegrcnt value */ | |
527 | u32 ipath_rcvegrcnt; | |
528 | /* kr_rcvtidbase value */ | |
529 | u32 ipath_rcvtidbase; | |
530 | /* kr_rcvtidcnt value */ | |
531 | u32 ipath_rcvtidcnt; | |
532 | /* kr_sendregbase */ | |
533 | u32 ipath_sregbase; | |
534 | /* kr_userregbase */ | |
535 | u32 ipath_uregbase; | |
536 | /* kr_counterregbase */ | |
537 | u32 ipath_cregbase; | |
538 | /* shadow the control register contents */ | |
539 | u32 ipath_control; | |
d41d3aeb BS |
540 | /* PCI revision register (HTC rev on FPGA) */ |
541 | u32 ipath_pcirev; | |
542 | ||
543 | /* chip address space used by 4k pio buffers */ | |
544 | u32 ipath_4kalign; | |
545 | /* The MTU programmed for this unit */ | |
546 | u32 ipath_ibmtu; | |
547 | /* | |
548 | * The max size IB packet, included IB headers that we can send. | |
549 | * Starts same as ipath_piosize, but is affected when ibmtu is | |
550 | * changed, or by size of eager buffers | |
551 | */ | |
552 | u32 ipath_ibmaxlen; | |
553 | /* | |
554 | * ibmaxlen at init time, limited by chip and by receive buffer | |
555 | * size. Not changed after init. | |
556 | */ | |
557 | u32 ipath_init_ibmaxlen; | |
558 | /* size of each rcvegrbuffer */ | |
559 | u32 ipath_rcvegrbufsize; | |
6ca2abf4 AJ |
560 | /* localbus width (1, 2,4,8,16,32) from config space */ |
561 | u32 ipath_lbus_width; | |
562 | /* localbus speed (HT: 200,400,800,1000; PCIe 2500) */ | |
563 | u32 ipath_lbus_speed; | |
d41d3aeb BS |
564 | /* |
565 | * number of sequential ibcstatus change for polling active/quiet | |
566 | * (i.e., link not coming up). | |
567 | */ | |
568 | u32 ipath_ibpollcnt; | |
569 | /* low and high portions of MSI capability/vector */ | |
570 | u32 ipath_msi_lo; | |
571 | /* saved after PCIe init for restore after reset */ | |
572 | u32 ipath_msi_hi; | |
573 | /* MSI data (vector) saved for restore */ | |
574 | u16 ipath_msi_data; | |
575 | /* MLID programmed for this instance */ | |
576 | u16 ipath_mlid; | |
577 | /* LID programmed for this instance */ | |
578 | u16 ipath_lid; | |
579 | /* list of pkeys programmed; 0 if not set */ | |
580 | u16 ipath_pkeys[4]; | |
8307c28e BS |
581 | /* |
582 | * ASCII serial number, from flash, large enough for original | |
583 | * all digit strings, and longer QLogic serial number format | |
584 | */ | |
585 | u8 ipath_serial[16]; | |
d41d3aeb BS |
586 | /* human readable board version */ |
587 | u8 ipath_boardversion[80]; | |
6ca2abf4 | 588 | u8 ipath_lbus_info[32]; /* human readable localbus info */ |
d41d3aeb BS |
589 | /* chip major rev, from ipath_revision */ |
590 | u8 ipath_majrev; | |
591 | /* chip minor rev, from ipath_revision */ | |
592 | u8 ipath_minrev; | |
593 | /* board rev, from ipath_revision */ | |
594 | u8 ipath_boardrev; | |
d41d3aeb BS |
595 | /* saved for restore after reset */ |
596 | u8 ipath_pci_cacheline; | |
597 | /* LID mask control */ | |
598 | u8 ipath_lmc; | |
c4bce803 DO |
599 | /* link width supported */ |
600 | u8 ipath_link_width_supported; | |
601 | /* link speed supported */ | |
602 | u8 ipath_link_speed_supported; | |
603 | u8 ipath_link_width_enabled; | |
604 | u8 ipath_link_speed_enabled; | |
605 | u8 ipath_link_width_active; | |
606 | u8 ipath_link_speed_active; | |
30fc5c31 BS |
607 | /* Rx Polarity inversion (compensate for ~tx on partner) */ |
608 | u8 ipath_rx_pol_inv; | |
fba75200 | 609 | |
9355fb6a RC |
610 | u8 ipath_r_portenable_shift; |
611 | u8 ipath_r_intravail_shift; | |
612 | u8 ipath_r_tailupd_shift; | |
613 | u8 ipath_r_portcfg_shift; | |
614 | ||
615 | /* unit # of this chip, if present */ | |
616 | int ipath_unit; | |
617 | ||
fba75200 BS |
618 | /* local link integrity counter */ |
619 | u32 ipath_lli_counter; | |
620 | /* local link integrity errors */ | |
621 | u32 ipath_lli_errors; | |
2c9446a1 BS |
622 | /* |
623 | * Above counts only cases where _successive_ LocalLinkIntegrity | |
624 | * errors were seen in the receive headers of kern-packets. | |
625 | * Below are the three (monotonically increasing) counters | |
626 | * maintained via GPIO interrupts on iba6120-rev2. | |
627 | */ | |
628 | u32 ipath_rxfc_unsupvl_errs; | |
629 | u32 ipath_overrun_thresh_errs; | |
630 | u32 ipath_lli_errs; | |
f62fe77a | 631 | |
3588423f AJ |
632 | /* status check work */ |
633 | struct delayed_work status_work; | |
634 | ||
f62fe77a BS |
635 | /* |
636 | * Not all devices managed by a driver instance are the same | |
637 | * type, so these fields must be per-device. | |
638 | */ | |
639 | u64 ipath_i_bitsextant; | |
640 | ipath_err_t ipath_e_bitsextant; | |
641 | ipath_err_t ipath_hwe_bitsextant; | |
642 | ||
643 | /* | |
644 | * Below should be computable from number of ports, | |
645 | * since they are never modified. | |
646 | */ | |
9355fb6a RC |
647 | u64 ipath_i_rcvavail_mask; |
648 | u64 ipath_i_rcvurg_mask; | |
c4bce803 DO |
649 | u16 ipath_i_rcvurg_shift; |
650 | u16 ipath_i_rcvavail_shift; | |
f62fe77a BS |
651 | |
652 | /* | |
653 | * Register bits for selecting i2c direction and values, used for | |
654 | * I2C serial flash. | |
655 | */ | |
d84e0b28 MA |
656 | u8 ipath_gpio_sda_num; |
657 | u8 ipath_gpio_scl_num; | |
658 | u8 ipath_i2c_chain_type; | |
f62fe77a BS |
659 | u64 ipath_gpio_sda; |
660 | u64 ipath_gpio_scl; | |
82466f00 | 661 | |
17b2eb9f MA |
662 | /* lock for doing RMW of shadows/regs for ExtCtrl and GPIO */ |
663 | spinlock_t ipath_gpio_lock; | |
664 | ||
c4bce803 DO |
665 | /* |
666 | * IB link and linktraining states and masks that vary per chip in | |
667 | * some way. Set at init, to avoid each IB status change interrupt | |
668 | */ | |
669 | u8 ibcs_ls_shift; | |
670 | u8 ibcs_lts_mask; | |
671 | u32 ibcs_mask; | |
672 | u32 ib_init; | |
673 | u32 ib_arm; | |
674 | u32 ib_active; | |
675 | ||
676 | u16 ipath_rhf_offset; /* offset of RHF within receive header entry */ | |
677 | ||
678 | /* | |
679 | * shift/mask for linkcmd, linkinitcmd, maxpktlen in ibccontol | |
680 | * reg. Changes for IBA7220 | |
681 | */ | |
682 | u8 ibcc_lic_mask; /* LinkInitCmd */ | |
683 | u8 ibcc_lc_shift; /* LinkCmd */ | |
684 | u8 ibcc_mpl_shift; /* Maxpktlen */ | |
685 | ||
686 | u8 delay_mult; | |
687 | ||
82466f00 MA |
688 | /* used to override LED behavior */ |
689 | u8 ipath_led_override; /* Substituted for normal value, if non-zero */ | |
690 | u16 ipath_led_override_timeoff; /* delta to next timer event */ | |
691 | u8 ipath_led_override_vals[2]; /* Alternates per blink-frame */ | |
692 | u8 ipath_led_override_phase; /* Just counts, LSB picks from vals[] */ | |
693 | atomic_t ipath_led_override_timer_active; | |
694 | /* Used to flash LEDs in override mode */ | |
695 | struct timer_list ipath_led_override_timer; | |
696 | ||
aecd3b5a MA |
697 | /* Support (including locks) for EEPROM logging of errors and time */ |
698 | /* control access to actual counters, timer */ | |
699 | spinlock_t ipath_eep_st_lock; | |
700 | /* control high-level access to EEPROM */ | |
2c45688f | 701 | struct mutex ipath_eep_lock; |
aecd3b5a MA |
702 | /* Below inc'd by ipath_snap_cntrs(), locked by ipath_eep_st_lock */ |
703 | uint64_t ipath_traffic_wds; | |
704 | /* active time is kept in seconds, but logged in hours */ | |
705 | atomic_t ipath_active_time; | |
706 | /* Below are nominal shadow of EEPROM, new since last EEPROM update */ | |
707 | uint8_t ipath_eep_st_errs[IPATH_EEP_LOG_CNT]; | |
708 | uint8_t ipath_eep_st_new_errs[IPATH_EEP_LOG_CNT]; | |
709 | uint16_t ipath_eep_hrs; | |
710 | /* | |
711 | * masks for which bits of errs, hwerrs that cause | |
712 | * each of the counters to increment. | |
713 | */ | |
714 | struct ipath_eep_log_mask ipath_eep_st_masks[IPATH_EEP_LOG_CNT]; | |
c4bce803 DO |
715 | |
716 | /* interrupt mitigation reload register info */ | |
717 | u16 ipath_jint_idle_ticks; /* idle clock ticks */ | |
718 | u16 ipath_jint_max_packets; /* max packets across all ports */ | |
d41d3aeb BS |
719 | }; |
720 | ||
58411d1c JG |
721 | /* ipath_hol_state values (stopping/starting user proc, send flushing) */ |
722 | #define IPATH_HOL_UP 0 | |
723 | #define IPATH_HOL_DOWN 1 | |
724 | /* ipath_hol_next toggle values, used when hol_state IPATH_HOL_DOWN */ | |
725 | #define IPATH_HOL_DOWNSTOP 0 | |
726 | #define IPATH_HOL_DOWNCONT 1 | |
727 | ||
9929b0fb BS |
728 | /* Private data for file operations */ |
729 | struct ipath_filedata { | |
730 | struct ipath_portdata *pd; | |
731 | unsigned subport; | |
732 | unsigned tidcursor; | |
733 | }; | |
d41d3aeb BS |
734 | extern struct list_head ipath_dev_list; |
735 | extern spinlock_t ipath_devs_lock; | |
736 | extern struct ipath_devdata *ipath_lookup(int unit); | |
737 | ||
d41d3aeb BS |
738 | int ipath_init_chip(struct ipath_devdata *, int); |
739 | int ipath_enable_wc(struct ipath_devdata *dd); | |
740 | void ipath_disable_wc(struct ipath_devdata *dd); | |
6ef6aee2 | 741 | int ipath_count_units(int *npresentp, int *nupp, int *maxportsp); |
d41d3aeb | 742 | void ipath_shutdown_device(struct ipath_devdata *); |
0f4fc5eb | 743 | void ipath_clear_freeze(struct ipath_devdata *); |
d41d3aeb BS |
744 | |
745 | struct file_operations; | |
2b8693c0 | 746 | int ipath_cdev_init(int minor, char *name, const struct file_operations *fops, |
d41d3aeb BS |
747 | struct cdev **cdevp, struct class_device **class_devp); |
748 | void ipath_cdev_cleanup(struct cdev **cdevp, | |
749 | struct class_device **class_devp); | |
750 | ||
a2acb2ff BS |
751 | int ipath_diag_add(struct ipath_devdata *); |
752 | void ipath_diag_remove(struct ipath_devdata *); | |
d41d3aeb | 753 | |
0fd41363 | 754 | extern wait_queue_head_t ipath_state_wait; |
d41d3aeb BS |
755 | |
756 | int ipath_user_add(struct ipath_devdata *dd); | |
a2acb2ff | 757 | void ipath_user_remove(struct ipath_devdata *dd); |
d41d3aeb BS |
758 | |
759 | struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t); | |
760 | ||
761 | extern int ipath_diag_inuse; | |
762 | ||
7d12e780 | 763 | irqreturn_t ipath_intr(int irq, void *devid); |
8ec1077b | 764 | int ipath_decode_err(char *buf, size_t blen, ipath_err_t err); |
d41d3aeb BS |
765 | #if __IPATH_INFO || __IPATH_DBG |
766 | extern const char *ipath_ibcstatus_str[]; | |
767 | #endif | |
768 | ||
769 | /* clean up any per-chip chip-specific stuff */ | |
770 | void ipath_chip_cleanup(struct ipath_devdata *); | |
771 | /* clean up any chip type-specific stuff */ | |
772 | void ipath_chip_done(void); | |
773 | ||
774 | /* check to see if we have to force ordering for write combining */ | |
775 | int ipath_unordered_wc(void); | |
776 | ||
777 | void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first, | |
778 | unsigned cnt); | |
3810f2a8 | 779 | void ipath_cancel_sends(struct ipath_devdata *, int); |
d41d3aeb BS |
780 | |
781 | int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *); | |
f37bda92 | 782 | void ipath_free_pddata(struct ipath_devdata *, struct ipath_portdata *); |
d41d3aeb BS |
783 | |
784 | int ipath_parse_ushort(const char *str, unsigned short *valp); | |
785 | ||
c59a80ac | 786 | void ipath_kreceive(struct ipath_portdata *); |
d41d3aeb BS |
787 | int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned); |
788 | int ipath_reset_device(int); | |
789 | void ipath_get_faststats(unsigned long); | |
140277e9 | 790 | int ipath_wait_linkstate(struct ipath_devdata *, u32, int); |
34b2aafe BS |
791 | int ipath_set_linkstate(struct ipath_devdata *, u8); |
792 | int ipath_set_mtu(struct ipath_devdata *, u16); | |
793 | int ipath_set_lid(struct ipath_devdata *, u32, u8); | |
30fc5c31 | 794 | int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv); |
6ac50727 DO |
795 | void ipath_enable_armlaunch(struct ipath_devdata *); |
796 | void ipath_disable_armlaunch(struct ipath_devdata *); | |
58411d1c JG |
797 | void ipath_hol_down(struct ipath_devdata *); |
798 | void ipath_hol_up(struct ipath_devdata *); | |
799 | void ipath_hol_event(unsigned long); | |
d41d3aeb BS |
800 | |
801 | /* for use in system calls, where we want to know device type, etc. */ | |
9929b0fb BS |
802 | #define port_fp(fp) ((struct ipath_filedata *)(fp)->private_data)->pd |
803 | #define subport_fp(fp) \ | |
804 | ((struct ipath_filedata *)(fp)->private_data)->subport | |
805 | #define tidcursor_fp(fp) \ | |
806 | ((struct ipath_filedata *)(fp)->private_data)->tidcursor | |
d41d3aeb BS |
807 | |
808 | /* | |
809 | * values for ipath_flags | |
810 | */ | |
a51a2513 RC |
811 | /* chip can report link latency (IB 1.2) */ |
812 | #define IPATH_HAS_LINK_LATENCY 0x1 | |
2ba3f56e | 813 | /* The chip is up and initted */ |
d41d3aeb BS |
814 | #define IPATH_INITTED 0x2 |
815 | /* set if any user code has set kr_rcvhdrsize */ | |
816 | #define IPATH_RCVHDRSZ_SET 0x4 | |
817 | /* The chip is present and valid for accesses */ | |
818 | #define IPATH_PRESENT 0x8 | |
819 | /* HT link0 is only 8 bits wide, ignore upper byte crc | |
820 | * errors, etc. */ | |
821 | #define IPATH_8BIT_IN_HT0 0x10 | |
822 | /* HT link1 is only 8 bits wide, ignore upper byte crc | |
823 | * errors, etc. */ | |
824 | #define IPATH_8BIT_IN_HT1 0x20 | |
825 | /* The link is down */ | |
826 | #define IPATH_LINKDOWN 0x40 | |
827 | /* The link level is up (0x11) */ | |
828 | #define IPATH_LINKINIT 0x80 | |
829 | /* The link is in the armed (0x21) state */ | |
830 | #define IPATH_LINKARMED 0x100 | |
831 | /* The link is in the active (0x31) state */ | |
832 | #define IPATH_LINKACTIVE 0x200 | |
833 | /* link current state is unknown */ | |
834 | #define IPATH_LINKUNK 0x400 | |
210d6ca3 RC |
835 | /* Write combining flush needed for PIO */ |
836 | #define IPATH_PIO_FLUSH_WC 0x1000 | |
9355fb6a RC |
837 | /* DMA Receive tail pointer */ |
838 | #define IPATH_NODMA_RTAIL 0x2000 | |
d41d3aeb BS |
839 | /* no IB cable, or no device on IB cable */ |
840 | #define IPATH_NOCABLE 0x4000 | |
841 | /* Supports port zero per packet receive interrupts via | |
842 | * GPIO */ | |
843 | #define IPATH_GPIO_INTR 0x8000 | |
844 | /* uses the coded 4byte TID, not 8 byte */ | |
845 | #define IPATH_4BYTE_TID 0x10000 | |
846 | /* packet/word counters are 32 bit, else those 4 counters | |
847 | * are 64bit */ | |
848 | #define IPATH_32BITCOUNTERS 0x20000 | |
7da0498e AJ |
849 | /* Interrupt register is 64 bits */ |
850 | #define IPATH_INTREG_64 0x40000 | |
9355fb6a | 851 | /* can miss port0 rx interrupts */ |
d41d3aeb | 852 | #define IPATH_DISABLED 0x80000 /* administratively disabled */ |
2c9446a1 BS |
853 | /* Use GPIO interrupts for new counters */ |
854 | #define IPATH_GPIO_ERRINTRS 0x100000 | |
4ea61b54 | 855 | #define IPATH_SWAP_PIOBUFS 0x200000 |
359193ef MA |
856 | /* Suppress heartbeat, even if turning off loopback */ |
857 | #define IPATH_NO_HRTBT 0x1000000 | |
858 | #define IPATH_HAS_MULT_IB_SPEED 0x8000000 | |
4330e4da MA |
859 | /* Linkdown-disable intentionally, Do not attempt to bring up */ |
860 | #define IPATH_IB_LINK_DISABLED 0x40000000 | |
58411d1c | 861 | #define IPATH_IB_FORCE_NOTIFY 0x80000000 /* force notify on next ib change */ |
2c9446a1 BS |
862 | |
863 | /* Bits in GPIO for the added interrupts */ | |
864 | #define IPATH_GPIO_PORT0_BIT 2 | |
865 | #define IPATH_GPIO_RXUVL_BIT 3 | |
866 | #define IPATH_GPIO_OVRUN_BIT 4 | |
867 | #define IPATH_GPIO_LLI_BIT 5 | |
868 | #define IPATH_GPIO_ERRINTR_MASK 0x38 | |
d41d3aeb BS |
869 | |
870 | /* portdata flag bit offsets */ | |
871 | /* waiting for a packet to arrive */ | |
872 | #define IPATH_PORT_WAITING_RCV 2 | |
947d7617 RC |
873 | /* master has not finished initializing */ |
874 | #define IPATH_PORT_MASTER_UNINIT 4 | |
f2d04231 RW |
875 | /* waiting for an urgent packet to arrive */ |
876 | #define IPATH_PORT_WAITING_URG 5 | |
d41d3aeb BS |
877 | |
878 | /* free up any allocated data at closes */ | |
879 | void ipath_free_data(struct ipath_portdata *dd); | |
c4b4d16e RC |
880 | u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32, u32 *); |
881 | void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start, | |
882 | unsigned len, int avail); | |
525d0ca1 BS |
883 | void ipath_init_iba6120_funcs(struct ipath_devdata *); |
884 | void ipath_init_iba6110_funcs(struct ipath_devdata *); | |
f2080fa3 | 885 | void ipath_get_eeprom_info(struct ipath_devdata *); |
aecd3b5a MA |
886 | int ipath_update_eeprom_log(struct ipath_devdata *dd); |
887 | void ipath_inc_eeprom_err(struct ipath_devdata *dd, u32 eidx, u32 incr); | |
d41d3aeb | 888 | u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg); |
c4b4d16e | 889 | void ipath_force_pio_avail_update(struct ipath_devdata *); |
49739b3e | 890 | void signal_ib_event(struct ipath_devdata *dd, enum ib_event_type ev); |
d41d3aeb | 891 | |
82466f00 MA |
892 | /* |
893 | * Set LED override, only the two LSBs have "public" meaning, but | |
894 | * any non-zero value substitutes them for the Link and LinkTrain | |
895 | * LED states. | |
896 | */ | |
897 | #define IPATH_LED_PHYS 1 /* Physical (linktraining) GREEN LED */ | |
898 | #define IPATH_LED_LOG 2 /* Logical (link) YELLOW LED */ | |
899 | void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val); | |
900 | ||
d41d3aeb BS |
901 | /* |
902 | * number of words used for protocol header if not set by ipath_userinit(); | |
903 | */ | |
904 | #define IPATH_DFLT_RCVHDRSIZE 9 | |
905 | ||
d41d3aeb | 906 | int ipath_get_user_pages(unsigned long, size_t, struct page **); |
d41d3aeb BS |
907 | void ipath_release_user_pages(struct page **, size_t); |
908 | void ipath_release_user_pages_on_close(struct page **, size_t); | |
909 | int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int); | |
910 | int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int); | |
d84e0b28 MA |
911 | int ipath_tempsense_read(struct ipath_devdata *, u8 regnum); |
912 | int ipath_tempsense_write(struct ipath_devdata *, u8 regnum, u8 data); | |
d41d3aeb BS |
913 | |
914 | /* these are used for the registers that vary with port */ | |
915 | void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg, | |
916 | unsigned, u64); | |
d41d3aeb BS |
917 | |
918 | /* | |
919 | * We could have a single register get/put routine, that takes a group type, | |
920 | * but this is somewhat clearer and cleaner. It also gives us some error | |
921 | * checking. 64 bit register reads should always work, but are inefficient | |
922 | * on opteron (the northbridge always generates 2 separate HT 32 bit reads), | |
923 | * so we use kreg32 wherever possible. User register and counter register | |
924 | * reads are always 32 bit reads, so only one form of those routines. | |
925 | */ | |
926 | ||
927 | /* | |
928 | * At the moment, none of the s-registers are writable, so no | |
929 | * ipath_write_sreg(), and none of the c-registers are writable, so no | |
930 | * ipath_write_creg(). | |
931 | */ | |
932 | ||
933 | /** | |
934 | * ipath_read_ureg32 - read 32-bit virtualized per-port register | |
935 | * @dd: device | |
936 | * @regno: register number | |
937 | * @port: port number | |
938 | * | |
939 | * Return the contents of a register that is virtualized to be per port. | |
685f97e8 BS |
940 | * Returns -1 on errors (not distinguishable from valid contents at |
941 | * runtime; we may add a separate error variable at some point). | |
d41d3aeb BS |
942 | */ |
943 | static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd, | |
944 | ipath_ureg regno, int port) | |
945 | { | |
c71c30dc | 946 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
947 | return 0; |
948 | ||
949 | return readl(regno + (u64 __iomem *) | |
950 | (dd->ipath_uregbase + | |
951 | (char __iomem *)dd->ipath_kregbase + | |
a18e26ae | 952 | dd->ipath_ureg_align * port)); |
d41d3aeb BS |
953 | } |
954 | ||
955 | /** | |
956 | * ipath_write_ureg - write 32-bit virtualized per-port register | |
957 | * @dd: device | |
958 | * @regno: register number | |
959 | * @value: value | |
960 | * @port: port | |
961 | * | |
962 | * Write the contents of a register that is virtualized to be per port. | |
963 | */ | |
964 | static inline void ipath_write_ureg(const struct ipath_devdata *dd, | |
965 | ipath_ureg regno, u64 value, int port) | |
966 | { | |
967 | u64 __iomem *ubase = (u64 __iomem *) | |
968 | (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase + | |
a18e26ae | 969 | dd->ipath_ureg_align * port); |
d41d3aeb BS |
970 | if (dd->ipath_kregbase) |
971 | writeq(value, &ubase[regno]); | |
972 | } | |
973 | ||
974 | static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd, | |
975 | ipath_kreg regno) | |
976 | { | |
c71c30dc | 977 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
978 | return -1; |
979 | return readl((u32 __iomem *) & dd->ipath_kregbase[regno]); | |
980 | } | |
981 | ||
982 | static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd, | |
983 | ipath_kreg regno) | |
984 | { | |
c71c30dc | 985 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
986 | return -1; |
987 | ||
988 | return readq(&dd->ipath_kregbase[regno]); | |
989 | } | |
990 | ||
991 | static inline void ipath_write_kreg(const struct ipath_devdata *dd, | |
992 | ipath_kreg regno, u64 value) | |
993 | { | |
994 | if (dd->ipath_kregbase) | |
995 | writeq(value, &dd->ipath_kregbase[regno]); | |
996 | } | |
997 | ||
998 | static inline u64 ipath_read_creg(const struct ipath_devdata *dd, | |
999 | ipath_sreg regno) | |
1000 | { | |
c71c30dc | 1001 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
1002 | return 0; |
1003 | ||
1004 | return readq(regno + (u64 __iomem *) | |
1005 | (dd->ipath_cregbase + | |
1006 | (char __iomem *)dd->ipath_kregbase)); | |
1007 | } | |
1008 | ||
1009 | static inline u32 ipath_read_creg32(const struct ipath_devdata *dd, | |
1010 | ipath_sreg regno) | |
1011 | { | |
c71c30dc | 1012 | if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) |
d41d3aeb BS |
1013 | return 0; |
1014 | return readl(regno + (u64 __iomem *) | |
1015 | (dd->ipath_cregbase + | |
1016 | (char __iomem *)dd->ipath_kregbase)); | |
1017 | } | |
1018 | ||
6c719cae RC |
1019 | static inline void ipath_write_creg(const struct ipath_devdata *dd, |
1020 | ipath_creg regno, u64 value) | |
1021 | { | |
1022 | if (dd->ipath_kregbase) | |
1023 | writeq(value, regno + (u64 __iomem *) | |
1024 | (dd->ipath_cregbase + | |
1025 | (char __iomem *)dd->ipath_kregbase)); | |
1026 | } | |
1027 | ||
c59a80ac RC |
1028 | static inline void ipath_clear_rcvhdrtail(const struct ipath_portdata *pd) |
1029 | { | |
1030 | *((u64 *) pd->port_rcvhdrtail_kvaddr) = 0ULL; | |
1031 | } | |
1032 | ||
1033 | static inline u32 ipath_get_rcvhdrtail(const struct ipath_portdata *pd) | |
1034 | { | |
1035 | return (u32) le64_to_cpu(*((volatile __le64 *) | |
1036 | pd->port_rcvhdrtail_kvaddr)); | |
1037 | } | |
1038 | ||
9355fb6a RC |
1039 | static inline u32 ipath_get_hdrqtail(const struct ipath_portdata *pd) |
1040 | { | |
1041 | const struct ipath_devdata *dd = pd->port_dd; | |
1042 | u32 hdrqtail; | |
1043 | ||
1044 | if (dd->ipath_flags & IPATH_NODMA_RTAIL) { | |
1045 | __le32 *rhf_addr; | |
1046 | u32 seq; | |
1047 | ||
1048 | rhf_addr = (__le32 *) pd->port_rcvhdrq + | |
1049 | pd->port_head + dd->ipath_rhf_offset; | |
1050 | seq = ipath_hdrget_seq(rhf_addr); | |
1051 | hdrqtail = pd->port_head; | |
1052 | if (seq == pd->port_seq_cnt) | |
1053 | hdrqtail++; | |
1054 | } else | |
1055 | hdrqtail = ipath_get_rcvhdrtail(pd); | |
1056 | ||
1057 | return hdrqtail; | |
1058 | } | |
1059 | ||
7da0498e AJ |
1060 | static inline u64 ipath_read_ireg(const struct ipath_devdata *dd, ipath_kreg r) |
1061 | { | |
1062 | return (dd->ipath_flags & IPATH_INTREG_64) ? | |
1063 | ipath_read_kreg64(dd, r) : ipath_read_kreg32(dd, r); | |
1064 | } | |
1065 | ||
c4bce803 DO |
1066 | /* |
1067 | * from contents of IBCStatus (or a saved copy), return linkstate | |
1068 | * Report ACTIVE_DEFER as ACTIVE, because we treat them the same | |
1069 | * everywhere, anyway (and should be, for almost all purposes). | |
1070 | */ | |
1071 | static inline u32 ipath_ib_linkstate(struct ipath_devdata *dd, u64 ibcs) | |
1072 | { | |
1073 | u32 state = (u32)(ibcs >> dd->ibcs_ls_shift) & | |
1074 | INFINIPATH_IBCS_LINKSTATE_MASK; | |
1075 | if (state == INFINIPATH_IBCS_L_STATE_ACT_DEFER) | |
1076 | state = INFINIPATH_IBCS_L_STATE_ACTIVE; | |
1077 | return state; | |
1078 | } | |
1079 | ||
1080 | /* from contents of IBCStatus (or a saved copy), return linktrainingstate */ | |
1081 | static inline u32 ipath_ib_linktrstate(struct ipath_devdata *dd, u64 ibcs) | |
1082 | { | |
1083 | return (u32)(ibcs >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) & | |
1084 | dd->ibcs_lts_mask; | |
1085 | } | |
1086 | ||
58411d1c JG |
1087 | /* |
1088 | * from contents of IBCStatus (or a saved copy), return logical link state | |
1089 | * combination of link state and linktraining state (down, active, init, | |
1090 | * arm, etc. | |
1091 | */ | |
1092 | static inline u32 ipath_ib_state(struct ipath_devdata *dd, u64 ibcs) | |
1093 | { | |
1094 | u32 ibs; | |
1095 | ibs = (u32)(ibcs >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) & | |
1096 | dd->ibcs_lts_mask; | |
1097 | ibs |= (u32)(ibcs & | |
1098 | (INFINIPATH_IBCS_LINKSTATE_MASK << dd->ibcs_ls_shift)); | |
1099 | return ibs; | |
1100 | } | |
1101 | ||
d41d3aeb BS |
1102 | /* |
1103 | * sysfs interface. | |
1104 | */ | |
1105 | ||
1106 | struct device_driver; | |
1107 | ||
b55f4f06 | 1108 | extern const char ib_ipath_version[]; |
d41d3aeb | 1109 | |
23b9c1ab | 1110 | extern struct attribute_group *ipath_driver_attr_groups[]; |
d41d3aeb BS |
1111 | |
1112 | int ipath_device_create_group(struct device *, struct ipath_devdata *); | |
1113 | void ipath_device_remove_group(struct device *, struct ipath_devdata *); | |
1114 | int ipath_expose_reset(struct device *); | |
1115 | ||
1116 | int ipath_init_ipathfs(void); | |
1117 | void ipath_exit_ipathfs(void); | |
1118 | int ipathfs_add_device(struct ipath_devdata *); | |
1119 | int ipathfs_remove_device(struct ipath_devdata *); | |
1120 | ||
1fd3b40f BS |
1121 | /* |
1122 | * dma_addr wrappers - all 0's invalid for hw | |
1123 | */ | |
1124 | dma_addr_t ipath_map_page(struct pci_dev *, struct page *, unsigned long, | |
1125 | size_t, int); | |
1126 | dma_addr_t ipath_map_single(struct pci_dev *, void *, size_t, int); | |
1127 | ||
d41d3aeb BS |
1128 | /* |
1129 | * Flush write combining store buffers (if present) and perform a write | |
1130 | * barrier. | |
1131 | */ | |
1132 | #if defined(CONFIG_X86_64) | |
1133 | #define ipath_flush_wc() asm volatile("sfence" ::: "memory") | |
1134 | #else | |
1135 | #define ipath_flush_wc() wmb() | |
1136 | #endif | |
1137 | ||
1138 | extern unsigned ipath_debug; /* debugging bit mask */ | |
72708a0a | 1139 | extern unsigned ipath_linkrecovery; |
826d8010 | 1140 | extern unsigned ipath_mtu4096; |
d41d3aeb | 1141 | |
9783ab40 BS |
1142 | #define IPATH_MAX_PARITY_ATTEMPTS 10000 /* max times to try recovery */ |
1143 | ||
d41d3aeb BS |
1144 | const char *ipath_get_unit_name(int unit); |
1145 | ||
1146 | extern struct mutex ipath_mutex; | |
1147 | ||
b55f4f06 | 1148 | #define IPATH_DRV_NAME "ib_ipath" |
d41d3aeb | 1149 | #define IPATH_MAJOR 233 |
a2acb2ff | 1150 | #define IPATH_USER_MINOR_BASE 0 |
98341f26 | 1151 | #define IPATH_DIAGPKT_MINOR 127 |
a2acb2ff BS |
1152 | #define IPATH_DIAG_MINOR_BASE 129 |
1153 | #define IPATH_NMINORS 255 | |
d41d3aeb BS |
1154 | |
1155 | #define ipath_dev_err(dd,fmt,...) \ | |
1156 | do { \ | |
1157 | const struct ipath_devdata *__dd = (dd); \ | |
1158 | if (__dd->pcidev) \ | |
1159 | dev_err(&__dd->pcidev->dev, "%s: " fmt, \ | |
1160 | ipath_get_unit_name(__dd->ipath_unit), \ | |
1161 | ##__VA_ARGS__); \ | |
1162 | else \ | |
1163 | printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \ | |
1164 | ipath_get_unit_name(__dd->ipath_unit), \ | |
1165 | ##__VA_ARGS__); \ | |
1166 | } while (0) | |
1167 | ||
1168 | #if _IPATH_DEBUGGING | |
1169 | ||
1170 | # define __IPATH_DBG_WHICH(which,fmt,...) \ | |
1171 | do { \ | |
2ba3f56e | 1172 | if (unlikely(ipath_debug & (which))) \ |
d41d3aeb BS |
1173 | printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \ |
1174 | __func__,##__VA_ARGS__); \ | |
1175 | } while(0) | |
1176 | ||
1177 | # define ipath_dbg(fmt,...) \ | |
1178 | __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__) | |
1179 | # define ipath_cdbg(which,fmt,...) \ | |
1180 | __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__) | |
1181 | ||
1182 | #else /* ! _IPATH_DEBUGGING */ | |
1183 | ||
1184 | # define ipath_dbg(fmt,...) | |
1185 | # define ipath_cdbg(which,fmt,...) | |
1186 | ||
1187 | #endif /* _IPATH_DEBUGGING */ | |
1188 | ||
8d588f8b BS |
1189 | /* |
1190 | * this is used for formatting hw error messages... | |
1191 | */ | |
1192 | struct ipath_hwerror_msgs { | |
1193 | u64 mask; | |
1194 | const char *msg; | |
1195 | }; | |
1196 | ||
1197 | #define INFINIPATH_HWE_MSG(a, b) { .mask = INFINIPATH_HWE_##a, .msg = b } | |
1198 | ||
1199 | /* in ipath_intr.c... */ | |
1200 | void ipath_format_hwerrors(u64 hwerrs, | |
1201 | const struct ipath_hwerror_msgs *hwerrmsgs, | |
1202 | size_t nhwerrmsgs, | |
1203 | char *msg, size_t lmsg); | |
1204 | ||
d41d3aeb | 1205 | #endif /* _IPATH_KERNEL_H */ |