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108ecf0d | 1 | /* |
e7eacd36 | 2 | * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved. |
108ecf0d BS |
3 | * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved. |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
34 | #include <linux/pci.h> | |
58411d1c | 35 | #include <linux/delay.h> |
108ecf0d BS |
36 | |
37 | #include "ipath_kernel.h" | |
b1c1b6a3 | 38 | #include "ipath_verbs.h" |
27b678dd | 39 | #include "ipath_common.h" |
108ecf0d | 40 | |
9783ab40 | 41 | |
89d1e09b BS |
42 | /* |
43 | * Called when we might have an error that is specific to a particular | |
44 | * PIO buffer, and may need to cancel that buffer, so it can be re-used. | |
45 | */ | |
e2ab41ca | 46 | void ipath_disarm_senderrbufs(struct ipath_devdata *dd) |
89d1e09b BS |
47 | { |
48 | u32 piobcnt; | |
49 | unsigned long sbuf[4]; | |
50 | /* | |
51 | * it's possible that sendbuffererror could have bits set; might | |
52 | * have already done this as a result of hardware error handling | |
53 | */ | |
54 | piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k; | |
55 | /* read these before writing errorclear */ | |
56 | sbuf[0] = ipath_read_kreg64( | |
57 | dd, dd->ipath_kregs->kr_sendbuffererror); | |
58 | sbuf[1] = ipath_read_kreg64( | |
59 | dd, dd->ipath_kregs->kr_sendbuffererror + 1); | |
bb917144 | 60 | if (piobcnt > 128) |
89d1e09b BS |
61 | sbuf[2] = ipath_read_kreg64( |
62 | dd, dd->ipath_kregs->kr_sendbuffererror + 2); | |
bb917144 | 63 | if (piobcnt > 192) |
89d1e09b BS |
64 | sbuf[3] = ipath_read_kreg64( |
65 | dd, dd->ipath_kregs->kr_sendbuffererror + 3); | |
bb917144 AJ |
66 | else |
67 | sbuf[3] = 0; | |
89d1e09b BS |
68 | |
69 | if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) { | |
70 | int i; | |
9380068f DO |
71 | if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG) && |
72 | dd->ipath_lastcancel > jiffies) { | |
89d1e09b BS |
73 | __IPATH_DBG_WHICH(__IPATH_PKTDBG|__IPATH_DBG, |
74 | "SendbufErrs %lx %lx", sbuf[0], | |
75 | sbuf[1]); | |
76 | if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128) | |
77 | printk(" %lx %lx ", sbuf[2], sbuf[3]); | |
78 | printk("\n"); | |
79 | } | |
80 | ||
81 | for (i = 0; i < piobcnt; i++) | |
e2ab41ca | 82 | if (test_bit(i, sbuf)) |
89d1e09b | 83 | ipath_disarm_piobufs(dd, i, 1); |
9380068f DO |
84 | /* ignore armlaunch errs for a bit */ |
85 | dd->ipath_lastcancel = jiffies+3; | |
89d1e09b BS |
86 | } |
87 | } | |
88 | ||
89 | ||
f37bda92 | 90 | /* These are all rcv-related errors which we want to count for stats */ |
108ecf0d BS |
91 | #define E_SUM_PKTERRS \ |
92 | (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \ | |
93 | INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \ | |
94 | INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \ | |
95 | INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \ | |
96 | INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \ | |
97 | INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP) | |
98 | ||
f37bda92 | 99 | /* These are all send-related errors which we want to count for stats */ |
108ecf0d BS |
100 | #define E_SUM_ERRS \ |
101 | (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \ | |
102 | INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ | |
103 | INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \ | |
104 | INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \ | |
105 | INFINIPATH_E_INVALIDADDR) | |
106 | ||
0f4fc5eb DO |
107 | /* |
108 | * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore | |
109 | * errors not related to freeze and cancelling buffers. Can't ignore | |
110 | * armlaunch because could get more while still cleaning up, and need | |
111 | * to cancel those as they happen. | |
112 | */ | |
113 | #define E_SPKT_ERRS_IGNORE \ | |
114 | (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ | |
115 | INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SMINPKTLEN | \ | |
116 | INFINIPATH_E_SPKTLEN) | |
117 | ||
f37bda92 BS |
118 | /* |
119 | * these are errors that can occur when the link changes state while | |
120 | * a packet is being sent or received. This doesn't cover things | |
121 | * like EBP or VCRC that can be the result of a sending having the | |
122 | * link change state, so we receive a "known bad" packet. | |
123 | */ | |
124 | #define E_SUM_LINK_PKTERRS \ | |
125 | (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \ | |
126 | INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \ | |
127 | INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \ | |
128 | INFINIPATH_E_RUNEXPCHAR) | |
129 | ||
108ecf0d BS |
130 | static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs) |
131 | { | |
108ecf0d | 132 | u64 ignore_this_time = 0; |
108ecf0d | 133 | |
e2ab41ca | 134 | ipath_disarm_senderrbufs(dd); |
f37bda92 | 135 | if ((errs & E_SUM_LINK_PKTERRS) && |
108ecf0d BS |
136 | !(dd->ipath_flags & IPATH_LINKACTIVE)) { |
137 | /* | |
138 | * This can happen when SMA is trying to bring the link | |
139 | * up, but the IB link changes state at the "wrong" time. | |
140 | * The IB logic then complains that the packet isn't | |
141 | * valid. We don't want to confuse people, so we just | |
142 | * don't print them, except at debug | |
143 | */ | |
f37bda92 BS |
144 | ipath_dbg("Ignoring packet errors %llx, because link not " |
145 | "ACTIVE\n", (unsigned long long) errs); | |
146 | ignore_this_time = errs & E_SUM_LINK_PKTERRS; | |
108ecf0d BS |
147 | } |
148 | ||
149 | return ignore_this_time; | |
150 | } | |
151 | ||
8d588f8b BS |
152 | /* generic hw error messages... */ |
153 | #define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \ | |
154 | { \ | |
155 | .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a << \ | |
156 | INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ), \ | |
157 | .msg = "TXE " #a " Memory Parity" \ | |
158 | } | |
159 | #define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \ | |
160 | { \ | |
161 | .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a << \ | |
162 | INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ), \ | |
163 | .msg = "RXE " #a " Memory Parity" \ | |
164 | } | |
165 | ||
166 | static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = { | |
167 | INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"), | |
168 | INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"), | |
169 | ||
170 | INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF), | |
171 | INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC), | |
172 | INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO), | |
173 | ||
174 | INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF), | |
175 | INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ), | |
176 | INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID), | |
177 | INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID), | |
178 | INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF), | |
179 | INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO), | |
180 | INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO), | |
181 | }; | |
182 | ||
183 | /** | |
184 | * ipath_format_hwmsg - format a single hwerror message | |
185 | * @msg message buffer | |
186 | * @msgl length of message buffer | |
187 | * @hwmsg message to add to message buffer | |
188 | */ | |
189 | static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg) | |
190 | { | |
191 | strlcat(msg, "[", msgl); | |
192 | strlcat(msg, hwmsg, msgl); | |
193 | strlcat(msg, "]", msgl); | |
194 | } | |
195 | ||
196 | /** | |
197 | * ipath_format_hwerrors - format hardware error messages for display | |
198 | * @hwerrs hardware errors bit vector | |
199 | * @hwerrmsgs hardware error descriptions | |
200 | * @nhwerrmsgs number of hwerrmsgs | |
201 | * @msg message buffer | |
202 | * @msgl message buffer length | |
203 | */ | |
204 | void ipath_format_hwerrors(u64 hwerrs, | |
205 | const struct ipath_hwerror_msgs *hwerrmsgs, | |
206 | size_t nhwerrmsgs, | |
207 | char *msg, size_t msgl) | |
208 | { | |
209 | int i; | |
210 | const int glen = | |
211 | sizeof(ipath_generic_hwerror_msgs) / | |
212 | sizeof(ipath_generic_hwerror_msgs[0]); | |
213 | ||
214 | for (i=0; i<glen; i++) { | |
215 | if (hwerrs & ipath_generic_hwerror_msgs[i].mask) { | |
216 | ipath_format_hwmsg(msg, msgl, | |
217 | ipath_generic_hwerror_msgs[i].msg); | |
218 | } | |
219 | } | |
220 | ||
221 | for (i=0; i<nhwerrmsgs; i++) { | |
222 | if (hwerrs & hwerrmsgs[i].mask) { | |
223 | ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg); | |
224 | } | |
225 | } | |
226 | } | |
227 | ||
108ecf0d | 228 | /* return the strings for the most common link states */ |
58411d1c | 229 | static char *ib_linkstate(struct ipath_devdata *dd, u64 ibcs) |
108ecf0d BS |
230 | { |
231 | char *ret; | |
58411d1c | 232 | u32 state; |
108ecf0d | 233 | |
58411d1c JG |
234 | state = ipath_ib_state(dd, ibcs); |
235 | if (state == dd->ib_init) | |
108ecf0d | 236 | ret = "Init"; |
58411d1c | 237 | else if (state == dd->ib_arm) |
108ecf0d | 238 | ret = "Arm"; |
58411d1c | 239 | else if (state == dd->ib_active) |
108ecf0d | 240 | ret = "Active"; |
58411d1c | 241 | else |
108ecf0d | 242 | ret = "Down"; |
108ecf0d BS |
243 | return ret; |
244 | } | |
245 | ||
49739b3e RC |
246 | void signal_ib_event(struct ipath_devdata *dd, enum ib_event_type ev) |
247 | { | |
248 | struct ib_event event; | |
249 | ||
250 | event.device = &dd->verbs_dev->ibdev; | |
251 | event.element.port_num = 1; | |
252 | event.event = ev; | |
253 | ib_dispatch_event(&event); | |
254 | } | |
255 | ||
108ecf0d | 256 | static void handle_e_ibstatuschanged(struct ipath_devdata *dd, |
58411d1c | 257 | ipath_err_t errs) |
108ecf0d | 258 | { |
58411d1c JG |
259 | u32 ltstate, lstate, ibstate, lastlstate; |
260 | u32 init = dd->ib_init; | |
261 | u32 arm = dd->ib_arm; | |
262 | u32 active = dd->ib_active; | |
263 | const u64 ibcs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus); | |
264 | ||
265 | lstate = ipath_ib_linkstate(dd, ibcs); /* linkstate */ | |
266 | ibstate = ipath_ib_state(dd, ibcs); | |
267 | /* linkstate at last interrupt */ | |
268 | lastlstate = ipath_ib_linkstate(dd, dd->ipath_lastibcstat); | |
269 | ltstate = ipath_ib_linktrstate(dd, ibcs); /* linktrainingtate */ | |
108ecf0d | 270 | |
555b203e DO |
271 | /* |
272 | * Since going into a recovery state causes the link state to go | |
273 | * down and since recovery is transitory, it is better if we "miss" | |
274 | * ever seeing the link training state go into recovery (i.e., | |
275 | * ignore this transition for link state special handling purposes) | |
276 | * without even updating ipath_lastibcstat. | |
277 | */ | |
278 | if ((ltstate == INFINIPATH_IBCS_LT_STATE_RECOVERRETRAIN) || | |
279 | (ltstate == INFINIPATH_IBCS_LT_STATE_RECOVERWAITRMT) || | |
280 | (ltstate == INFINIPATH_IBCS_LT_STATE_RECOVERIDLE)) | |
281 | goto done; | |
282 | ||
108ecf0d | 283 | /* |
58411d1c JG |
284 | * if linkstate transitions into INIT from any of the various down |
285 | * states, or if it transitions from any of the up (INIT or better) | |
286 | * states into any of the down states (except link recovery), then | |
287 | * call the chip-specific code to take appropriate actions. | |
108ecf0d | 288 | */ |
58411d1c JG |
289 | if (lstate >= INFINIPATH_IBCS_L_STATE_INIT && |
290 | lastlstate == INFINIPATH_IBCS_L_STATE_DOWN) { | |
291 | /* transitioned to UP */ | |
292 | if (dd->ipath_f_ib_updown(dd, 1, ibcs)) { | |
4330e4da MA |
293 | /* link came up, so we must no longer be disabled */ |
294 | dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED; | |
58411d1c JG |
295 | ipath_cdbg(LINKVERB, "LinkUp handled, skipped\n"); |
296 | goto skip_ibchange; /* chip-code handled */ | |
297 | } | |
298 | } else if ((lastlstate >= INFINIPATH_IBCS_L_STATE_INIT || | |
299 | (dd->ipath_flags & IPATH_IB_FORCE_NOTIFY)) && | |
555b203e | 300 | ltstate <= INFINIPATH_IBCS_LT_STATE_CFGWAITRMT && |
58411d1c JG |
301 | ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) { |
302 | int handled; | |
303 | handled = dd->ipath_f_ib_updown(dd, 0, ibcs); | |
304 | dd->ipath_flags &= ~IPATH_IB_FORCE_NOTIFY; | |
305 | if (handled) { | |
306 | ipath_cdbg(LINKVERB, "LinkDown handled, skipped\n"); | |
307 | goto skip_ibchange; /* chip-code handled */ | |
308 | } | |
309 | } | |
f37bda92 BS |
310 | |
311 | /* | |
58411d1c JG |
312 | * Significant enough to always print and get into logs, if it was |
313 | * unexpected. If it was a requested state change, we'll have | |
314 | * already cleared the flags, so we won't print this warning | |
f37bda92 | 315 | */ |
58411d1c JG |
316 | if ((ibstate != arm && ibstate != active) && |
317 | (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) { | |
318 | dev_info(&dd->pcidev->dev, "Link state changed from %s " | |
319 | "to %s\n", (dd->ipath_flags & IPATH_LINKARMED) ? | |
320 | "ARM" : "ACTIVE", ib_linkstate(dd, ibcs)); | |
f37bda92 | 321 | } |
108ecf0d BS |
322 | |
323 | if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE || | |
324 | ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) { | |
58411d1c JG |
325 | u32 lastlts; |
326 | lastlts = ipath_ib_linktrstate(dd, dd->ipath_lastibcstat); | |
108ecf0d | 327 | /* |
58411d1c JG |
328 | * Ignore cycling back and forth from Polling.Active to |
329 | * Polling.Quiet while waiting for the other end of the link | |
330 | * to come up, except to try and decide if we are connected | |
331 | * to a live IB device or not. We will cycle back and | |
332 | * forth between them if no cable is plugged in, the other | |
333 | * device is powered off or disabled, etc. | |
108ecf0d | 334 | */ |
58411d1c JG |
335 | if (lastlts == INFINIPATH_IBCS_LT_STATE_POLLACTIVE || |
336 | lastlts == INFINIPATH_IBCS_LT_STATE_POLLQUIET) { | |
bb917144 AJ |
337 | if (!(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) && |
338 | (++dd->ipath_ibpollcnt == 40)) { | |
108ecf0d BS |
339 | dd->ipath_flags |= IPATH_NOCABLE; |
340 | *dd->ipath_statusp |= | |
341 | IPATH_STATUS_IB_NOCABLE; | |
58411d1c JG |
342 | ipath_cdbg(LINKVERB, "Set NOCABLE\n"); |
343 | } | |
344 | ipath_cdbg(LINKVERB, "POLL change to %s (%x)\n", | |
345 | ipath_ibcstatus_str[ltstate], ibstate); | |
108ecf0d BS |
346 | goto skip_ibchange; |
347 | } | |
348 | } | |
58411d1c JG |
349 | |
350 | dd->ipath_ibpollcnt = 0; /* not poll*, now */ | |
108ecf0d | 351 | ipath_stats.sps_iblink++; |
58411d1c | 352 | |
72708a0a DO |
353 | if (ibstate != init && dd->ipath_lastlinkrecov && ipath_linkrecovery) { |
354 | u64 linkrecov; | |
355 | linkrecov = ipath_snap_cntr(dd, | |
356 | dd->ipath_cregs->cr_iblinkerrrecovcnt); | |
357 | if (linkrecov != dd->ipath_lastlinkrecov) { | |
358 | ipath_dbg("IB linkrecov up %Lx (%s %s) recov %Lu\n", | |
359 | ibcs, ib_linkstate(dd, ibcs), | |
360 | ipath_ibcstatus_str[ltstate], | |
361 | linkrecov); | |
362 | /* and no more until active again */ | |
363 | dd->ipath_lastlinkrecov = 0; | |
364 | ipath_set_linkstate(dd, IPATH_IB_LINKDOWN); | |
365 | goto skip_ibchange; | |
366 | } | |
367 | } | |
368 | ||
58411d1c JG |
369 | if (ibstate == init || ibstate == arm || ibstate == active) { |
370 | *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE; | |
371 | if (ibstate == init || ibstate == arm) { | |
372 | *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; | |
373 | if (dd->ipath_flags & IPATH_LINKACTIVE) | |
374 | signal_ib_event(dd, IB_EVENT_PORT_ERR); | |
375 | } | |
376 | if (ibstate == arm) { | |
377 | dd->ipath_flags |= IPATH_LINKARMED; | |
378 | dd->ipath_flags &= ~(IPATH_LINKUNK | | |
379 | IPATH_LINKINIT | IPATH_LINKDOWN | | |
380 | IPATH_LINKACTIVE | IPATH_NOCABLE); | |
381 | ipath_hol_down(dd); | |
382 | } else if (ibstate == init) { | |
383 | /* | |
384 | * set INIT and DOWN. Down is checked by | |
385 | * most of the other code, but INIT is | |
386 | * useful to know in a few places. | |
387 | */ | |
388 | dd->ipath_flags |= IPATH_LINKINIT | | |
389 | IPATH_LINKDOWN; | |
390 | dd->ipath_flags &= ~(IPATH_LINKUNK | | |
391 | IPATH_LINKARMED | IPATH_LINKACTIVE | | |
392 | IPATH_NOCABLE); | |
393 | ipath_hol_down(dd); | |
394 | } else { /* active */ | |
72708a0a DO |
395 | dd->ipath_lastlinkrecov = ipath_snap_cntr(dd, |
396 | dd->ipath_cregs->cr_iblinkerrrecovcnt); | |
58411d1c JG |
397 | *dd->ipath_statusp |= |
398 | IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF; | |
399 | dd->ipath_flags |= IPATH_LINKACTIVE; | |
400 | dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT | |
401 | | IPATH_LINKDOWN | IPATH_LINKARMED | | |
402 | IPATH_NOCABLE); | |
124b4dcb DO |
403 | if (dd->ipath_flags & IPATH_HAS_SEND_DMA) |
404 | ipath_restart_sdma(dd); | |
58411d1c JG |
405 | signal_ib_event(dd, IB_EVENT_PORT_ACTIVE); |
406 | /* LED active not handled in chip _f_updown */ | |
407 | dd->ipath_f_setextled(dd, lstate, ltstate); | |
408 | ipath_hol_up(dd); | |
409 | } | |
410 | ||
411 | /* | |
412 | * print after we've already done the work, so as not to | |
413 | * delay the state changes and notifications, for debugging | |
414 | */ | |
415 | if (lstate == lastlstate) | |
416 | ipath_cdbg(LINKVERB, "Unchanged from last: %s " | |
417 | "(%x)\n", ib_linkstate(dd, ibcs), ibstate); | |
418 | else | |
419 | ipath_cdbg(VERBOSE, "Unit %u: link up to %s %s (%x)\n", | |
420 | dd->ipath_unit, ib_linkstate(dd, ibcs), | |
421 | ipath_ibcstatus_str[ltstate], ibstate); | |
422 | } else { /* down */ | |
49739b3e RC |
423 | if (dd->ipath_flags & IPATH_LINKACTIVE) |
424 | signal_ib_event(dd, IB_EVENT_PORT_ERR); | |
108ecf0d BS |
425 | dd->ipath_flags |= IPATH_LINKDOWN; |
426 | dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT | |
427 | | IPATH_LINKACTIVE | | |
428 | IPATH_LINKARMED); | |
429 | *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; | |
fba75200 | 430 | dd->ipath_lli_counter = 0; |
108ecf0d | 431 | |
58411d1c JG |
432 | if (lastlstate != INFINIPATH_IBCS_L_STATE_DOWN) |
433 | ipath_cdbg(VERBOSE, "Unit %u link state down " | |
434 | "(state 0x%x), from %s\n", | |
435 | dd->ipath_unit, lstate, | |
436 | ib_linkstate(dd, dd->ipath_lastibcstat)); | |
437 | else | |
438 | ipath_cdbg(LINKVERB, "Unit %u link state changed " | |
439 | "to %s (0x%x) from down (%x)\n", | |
440 | dd->ipath_unit, | |
441 | ipath_ibcstatus_str[ltstate], | |
442 | ibstate, lastlstate); | |
108ecf0d | 443 | } |
58411d1c | 444 | |
108ecf0d | 445 | skip_ibchange: |
58411d1c | 446 | dd->ipath_lastibcstat = ibcs; |
555b203e DO |
447 | done: |
448 | return; | |
108ecf0d BS |
449 | } |
450 | ||
451 | static void handle_supp_msgs(struct ipath_devdata *dd, | |
124b4dcb | 452 | unsigned supp_msgs, char *msg, u32 msgsz) |
108ecf0d BS |
453 | { |
454 | /* | |
455 | * Print the message unless it's ibc status change only, which | |
456 | * happens so often we never want to count it. | |
457 | */ | |
458 | if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) { | |
8ec1077b | 459 | int iserr; |
124b4dcb DO |
460 | ipath_err_t mask; |
461 | iserr = ipath_decode_err(dd, msg, msgsz, | |
164ef7a2 DO |
462 | dd->ipath_lasterror & |
463 | ~INFINIPATH_E_IBSTATUSCHANGED); | |
124b4dcb DO |
464 | |
465 | mask = INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL | | |
466 | INFINIPATH_E_PKTERRS | INFINIPATH_E_SDMADISABLED; | |
467 | ||
468 | /* if we're in debug, then don't mask SDMADISABLED msgs */ | |
469 | if (ipath_debug & __IPATH_DBG) | |
470 | mask &= ~INFINIPATH_E_SDMADISABLED; | |
471 | ||
472 | if (dd->ipath_lasterror & ~mask) | |
108ecf0d BS |
473 | ipath_dev_err(dd, "Suppressed %u messages for " |
474 | "fast-repeating errors (%s) (%llx)\n", | |
475 | supp_msgs, msg, | |
476 | (unsigned long long) | |
477 | dd->ipath_lasterror); | |
478 | else { | |
479 | /* | |
480 | * rcvegrfull and rcvhdrqfull are "normal", for some | |
481 | * types of processes (mostly benchmarks) that send | |
482 | * huge numbers of messages, while not processing | |
483 | * them. So only complain about these at debug | |
484 | * level. | |
485 | */ | |
8ec1077b BS |
486 | if (iserr) |
487 | ipath_dbg("Suppressed %u messages for %s\n", | |
488 | supp_msgs, msg); | |
489 | else | |
490 | ipath_cdbg(ERRPKT, | |
491 | "Suppressed %u messages for %s\n", | |
492 | supp_msgs, msg); | |
108ecf0d BS |
493 | } |
494 | } | |
495 | } | |
496 | ||
497 | static unsigned handle_frequent_errors(struct ipath_devdata *dd, | |
164ef7a2 | 498 | ipath_err_t errs, char *msg, |
124b4dcb | 499 | u32 msgsz, int *noprint) |
108ecf0d BS |
500 | { |
501 | unsigned long nc; | |
502 | static unsigned long nextmsg_time; | |
503 | static unsigned nmsgs, supp_msgs; | |
504 | ||
505 | /* | |
506 | * Throttle back "fast" messages to no more than 10 per 5 seconds. | |
507 | * This isn't perfect, but it's a reasonable heuristic. If we get | |
508 | * more than 10, give a 6x longer delay. | |
509 | */ | |
510 | nc = jiffies; | |
511 | if (nmsgs > 10) { | |
512 | if (time_before(nc, nextmsg_time)) { | |
513 | *noprint = 1; | |
514 | if (!supp_msgs++) | |
515 | nextmsg_time = nc + HZ * 3; | |
516 | } | |
517 | else if (supp_msgs) { | |
164ef7a2 | 518 | handle_supp_msgs(dd, supp_msgs, msg, msgsz); |
108ecf0d BS |
519 | supp_msgs = 0; |
520 | nmsgs = 0; | |
521 | } | |
522 | } | |
523 | else if (!nmsgs++ || time_after(nc, nextmsg_time)) | |
524 | nextmsg_time = nc + HZ / 2; | |
525 | ||
526 | return supp_msgs; | |
527 | } | |
528 | ||
124b4dcb DO |
529 | static void handle_sdma_errors(struct ipath_devdata *dd, ipath_err_t errs) |
530 | { | |
531 | unsigned long flags; | |
532 | int expected; | |
533 | ||
534 | if (ipath_debug & __IPATH_DBG) { | |
535 | char msg[128]; | |
536 | ipath_decode_err(dd, msg, sizeof msg, errs & | |
537 | INFINIPATH_E_SDMAERRS); | |
538 | ipath_dbg("errors %lx (%s)\n", (unsigned long)errs, msg); | |
539 | } | |
540 | if (ipath_debug & __IPATH_VERBDBG) { | |
541 | unsigned long tl, hd, status, lengen; | |
542 | tl = ipath_read_kreg64(dd, dd->ipath_kregs->kr_senddmatail); | |
543 | hd = ipath_read_kreg64(dd, dd->ipath_kregs->kr_senddmahead); | |
544 | status = ipath_read_kreg64(dd | |
545 | , dd->ipath_kregs->kr_senddmastatus); | |
546 | lengen = ipath_read_kreg64(dd, | |
547 | dd->ipath_kregs->kr_senddmalengen); | |
548 | ipath_cdbg(VERBOSE, "sdma tl 0x%lx hd 0x%lx status 0x%lx " | |
549 | "lengen 0x%lx\n", tl, hd, status, lengen); | |
550 | } | |
551 | ||
552 | spin_lock_irqsave(&dd->ipath_sdma_lock, flags); | |
553 | __set_bit(IPATH_SDMA_DISABLED, &dd->ipath_sdma_status); | |
554 | expected = test_bit(IPATH_SDMA_ABORTING, &dd->ipath_sdma_status); | |
555 | spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags); | |
556 | if (!expected) | |
557 | ipath_cancel_sends(dd, 1); | |
558 | } | |
559 | ||
560 | static void handle_sdma_intr(struct ipath_devdata *dd, u64 istat) | |
561 | { | |
562 | unsigned long flags; | |
563 | int expected; | |
564 | ||
565 | if ((istat & INFINIPATH_I_SDMAINT) && | |
566 | !test_bit(IPATH_SDMA_SHUTDOWN, &dd->ipath_sdma_status)) | |
567 | ipath_sdma_intr(dd); | |
568 | ||
569 | if (istat & INFINIPATH_I_SDMADISABLED) { | |
570 | expected = test_bit(IPATH_SDMA_ABORTING, | |
571 | &dd->ipath_sdma_status); | |
572 | ipath_dbg("%s SDmaDisabled intr\n", | |
573 | expected ? "expected" : "unexpected"); | |
574 | spin_lock_irqsave(&dd->ipath_sdma_lock, flags); | |
575 | __set_bit(IPATH_SDMA_DISABLED, &dd->ipath_sdma_status); | |
576 | spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags); | |
577 | if (!expected) | |
578 | ipath_cancel_sends(dd, 1); | |
579 | if (!test_bit(IPATH_SDMA_SHUTDOWN, &dd->ipath_sdma_status)) | |
580 | tasklet_hi_schedule(&dd->ipath_sdma_abort_task); | |
581 | } | |
582 | } | |
583 | ||
584 | static int handle_hdrq_full(struct ipath_devdata *dd) | |
585 | { | |
586 | int chkerrpkts = 0; | |
587 | u32 hd, tl; | |
588 | u32 i; | |
589 | ||
590 | ipath_stats.sps_hdrqfull++; | |
591 | for (i = 0; i < dd->ipath_cfgports; i++) { | |
592 | struct ipath_portdata *pd = dd->ipath_pd[i]; | |
593 | ||
594 | if (i == 0) { | |
595 | /* | |
596 | * For kernel receive queues, we just want to know | |
597 | * if there are packets in the queue that we can | |
598 | * process. | |
599 | */ | |
600 | if (pd->port_head != ipath_get_hdrqtail(pd)) | |
601 | chkerrpkts |= 1 << i; | |
602 | continue; | |
603 | } | |
604 | ||
605 | /* Skip if user context is not open */ | |
606 | if (!pd || !pd->port_cnt) | |
607 | continue; | |
608 | ||
609 | /* Don't report the same point multiple times. */ | |
610 | if (dd->ipath_flags & IPATH_NODMA_RTAIL) | |
611 | tl = ipath_read_ureg32(dd, ur_rcvhdrtail, i); | |
612 | else | |
613 | tl = ipath_get_rcvhdrtail(pd); | |
614 | if (tl == pd->port_lastrcvhdrqtail) | |
615 | continue; | |
616 | ||
617 | hd = ipath_read_ureg32(dd, ur_rcvhdrhead, i); | |
618 | if (hd == (tl + 1) || (!hd && tl == dd->ipath_hdrqlast)) { | |
619 | pd->port_lastrcvhdrqtail = tl; | |
620 | pd->port_hdrqfull++; | |
621 | /* flush hdrqfull so that poll() sees it */ | |
622 | wmb(); | |
623 | wake_up_interruptible(&pd->port_wait); | |
624 | } | |
625 | } | |
626 | ||
627 | return chkerrpkts; | |
628 | } | |
629 | ||
f5f99929 | 630 | static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs) |
108ecf0d | 631 | { |
164ef7a2 | 632 | char msg[128]; |
108ecf0d | 633 | u64 ignore_this_time = 0; |
124b4dcb | 634 | u64 iserr = 0; |
108ecf0d BS |
635 | int chkerrpkts = 0, noprint = 0; |
636 | unsigned supp_msgs; | |
aecd3b5a | 637 | int log_idx; |
108ecf0d | 638 | |
124b4dcb DO |
639 | /* |
640 | * don't report errors that are masked, either at init | |
641 | * (not set in ipath_errormask), or temporarily (set in | |
642 | * ipath_maskederrs) | |
643 | */ | |
644 | errs &= dd->ipath_errormask & ~dd->ipath_maskederrs; | |
108ecf0d | 645 | |
124b4dcb DO |
646 | supp_msgs = handle_frequent_errors(dd, errs, msg, (u32)sizeof msg, |
647 | &noprint); | |
108ecf0d BS |
648 | |
649 | /* do these first, they are most important */ | |
650 | if (errs & INFINIPATH_E_HARDWARE) { | |
651 | /* reuse same msg buf */ | |
652 | dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg); | |
aecd3b5a MA |
653 | } else { |
654 | u64 mask; | |
655 | for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx) { | |
656 | mask = dd->ipath_eep_st_masks[log_idx].errs_to_log; | |
657 | if (errs & mask) | |
658 | ipath_inc_eeprom_err(dd, log_idx, 1); | |
659 | } | |
108ecf0d BS |
660 | } |
661 | ||
124b4dcb DO |
662 | if (errs & INFINIPATH_E_SDMAERRS) |
663 | handle_sdma_errors(dd, errs); | |
664 | ||
f62fe77a | 665 | if (!noprint && (errs & ~dd->ipath_e_bitsextant)) |
108ecf0d BS |
666 | ipath_dev_err(dd, "error interrupt with unknown errors " |
667 | "%llx set\n", (unsigned long long) | |
f62fe77a | 668 | (errs & ~dd->ipath_e_bitsextant)); |
108ecf0d BS |
669 | |
670 | if (errs & E_SUM_ERRS) | |
671 | ignore_this_time = handle_e_sum_errs(dd, errs); | |
f37bda92 BS |
672 | else if ((errs & E_SUM_LINK_PKTERRS) && |
673 | !(dd->ipath_flags & IPATH_LINKACTIVE)) { | |
674 | /* | |
675 | * This can happen when SMA is trying to bring the link | |
676 | * up, but the IB link changes state at the "wrong" time. | |
677 | * The IB logic then complains that the packet isn't | |
678 | * valid. We don't want to confuse people, so we just | |
679 | * don't print them, except at debug | |
680 | */ | |
681 | ipath_dbg("Ignoring packet errors %llx, because link not " | |
682 | "ACTIVE\n", (unsigned long long) errs); | |
683 | ignore_this_time = errs & E_SUM_LINK_PKTERRS; | |
684 | } | |
108ecf0d BS |
685 | |
686 | if (supp_msgs == 250000) { | |
8ec1077b | 687 | int s_iserr; |
108ecf0d BS |
688 | /* |
689 | * It's not entirely reasonable assuming that the errors set | |
690 | * in the last clear period are all responsible for the | |
691 | * problem, but the alternative is to assume it's the only | |
692 | * ones on this particular interrupt, which also isn't great | |
693 | */ | |
694 | dd->ipath_maskederrs |= dd->ipath_lasterror | errs; | |
2ba3f56e | 695 | |
78d1e02f | 696 | dd->ipath_errormask &= ~dd->ipath_maskederrs; |
108ecf0d | 697 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, |
2ba3f56e | 698 | dd->ipath_errormask); |
124b4dcb | 699 | s_iserr = ipath_decode_err(dd, msg, sizeof msg, |
2ba3f56e | 700 | dd->ipath_maskederrs); |
108ecf0d | 701 | |
78d1e02f | 702 | if (dd->ipath_maskederrs & |
2ba3f56e RC |
703 | ~(INFINIPATH_E_RRCVEGRFULL | |
704 | INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS)) | |
8ec1077b BS |
705 | ipath_dev_err(dd, "Temporarily disabling " |
706 | "error(s) %llx reporting; too frequent (%s)\n", | |
2ba3f56e | 707 | (unsigned long long) dd->ipath_maskederrs, |
78d1e02f | 708 | msg); |
108ecf0d BS |
709 | else { |
710 | /* | |
711 | * rcvegrfull and rcvhdrqfull are "normal", | |
712 | * for some types of processes (mostly benchmarks) | |
713 | * that send huge numbers of messages, while not | |
714 | * processing them. So only complain about | |
715 | * these at debug level. | |
716 | */ | |
8ec1077b BS |
717 | if (s_iserr) |
718 | ipath_dbg("Temporarily disabling reporting " | |
719 | "too frequent queue full errors (%s)\n", | |
720 | msg); | |
721 | else | |
722 | ipath_cdbg(ERRPKT, | |
723 | "Temporarily disabling reporting too" | |
724 | " frequent packet errors (%s)\n", | |
725 | msg); | |
108ecf0d BS |
726 | } |
727 | ||
728 | /* | |
729 | * Re-enable the masked errors after around 3 minutes. in | |
730 | * ipath_get_faststats(). If we have a series of fast | |
731 | * repeating but different errors, the interval will keep | |
732 | * stretching out, but that's OK, as that's pretty | |
733 | * catastrophic. | |
734 | */ | |
735 | dd->ipath_unmasktime = jiffies + HZ * 180; | |
736 | } | |
737 | ||
738 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs); | |
739 | if (ignore_this_time) | |
740 | errs &= ~ignore_this_time; | |
741 | if (errs & ~dd->ipath_lasterror) { | |
742 | errs &= ~dd->ipath_lasterror; | |
743 | /* never suppress duplicate hwerrors or ibstatuschange */ | |
744 | dd->ipath_lasterror |= errs & | |
745 | ~(INFINIPATH_E_HARDWARE | | |
746 | INFINIPATH_E_IBSTATUSCHANGED); | |
747 | } | |
89d1e09b | 748 | |
124b4dcb DO |
749 | if (errs & INFINIPATH_E_SENDSPECIALTRIGGER) { |
750 | dd->ipath_spectriggerhit++; | |
751 | ipath_dbg("%lu special trigger hits\n", | |
752 | dd->ipath_spectriggerhit); | |
753 | } | |
754 | ||
755 | /* likely due to cancel; so suppress message unless verbose */ | |
89d1e09b BS |
756 | if ((errs & (INFINIPATH_E_SPKTLEN | INFINIPATH_E_SPIOARMLAUNCH)) && |
757 | dd->ipath_lastcancel > jiffies) { | |
124b4dcb DO |
758 | /* armlaunch takes precedence; it often causes both. */ |
759 | ipath_cdbg(VERBOSE, | |
760 | "Suppressed %s error (%llx) after sendbuf cancel\n", | |
761 | (errs & INFINIPATH_E_SPIOARMLAUNCH) ? | |
762 | "armlaunch" : "sendpktlen", (unsigned long long)errs); | |
89d1e09b BS |
763 | errs &= ~(INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SPKTLEN); |
764 | } | |
765 | ||
108ecf0d | 766 | if (!errs) |
f5f99929 | 767 | return 0; |
108ecf0d | 768 | |
124b4dcb DO |
769 | if (!noprint) { |
770 | ipath_err_t mask; | |
108ecf0d | 771 | /* |
124b4dcb DO |
772 | * The ones we mask off are handled specially below |
773 | * or above. Also mask SDMADISABLED by default as it | |
774 | * is too chatty. | |
108ecf0d | 775 | */ |
124b4dcb DO |
776 | mask = INFINIPATH_E_IBSTATUSCHANGED | |
777 | INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL | | |
778 | INFINIPATH_E_HARDWARE | INFINIPATH_E_SDMADISABLED; | |
779 | ||
780 | /* if we're in debug, then don't mask SDMADISABLED msgs */ | |
781 | if (ipath_debug & __IPATH_DBG) | |
782 | mask &= ~INFINIPATH_E_SDMADISABLED; | |
783 | ||
784 | ipath_decode_err(dd, msg, sizeof msg, errs & ~mask); | |
785 | } else | |
108ecf0d BS |
786 | /* so we don't need if (!noprint) at strlcat's below */ |
787 | *msg = 0; | |
788 | ||
789 | if (errs & E_SUM_PKTERRS) { | |
790 | ipath_stats.sps_pkterrs++; | |
791 | chkerrpkts = 1; | |
792 | } | |
793 | if (errs & E_SUM_ERRS) | |
794 | ipath_stats.sps_errs++; | |
795 | ||
796 | if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) { | |
797 | ipath_stats.sps_crcerrs++; | |
798 | chkerrpkts = 1; | |
799 | } | |
8ec1077b BS |
800 | iserr = errs & ~(E_SUM_PKTERRS | INFINIPATH_E_PKTERRS); |
801 | ||
108ecf0d BS |
802 | |
803 | /* | |
804 | * We don't want to print these two as they happen, or we can make | |
805 | * the situation even worse, because it takes so long to print | |
806 | * messages to serial consoles. Kernel ports get printed from | |
807 | * fast_stats, no more than every 5 seconds, user ports get printed | |
808 | * on close | |
809 | */ | |
124b4dcb DO |
810 | if (errs & INFINIPATH_E_RRCVHDRFULL) |
811 | chkerrpkts |= handle_hdrq_full(dd); | |
108ecf0d | 812 | if (errs & INFINIPATH_E_RRCVEGRFULL) { |
c59a80ac RC |
813 | struct ipath_portdata *pd = dd->ipath_pd[0]; |
814 | ||
108ecf0d BS |
815 | /* |
816 | * since this is of less importance and not likely to | |
817 | * happen without also getting hdrfull, only count | |
818 | * occurrences; don't check each port (or even the kernel | |
819 | * vs user) | |
820 | */ | |
821 | ipath_stats.sps_etidfull++; | |
9355fb6a | 822 | if (pd->port_head != ipath_get_hdrqtail(pd)) |
124b4dcb | 823 | chkerrpkts |= 1; |
108ecf0d BS |
824 | } |
825 | ||
826 | /* | |
827 | * do this before IBSTATUSCHANGED, in case both bits set in a single | |
828 | * interrupt; we want the STATUSCHANGE to "win", so we do our | |
829 | * internal copy of state machine correctly | |
830 | */ | |
831 | if (errs & INFINIPATH_E_RIBLOSTLINK) { | |
832 | /* | |
833 | * force through block below | |
834 | */ | |
835 | errs |= INFINIPATH_E_IBSTATUSCHANGED; | |
836 | ipath_stats.sps_iblink++; | |
837 | dd->ipath_flags |= IPATH_LINKDOWN; | |
838 | dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT | |
839 | | IPATH_LINKARMED | IPATH_LINKACTIVE); | |
840 | *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY; | |
108ecf0d | 841 | |
58411d1c JG |
842 | ipath_dbg("Lost link, link now down (%s)\n", |
843 | ipath_ibcstatus_str[ipath_read_kreg64(dd, | |
844 | dd->ipath_kregs->kr_ibcstatus) & 0xf]); | |
108ecf0d BS |
845 | } |
846 | if (errs & INFINIPATH_E_IBSTATUSCHANGED) | |
58411d1c | 847 | handle_e_ibstatuschanged(dd, errs); |
108ecf0d BS |
848 | |
849 | if (errs & INFINIPATH_E_RESET) { | |
850 | if (!noprint) | |
851 | ipath_dev_err(dd, "Got reset, requires re-init " | |
852 | "(unload and reload driver)\n"); | |
853 | dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */ | |
854 | /* mark as having had error */ | |
855 | *dd->ipath_statusp |= IPATH_STATUS_HWERROR; | |
856 | *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF; | |
857 | } | |
858 | ||
8ec1077b BS |
859 | if (!noprint && *msg) { |
860 | if (iserr) | |
861 | ipath_dev_err(dd, "%s error\n", msg); | |
8ec1077b | 862 | } |
0fd41363 BS |
863 | if (dd->ipath_state_wanted & dd->ipath_flags) { |
864 | ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, " | |
865 | "waking\n", dd->ipath_state_wanted, | |
108ecf0d | 866 | dd->ipath_flags); |
0fd41363 | 867 | wake_up_interruptible(&ipath_state_wait); |
108ecf0d BS |
868 | } |
869 | ||
f5f99929 | 870 | return chkerrpkts; |
108ecf0d BS |
871 | } |
872 | ||
0f4fc5eb DO |
873 | /* |
874 | * try to cleanup as much as possible for anything that might have gone | |
875 | * wrong while in freeze mode, such as pio buffers being written by user | |
876 | * processes (causing armlaunch), send errors due to going into freeze mode, | |
877 | * etc., and try to avoid causing extra interrupts while doing so. | |
878 | * Forcibly update the in-memory pioavail register copies after cleanup | |
e2ab41ca DO |
879 | * because the chip won't do it while in freeze mode (the register values |
880 | * themselves are kept correct). | |
0f4fc5eb DO |
881 | * Make sure that we don't lose any important interrupts by using the chip |
882 | * feature that says that writing 0 to a bit in *clear that is set in | |
883 | * *status will cause an interrupt to be generated again (if allowed by | |
884 | * the *mask value). | |
885 | */ | |
886 | void ipath_clear_freeze(struct ipath_devdata *dd) | |
887 | { | |
0f4fc5eb DO |
888 | /* disable error interrupts, to avoid confusion */ |
889 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 0ULL); | |
890 | ||
78d1e02f DO |
891 | /* also disable interrupts; errormask is sometimes overwriten */ |
892 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL); | |
893 | ||
b4d390d8 | 894 | ipath_cancel_sends(dd, 1); |
e2ab41ca DO |
895 | |
896 | /* clear the freeze, and be sure chip saw it */ | |
0f4fc5eb DO |
897 | ipath_write_kreg(dd, dd->ipath_kregs->kr_control, |
898 | dd->ipath_control); | |
e2ab41ca | 899 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); |
0f4fc5eb | 900 | |
e2ab41ca | 901 | /* force in-memory update now we are out of freeze */ |
c4b4d16e | 902 | ipath_force_pio_avail_update(dd); |
0f4fc5eb | 903 | |
0f4fc5eb DO |
904 | /* |
905 | * force new interrupt if any hwerr, error or interrupt bits are | |
906 | * still set, and clear "safe" send packet errors related to freeze | |
907 | * and cancelling sends. Re-enable error interrupts before possible | |
908 | * force of re-interrupt on pending interrupts. | |
909 | */ | |
910 | ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, 0ULL); | |
911 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, | |
912 | E_SPKT_ERRS_IGNORE); | |
913 | ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, | |
78d1e02f DO |
914 | dd->ipath_errormask); |
915 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, -1LL); | |
0f4fc5eb DO |
916 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL); |
917 | } | |
918 | ||
919 | ||
108ecf0d BS |
920 | /* this is separate to allow for better optimization of ipath_intr() */ |
921 | ||
e193e332 | 922 | static noinline void ipath_bad_intr(struct ipath_devdata *dd, u32 *unexpectp) |
108ecf0d BS |
923 | { |
924 | /* | |
925 | * sometimes happen during driver init and unload, don't want | |
926 | * to process any interrupts at that point | |
927 | */ | |
928 | ||
929 | /* this is just a bandaid, not a fix, if something goes badly | |
930 | * wrong */ | |
931 | if (++*unexpectp > 100) { | |
932 | if (++*unexpectp > 105) { | |
933 | /* | |
934 | * ok, we must be taking somebody else's interrupts, | |
935 | * due to a messed up mptable and/or PIRQ table, so | |
936 | * unregister the interrupt. We've seen this during | |
937 | * linuxbios development work, and it may happen in | |
938 | * the future again. | |
939 | */ | |
51f65ebc | 940 | if (dd->pcidev && dd->ipath_irq) { |
108ecf0d BS |
941 | ipath_dev_err(dd, "Now %u unexpected " |
942 | "interrupts, unregistering " | |
943 | "interrupt handler\n", | |
944 | *unexpectp); | |
51f65ebc BS |
945 | ipath_dbg("free_irq of irq %d\n", |
946 | dd->ipath_irq); | |
947 | dd->ipath_f_free_irq(dd); | |
108ecf0d BS |
948 | } |
949 | } | |
7da0498e | 950 | if (ipath_read_ireg(dd, dd->ipath_kregs->kr_intmask)) { |
108ecf0d BS |
951 | ipath_dev_err(dd, "%u unexpected interrupts, " |
952 | "disabling interrupts completely\n", | |
953 | *unexpectp); | |
954 | /* | |
955 | * disable all interrupts, something is very wrong | |
956 | */ | |
957 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, | |
958 | 0ULL); | |
959 | } | |
960 | } else if (*unexpectp > 1) | |
961 | ipath_dbg("Interrupt when not ready, should not happen, " | |
962 | "ignoring\n"); | |
963 | } | |
964 | ||
e193e332 | 965 | static noinline void ipath_bad_regread(struct ipath_devdata *dd) |
108ecf0d BS |
966 | { |
967 | static int allbits; | |
968 | ||
969 | /* separate routine, for better optimization of ipath_intr() */ | |
970 | ||
971 | /* | |
972 | * We print the message and disable interrupts, in hope of | |
973 | * having a better chance of debugging the problem. | |
974 | */ | |
975 | ipath_dev_err(dd, | |
976 | "Read of interrupt status failed (all bits set)\n"); | |
977 | if (allbits++) { | |
978 | /* disable all interrupts, something is very wrong */ | |
979 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL); | |
980 | if (allbits == 2) { | |
981 | ipath_dev_err(dd, "Still bad interrupt status, " | |
982 | "unregistering interrupt\n"); | |
51f65ebc | 983 | dd->ipath_f_free_irq(dd); |
108ecf0d BS |
984 | } else if (allbits > 2) { |
985 | if ((allbits % 10000) == 0) | |
986 | printk("."); | |
987 | } else | |
988 | ipath_dev_err(dd, "Disabling interrupts, " | |
989 | "multiple errors\n"); | |
990 | } | |
991 | } | |
992 | ||
108ecf0d BS |
993 | static void handle_layer_pioavail(struct ipath_devdata *dd) |
994 | { | |
e342c119 | 995 | unsigned long flags; |
108ecf0d BS |
996 | int ret; |
997 | ||
b1c1b6a3 | 998 | ret = ipath_ib_piobufavail(dd->verbs_dev); |
108ecf0d | 999 | if (ret > 0) |
d562a5ae | 1000 | goto set; |
108ecf0d BS |
1001 | |
1002 | return; | |
d562a5ae | 1003 | set: |
e342c119 JG |
1004 | spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); |
1005 | dd->ipath_sendctrl |= INFINIPATH_S_PIOINTBUFAVAIL; | |
108ecf0d BS |
1006 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, |
1007 | dd->ipath_sendctrl); | |
e342c119 JG |
1008 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); |
1009 | spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); | |
108ecf0d BS |
1010 | } |
1011 | ||
13aef494 BS |
1012 | /* |
1013 | * Handle receive interrupts for user ports; this means a user | |
1014 | * process was waiting for a packet to arrive, and didn't want | |
1015 | * to poll | |
1016 | */ | |
9355fb6a | 1017 | static void handle_urcv(struct ipath_devdata *dd, u64 istat) |
108ecf0d BS |
1018 | { |
1019 | u64 portr; | |
1020 | int i; | |
1021 | int rcvdint = 0; | |
1022 | ||
2f01a700 AJ |
1023 | /* |
1024 | * test_and_clear_bit(IPATH_PORT_WAITING_RCV) and | |
1025 | * test_and_clear_bit(IPATH_PORT_WAITING_URG) below | |
1026 | * would both like timely updates of the bits so that | |
1027 | * we don't pass them by unnecessarily. the rmb() | |
1028 | * here ensures that we see them promptly -- the | |
1029 | * corresponding wmb()'s are in ipath_poll_urgent() | |
1030 | * and ipath_poll_next()... | |
1031 | */ | |
70c51da2 | 1032 | rmb(); |
9355fb6a RC |
1033 | portr = ((istat >> dd->ipath_i_rcvavail_shift) & |
1034 | dd->ipath_i_rcvavail_mask) | | |
1035 | ((istat >> dd->ipath_i_rcvurg_shift) & | |
1036 | dd->ipath_i_rcvurg_mask); | |
13aef494 | 1037 | for (i = 1; i < dd->ipath_cfgports; i++) { |
108ecf0d | 1038 | struct ipath_portdata *pd = dd->ipath_pd[i]; |
2ba3f56e | 1039 | |
f2d04231 | 1040 | if (portr & (1 << i) && pd && pd->port_cnt) { |
70c51da2 AJ |
1041 | if (test_and_clear_bit(IPATH_PORT_WAITING_RCV, |
1042 | &pd->port_flag)) { | |
d8274869 | 1043 | clear_bit(i + dd->ipath_r_intravail_shift, |
f2d04231 RW |
1044 | &dd->ipath_rcvctrl); |
1045 | wake_up_interruptible(&pd->port_wait); | |
1046 | rcvdint = 1; | |
70c51da2 AJ |
1047 | } else if (test_and_clear_bit(IPATH_PORT_WAITING_URG, |
1048 | &pd->port_flag)) { | |
1049 | pd->port_urgent++; | |
f2d04231 RW |
1050 | wake_up_interruptible(&pd->port_wait); |
1051 | } | |
108ecf0d BS |
1052 | } |
1053 | } | |
1054 | if (rcvdint) { | |
1055 | /* only want to take one interrupt, so turn off the rcv | |
9355fb6a | 1056 | * interrupt for all the ports that we set the rcv_waiting |
108ecf0d BS |
1057 | * (but never for kernel port) |
1058 | */ | |
1059 | ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, | |
1060 | dd->ipath_rcvctrl); | |
1061 | } | |
1062 | } | |
1063 | ||
7d12e780 | 1064 | irqreturn_t ipath_intr(int irq, void *data) |
108ecf0d BS |
1065 | { |
1066 | struct ipath_devdata *dd = data; | |
124b4dcb | 1067 | u64 istat, chk0rcv = 0; |
108ecf0d | 1068 | ipath_err_t estat = 0; |
108ecf0d | 1069 | irqreturn_t ret; |
13aef494 | 1070 | static unsigned unexpected = 0; |
9355fb6a | 1071 | u64 kportrbits; |
13aef494 BS |
1072 | |
1073 | ipath_stats.sps_ints++; | |
108ecf0d | 1074 | |
3588423f AJ |
1075 | if (dd->ipath_int_counter != (u32) -1) |
1076 | dd->ipath_int_counter++; | |
1077 | ||
13aef494 | 1078 | if (!(dd->ipath_flags & IPATH_PRESENT)) { |
c71c30dc | 1079 | /* |
13aef494 | 1080 | * This return value is not great, but we do not want the |
c71c30dc BS |
1081 | * interrupt core code to remove our interrupt handler |
1082 | * because we don't appear to be handling an interrupt | |
1083 | * during a chip reset. | |
1084 | */ | |
1085 | return IRQ_HANDLED; | |
1086 | } | |
1087 | ||
13aef494 BS |
1088 | /* |
1089 | * this needs to be flags&initted, not statusp, so we keep | |
1090 | * taking interrupts even after link goes down, etc. | |
1091 | * Also, we *must* clear the interrupt at some point, or we won't | |
1092 | * take it again, which can be real bad for errors, etc... | |
1093 | */ | |
1094 | ||
1095 | if (!(dd->ipath_flags & IPATH_INITTED)) { | |
1096 | ipath_bad_intr(dd, &unexpected); | |
1097 | ret = IRQ_NONE; | |
1098 | goto bail; | |
1099 | } | |
1100 | ||
7da0498e | 1101 | istat = ipath_read_ireg(dd, dd->ipath_kregs->kr_intstatus); |
f5f99929 | 1102 | |
108ecf0d BS |
1103 | if (unlikely(!istat)) { |
1104 | ipath_stats.sps_nullintr++; | |
1105 | ret = IRQ_NONE; /* not our interrupt, or already handled */ | |
1106 | goto bail; | |
1107 | } | |
1108 | if (unlikely(istat == -1)) { | |
1109 | ipath_bad_regread(dd); | |
1110 | /* don't know if it was our interrupt or not */ | |
1111 | ret = IRQ_NONE; | |
1112 | goto bail; | |
1113 | } | |
1114 | ||
108ecf0d BS |
1115 | if (unexpected) |
1116 | unexpected = 0; | |
1117 | ||
f62fe77a | 1118 | if (unlikely(istat & ~dd->ipath_i_bitsextant)) |
108ecf0d | 1119 | ipath_dev_err(dd, |
124b4dcb DO |
1120 | "interrupt with unknown interrupts %Lx set\n", |
1121 | istat & ~dd->ipath_i_bitsextant); | |
1122 | else if (istat & ~INFINIPATH_I_ERROR) /* errors do own printing */ | |
1123 | ipath_cdbg(VERBOSE, "intr stat=0x%Lx\n", istat); | |
108ecf0d | 1124 | |
124b4dcb | 1125 | if (istat & INFINIPATH_I_ERROR) { |
108ecf0d BS |
1126 | ipath_stats.sps_errints++; |
1127 | estat = ipath_read_kreg64(dd, | |
1128 | dd->ipath_kregs->kr_errorstatus); | |
1129 | if (!estat) | |
124b4dcb | 1130 | dev_info(&dd->pcidev->dev, "error interrupt (%Lx), " |
108ecf0d BS |
1131 | "but no error bits set!\n", istat); |
1132 | else if (estat == -1LL) | |
1133 | /* | |
1134 | * should we try clearing all, or hope next read | |
1135 | * works? | |
1136 | */ | |
1137 | ipath_dev_err(dd, "Read of error status failed " | |
1138 | "(all bits set); ignoring\n"); | |
1139 | else | |
9355fb6a | 1140 | chk0rcv |= handle_errors(dd, estat); |
108ecf0d BS |
1141 | } |
1142 | ||
1143 | if (istat & INFINIPATH_I_GPIO) { | |
13aef494 | 1144 | /* |
2c9446a1 BS |
1145 | * GPIO interrupts fall in two broad classes: |
1146 | * GPIO_2 indicates (on some HT4xx boards) that a packet | |
1147 | * has arrived for Port 0. Checking for this | |
1148 | * is controlled by flag IPATH_GPIO_INTR. | |
327a338d AJ |
1149 | * GPIO_3..5 on IBA6120 Rev2 and IBA6110 Rev4 chips indicate |
1150 | * errors that we need to count. Checking for this | |
2c9446a1 | 1151 | * is controlled by flag IPATH_GPIO_ERRINTRS. |
13aef494 | 1152 | */ |
2c9446a1 BS |
1153 | u32 gpiostatus; |
1154 | u32 to_clear = 0; | |
1155 | ||
1156 | gpiostatus = ipath_read_kreg32( | |
1157 | dd, dd->ipath_kregs->kr_gpio_status); | |
2ba3f56e | 1158 | /* First the error-counter case. */ |
2c9446a1 BS |
1159 | if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) && |
1160 | (dd->ipath_flags & IPATH_GPIO_ERRINTRS)) { | |
1161 | /* want to clear the bits we see asserted. */ | |
1162 | to_clear |= (gpiostatus & IPATH_GPIO_ERRINTR_MASK); | |
1163 | ||
1164 | /* | |
1165 | * Count appropriately, clear bits out of our copy, | |
1166 | * as they have been "handled". | |
1167 | */ | |
1168 | if (gpiostatus & (1 << IPATH_GPIO_RXUVL_BIT)) { | |
1169 | ipath_dbg("FlowCtl on UnsupVL\n"); | |
1170 | dd->ipath_rxfc_unsupvl_errs++; | |
1171 | } | |
1172 | if (gpiostatus & (1 << IPATH_GPIO_OVRUN_BIT)) { | |
1173 | ipath_dbg("Overrun Threshold exceeded\n"); | |
1174 | dd->ipath_overrun_thresh_errs++; | |
1175 | } | |
1176 | if (gpiostatus & (1 << IPATH_GPIO_LLI_BIT)) { | |
1177 | ipath_dbg("Local Link Integrity error\n"); | |
1178 | dd->ipath_lli_errs++; | |
1179 | } | |
1180 | gpiostatus &= ~IPATH_GPIO_ERRINTR_MASK; | |
108ecf0d | 1181 | } |
2c9446a1 BS |
1182 | /* Now the Port0 Receive case */ |
1183 | if ((gpiostatus & (1 << IPATH_GPIO_PORT0_BIT)) && | |
1184 | (dd->ipath_flags & IPATH_GPIO_INTR)) { | |
1185 | /* | |
1186 | * GPIO status bit 2 is set, and we expected it. | |
1187 | * clear it and indicate in p0bits. | |
1188 | * This probably only happens if a Port0 pkt | |
1189 | * arrives at _just_ the wrong time, and we | |
1190 | * handle that by seting chk0rcv; | |
1191 | */ | |
1192 | to_clear |= (1 << IPATH_GPIO_PORT0_BIT); | |
1193 | gpiostatus &= ~(1 << IPATH_GPIO_PORT0_BIT); | |
f5f99929 | 1194 | chk0rcv = 1; |
108ecf0d | 1195 | } |
8f140b40 | 1196 | if (gpiostatus) { |
2c9446a1 BS |
1197 | /* |
1198 | * Some unexpected bits remain. If they could have | |
1199 | * caused the interrupt, complain and clear. | |
6a733cdc MA |
1200 | * To avoid repetition of this condition, also clear |
1201 | * the mask. It is almost certainly due to error. | |
2c9446a1 | 1202 | */ |
8f140b40 AJ |
1203 | const u32 mask = (u32) dd->ipath_gpio_mask; |
1204 | ||
2c9446a1 BS |
1205 | if (mask & gpiostatus) { |
1206 | ipath_dbg("Unexpected GPIO IRQ bits %x\n", | |
1207 | gpiostatus & mask); | |
1208 | to_clear |= (gpiostatus & mask); | |
6a733cdc MA |
1209 | dd->ipath_gpio_mask &= ~(gpiostatus & mask); |
1210 | ipath_write_kreg(dd, | |
1211 | dd->ipath_kregs->kr_gpio_mask, | |
1212 | dd->ipath_gpio_mask); | |
2c9446a1 BS |
1213 | } |
1214 | } | |
1215 | if (to_clear) { | |
1216 | ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear, | |
1217 | (u64) to_clear); | |
1218 | } | |
108ecf0d BS |
1219 | } |
1220 | ||
1221 | /* | |
57abad25 BS |
1222 | * Clear the interrupt bits we found set, unless they are receive |
1223 | * related, in which case we already cleared them above, and don't | |
1224 | * want to clear them again, because we might lose an interrupt. | |
1225 | * Clear it early, so we "know" know the chip will have seen this by | |
1226 | * the time we process the queue, and will re-interrupt if necessary. | |
1227 | * The processor itself won't take the interrupt again until we return. | |
108ecf0d BS |
1228 | */ |
1229 | ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat); | |
1230 | ||
13aef494 | 1231 | /* |
9355fb6a RC |
1232 | * Handle kernel receive queues before checking for pio buffers |
1233 | * available since receives can overflow; piobuf waiters can afford | |
1234 | * a few extra cycles, since they were waiting anyway, and user's | |
1235 | * waiting for receive are at the bottom. | |
13aef494 | 1236 | */ |
9355fb6a RC |
1237 | kportrbits = (1ULL << dd->ipath_i_rcvavail_shift) | |
1238 | (1ULL << dd->ipath_i_rcvurg_shift); | |
1239 | if (chk0rcv || (istat & kportrbits)) { | |
1240 | istat &= ~kportrbits; | |
c59a80ac | 1241 | ipath_kreceive(dd->ipath_pd[0]); |
13aef494 | 1242 | } |
f5f99929 | 1243 | |
9355fb6a RC |
1244 | if (istat & ((dd->ipath_i_rcvavail_mask << dd->ipath_i_rcvavail_shift) | |
1245 | (dd->ipath_i_rcvurg_mask << dd->ipath_i_rcvurg_shift))) | |
13aef494 BS |
1246 | handle_urcv(dd, istat); |
1247 | ||
124b4dcb DO |
1248 | if (istat & (INFINIPATH_I_SDMAINT | INFINIPATH_I_SDMADISABLED)) |
1249 | handle_sdma_intr(dd, istat); | |
1250 | ||
108ecf0d | 1251 | if (istat & INFINIPATH_I_SPIOBUFAVAIL) { |
e342c119 JG |
1252 | unsigned long flags; |
1253 | ||
1254 | spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags); | |
1255 | dd->ipath_sendctrl &= ~INFINIPATH_S_PIOINTBUFAVAIL; | |
108ecf0d BS |
1256 | ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, |
1257 | dd->ipath_sendctrl); | |
e342c119 JG |
1258 | ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch); |
1259 | spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags); | |
108ecf0d | 1260 | |
e2ab41ca DO |
1261 | /* always process; sdma verbs uses PIO for acks and VL15 */ |
1262 | handle_layer_pioavail(dd); | |
108ecf0d BS |
1263 | } |
1264 | ||
108ecf0d BS |
1265 | ret = IRQ_HANDLED; |
1266 | ||
1267 | bail: | |
1268 | return ret; | |
1269 | } |