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IB/ipath: Generalize some xxx_SHIFT macros
[net-next-2.6.git] / drivers / infiniband / hw / ipath / ipath_iba6120.c
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dc741bbd 1/*
87427da5 2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
dc741bbd
BS		 3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33/*
34 * This file contains all of the code that is specific to the
525d0ca1 35 * InfiniPath PCIe chip.
dc741bbd
BS		 36 */
37
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41
42
43#include "ipath_kernel.h"
44#include "ipath_registers.h"
45
f5408ac7
BS		 46static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64);
47
dc741bbd
BS		 48/*
49 * This file contains all the chip-specific register information and
525d0ca1 50 * access functions for the QLogic InfiniPath PCI-Express chip.
dc741bbd 51 *
525d0ca1 52 * This lists the InfiniPath registers, in the actual chip layout.
dc741bbd
BS		 53 * This structure should never be directly accessed.
54 */
55struct _infinipath_do_not_use_kernel_regs {
56 unsigned long long Revision;
57 unsigned long long Control;
58 unsigned long long PageAlign;
59 unsigned long long PortCnt;
60 unsigned long long DebugPortSelect;
61 unsigned long long Reserved0;
62 unsigned long long SendRegBase;
63 unsigned long long UserRegBase;
64 unsigned long long CounterRegBase;
65 unsigned long long Scratch;
66 unsigned long long Reserved1;
67 unsigned long long Reserved2;
68 unsigned long long IntBlocked;
69 unsigned long long IntMask;
70 unsigned long long IntStatus;
71 unsigned long long IntClear;
72 unsigned long long ErrorMask;
73 unsigned long long ErrorStatus;
74 unsigned long long ErrorClear;
75 unsigned long long HwErrMask;
76 unsigned long long HwErrStatus;
77 unsigned long long HwErrClear;
78 unsigned long long HwDiagCtrl;
79 unsigned long long MDIO;
80 unsigned long long IBCStatus;
81 unsigned long long IBCCtrl;
82 unsigned long long ExtStatus;
83 unsigned long long ExtCtrl;
84 unsigned long long GPIOOut;
85 unsigned long long GPIOMask;
86 unsigned long long GPIOStatus;
87 unsigned long long GPIOClear;
88 unsigned long long RcvCtrl;
89 unsigned long long RcvBTHQP;
90 unsigned long long RcvHdrSize;
91 unsigned long long RcvHdrCnt;
92 unsigned long long RcvHdrEntSize;
93 unsigned long long RcvTIDBase;
94 unsigned long long RcvTIDCnt;
95 unsigned long long RcvEgrBase;
96 unsigned long long RcvEgrCnt;
97 unsigned long long RcvBufBase;
98 unsigned long long RcvBufSize;
99 unsigned long long RxIntMemBase;
100 unsigned long long RxIntMemSize;
101 unsigned long long RcvPartitionKey;
102 unsigned long long Reserved3;
103 unsigned long long RcvPktLEDCnt;
104 unsigned long long Reserved4[8];
105 unsigned long long SendCtrl;
106 unsigned long long SendPIOBufBase;
107 unsigned long long SendPIOSize;
108 unsigned long long SendPIOBufCnt;
109 unsigned long long SendPIOAvailAddr;
110 unsigned long long TxIntMemBase;
111 unsigned long long TxIntMemSize;
112 unsigned long long Reserved5;
113 unsigned long long PCIeRBufTestReg0;
114 unsigned long long PCIeRBufTestReg1;
115 unsigned long long Reserved51[6];
116 unsigned long long SendBufferError;
117 unsigned long long SendBufferErrorCONT1;
118 unsigned long long Reserved6SBE[6];
119 unsigned long long RcvHdrAddr0;
120 unsigned long long RcvHdrAddr1;
121 unsigned long long RcvHdrAddr2;
122 unsigned long long RcvHdrAddr3;
123 unsigned long long RcvHdrAddr4;
124 unsigned long long Reserved7RHA[11];
125 unsigned long long RcvHdrTailAddr0;
126 unsigned long long RcvHdrTailAddr1;
127 unsigned long long RcvHdrTailAddr2;
128 unsigned long long RcvHdrTailAddr3;
129 unsigned long long RcvHdrTailAddr4;
130 unsigned long long Reserved8RHTA[11];
131 unsigned long long Reserved9SW[8];
132 unsigned long long SerdesConfig0;
133 unsigned long long SerdesConfig1;
134 unsigned long long SerdesStatus;
135 unsigned long long XGXSConfig;
136 unsigned long long IBPLLCfg;
137 unsigned long long Reserved10SW2[3];
138 unsigned long long PCIEQ0SerdesConfig0;
139 unsigned long long PCIEQ0SerdesConfig1;
140 unsigned long long PCIEQ0SerdesStatus;
141 unsigned long long Reserved11;
142 unsigned long long PCIEQ1SerdesConfig0;
143 unsigned long long PCIEQ1SerdesConfig1;
144 unsigned long long PCIEQ1SerdesStatus;
145 unsigned long long Reserved12;
146};
147
148#define IPATH_KREG_OFFSET(field) (offsetof(struct \
149 _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
150#define IPATH_CREG_OFFSET(field) (offsetof( \
151 struct infinipath_counters, field) / sizeof(u64))
152
153static const struct ipath_kregs ipath_pe_kregs = {
154 .kr_control = IPATH_KREG_OFFSET(Control),
155 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
156 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
157 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
158 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
159 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
160 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
161 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
162 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
163 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
164 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
165 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
166 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
167 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
168 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
169 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
170 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
171 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
172 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
173 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
174 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
175 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
176 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
177 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
178 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
179 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
180 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
181 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
182 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
183 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
184 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
185 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
186 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
187 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
188 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
189 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
190 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
191 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
192 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
193 .kr_revision = IPATH_KREG_OFFSET(Revision),
194 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
195 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
196 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
197 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
198 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
199 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
200 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
201 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
202 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
203 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
204 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
205 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
206 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
207 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
208 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
209 .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
210
211 /*
c8c6f5d4
BS		 212 * These should not be used directly via ipath_write_kreg64(),
213 * use them with ipath_write_kreg64_port(),
dc741bbd
BS		 214 */
215 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
216 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
217
dc741bbd
BS		 218 /* The rcvpktled register controls one of the debug port signals, so
219 * a packet activity LED can be connected to it. */
220 .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
221 .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
222 .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
223 .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
224 .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
225 .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
226 .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
227 .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
228 .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
229};
230
231static const struct ipath_cregs ipath_pe_cregs = {
232 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
233 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
234 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
235 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
236 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
237 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
238 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
239 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
240 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
241 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
242 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
243 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
244 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
245 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
246 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
247 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
248 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
249 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
250 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
251 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
252 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
253 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
254 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
255 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
256 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
257 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
258 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
259 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
260 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
261 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
262 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
263 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
264 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
265};
266
267/* kr_intstatus, kr_intclear, kr_intmask bits */
f62fe77a
BS		 268#define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
269#define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
dc741bbd
BS		 270
271/* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
272#define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
273#define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
274#define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
275#define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
276#define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
277#define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
278#define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
279#define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
280#define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
281#define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
282#define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
283#define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL
284
285/* kr_extstatus bits */
286#define INFINIPATH_EXTS_FREQSEL 0x2
287#define INFINIPATH_EXTS_SERDESSEL 0x4
288#define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
289#define INFINIPATH_EXTS_MEMBIST_FOUND 0x0000000000008000
290
291#define _IPATH_GPIO_SDA_NUM 1
292#define _IPATH_GPIO_SCL_NUM 0
293
294#define IPATH_GPIO_SDA (1ULL << \
295 (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
296#define IPATH_GPIO_SCL (1ULL << \
297 (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
298
d8274869
DO		 299#define INFINIPATH_R_INTRAVAIL_SHIFT 16
300#define INFINIPATH_R_TAILUPD_SHIFT 31
301
8d588f8b
BS		 302/* 6120 specific hardware errors... */
303static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
304 INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
305 INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
306 /*
307 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
308 * parity or memory parity error failures, because most likely we
309 * won't be able to talk to the core of the chip. Nonetheless, we
310 * might see them, if they are in parts of the PCIe core that aren't
311 * essential.
312 */
313 INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
314 INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
315 INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
316 INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
317 INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
318 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
319 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
320};
321
9783ab40
BS		 322#define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
323 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
324 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
325
326static int ipath_pe_txe_recover(struct ipath_devdata *);
cf5b60aa
DO		 327static void ipath_pe_put_tid_2(struct ipath_devdata *, u64 __iomem *,
328 u32, unsigned long);
9783ab40 329
dc741bbd
BS		 330/**
331 * ipath_pe_handle_hwerrors - display hardware errors.
332 * @dd: the infinipath device
333 * @msg: the output buffer
334 * @msgl: the size of the output buffer
335 *
336 * Use same msg buffer as regular errors to avoid excessive stack
337 * use. Most hardware errors are catastrophic, but for right now,
338 * we'll print them and continue. We reuse the same message buffer as
339 * ipath_handle_errors() to avoid excessive stack usage.
340 */
ac2ae4c9
RD		 341static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
342 size_t msgl)
dc741bbd
BS		 343{
344 ipath_err_t hwerrs;
345 u32 bits, ctrl;
346 int isfatal = 0;
347 char bitsmsg[64];
aecd3b5a 348 int log_idx;
dc741bbd
BS		 349
350 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
351 if (!hwerrs) {
352 /*
353 * better than printing cofusing messages
354 * This seems to be related to clearing the crc error, or
355 * the pll error during init.
356 */
357 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
358 return;
359 } else if (hwerrs == ~0ULL) {
360 ipath_dev_err(dd, "Read of hardware error status failed "
361 "(all bits set); ignoring\n");
362 return;
363 }
364 ipath_stats.sps_hwerrs++;
365
366 /* Always clear the error status register, except MEMBISTFAIL,
367 * regardless of whether we continue or stop using the chip.
368 * We want that set so we know it failed, even across driver reload.
369 * We'll still ignore it in the hwerrmask. We do this partly for
370 * diagnostics, but also for support */
371 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
372 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
373
374 hwerrs &= dd->ipath_hwerrmask;
375
aecd3b5a
MA		 376 /* We log some errors to EEPROM, check if we have any of those. */
377 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
378 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
379 ipath_inc_eeprom_err(dd, log_idx, 1);
380
dc741bbd
BS		 381 /*
382 * make sure we get this much out, unless told to be quiet,
383 * or it's occurred within the last 5 seconds
384 */
89d1e09b
BS		 385 if ((hwerrs & ~(dd->ipath_lasthwerror |
386 ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
387 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
388 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
dc741bbd
BS		 389 (ipath_debug & __IPATH_VERBDBG))
390 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
391 "(cleared)\n", (unsigned long long) hwerrs);
392 dd->ipath_lasthwerror |= hwerrs;
393
f62fe77a 394 if (hwerrs & ~dd->ipath_hwe_bitsextant)
dc741bbd
BS		 395 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
396 "%llx set\n", (unsigned long long)
f62fe77a 397 (hwerrs & ~dd->ipath_hwe_bitsextant));
dc741bbd
BS		 398
399 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
400 if (ctrl & INFINIPATH_C_FREEZEMODE) {
89d1e09b
BS		 401 /*
402 * parity errors in send memory are recoverable,
403 * just cancel the send (if indicated in * sendbuffererror),
404 * count the occurrence, unfreeze (if no other handled
405 * hardware error bits are set), and continue. They can
406 * occur if a processor speculative read is done to the PIO
407 * buffer while we are sending a packet, for example.
408 */
9783ab40
BS		 409 if ((hwerrs & TXE_PIO_PARITY) && ipath_pe_txe_recover(dd))
410 hwerrs &= ~TXE_PIO_PARITY;
dc741bbd
BS		 411 if (hwerrs) {
412 /*
413 * if any set that we aren't ignoring only make the
414 * complaint once, in case it's stuck or recurring,
415 * and we get here multiple times
f5408ac7
BS		 416 * Force link down, so switch knows, and
417 * LEDs are turned off
dc741bbd
BS		 418 */
419 if (dd->ipath_flags & IPATH_INITTED) {
f5408ac7
BS		 420 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
421 ipath_setup_pe_setextled(dd,
422 INFINIPATH_IBCS_L_STATE_DOWN,
423 INFINIPATH_IBCS_LT_STATE_DISABLED);
ff0b8597
BS		 424 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
425 "mode), no longer usable, SN %.16s\n",
426 dd->ipath_serial);
dc741bbd
BS		 427 isfatal = 1;
428 }
429 /*
430 * Mark as having had an error for driver, and also
431 * for /sys and status word mapped to user programs.
432 * This marks unit as not usable, until reset
433 */
434 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
435 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
436 dd->ipath_flags &= ~IPATH_INITTED;
437 } else {
9380068f
DO		 438 static u32 freeze_cnt;
439
440 freeze_cnt++;
441 ipath_dbg("Clearing freezemode on ignored or recovered "
442 "hardware error (%u)\n", freeze_cnt);
0f4fc5eb 443 ipath_clear_freeze(dd);
dc741bbd
BS		 444 }
445 }
446
447 *msg = '\0';
448
449 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
525d0ca1 450 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
dc741bbd
BS		 451 msgl);
452 /* ignore from now on, so disable until driver reloaded */
453 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
454 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
455 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
456 dd->ipath_hwerrmask);
457 }
8d588f8b
BS		 458
459 ipath_format_hwerrors(hwerrs,
460 ipath_6120_hwerror_msgs,
461 sizeof(ipath_6120_hwerror_msgs)/
462 sizeof(ipath_6120_hwerror_msgs[0]),
463 msg, msgl);
464
dc741bbd
BS		 465 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
466 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
467 bits = (u32) ((hwerrs >>
468 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
469 INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
470 snprintf(bitsmsg, sizeof bitsmsg,
471 "[PCIe Mem Parity Errs %x] ", bits);
472 strlcat(msg, bitsmsg, msgl);
473 }
dc741bbd
BS		 474
475#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
476 INFINIPATH_HWE_COREPLL_RFSLIP )
477
478 if (hwerrs & _IPATH_PLL_FAIL) {
479 snprintf(bitsmsg, sizeof bitsmsg,
525d0ca1 480 "[PLL failed (%llx), InfiniPath hardware unusable]",
dc741bbd
BS		 481 (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
482 strlcat(msg, bitsmsg, msgl);
483 /* ignore from now on, so disable until driver reloaded */
484 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
485 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
486 dd->ipath_hwerrmask);
487 }
488
489 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
490 /*
491 * If it occurs, it is left masked since the eternal
492 * interface is unused
493 */
494 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
495 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
496 dd->ipath_hwerrmask);
497 }
498
f5408ac7
BS		 499 if (*msg)
500 ipath_dev_err(dd, "%s hardware error\n", msg);
dc741bbd
BS		 501 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
502 /*
503 * for /sys status file ; if no trailing } is copied, we'll
504 * know it was truncated.
505 */
506 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
507 "{%s}", msg);
508 }
509}
510
511/**
512 * ipath_pe_boardname - fill in the board name
513 * @dd: the infinipath device
514 * @name: the output buffer
515 * @namelen: the size of the output buffer
516 *
517 * info is based on the board revision register
518 */
519static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
520 size_t namelen)
521{
522 char *n = NULL;
523 u8 boardrev = dd->ipath_boardrev;
524 int ret;
525
526 switch (boardrev) {
527 case 0:
528 n = "InfiniPath_Emulation";
529 break;
530 case 1:
525d0ca1 531 n = "InfiniPath_QLE7140-Bringup";
dc741bbd
BS		 532 break;
533 case 2:
525d0ca1 534 n = "InfiniPath_QLE7140";
dc741bbd
BS		 535 break;
536 case 3:
525d0ca1 537 n = "InfiniPath_QMI7140";
dc741bbd
BS		 538 break;
539 case 4:
525d0ca1
BS		 540 n = "InfiniPath_QEM7140";
541 break;
542 case 5:
543 n = "InfiniPath_QMH7140";
dc741bbd 544 break;
bf3258ec
BS		 545 case 6:
546 n = "InfiniPath_QLE7142";
547 break;
dc741bbd
BS		 548 default:
549 ipath_dev_err(dd,
550 "Don't yet know about board with ID %u\n",
551 boardrev);
525d0ca1 552 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
dc741bbd
BS		 553 boardrev);
554 break;
555 }
556 if (n)
557 snprintf(name, namelen, "%s", n);
558
8307c28e 559 if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
525d0ca1 560 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
dc741bbd
BS		 561 dd->ipath_majrev, dd->ipath_minrev);
562 ret = 1;
cf5b60aa 563 } else {
dc741bbd 564 ret = 0;
cf5b60aa
DO		 565 if (dd->ipath_minrev >= 2)
566 dd->ipath_f_put_tid = ipath_pe_put_tid_2;
567 }
dc741bbd
BS		 568
569 return ret;
570}
571
572/**
573 * ipath_pe_init_hwerrors - enable hardware errors
574 * @dd: the infinipath device
575 *
576 * now that we have finished initializing everything that might reasonably
577 * cause a hardware error, and cleared those errors bits as they occur,
578 * we can enable hardware errors in the mask (potentially enabling
579 * freeze mode), and enable hardware errors as errors (along with
580 * everything else) in errormask
581 */
ac2ae4c9 582static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
dc741bbd
BS		 583{
584 ipath_err_t val;
585 u64 extsval;
586
587 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
588
589 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
590 ipath_dev_err(dd, "MemBIST did not complete!\n");
9783ab40
BS		 591 if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
592 ipath_dbg("MemBIST corrected\n");
dc741bbd
BS		 593
594 val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */
595
596 if (!dd->ipath_boardrev) // no PLL for Emulator
597 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
598
2c9446a1
BS		 599 if (dd->ipath_minrev < 2) {
600 /* workaround bug 9460 in internal interface bus parity
601 * checking. Fixed (HW bug 9490) in Rev2.
602 */
603 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
604 }
dc741bbd
BS		 605 dd->ipath_hwerrmask = val;
606}
607
608/**
609 * ipath_pe_bringup_serdes - bring up the serdes
610 * @dd: the infinipath device
611 */
ac2ae4c9 612static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
dc741bbd 613{
44f8e3f3 614 u64 val, config1, prev_val;
2c9446a1 615 int ret = 0;
dc741bbd
BS		 616
617 ipath_dbg("Trying to bringup serdes\n");
618
619 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
620 INFINIPATH_HWE_SERDESPLLFAILED) {
621 ipath_dbg("At start, serdes PLL failed bit set "
622 "in hwerrstatus, clearing and continuing\n");
623 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
624 INFINIPATH_HWE_SERDESPLLFAILED);
625 }
626
627 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
628 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
629
630 ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
631 "xgxsconfig %llx\n", (unsigned long long) val,
632 (unsigned long long) config1, (unsigned long long)
633 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
634
635 /*
636 * Force reset on, also set rxdetect enable. Must do before reading
637 * serdesstatus at least for simulation, or some of the bits in
638 * serdes status will come back as undefined and cause simulation
639 * failures
640 */
641 val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
642 | INFINIPATH_SERDC0_L1PWR_DN;
643 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
644 /* be sure chip saw it */
44f8e3f3 645 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
dc741bbd
BS		 646 udelay(5); /* need pll reset set at least for a bit */
647 /*
648 * after PLL is reset, set the per-lane Resets and TxIdle and
649 * clear the PLL reset and rxdetect (to get falling edge).
650 * Leave L1PWR bits set (permanently)
651 */
652 val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
653 | INFINIPATH_SERDC0_L1PWR_DN);
654 val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
655 ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
656 "and txidle (%llx)\n", (unsigned long long) val);
657 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
658 /* be sure chip saw it */
44f8e3f3 659 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
dc741bbd
BS		 660 /* need PLL reset clear for at least 11 usec before lane
661 * resets cleared; give it a few more to be sure */
662 udelay(15);
663 val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
664
665 ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
666 "(writing %llx)\n", (unsigned long long) val);
667 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
668 /* be sure chip saw it */
669 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
670
671 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2c9446a1 672 prev_val = val;
dc741bbd
BS		 673 if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
674 INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
675 val &=
676 ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
677 INFINIPATH_XGXS_MDIOADDR_SHIFT);
678 /* MDIO address 3 */
679 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
dc741bbd
BS		 680 }
681 if (val & INFINIPATH_XGXS_RESET) {
682 val &= ~INFINIPATH_XGXS_RESET;
dc741bbd 683 }
30fc5c31
BS		 684 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
685 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
686 /* need to compensate for Tx inversion in partner */
687 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
688 INFINIPATH_XGXS_RX_POL_SHIFT);
689 val |= dd->ipath_rx_pol_inv <<
690 INFINIPATH_XGXS_RX_POL_SHIFT;
30fc5c31 691 }
2c9446a1 692 if (val != prev_val)
dc741bbd
BS		 693 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
694
695 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
696
697 /* clear current and de-emphasis bits */
698 config1 &= ~0x0ffffffff00ULL;
699 /* set current to 20ma */
700 config1 |= 0x00000000000ULL;
701 /* set de-emphasis to -5.68dB */
702 config1 |= 0x0cccc000000ULL;
703 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
704
705 ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
706 "config1=%llx, sstatus=%llx xgxs=%llx\n",
707 (unsigned long long) val, (unsigned long long) config1,
708 (unsigned long long)
709 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
710 (unsigned long long)
711 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
712
713 if (!ipath_waitfor_mdio_cmdready(dd)) {
714 ipath_write_kreg(
715 dd, dd->ipath_kregs->kr_mdio,
716 ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
717 IPATH_MDIO_CTRL_XGXS_REG_8, 0));
718 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
719 IPATH_MDIO_DATAVALID, &val))
720 ipath_dbg("Never got MDIO data for XGXS "
721 "status read\n");
722 else
723 ipath_cdbg(VERBOSE, "MDIO Read reg8, "
724 "'bank' 31 %x\n", (u32) val);
725 } else
726 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
727
728 return ret;
729}
730
731/**
732 * ipath_pe_quiet_serdes - set serdes to txidle
733 * @dd: the infinipath device
734 * Called when driver is being unloaded
735 */
ac2ae4c9 736static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
dc741bbd
BS		 737{
738 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
739
740 val |= INFINIPATH_SERDC0_TXIDLE;
741 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
742 (unsigned long long) val);
743 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
744}
745
dc741bbd
BS		 746static int ipath_pe_intconfig(struct ipath_devdata *dd)
747{
2c9446a1
BS		 748 u32 chiprev;
749
750 /*
751 * If the chip supports added error indication via GPIO pins,
752 * enable interrupts on those bits so the interrupt routine
753 * can count the events. Also set flag so interrupt routine
754 * can know they are expected.
755 */
756 chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
757 if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
758 /* Rev2+ reports extra errors via internal GPIO pins */
759 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
8f140b40
AJ		 760 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
761 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
762 dd->ipath_gpio_mask);
2c9446a1 763 }
dc741bbd
BS		 764 return 0;
765}
766
767/**
768 * ipath_setup_pe_setextled - set the state of the two external LEDs
769 * @dd: the infinipath device
770 * @lst: the L state
771 * @ltst: the LT state
772
773 * These LEDs indicate the physical and logical state of IB link.
774 * For this chip (at least with recommended board pinouts), LED1
775 * is Yellow (logical state) and LED2 is Green (physical state),
776 *
777 * Note: We try to match the Mellanox HCA LED behavior as best
778 * we can. Green indicates physical link state is OK (something is
779 * plugged in, and we can train).
780 * Amber indicates the link is logically up (ACTIVE).
781 * Mellanox further blinks the amber LED to indicate data packet
782 * activity, but we have no hardware support for that, so it would
783 * require waking up every 10-20 msecs and checking the counters
784 * on the chip, and then turning the LED off if appropriate. That's
785 * visible overhead, so not something we will do.
786 *
787 */
788static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
789 u64 ltst)
790{
791 u64 extctl;
17b2eb9f 792 unsigned long flags = 0;
dc741bbd
BS		 793
794 /* the diags use the LED to indicate diag info, so we leave
795 * the external LED alone when the diags are running */
796 if (ipath_diag_inuse)
797 return;
798
82466f00
MA		 799 /* Allow override of LED display for, e.g. Locating system in rack */
800 if (dd->ipath_led_override) {
801 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
802 ? INFINIPATH_IBCS_LT_STATE_LINKUP
803 : INFINIPATH_IBCS_LT_STATE_DISABLED;
804 lst = (dd->ipath_led_override & IPATH_LED_LOG)
805 ? INFINIPATH_IBCS_L_STATE_ACTIVE
806 : INFINIPATH_IBCS_L_STATE_DOWN;
807 }
808
17b2eb9f 809 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
dc741bbd
BS		 810 extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
811 INFINIPATH_EXTC_LED2PRIPORT_ON);
812
813 if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
814 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
815 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
816 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
817 dd->ipath_extctrl = extctl;
818 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
17b2eb9f 819 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
dc741bbd
BS		 820}
821
822/**
823 * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
824 * @dd: the infinipath device
825 *
826 * This is called during driver unload.
827 * We do the pci_disable_msi here, not in generic code, because it
525d0ca1
BS		 828 * isn't used for the HT chips. If we do end up needing pci_enable_msi
829 * at some point in the future for HT, we'll move the call back
dc741bbd
BS		 830 * into the main init_one code.
831 */
832static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
833{
834 dd->ipath_msi_lo = 0; /* just in case unload fails */
835 pci_disable_msi(dd->pcidev);
836}
837
838/**
839 * ipath_setup_pe_config - setup PCIe config related stuff
840 * @dd: the infinipath device
841 * @pdev: the PCI device
842 *
843 * The pci_enable_msi() call will fail on systems with MSI quirks
844 * such as those with AMD8131, even if the device of interest is not
845 * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
846 * late in 2.6.16).
847 * All that can be done is to edit the kernel source to remove the quirk
848 * check until that is fixed.
525d0ca1
BS		 849 * We do not need to call enable_msi() for our HyperTransport chip,
850 * even though it uses MSI, and we want to avoid the quirk warning, so
851 * So we call enable_msi only for PCIe. If we do end up needing
852 * pci_enable_msi at some point in the future for HT, we'll move the
dc741bbd
BS		 853 * call back into the main init_one code.
854 * We save the msi lo and hi values, so we can restore them after
855 * chip reset (the kernel PCI infrastructure doesn't yet handle that
856 * correctly).
857 */
858static int ipath_setup_pe_config(struct ipath_devdata *dd,
859 struct pci_dev *pdev)
860{
861 int pos, ret;
862
863 dd->ipath_msi_lo = 0; /* used as a flag during reset processing */
864 ret = pci_enable_msi(dd->pcidev);
865 if (ret)
866 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
867 "interrupts may not work\n", ret);
868 /* continue even if it fails, we may still be OK... */
0a1336c8 869 dd->ipath_irq = pdev->irq;
dc741bbd
BS		 870
871 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
872 u16 control;
873 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
874 &dd->ipath_msi_lo);
875 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
876 &dd->ipath_msi_hi);
877 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
878 &control);
879 /* now save the data (vector) info */
880 pci_read_config_word(dd->pcidev,
881 pos + ((control & PCI_MSI_FLAGS_64BIT)
882 ? 12 : 8),
883 &dd->ipath_msi_data);
884 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
885 "0x%x, control=0x%x\n", dd->ipath_msi_data,
886 pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
887 control);
888 /* we save the cachelinesize also, although it doesn't
889 * really matter */
890 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
891 &dd->ipath_pci_cacheline);
892 } else
893 ipath_dev_err(dd, "Can't find MSI capability, "
894 "can't save MSI settings for reset\n");
895 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
896 u16 linkstat;
897 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
898 &linkstat);
899 linkstat >>= 4;
900 linkstat &= 0x1f;
901 if (linkstat != 8)
902 ipath_dev_err(dd, "PCIe width %u, "
903 "performance reduced\n", linkstat);
904 }
905 else
906 ipath_dev_err(dd, "Can't find PCI Express "
907 "capability!\n");
908 return 0;
909}
910
f62fe77a 911static void ipath_init_pe_variables(struct ipath_devdata *dd)
dc741bbd
BS		 912{
913 /*
914 * bits for selecting i2c direction and values,
915 * used for I2C serial flash
916 */
f62fe77a
BS		 917 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
918 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
919 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
920 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
dc741bbd 921
d8274869
DO		 922 /* Fill in shifts for RcvCtrl. */
923 dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
924 dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
925 dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
926 dd->ipath_r_portcfg_shift = 0; /* Not on IBA6120 */
927
dc741bbd 928 /* variables for sanity checking interrupt and errors */
f62fe77a 929 dd->ipath_hwe_bitsextant =
dc741bbd
BS		 930 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
931 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
89d1e09b
BS		 932 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
933 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
dc741bbd
BS		 934 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
935 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
936 INFINIPATH_HWE_PCIE1PLLFAILED |
937 INFINIPATH_HWE_PCIE0PLLFAILED |
938 INFINIPATH_HWE_PCIEPOISONEDTLP |
939 INFINIPATH_HWE_PCIECPLTIMEOUT |
940 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
941 INFINIPATH_HWE_PCIEBUSPARITYXADM |
942 INFINIPATH_HWE_PCIEBUSPARITYRADM |
943 INFINIPATH_HWE_MEMBISTFAILED |
944 INFINIPATH_HWE_COREPLL_FBSLIP |
945 INFINIPATH_HWE_COREPLL_RFSLIP |
946 INFINIPATH_HWE_SERDESPLLFAILED |
947 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
948 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
f62fe77a 949 dd->ipath_i_bitsextant =
dc741bbd
BS		 950 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
951 (INFINIPATH_I_RCVAVAIL_MASK <<
952 INFINIPATH_I_RCVAVAIL_SHIFT) |
953 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
954 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
f62fe77a 955 dd->ipath_e_bitsextant =
dc741bbd
BS		 956 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
957 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
958 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
959 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
960 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
961 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
962 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
963 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
964 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
965 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
966 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
967 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
968 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
969 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
970 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
971 INFINIPATH_E_HARDWARE;
972
f62fe77a
BS		 973 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
974 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
aecd3b5a
MA		 975
976 /*
977 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
978 * 2 is Some Misc, 3 is reserved for future.
979 */
980 dd->ipath_eep_st_masks[0].hwerrs_to_log =
981 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
982 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
983
984 /* Ignore errors in PIO/PBC on systems with unordered write-combining */
985 if (ipath_unordered_wc())
986 dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
987
988 dd->ipath_eep_st_masks[1].hwerrs_to_log =
989 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
990 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
991
992 dd->ipath_eep_st_masks[2].errs_to_log =
993 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
994
995
dc741bbd
BS		 996}
997
998/* setup the MSI stuff again after a reset. I'd like to just call
999 * pci_enable_msi() and request_irq() again, but when I do that,
1000 * the MSI enable bit doesn't get set in the command word, and
1001 * we switch to to a different interrupt vector, which is confusing,
1002 * so I instead just do it all inline. Perhaps somehow can tie this
1003 * into the PCIe hotplug support at some point
1004 * Note, because I'm doing it all here, I don't call pci_disable_msi()
1005 * or free_irq() at the start of ipath_setup_pe_reset().
1006 */
1007static int ipath_reinit_msi(struct ipath_devdata *dd)
1008{
1009 int pos;
1010 u16 control;
1011 int ret;
1012
1013 if (!dd->ipath_msi_lo) {
1014 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
1015 "initial setup failed?\n");
1016 ret = 0;
1017 goto bail;
1018 }
1019
1020 if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1021 ipath_dev_err(dd, "Can't find MSI capability, "
1022 "can't restore MSI settings\n");
1023 ret = 0;
1024 goto bail;
1025 }
1026 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1027 dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1028 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1029 dd->ipath_msi_lo);
1030 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1031 dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1032 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1033 dd->ipath_msi_hi);
1034 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1035 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1036 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1037 "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1038 control, control | PCI_MSI_FLAGS_ENABLE);
1039 control |= PCI_MSI_FLAGS_ENABLE;
1040 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1041 control);
1042 }
1043 /* now rewrite the data (vector) info */
1044 pci_write_config_word(dd->pcidev, pos +
1045 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1046 dd->ipath_msi_data);
1047 /* we restore the cachelinesize also, although it doesn't really
1048 * matter */
1049 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1050 dd->ipath_pci_cacheline);
1051 /* and now set the pci master bit again */
1052 pci_set_master(dd->pcidev);
1053 ret = 1;
1054
1055bail:
1056 return ret;
1057}
1058
1059/* This routine sleeps, so it can only be called from user context, not
1060 * from interrupt context. If we need interrupt context, we can split
1061 * it into two routines.
1062*/
1063static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1064{
1065 u64 val;
1066 int i;
1067 int ret;
1068
1069 /* Use ERROR so it shows up in logs, etc. */
525d0ca1 1070 ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
c71c30dc
BS		 1071 /* keep chip from being accessed in a few places */
1072 dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
dc741bbd
BS		 1073 val = dd->ipath_control | INFINIPATH_C_RESET;
1074 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1075 mb();
1076
1077 for (i = 1; i <= 5; i++) {
1078 int r;
1079 /* allow MBIST, etc. to complete; longer on each retry.
1080 * We sometimes get machine checks from bus timeout if no
1081 * response, so for now, make it *really* long.
1082 */
1083 msleep(1000 + (1 + i) * 2000);
1084 if ((r =
1085 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1086 dd->ipath_pcibar0)))
1087 ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1088 r);
1089 if ((r =
1090 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1091 dd->ipath_pcibar1)))
1092 ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1093 r);
1094 /* now re-enable memory access */
1095 if ((r = pci_enable_device(dd->pcidev)))
1096 ipath_dev_err(dd, "pci_enable_device failed after "
1097 "reset: %d\n", r);
c71c30dc
BS		 1098 /* whether it worked or not, mark as present, again */
1099 dd->ipath_flags |= IPATH_PRESENT;
dc741bbd
BS		 1100 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1101 if (val == dd->ipath_revision) {
1102 ipath_cdbg(VERBOSE, "Got matching revision "
1103 "register %llx on try %d\n",
1104 (unsigned long long) val, i);
1105 ret = ipath_reinit_msi(dd);
1106 goto bail;
1107 }
1108 /* Probably getting -1 back */
1109 ipath_dbg("Didn't get expected revision register, "
1110 "got %llx, try %d\n", (unsigned long long) val,
1111 i + 1);
1112 }
1113 ret = 0; /* failed */
1114
1115bail:
1116 return ret;
1117}
1118
1119/**
1120 * ipath_pe_put_tid - write a TID in chip
1121 * @dd: the infinipath device
1122 * @tidptr: pointer to the expected TID (in chip) to udpate
f716cdfe 1123 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
dc741bbd
BS		 1124 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1125 *
1126 * This exists as a separate routine to allow for special locking etc.
1127 * It's used for both the full cleanup on exit, as well as the normal
1128 * setup and teardown.
1129 */
1130static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1131 u32 type, unsigned long pa)
1132{
1133 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1134 unsigned long flags = 0; /* keep gcc quiet */
1135
1136 if (pa != dd->ipath_tidinvalid) {
1137 if (pa & ((1U << 11) - 1)) {
1138 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1139 "not 4KB aligned!\n", pa);
1140 return;
1141 }
1142 pa >>= 11;
1143 /* paranoia check */
1144 if (pa & (7<<29))
1145 ipath_dev_err(dd,
1146 "BUG: Physical page address 0x%lx "
1147 "has bits set in 31-29\n", pa);
1148
f716cdfe 1149 if (type == RCVHQ_RCV_TYPE_EAGER)
dc741bbd
BS		 1150 pa |= dd->ipath_tidtemplate;
1151 else /* for now, always full 4KB page */
1152 pa |= 2 << 29;
1153 }
1154
9ef8617a
DO		 1155 /*
1156 * Workaround chip bug 9437 by writing the scratch register
1157 * before and after the TID, and with an io write barrier.
1158 * We use a spinlock around the writes, so they can't intermix
1159 * with other TID (eager or expected) writes (the chip bug
1160 * is triggered by back to back TID writes). Unfortunately, this
1161 * call can be done from interrupt level for the port 0 eager TIDs,
1162 * so we have to use irqsave locks.
dc741bbd
BS		 1163 */
1164 spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1165 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1166 if (dd->ipath_kregbase)
1167 writel(pa, tidp32);
1168 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1169 mmiowb();
1170 spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1171}
2c9446a1
BS		 1172/**
1173 * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1174 * @dd: the infinipath device
1175 * @tidptr: pointer to the expected TID (in chip) to udpate
f716cdfe 1176 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
2c9446a1
BS		 1177 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1178 *
1179 * This exists as a separate routine to allow for selection of the
1180 * appropriate "flavor". The static calls in cleanup just use the
1181 * revision-agnostic form, as they are not performance critical.
1182 */
1183static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1184 u32 type, unsigned long pa)
1185{
1186 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1187
1188 if (pa != dd->ipath_tidinvalid) {
1189 if (pa & ((1U << 11) - 1)) {
1190 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1fd3b40f 1191 "not 2KB aligned!\n", pa);
2c9446a1
BS		 1192 return;
1193 }
1194 pa >>= 11;
1195 /* paranoia check */
1196 if (pa & (7<<29))
1197 ipath_dev_err(dd,
1198 "BUG: Physical page address 0x%lx "
1199 "has bits set in 31-29\n", pa);
1200
f716cdfe 1201 if (type == RCVHQ_RCV_TYPE_EAGER)
2c9446a1
BS		 1202 pa |= dd->ipath_tidtemplate;
1203 else /* for now, always full 4KB page */
1204 pa |= 2 << 29;
1205 }
1206 if (dd->ipath_kregbase)
1207 writel(pa, tidp32);
1208 mmiowb();
1209}
1210
dc741bbd
BS		 1211
1212/**
1213 * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1214 * @dd: the infinipath device
1215 * @port: the port
1216 *
1217 * clear all TID entries for a port, expected and eager.
525d0ca1 1218 * Used from ipath_close(). On this chip, TIDs are only 32 bits,
dc741bbd
BS		 1219 * not 64, but they are still on 64 bit boundaries, so tidbase
1220 * is declared as u64 * for the pointer math, even though we write 32 bits
1221 */
1222static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1223{
1224 u64 __iomem *tidbase;
1225 unsigned long tidinv;
1226 int i;
1227
1228 if (!dd->ipath_kregbase)
1229 return;
1230
1231 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1232
1233 tidinv = dd->ipath_tidinvalid;
1234 tidbase = (u64 __iomem *)
1235 ((char __iomem *)(dd->ipath_kregbase) +
1236 dd->ipath_rcvtidbase +
1237 port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1238
1239 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
cf5b60aa 1240 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
f716cdfe 1241 tidinv);
dc741bbd
BS		 1242
1243 tidbase = (u64 __iomem *)
1244 ((char __iomem *)(dd->ipath_kregbase) +
1245 dd->ipath_rcvegrbase +
1246 port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1247
1248 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
cf5b60aa 1249 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
f716cdfe 1250 tidinv);
dc741bbd
BS		 1251}
1252
1253/**
1254 * ipath_pe_tidtemplate - setup constants for TID updates
1255 * @dd: the infinipath device
1256 *
1257 * We setup stuff that we use a lot, to avoid calculating each time
1258 */
1259static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1260{
1261 u32 egrsize = dd->ipath_rcvegrbufsize;
1262
1263 /* For now, we always allocate 4KB buffers (at init) so we can
1264 * receive max size packets. We may want a module parameter to
1265 * specify 2KB or 4KB and/or make be per port instead of per device
1266 * for those who want to reduce memory footprint. Note that the
1267 * ipath_rcvhdrentsize size must be large enough to hold the largest
1268 * IB header (currently 96 bytes) that we expect to handle (plus of
1269 * course the 2 dwords of RHF).
1270 */
1271 if (egrsize == 2048)
1272 dd->ipath_tidtemplate = 1U << 29;
1273 else if (egrsize == 4096)
1274 dd->ipath_tidtemplate = 2U << 29;
1275 else {
1276 egrsize = 4096;
1277 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1278 "%u, using %u\n", dd->ipath_rcvegrbufsize,
1279 egrsize);
1280 dd->ipath_tidtemplate = 2U << 29;
1281 }
1282 dd->ipath_tidinvalid = 0;
1283}
1284
1285static int ipath_pe_early_init(struct ipath_devdata *dd)
1286{
1287 dd->ipath_flags |= IPATH_4BYTE_TID;
210d6ca3
RC		 1288 if (ipath_unordered_wc())
1289 dd->ipath_flags |= IPATH_PIO_FLUSH_WC;
dc741bbd
BS		 1290
1291 /*
525d0ca1
BS		 1292 * For openfabrics, we need to be able to handle an IB header of
1293 * 24 dwords. HT chip has arbitrary sized receive buffers, so we
1294 * made them the same size as the PIO buffers. This chip does not
dc741bbd
BS		 1295 * handle arbitrary size buffers, so we need the header large enough
1296 * to handle largest IB header, but still have room for a 2KB MTU
1297 * standard IB packet.
1298 */
1299 dd->ipath_rcvhdrentsize = 24;
1300 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1301
525d0ca1
BS		 1302 /*
1303 * To truly support a 4KB MTU (for usermode), we need to
1304 * bump this to a larger value. For now, we use them for
1305 * the kernel only.
dc741bbd
BS		 1306 */
1307 dd->ipath_rcvegrbufsize = 2048;
1308 /*
1309 * the min() check here is currently a nop, but it may not always
1310 * be, depending on just how we do ipath_rcvegrbufsize
1311 */
1312 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1313 dd->ipath_rcvegrbufsize +
1314 (dd->ipath_rcvhdrentsize << 2));
1315 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1316
1317 /*
525d0ca1 1318 * We can request a receive interrupt for 1 or
dc741bbd 1319 * more packets from current offset. For now, we set this
525d0ca1 1320 * up for a single packet.
dc741bbd
BS		 1321 */
1322 dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1323
f2080fa3
BS		 1324 ipath_get_eeprom_info(dd);
1325
dc741bbd
BS		 1326 return 0;
1327}
1328
1329int __attribute__((weak)) ipath_unordered_wc(void)
1330{
1331 return 0;
1332}
1333
1334/**
1335 * ipath_init_pe_get_base_info - set chip-specific flags for user code
2c9446a1 1336 * @pd: the infinipath port
dc741bbd
BS		 1337 * @kbase: ipath_base_info pointer
1338 *
1339 * We set the PCIE flag because the lower bandwidth on PCIe vs
d08df601 1340 * HyperTransport can affect some user packet algorithms.
dc741bbd
BS		 1341 */
1342static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1343{
1344 struct ipath_base_info *kinfo = kbase;
2c9446a1 1345 struct ipath_devdata *dd;
dc741bbd
BS		 1346
1347 if (ipath_unordered_wc()) {
1348 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1349 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1350 }
1351 else
1352 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1353
2c9446a1
BS		 1354 if (pd == NULL)
1355 goto done;
1356
1357 dd = pd->port_dd;
1358
2c9446a1 1359done:
20bed343
AJ		 1360 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE |
1361 IPATH_RUNTIME_FORCE_PIOAVAIL | IPATH_RUNTIME_PIO_REGSWAPPED;
dc741bbd
BS		 1362 return 0;
1363}
1364
51f65ebc
BS		 1365static void ipath_pe_free_irq(struct ipath_devdata *dd)
1366{
1367 free_irq(dd->ipath_irq, dd);
1368 dd->ipath_irq = 0;
1369}
1370
9783ab40
BS		 1371/*
1372 * On platforms using this chip, and not having ordered WC stores, we
1373 * can get TXE parity errors due to speculative reads to the PIO buffers,
1374 * and this, due to a chip bug can result in (many) false parity error
1375 * reports. So it's a debug print on those, and an info print on systems
1376 * where the speculative reads don't occur.
1377 * Because we can get lots of false errors, we have no upper limit
1378 * on recovery attempts on those platforms.
1379 */
1380static int ipath_pe_txe_recover(struct ipath_devdata *dd)
1381{
1382 if (ipath_unordered_wc())
1383 ipath_dbg("Recovering from TXE PIO parity error\n");
1384 else {
1385 int cnt = ++ipath_stats.sps_txeparity;
1386 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS) {
1387 if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1388 ipath_dev_err(dd,
1389 "Too many attempts to recover from "
1390 "TXE parity, giving up\n");
1391 return 0;
1392 }
1393 dev_info(&dd->pcidev->dev,
1394 "Recovering from TXE PIO parity error\n");
1395 }
9783ab40
BS		 1396 return 1;
1397}
1398
dc741bbd 1399/**
525d0ca1 1400 * ipath_init_iba6120_funcs - set up the chip-specific function pointers
dc741bbd
BS		 1401 * @dd: the infinipath device
1402 *
1403 * This is global, and is called directly at init to set up the
1404 * chip-specific function pointers for later use.
1405 */
525d0ca1 1406void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
dc741bbd
BS		 1407{
1408 dd->ipath_f_intrsetup = ipath_pe_intconfig;
1409 dd->ipath_f_bus = ipath_setup_pe_config;
1410 dd->ipath_f_reset = ipath_setup_pe_reset;
1411 dd->ipath_f_get_boardname = ipath_pe_boardname;
1412 dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1413 dd->ipath_f_early_init = ipath_pe_early_init;
1414 dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1415 dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1416 dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1417 dd->ipath_f_clear_tids = ipath_pe_clear_tids;
cf5b60aa
DO		 1418 /*
1419 * this may get changed after we read the chip revision,
1420 * but we start with the safe version for all revs
1421 */
1422 dd->ipath_f_put_tid = ipath_pe_put_tid;
dc741bbd
BS		 1423 dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1424 dd->ipath_f_setextled = ipath_setup_pe_setextled;
1425 dd->ipath_f_get_base_info = ipath_pe_get_base_info;
51f65ebc 1426 dd->ipath_f_free_irq = ipath_pe_free_irq;
dc741bbd
BS		 1427
1428 /* initialize chip-specific variables */
1429 dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1430
1431 /*
1432 * setup the register offsets, since they are different for each
1433 * chip
1434 */
1435 dd->ipath_kregs = &ipath_pe_kregs;
1436 dd->ipath_cregs = &ipath_pe_cregs;
1437
f62fe77a 1438 ipath_init_pe_variables(dd);
dc741bbd
BS		 1439}
1440
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