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IB/ipath: Remove unused MDIO interface code
[net-next-2.6.git] / drivers / infiniband / hw / ipath / ipath_iba6120.c
CommitLineData
dc741bbd 1/*
87427da5 2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
dc741bbd
BS		 3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33/*
34 * This file contains all of the code that is specific to the
525d0ca1 35 * InfiniPath PCIe chip.
dc741bbd
BS		 36 */
37
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41
42
43#include "ipath_kernel.h"
44#include "ipath_registers.h"
45
f5408ac7
BS		 46static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64);
47
dc741bbd
BS		 48/*
49 * This file contains all the chip-specific register information and
525d0ca1 50 * access functions for the QLogic InfiniPath PCI-Express chip.
dc741bbd 51 *
525d0ca1 52 * This lists the InfiniPath registers, in the actual chip layout.
dc741bbd
BS		 53 * This structure should never be directly accessed.
54 */
55struct _infinipath_do_not_use_kernel_regs {
56 unsigned long long Revision;
57 unsigned long long Control;
58 unsigned long long PageAlign;
59 unsigned long long PortCnt;
60 unsigned long long DebugPortSelect;
61 unsigned long long Reserved0;
62 unsigned long long SendRegBase;
63 unsigned long long UserRegBase;
64 unsigned long long CounterRegBase;
65 unsigned long long Scratch;
66 unsigned long long Reserved1;
67 unsigned long long Reserved2;
68 unsigned long long IntBlocked;
69 unsigned long long IntMask;
70 unsigned long long IntStatus;
71 unsigned long long IntClear;
72 unsigned long long ErrorMask;
73 unsigned long long ErrorStatus;
74 unsigned long long ErrorClear;
75 unsigned long long HwErrMask;
76 unsigned long long HwErrStatus;
77 unsigned long long HwErrClear;
78 unsigned long long HwDiagCtrl;
79 unsigned long long MDIO;
80 unsigned long long IBCStatus;
81 unsigned long long IBCCtrl;
82 unsigned long long ExtStatus;
83 unsigned long long ExtCtrl;
84 unsigned long long GPIOOut;
85 unsigned long long GPIOMask;
86 unsigned long long GPIOStatus;
87 unsigned long long GPIOClear;
88 unsigned long long RcvCtrl;
89 unsigned long long RcvBTHQP;
90 unsigned long long RcvHdrSize;
91 unsigned long long RcvHdrCnt;
92 unsigned long long RcvHdrEntSize;
93 unsigned long long RcvTIDBase;
94 unsigned long long RcvTIDCnt;
95 unsigned long long RcvEgrBase;
96 unsigned long long RcvEgrCnt;
97 unsigned long long RcvBufBase;
98 unsigned long long RcvBufSize;
99 unsigned long long RxIntMemBase;
100 unsigned long long RxIntMemSize;
101 unsigned long long RcvPartitionKey;
102 unsigned long long Reserved3;
103 unsigned long long RcvPktLEDCnt;
104 unsigned long long Reserved4[8];
105 unsigned long long SendCtrl;
106 unsigned long long SendPIOBufBase;
107 unsigned long long SendPIOSize;
108 unsigned long long SendPIOBufCnt;
109 unsigned long long SendPIOAvailAddr;
110 unsigned long long TxIntMemBase;
111 unsigned long long TxIntMemSize;
112 unsigned long long Reserved5;
113 unsigned long long PCIeRBufTestReg0;
114 unsigned long long PCIeRBufTestReg1;
115 unsigned long long Reserved51[6];
116 unsigned long long SendBufferError;
117 unsigned long long SendBufferErrorCONT1;
118 unsigned long long Reserved6SBE[6];
119 unsigned long long RcvHdrAddr0;
120 unsigned long long RcvHdrAddr1;
121 unsigned long long RcvHdrAddr2;
122 unsigned long long RcvHdrAddr3;
123 unsigned long long RcvHdrAddr4;
124 unsigned long long Reserved7RHA[11];
125 unsigned long long RcvHdrTailAddr0;
126 unsigned long long RcvHdrTailAddr1;
127 unsigned long long RcvHdrTailAddr2;
128 unsigned long long RcvHdrTailAddr3;
129 unsigned long long RcvHdrTailAddr4;
130 unsigned long long Reserved8RHTA[11];
131 unsigned long long Reserved9SW[8];
132 unsigned long long SerdesConfig0;
133 unsigned long long SerdesConfig1;
134 unsigned long long SerdesStatus;
135 unsigned long long XGXSConfig;
136 unsigned long long IBPLLCfg;
137 unsigned long long Reserved10SW2[3];
138 unsigned long long PCIEQ0SerdesConfig0;
139 unsigned long long PCIEQ0SerdesConfig1;
140 unsigned long long PCIEQ0SerdesStatus;
141 unsigned long long Reserved11;
142 unsigned long long PCIEQ1SerdesConfig0;
143 unsigned long long PCIEQ1SerdesConfig1;
144 unsigned long long PCIEQ1SerdesStatus;
145 unsigned long long Reserved12;
146};
147
3029fcc3
RC		 148struct _infinipath_do_not_use_counters {
149 __u64 LBIntCnt;
150 __u64 LBFlowStallCnt;
151 __u64 Reserved1;
152 __u64 TxUnsupVLErrCnt;
153 __u64 TxDataPktCnt;
154 __u64 TxFlowPktCnt;
155 __u64 TxDwordCnt;
156 __u64 TxLenErrCnt;
157 __u64 TxMaxMinLenErrCnt;
158 __u64 TxUnderrunCnt;
159 __u64 TxFlowStallCnt;
160 __u64 TxDroppedPktCnt;
161 __u64 RxDroppedPktCnt;
162 __u64 RxDataPktCnt;
163 __u64 RxFlowPktCnt;
164 __u64 RxDwordCnt;
165 __u64 RxLenErrCnt;
166 __u64 RxMaxMinLenErrCnt;
167 __u64 RxICRCErrCnt;
168 __u64 RxVCRCErrCnt;
169 __u64 RxFlowCtrlErrCnt;
170 __u64 RxBadFormatCnt;
171 __u64 RxLinkProblemCnt;
172 __u64 RxEBPCnt;
173 __u64 RxLPCRCErrCnt;
174 __u64 RxBufOvflCnt;
175 __u64 RxTIDFullErrCnt;
176 __u64 RxTIDValidErrCnt;
177 __u64 RxPKeyMismatchCnt;
178 __u64 RxP0HdrEgrOvflCnt;
179 __u64 RxP1HdrEgrOvflCnt;
180 __u64 RxP2HdrEgrOvflCnt;
181 __u64 RxP3HdrEgrOvflCnt;
182 __u64 RxP4HdrEgrOvflCnt;
183 __u64 RxP5HdrEgrOvflCnt;
184 __u64 RxP6HdrEgrOvflCnt;
185 __u64 RxP7HdrEgrOvflCnt;
186 __u64 RxP8HdrEgrOvflCnt;
187 __u64 Reserved6;
188 __u64 Reserved7;
189 __u64 IBStatusChangeCnt;
190 __u64 IBLinkErrRecoveryCnt;
191 __u64 IBLinkDownedCnt;
192 __u64 IBSymbolErrCnt;
193};
194
195#define IPATH_KREG_OFFSET(field) (offsetof( \
196 struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
dc741bbd 197#define IPATH_CREG_OFFSET(field) (offsetof( \
3029fcc3 198 struct _infinipath_do_not_use_counters, field) / sizeof(u64))
dc741bbd
BS		 199
200static const struct ipath_kregs ipath_pe_kregs = {
201 .kr_control = IPATH_KREG_OFFSET(Control),
202 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
203 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
204 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
205 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
206 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
207 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
208 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
209 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
210 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
211 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
212 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
213 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
214 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
215 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
216 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
217 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
218 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
219 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
220 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
221 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
222 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
223 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
224 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
225 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
226 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
227 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
228 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
229 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
230 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
231 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
232 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
233 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
234 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
235 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
236 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
237 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
238 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
239 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
240 .kr_revision = IPATH_KREG_OFFSET(Revision),
241 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
242 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
243 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
244 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
245 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
246 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
247 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
248 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
249 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
250 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
251 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
252 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
253 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
254 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
255 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
256 .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
257
258 /*
c8c6f5d4
BS		 259 * These should not be used directly via ipath_write_kreg64(),
260 * use them with ipath_write_kreg64_port(),
dc741bbd
BS		 261 */
262 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
263 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
264
dc741bbd
BS		 265 /* The rcvpktled register controls one of the debug port signals, so
266 * a packet activity LED can be connected to it. */
267 .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
268 .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
269 .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
270 .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
271 .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
272 .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
273 .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
274 .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
275 .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
276};
277
278static const struct ipath_cregs ipath_pe_cregs = {
279 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
280 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
281 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
282 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
283 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
284 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
285 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
286 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
287 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
288 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
289 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
290 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
291 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
292 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
293 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
294 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
295 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
296 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
297 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
298 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
299 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
300 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
301 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
302 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
303 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
304 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
305 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
306 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
307 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
308 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
309 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
310 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
311 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
312};
313
314/* kr_intstatus, kr_intclear, kr_intmask bits */
f62fe77a
BS		 315#define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
316#define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
dc741bbd
BS		 317
318/* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
319#define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
320#define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
321#define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
322#define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
323#define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
324#define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
325#define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
326#define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
327#define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
328#define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
329#define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
330#define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL
331
332/* kr_extstatus bits */
333#define INFINIPATH_EXTS_FREQSEL 0x2
334#define INFINIPATH_EXTS_SERDESSEL 0x4
335#define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
336#define INFINIPATH_EXTS_MEMBIST_FOUND 0x0000000000008000
337
338#define _IPATH_GPIO_SDA_NUM 1
339#define _IPATH_GPIO_SCL_NUM 0
340
341#define IPATH_GPIO_SDA (1ULL << \
342 (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
343#define IPATH_GPIO_SCL (1ULL << \
344 (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
345
d8274869
DO		 346#define INFINIPATH_R_INTRAVAIL_SHIFT 16
347#define INFINIPATH_R_TAILUPD_SHIFT 31
348
8d588f8b
BS		 349/* 6120 specific hardware errors... */
350static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
351 INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
352 INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
353 /*
354 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
355 * parity or memory parity error failures, because most likely we
356 * won't be able to talk to the core of the chip. Nonetheless, we
357 * might see them, if they are in parts of the PCIe core that aren't
358 * essential.
359 */
360 INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
361 INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
362 INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
363 INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
364 INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
365 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
366 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
367};
368
9783ab40
BS		 369#define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
370 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
371 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
372
373static int ipath_pe_txe_recover(struct ipath_devdata *);
cf5b60aa
DO		 374static void ipath_pe_put_tid_2(struct ipath_devdata *, u64 __iomem *,
375 u32, unsigned long);
9783ab40 376
dc741bbd
BS		 377/**
378 * ipath_pe_handle_hwerrors - display hardware errors.
379 * @dd: the infinipath device
380 * @msg: the output buffer
381 * @msgl: the size of the output buffer
382 *
383 * Use same msg buffer as regular errors to avoid excessive stack
384 * use. Most hardware errors are catastrophic, but for right now,
385 * we'll print them and continue. We reuse the same message buffer as
386 * ipath_handle_errors() to avoid excessive stack usage.
387 */
ac2ae4c9
RD		 388static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
389 size_t msgl)
dc741bbd
BS		 390{
391 ipath_err_t hwerrs;
392 u32 bits, ctrl;
393 int isfatal = 0;
394 char bitsmsg[64];
aecd3b5a 395 int log_idx;
dc741bbd
BS		 396
397 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
398 if (!hwerrs) {
399 /*
400 * better than printing cofusing messages
401 * This seems to be related to clearing the crc error, or
402 * the pll error during init.
403 */
404 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
405 return;
406 } else if (hwerrs == ~0ULL) {
407 ipath_dev_err(dd, "Read of hardware error status failed "
408 "(all bits set); ignoring\n");
409 return;
410 }
411 ipath_stats.sps_hwerrs++;
412
413 /* Always clear the error status register, except MEMBISTFAIL,
414 * regardless of whether we continue or stop using the chip.
415 * We want that set so we know it failed, even across driver reload.
416 * We'll still ignore it in the hwerrmask. We do this partly for
417 * diagnostics, but also for support */
418 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
419 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
420
421 hwerrs &= dd->ipath_hwerrmask;
422
aecd3b5a
MA		 423 /* We log some errors to EEPROM, check if we have any of those. */
424 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
425 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
426 ipath_inc_eeprom_err(dd, log_idx, 1);
427
dc741bbd
BS		 428 /*
429 * make sure we get this much out, unless told to be quiet,
430 * or it's occurred within the last 5 seconds
431 */
89d1e09b
BS		 432 if ((hwerrs & ~(dd->ipath_lasthwerror |
433 ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
434 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
435 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
dc741bbd
BS		 436 (ipath_debug & __IPATH_VERBDBG))
437 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
438 "(cleared)\n", (unsigned long long) hwerrs);
439 dd->ipath_lasthwerror |= hwerrs;
440
f62fe77a 441 if (hwerrs & ~dd->ipath_hwe_bitsextant)
dc741bbd
BS		 442 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
443 "%llx set\n", (unsigned long long)
f62fe77a 444 (hwerrs & ~dd->ipath_hwe_bitsextant));
dc741bbd
BS		 445
446 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
447 if (ctrl & INFINIPATH_C_FREEZEMODE) {
89d1e09b
BS		 448 /*
449 * parity errors in send memory are recoverable,
450 * just cancel the send (if indicated in * sendbuffererror),
451 * count the occurrence, unfreeze (if no other handled
452 * hardware error bits are set), and continue. They can
453 * occur if a processor speculative read is done to the PIO
454 * buffer while we are sending a packet, for example.
455 */
9783ab40
BS		 456 if ((hwerrs & TXE_PIO_PARITY) && ipath_pe_txe_recover(dd))
457 hwerrs &= ~TXE_PIO_PARITY;
dc741bbd
BS		 458 if (hwerrs) {
459 /*
460 * if any set that we aren't ignoring only make the
461 * complaint once, in case it's stuck or recurring,
462 * and we get here multiple times
f5408ac7
BS		 463 * Force link down, so switch knows, and
464 * LEDs are turned off
dc741bbd
BS		 465 */
466 if (dd->ipath_flags & IPATH_INITTED) {
f5408ac7
BS		 467 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
468 ipath_setup_pe_setextled(dd,
469 INFINIPATH_IBCS_L_STATE_DOWN,
470 INFINIPATH_IBCS_LT_STATE_DISABLED);
ff0b8597
BS		 471 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
472 "mode), no longer usable, SN %.16s\n",
473 dd->ipath_serial);
dc741bbd
BS		 474 isfatal = 1;
475 }
476 /*
477 * Mark as having had an error for driver, and also
478 * for /sys and status word mapped to user programs.
479 * This marks unit as not usable, until reset
480 */
481 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
482 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
483 dd->ipath_flags &= ~IPATH_INITTED;
484 } else {
9380068f
DO		 485 static u32 freeze_cnt;
486
487 freeze_cnt++;
488 ipath_dbg("Clearing freezemode on ignored or recovered "
489 "hardware error (%u)\n", freeze_cnt);
0f4fc5eb 490 ipath_clear_freeze(dd);
dc741bbd
BS		 491 }
492 }
493
494 *msg = '\0';
495
496 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
525d0ca1 497 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
dc741bbd
BS		 498 msgl);
499 /* ignore from now on, so disable until driver reloaded */
500 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
501 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
502 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
503 dd->ipath_hwerrmask);
504 }
8d588f8b
BS		 505
506 ipath_format_hwerrors(hwerrs,
507 ipath_6120_hwerror_msgs,
508 sizeof(ipath_6120_hwerror_msgs)/
509 sizeof(ipath_6120_hwerror_msgs[0]),
510 msg, msgl);
511
dc741bbd
BS		 512 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
513 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
514 bits = (u32) ((hwerrs >>
515 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
516 INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
517 snprintf(bitsmsg, sizeof bitsmsg,
518 "[PCIe Mem Parity Errs %x] ", bits);
519 strlcat(msg, bitsmsg, msgl);
520 }
dc741bbd
BS		 521
522#define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
523 INFINIPATH_HWE_COREPLL_RFSLIP )
524
525 if (hwerrs & _IPATH_PLL_FAIL) {
526 snprintf(bitsmsg, sizeof bitsmsg,
525d0ca1 527 "[PLL failed (%llx), InfiniPath hardware unusable]",
dc741bbd
BS		 528 (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
529 strlcat(msg, bitsmsg, msgl);
530 /* ignore from now on, so disable until driver reloaded */
531 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
532 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
533 dd->ipath_hwerrmask);
534 }
535
536 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
537 /*
9e2ef36b 538 * If it occurs, it is left masked since the external
dc741bbd
BS		 539 * interface is unused
540 */
541 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
542 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
543 dd->ipath_hwerrmask);
544 }
545
f5408ac7
BS		 546 if (*msg)
547 ipath_dev_err(dd, "%s hardware error\n", msg);
dc741bbd
BS		 548 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
549 /*
550 * for /sys status file ; if no trailing } is copied, we'll
551 * know it was truncated.
552 */
553 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
554 "{%s}", msg);
555 }
556}
557
558/**
559 * ipath_pe_boardname - fill in the board name
560 * @dd: the infinipath device
561 * @name: the output buffer
562 * @namelen: the size of the output buffer
563 *
564 * info is based on the board revision register
565 */
566static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
567 size_t namelen)
568{
569 char *n = NULL;
570 u8 boardrev = dd->ipath_boardrev;
571 int ret;
572
573 switch (boardrev) {
574 case 0:
575 n = "InfiniPath_Emulation";
576 break;
577 case 1:
525d0ca1 578 n = "InfiniPath_QLE7140-Bringup";
dc741bbd
BS		 579 break;
580 case 2:
525d0ca1 581 n = "InfiniPath_QLE7140";
dc741bbd
BS		 582 break;
583 case 3:
525d0ca1 584 n = "InfiniPath_QMI7140";
dc741bbd
BS		 585 break;
586 case 4:
525d0ca1
BS		 587 n = "InfiniPath_QEM7140";
588 break;
589 case 5:
590 n = "InfiniPath_QMH7140";
dc741bbd 591 break;
bf3258ec
BS		 592 case 6:
593 n = "InfiniPath_QLE7142";
594 break;
dc741bbd
BS		 595 default:
596 ipath_dev_err(dd,
597 "Don't yet know about board with ID %u\n",
598 boardrev);
525d0ca1 599 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
dc741bbd
BS		 600 boardrev);
601 break;
602 }
603 if (n)
604 snprintf(name, namelen, "%s", n);
605
8307c28e 606 if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
525d0ca1 607 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
dc741bbd
BS		 608 dd->ipath_majrev, dd->ipath_minrev);
609 ret = 1;
cf5b60aa 610 } else {
dc741bbd 611 ret = 0;
cf5b60aa
DO		 612 if (dd->ipath_minrev >= 2)
613 dd->ipath_f_put_tid = ipath_pe_put_tid_2;
614 }
dc741bbd 615
a18e26ae
RC		 616
617 /*
618 * set here, not in ipath_init_*_funcs because we have to do
619 * it after we can read chip registers.
620 */
621 dd->ipath_ureg_align =
622 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
623
dc741bbd
BS		 624 return ret;
625}
626
627/**
628 * ipath_pe_init_hwerrors - enable hardware errors
629 * @dd: the infinipath device
630 *
631 * now that we have finished initializing everything that might reasonably
632 * cause a hardware error, and cleared those errors bits as they occur,
633 * we can enable hardware errors in the mask (potentially enabling
634 * freeze mode), and enable hardware errors as errors (along with
635 * everything else) in errormask
636 */
ac2ae4c9 637static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
dc741bbd
BS		 638{
639 ipath_err_t val;
640 u64 extsval;
641
642 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
643
644 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
645 ipath_dev_err(dd, "MemBIST did not complete!\n");
9783ab40
BS		 646 if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
647 ipath_dbg("MemBIST corrected\n");
dc741bbd
BS		 648
649 val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */
650
651 if (!dd->ipath_boardrev) // no PLL for Emulator
652 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
653
2c9446a1
BS		 654 if (dd->ipath_minrev < 2) {
655 /* workaround bug 9460 in internal interface bus parity
656 * checking. Fixed (HW bug 9490) in Rev2.
657 */
658 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
659 }
dc741bbd
BS		 660 dd->ipath_hwerrmask = val;
661}
662
663/**
664 * ipath_pe_bringup_serdes - bring up the serdes
665 * @dd: the infinipath device
666 */
ac2ae4c9 667static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
dc741bbd 668{
44f8e3f3 669 u64 val, config1, prev_val;
2c9446a1 670 int ret = 0;
dc741bbd
BS		 671
672 ipath_dbg("Trying to bringup serdes\n");
673
674 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
675 INFINIPATH_HWE_SERDESPLLFAILED) {
676 ipath_dbg("At start, serdes PLL failed bit set "
677 "in hwerrstatus, clearing and continuing\n");
678 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
679 INFINIPATH_HWE_SERDESPLLFAILED);
680 }
681
682 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
683 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
684
685 ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
686 "xgxsconfig %llx\n", (unsigned long long) val,
687 (unsigned long long) config1, (unsigned long long)
688 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
689
690 /*
691 * Force reset on, also set rxdetect enable. Must do before reading
692 * serdesstatus at least for simulation, or some of the bits in
693 * serdes status will come back as undefined and cause simulation
694 * failures
695 */
696 val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
697 | INFINIPATH_SERDC0_L1PWR_DN;
698 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
699 /* be sure chip saw it */
44f8e3f3 700 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
dc741bbd
BS		 701 udelay(5); /* need pll reset set at least for a bit */
702 /*
703 * after PLL is reset, set the per-lane Resets and TxIdle and
704 * clear the PLL reset and rxdetect (to get falling edge).
705 * Leave L1PWR bits set (permanently)
706 */
707 val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
708 | INFINIPATH_SERDC0_L1PWR_DN);
709 val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
710 ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
711 "and txidle (%llx)\n", (unsigned long long) val);
712 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
713 /* be sure chip saw it */
44f8e3f3 714 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
dc741bbd
BS		 715 /* need PLL reset clear for at least 11 usec before lane
716 * resets cleared; give it a few more to be sure */
717 udelay(15);
718 val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
719
720 ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
721 "(writing %llx)\n", (unsigned long long) val);
722 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
723 /* be sure chip saw it */
724 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
725
726 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2c9446a1 727 prev_val = val;
73872733 728 if (val & INFINIPATH_XGXS_RESET)
dc741bbd 729 val &= ~INFINIPATH_XGXS_RESET;
30fc5c31
BS		 730 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
731 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
732 /* need to compensate for Tx inversion in partner */
733 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
734 INFINIPATH_XGXS_RX_POL_SHIFT);
735 val |= dd->ipath_rx_pol_inv <<
736 INFINIPATH_XGXS_RX_POL_SHIFT;
30fc5c31 737 }
2c9446a1 738 if (val != prev_val)
dc741bbd
BS		 739 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
740
741 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
742
743 /* clear current and de-emphasis bits */
744 config1 &= ~0x0ffffffff00ULL;
745 /* set current to 20ma */
746 config1 |= 0x00000000000ULL;
747 /* set de-emphasis to -5.68dB */
748 config1 |= 0x0cccc000000ULL;
749 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
750
751 ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
752 "config1=%llx, sstatus=%llx xgxs=%llx\n",
753 (unsigned long long) val, (unsigned long long) config1,
754 (unsigned long long)
755 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
756 (unsigned long long)
757 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
758
dc741bbd
BS		 759 return ret;
760}
761
762/**
763 * ipath_pe_quiet_serdes - set serdes to txidle
764 * @dd: the infinipath device
765 * Called when driver is being unloaded
766 */
ac2ae4c9 767static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
dc741bbd
BS		 768{
769 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
770
771 val |= INFINIPATH_SERDC0_TXIDLE;
772 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
773 (unsigned long long) val);
774 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
775}
776
dc741bbd
BS		 777static int ipath_pe_intconfig(struct ipath_devdata *dd)
778{
2c9446a1
BS		 779 u32 chiprev;
780
781 /*
782 * If the chip supports added error indication via GPIO pins,
783 * enable interrupts on those bits so the interrupt routine
784 * can count the events. Also set flag so interrupt routine
785 * can know they are expected.
786 */
787 chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
788 if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
789 /* Rev2+ reports extra errors via internal GPIO pins */
790 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
8f140b40
AJ		 791 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
792 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
793 dd->ipath_gpio_mask);
2c9446a1 794 }
dc741bbd
BS		 795 return 0;
796}
797
798/**
799 * ipath_setup_pe_setextled - set the state of the two external LEDs
800 * @dd: the infinipath device
801 * @lst: the L state
802 * @ltst: the LT state
803
804 * These LEDs indicate the physical and logical state of IB link.
805 * For this chip (at least with recommended board pinouts), LED1
806 * is Yellow (logical state) and LED2 is Green (physical state),
807 *
808 * Note: We try to match the Mellanox HCA LED behavior as best
809 * we can. Green indicates physical link state is OK (something is
810 * plugged in, and we can train).
811 * Amber indicates the link is logically up (ACTIVE).
812 * Mellanox further blinks the amber LED to indicate data packet
813 * activity, but we have no hardware support for that, so it would
814 * require waking up every 10-20 msecs and checking the counters
815 * on the chip, and then turning the LED off if appropriate. That's
816 * visible overhead, so not something we will do.
817 *
818 */
819static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
820 u64 ltst)
821{
822 u64 extctl;
17b2eb9f 823 unsigned long flags = 0;
dc741bbd
BS		 824
825 /* the diags use the LED to indicate diag info, so we leave
826 * the external LED alone when the diags are running */
827 if (ipath_diag_inuse)
828 return;
829
82466f00
MA		 830 /* Allow override of LED display for, e.g. Locating system in rack */
831 if (dd->ipath_led_override) {
832 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
833 ? INFINIPATH_IBCS_LT_STATE_LINKUP
834 : INFINIPATH_IBCS_LT_STATE_DISABLED;
835 lst = (dd->ipath_led_override & IPATH_LED_LOG)
836 ? INFINIPATH_IBCS_L_STATE_ACTIVE
837 : INFINIPATH_IBCS_L_STATE_DOWN;
838 }
839
17b2eb9f 840 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
dc741bbd
BS		 841 extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
842 INFINIPATH_EXTC_LED2PRIPORT_ON);
843
844 if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
845 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
846 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
847 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
848 dd->ipath_extctrl = extctl;
849 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
17b2eb9f 850 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
dc741bbd
BS		 851}
852
853/**
854 * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
855 * @dd: the infinipath device
856 *
857 * This is called during driver unload.
858 * We do the pci_disable_msi here, not in generic code, because it
525d0ca1
BS		 859 * isn't used for the HT chips. If we do end up needing pci_enable_msi
860 * at some point in the future for HT, we'll move the call back
dc741bbd
BS		 861 * into the main init_one code.
862 */
863static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
864{
865 dd->ipath_msi_lo = 0; /* just in case unload fails */
866 pci_disable_msi(dd->pcidev);
867}
868
869/**
870 * ipath_setup_pe_config - setup PCIe config related stuff
871 * @dd: the infinipath device
872 * @pdev: the PCI device
873 *
874 * The pci_enable_msi() call will fail on systems with MSI quirks
875 * such as those with AMD8131, even if the device of interest is not
876 * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
877 * late in 2.6.16).
878 * All that can be done is to edit the kernel source to remove the quirk
879 * check until that is fixed.
525d0ca1
BS		 880 * We do not need to call enable_msi() for our HyperTransport chip,
881 * even though it uses MSI, and we want to avoid the quirk warning, so
882 * So we call enable_msi only for PCIe. If we do end up needing
883 * pci_enable_msi at some point in the future for HT, we'll move the
dc741bbd
BS		 884 * call back into the main init_one code.
885 * We save the msi lo and hi values, so we can restore them after
886 * chip reset (the kernel PCI infrastructure doesn't yet handle that
887 * correctly).
888 */
889static int ipath_setup_pe_config(struct ipath_devdata *dd,
890 struct pci_dev *pdev)
891{
892 int pos, ret;
893
894 dd->ipath_msi_lo = 0; /* used as a flag during reset processing */
895 ret = pci_enable_msi(dd->pcidev);
896 if (ret)
897 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
898 "interrupts may not work\n", ret);
899 /* continue even if it fails, we may still be OK... */
0a1336c8 900 dd->ipath_irq = pdev->irq;
dc741bbd
BS		 901
902 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
903 u16 control;
904 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
905 &dd->ipath_msi_lo);
906 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
907 &dd->ipath_msi_hi);
908 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
909 &control);
910 /* now save the data (vector) info */
911 pci_read_config_word(dd->pcidev,
912 pos + ((control & PCI_MSI_FLAGS_64BIT)
913 ? 12 : 8),
914 &dd->ipath_msi_data);
915 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
916 "0x%x, control=0x%x\n", dd->ipath_msi_data,
917 pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
918 control);
919 /* we save the cachelinesize also, although it doesn't
920 * really matter */
921 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
922 &dd->ipath_pci_cacheline);
923 } else
924 ipath_dev_err(dd, "Can't find MSI capability, "
925 "can't save MSI settings for reset\n");
926 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
927 u16 linkstat;
928 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
929 &linkstat);
930 linkstat >>= 4;
931 linkstat &= 0x1f;
932 if (linkstat != 8)
933 ipath_dev_err(dd, "PCIe width %u, "
934 "performance reduced\n", linkstat);
935 }
936 else
937 ipath_dev_err(dd, "Can't find PCI Express "
938 "capability!\n");
939 return 0;
940}
941
f62fe77a 942static void ipath_init_pe_variables(struct ipath_devdata *dd)
dc741bbd
BS		 943{
944 /*
945 * bits for selecting i2c direction and values,
946 * used for I2C serial flash
947 */
f62fe77a
BS		 948 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
949 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
950 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
951 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
dc741bbd 952
d8274869
DO		 953 /* Fill in shifts for RcvCtrl. */
954 dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
955 dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
956 dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
957 dd->ipath_r_portcfg_shift = 0; /* Not on IBA6120 */
958
dc741bbd 959 /* variables for sanity checking interrupt and errors */
f62fe77a 960 dd->ipath_hwe_bitsextant =
dc741bbd
BS		 961 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
962 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
89d1e09b
BS		 963 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
964 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
dc741bbd
BS		 965 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
966 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
967 INFINIPATH_HWE_PCIE1PLLFAILED |
968 INFINIPATH_HWE_PCIE0PLLFAILED |
969 INFINIPATH_HWE_PCIEPOISONEDTLP |
970 INFINIPATH_HWE_PCIECPLTIMEOUT |
971 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
972 INFINIPATH_HWE_PCIEBUSPARITYXADM |
973 INFINIPATH_HWE_PCIEBUSPARITYRADM |
974 INFINIPATH_HWE_MEMBISTFAILED |
975 INFINIPATH_HWE_COREPLL_FBSLIP |
976 INFINIPATH_HWE_COREPLL_RFSLIP |
977 INFINIPATH_HWE_SERDESPLLFAILED |
978 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
979 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
f62fe77a 980 dd->ipath_i_bitsextant =
dc741bbd
BS		 981 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
982 (INFINIPATH_I_RCVAVAIL_MASK <<
983 INFINIPATH_I_RCVAVAIL_SHIFT) |
984 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
985 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
f62fe77a 986 dd->ipath_e_bitsextant =
dc741bbd
BS		 987 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
988 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
989 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
990 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
991 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
992 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
993 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
994 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
995 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
996 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
997 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
998 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
999 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1000 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1001 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1002 INFINIPATH_E_HARDWARE;
1003
f62fe77a
BS		 1004 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1005 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
aecd3b5a
MA		 1006
1007 /*
1008 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1009 * 2 is Some Misc, 3 is reserved for future.
1010 */
1011 dd->ipath_eep_st_masks[0].hwerrs_to_log =
1012 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1013 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1014
1015 /* Ignore errors in PIO/PBC on systems with unordered write-combining */
1016 if (ipath_unordered_wc())
1017 dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
1018
1019 dd->ipath_eep_st_masks[1].hwerrs_to_log =
1020 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1021 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1022
1023 dd->ipath_eep_st_masks[2].errs_to_log =
1024 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
1025
1026
dc741bbd
BS		 1027}
1028
1029/* setup the MSI stuff again after a reset. I'd like to just call
1030 * pci_enable_msi() and request_irq() again, but when I do that,
1031 * the MSI enable bit doesn't get set in the command word, and
1032 * we switch to to a different interrupt vector, which is confusing,
1033 * so I instead just do it all inline. Perhaps somehow can tie this
1034 * into the PCIe hotplug support at some point
1035 * Note, because I'm doing it all here, I don't call pci_disable_msi()
1036 * or free_irq() at the start of ipath_setup_pe_reset().
1037 */
1038static int ipath_reinit_msi(struct ipath_devdata *dd)
1039{
1040 int pos;
1041 u16 control;
1042 int ret;
1043
1044 if (!dd->ipath_msi_lo) {
1045 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
1046 "initial setup failed?\n");
1047 ret = 0;
1048 goto bail;
1049 }
1050
1051 if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1052 ipath_dev_err(dd, "Can't find MSI capability, "
1053 "can't restore MSI settings\n");
1054 ret = 0;
1055 goto bail;
1056 }
1057 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1058 dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1059 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1060 dd->ipath_msi_lo);
1061 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1062 dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1063 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1064 dd->ipath_msi_hi);
1065 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1066 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1067 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1068 "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1069 control, control | PCI_MSI_FLAGS_ENABLE);
1070 control |= PCI_MSI_FLAGS_ENABLE;
1071 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1072 control);
1073 }
1074 /* now rewrite the data (vector) info */
1075 pci_write_config_word(dd->pcidev, pos +
1076 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1077 dd->ipath_msi_data);
1078 /* we restore the cachelinesize also, although it doesn't really
1079 * matter */
1080 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1081 dd->ipath_pci_cacheline);
1082 /* and now set the pci master bit again */
1083 pci_set_master(dd->pcidev);
1084 ret = 1;
1085
1086bail:
1087 return ret;
1088}
1089
1090/* This routine sleeps, so it can only be called from user context, not
1091 * from interrupt context. If we need interrupt context, we can split
1092 * it into two routines.
1093*/
1094static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1095{
1096 u64 val;
1097 int i;
1098 int ret;
1099
1100 /* Use ERROR so it shows up in logs, etc. */
525d0ca1 1101 ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
c71c30dc
BS		 1102 /* keep chip from being accessed in a few places */
1103 dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
dc741bbd
BS		 1104 val = dd->ipath_control | INFINIPATH_C_RESET;
1105 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1106 mb();
1107
1108 for (i = 1; i <= 5; i++) {
1109 int r;
1110 /* allow MBIST, etc. to complete; longer on each retry.
1111 * We sometimes get machine checks from bus timeout if no
1112 * response, so for now, make it *really* long.
1113 */
1114 msleep(1000 + (1 + i) * 2000);
1115 if ((r =
1116 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1117 dd->ipath_pcibar0)))
1118 ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1119 r);
1120 if ((r =
1121 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1122 dd->ipath_pcibar1)))
1123 ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1124 r);
1125 /* now re-enable memory access */
1126 if ((r = pci_enable_device(dd->pcidev)))
1127 ipath_dev_err(dd, "pci_enable_device failed after "
1128 "reset: %d\n", r);
c71c30dc
BS		 1129 /* whether it worked or not, mark as present, again */
1130 dd->ipath_flags |= IPATH_PRESENT;
dc741bbd
BS		 1131 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1132 if (val == dd->ipath_revision) {
1133 ipath_cdbg(VERBOSE, "Got matching revision "
1134 "register %llx on try %d\n",
1135 (unsigned long long) val, i);
1136 ret = ipath_reinit_msi(dd);
1137 goto bail;
1138 }
1139 /* Probably getting -1 back */
1140 ipath_dbg("Didn't get expected revision register, "
1141 "got %llx, try %d\n", (unsigned long long) val,
1142 i + 1);
1143 }
1144 ret = 0; /* failed */
1145
1146bail:
1147 return ret;
1148}
1149
1150/**
1151 * ipath_pe_put_tid - write a TID in chip
1152 * @dd: the infinipath device
1153 * @tidptr: pointer to the expected TID (in chip) to udpate
f716cdfe 1154 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
dc741bbd
BS		 1155 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1156 *
1157 * This exists as a separate routine to allow for special locking etc.
1158 * It's used for both the full cleanup on exit, as well as the normal
1159 * setup and teardown.
1160 */
1161static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1162 u32 type, unsigned long pa)
1163{
1164 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1165 unsigned long flags = 0; /* keep gcc quiet */
1166
1167 if (pa != dd->ipath_tidinvalid) {
1168 if (pa & ((1U << 11) - 1)) {
1169 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1170 "not 4KB aligned!\n", pa);
1171 return;
1172 }
1173 pa >>= 11;
1174 /* paranoia check */
1175 if (pa & (7<<29))
1176 ipath_dev_err(dd,
1177 "BUG: Physical page address 0x%lx "
1178 "has bits set in 31-29\n", pa);
1179
f716cdfe 1180 if (type == RCVHQ_RCV_TYPE_EAGER)
dc741bbd
BS		 1181 pa |= dd->ipath_tidtemplate;
1182 else /* for now, always full 4KB page */
1183 pa |= 2 << 29;
1184 }
1185
9ef8617a
DO		 1186 /*
1187 * Workaround chip bug 9437 by writing the scratch register
1188 * before and after the TID, and with an io write barrier.
1189 * We use a spinlock around the writes, so they can't intermix
1190 * with other TID (eager or expected) writes (the chip bug
1191 * is triggered by back to back TID writes). Unfortunately, this
1192 * call can be done from interrupt level for the port 0 eager TIDs,
1193 * so we have to use irqsave locks.
dc741bbd
BS		 1194 */
1195 spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1196 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1197 if (dd->ipath_kregbase)
1198 writel(pa, tidp32);
1199 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1200 mmiowb();
1201 spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1202}
2c9446a1
BS		 1203/**
1204 * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1205 * @dd: the infinipath device
1206 * @tidptr: pointer to the expected TID (in chip) to udpate
f716cdfe 1207 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
2c9446a1
BS		 1208 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1209 *
1210 * This exists as a separate routine to allow for selection of the
1211 * appropriate "flavor". The static calls in cleanup just use the
1212 * revision-agnostic form, as they are not performance critical.
1213 */
1214static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1215 u32 type, unsigned long pa)
1216{
1217 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1218
1219 if (pa != dd->ipath_tidinvalid) {
1220 if (pa & ((1U << 11) - 1)) {
1221 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1fd3b40f 1222 "not 2KB aligned!\n", pa);
2c9446a1
BS		 1223 return;
1224 }
1225 pa >>= 11;
1226 /* paranoia check */
1227 if (pa & (7<<29))
1228 ipath_dev_err(dd,
1229 "BUG: Physical page address 0x%lx "
1230 "has bits set in 31-29\n", pa);
1231
f716cdfe 1232 if (type == RCVHQ_RCV_TYPE_EAGER)
2c9446a1
BS		 1233 pa |= dd->ipath_tidtemplate;
1234 else /* for now, always full 4KB page */
1235 pa |= 2 << 29;
1236 }
1237 if (dd->ipath_kregbase)
1238 writel(pa, tidp32);
1239 mmiowb();
1240}
1241
dc741bbd
BS		 1242
1243/**
1244 * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1245 * @dd: the infinipath device
1246 * @port: the port
1247 *
1248 * clear all TID entries for a port, expected and eager.
525d0ca1 1249 * Used from ipath_close(). On this chip, TIDs are only 32 bits,
dc741bbd
BS		 1250 * not 64, but they are still on 64 bit boundaries, so tidbase
1251 * is declared as u64 * for the pointer math, even though we write 32 bits
1252 */
1253static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1254{
1255 u64 __iomem *tidbase;
1256 unsigned long tidinv;
1257 int i;
1258
1259 if (!dd->ipath_kregbase)
1260 return;
1261
1262 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1263
1264 tidinv = dd->ipath_tidinvalid;
1265 tidbase = (u64 __iomem *)
1266 ((char __iomem *)(dd->ipath_kregbase) +
1267 dd->ipath_rcvtidbase +
1268 port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1269
1270 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
cf5b60aa 1271 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
f716cdfe 1272 tidinv);
dc741bbd
BS		 1273
1274 tidbase = (u64 __iomem *)
1275 ((char __iomem *)(dd->ipath_kregbase) +
1276 dd->ipath_rcvegrbase +
1277 port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1278
1279 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
cf5b60aa 1280 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
f716cdfe 1281 tidinv);
dc741bbd
BS		 1282}
1283
1284/**
1285 * ipath_pe_tidtemplate - setup constants for TID updates
1286 * @dd: the infinipath device
1287 *
1288 * We setup stuff that we use a lot, to avoid calculating each time
1289 */
1290static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1291{
1292 u32 egrsize = dd->ipath_rcvegrbufsize;
1293
1294 /* For now, we always allocate 4KB buffers (at init) so we can
1295 * receive max size packets. We may want a module parameter to
1296 * specify 2KB or 4KB and/or make be per port instead of per device
1297 * for those who want to reduce memory footprint. Note that the
1298 * ipath_rcvhdrentsize size must be large enough to hold the largest
1299 * IB header (currently 96 bytes) that we expect to handle (plus of
1300 * course the 2 dwords of RHF).
1301 */
1302 if (egrsize == 2048)
1303 dd->ipath_tidtemplate = 1U << 29;
1304 else if (egrsize == 4096)
1305 dd->ipath_tidtemplate = 2U << 29;
1306 else {
1307 egrsize = 4096;
1308 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1309 "%u, using %u\n", dd->ipath_rcvegrbufsize,
1310 egrsize);
1311 dd->ipath_tidtemplate = 2U << 29;
1312 }
1313 dd->ipath_tidinvalid = 0;
1314}
1315
1316static int ipath_pe_early_init(struct ipath_devdata *dd)
1317{
1318 dd->ipath_flags |= IPATH_4BYTE_TID;
210d6ca3
RC		 1319 if (ipath_unordered_wc())
1320 dd->ipath_flags |= IPATH_PIO_FLUSH_WC;
dc741bbd
BS		 1321
1322 /*
525d0ca1
BS		 1323 * For openfabrics, we need to be able to handle an IB header of
1324 * 24 dwords. HT chip has arbitrary sized receive buffers, so we
1325 * made them the same size as the PIO buffers. This chip does not
dc741bbd
BS		 1326 * handle arbitrary size buffers, so we need the header large enough
1327 * to handle largest IB header, but still have room for a 2KB MTU
1328 * standard IB packet.
1329 */
1330 dd->ipath_rcvhdrentsize = 24;
1331 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1332
525d0ca1
BS		 1333 /*
1334 * To truly support a 4KB MTU (for usermode), we need to
1335 * bump this to a larger value. For now, we use them for
1336 * the kernel only.
dc741bbd
BS		 1337 */
1338 dd->ipath_rcvegrbufsize = 2048;
1339 /*
1340 * the min() check here is currently a nop, but it may not always
1341 * be, depending on just how we do ipath_rcvegrbufsize
1342 */
1343 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1344 dd->ipath_rcvegrbufsize +
1345 (dd->ipath_rcvhdrentsize << 2));
1346 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1347
1348 /*
525d0ca1 1349 * We can request a receive interrupt for 1 or
dc741bbd 1350 * more packets from current offset. For now, we set this
525d0ca1 1351 * up for a single packet.
dc741bbd
BS		 1352 */
1353 dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1354
f2080fa3
BS		 1355 ipath_get_eeprom_info(dd);
1356
dc741bbd
BS		 1357 return 0;
1358}
1359
1360int __attribute__((weak)) ipath_unordered_wc(void)
1361{
1362 return 0;
1363}
1364
1365/**
1366 * ipath_init_pe_get_base_info - set chip-specific flags for user code
2c9446a1 1367 * @pd: the infinipath port
dc741bbd
BS		 1368 * @kbase: ipath_base_info pointer
1369 *
1370 * We set the PCIE flag because the lower bandwidth on PCIe vs
d08df601 1371 * HyperTransport can affect some user packet algorithms.
dc741bbd
BS		 1372 */
1373static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1374{
1375 struct ipath_base_info *kinfo = kbase;
2c9446a1 1376 struct ipath_devdata *dd;
dc741bbd
BS		 1377
1378 if (ipath_unordered_wc()) {
1379 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1380 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1381 }
1382 else
1383 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1384
2c9446a1
BS		 1385 if (pd == NULL)
1386 goto done;
1387
1388 dd = pd->port_dd;
1389
2c9446a1 1390done:
20bed343
AJ		 1391 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE |
1392 IPATH_RUNTIME_FORCE_PIOAVAIL | IPATH_RUNTIME_PIO_REGSWAPPED;
dc741bbd
BS		 1393 return 0;
1394}
1395
51f65ebc
BS		 1396static void ipath_pe_free_irq(struct ipath_devdata *dd)
1397{
1398 free_irq(dd->ipath_irq, dd);
1399 dd->ipath_irq = 0;
1400}
1401
60948a41
RC		 1402static void ipath_pe_config_ports(struct ipath_devdata *dd, ushort cfgports)
1403{
1404 dd->ipath_portcnt =
1405 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1406 dd->ipath_p0_rcvegrcnt =
1407 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
1408}
1409
3029fcc3
RC		 1410static void ipath_pe_read_counters(struct ipath_devdata *dd,
1411 struct infinipath_counters *cntrs)
1412{
1413 cntrs->LBIntCnt =
1414 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt));
1415 cntrs->LBFlowStallCnt =
1416 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt));
1417 cntrs->TxSDmaDescCnt = 0;
1418 cntrs->TxUnsupVLErrCnt =
1419 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt));
1420 cntrs->TxDataPktCnt =
1421 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt));
1422 cntrs->TxFlowPktCnt =
1423 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt));
1424 cntrs->TxDwordCnt =
1425 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt));
1426 cntrs->TxLenErrCnt =
1427 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt));
1428 cntrs->TxMaxMinLenErrCnt =
1429 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt));
1430 cntrs->TxUnderrunCnt =
1431 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt));
1432 cntrs->TxFlowStallCnt =
1433 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt));
1434 cntrs->TxDroppedPktCnt =
1435 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt));
1436 cntrs->RxDroppedPktCnt =
1437 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt));
1438 cntrs->RxDataPktCnt =
1439 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt));
1440 cntrs->RxFlowPktCnt =
1441 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt));
1442 cntrs->RxDwordCnt =
1443 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt));
1444 cntrs->RxLenErrCnt =
1445 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt));
1446 cntrs->RxMaxMinLenErrCnt =
1447 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt));
1448 cntrs->RxICRCErrCnt =
1449 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt));
1450 cntrs->RxVCRCErrCnt =
1451 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt));
1452 cntrs->RxFlowCtrlErrCnt =
1453 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt));
1454 cntrs->RxBadFormatCnt =
1455 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt));
1456 cntrs->RxLinkProblemCnt =
1457 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt));
1458 cntrs->RxEBPCnt =
1459 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt));
1460 cntrs->RxLPCRCErrCnt =
1461 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt));
1462 cntrs->RxBufOvflCnt =
1463 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt));
1464 cntrs->RxTIDFullErrCnt =
1465 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt));
1466 cntrs->RxTIDValidErrCnt =
1467 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt));
1468 cntrs->RxPKeyMismatchCnt =
1469 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt));
1470 cntrs->RxP0HdrEgrOvflCnt =
1471 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt));
1472 cntrs->RxP1HdrEgrOvflCnt =
1473 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt));
1474 cntrs->RxP2HdrEgrOvflCnt =
1475 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt));
1476 cntrs->RxP3HdrEgrOvflCnt =
1477 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt));
1478 cntrs->RxP4HdrEgrOvflCnt =
1479 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt));
1480 cntrs->RxP5HdrEgrOvflCnt = 0;
1481 cntrs->RxP6HdrEgrOvflCnt = 0;
1482 cntrs->RxP7HdrEgrOvflCnt = 0;
1483 cntrs->RxP8HdrEgrOvflCnt = 0;
1484 cntrs->RxP9HdrEgrOvflCnt = 0;
1485 cntrs->RxP10HdrEgrOvflCnt = 0;
1486 cntrs->RxP11HdrEgrOvflCnt = 0;
1487 cntrs->RxP12HdrEgrOvflCnt = 0;
1488 cntrs->RxP13HdrEgrOvflCnt = 0;
1489 cntrs->RxP14HdrEgrOvflCnt = 0;
1490 cntrs->RxP15HdrEgrOvflCnt = 0;
1491 cntrs->RxP16HdrEgrOvflCnt = 0;
1492 cntrs->IBStatusChangeCnt =
1493 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt));
1494 cntrs->IBLinkErrRecoveryCnt =
1495 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt));
1496 cntrs->IBLinkDownedCnt =
1497 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt));
1498 cntrs->IBSymbolErrCnt =
1499 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt));
1500 cntrs->RxVL15DroppedPktCnt = 0;
1501 cntrs->RxOtherLocalPhyErrCnt = 0;
1502 cntrs->PcieRetryBufDiagQwordCnt = 0;
1503 cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs;
1504 cntrs->LocalLinkIntegrityErrCnt = dd->ipath_lli_errs;
1505 cntrs->RxVlErrCnt = 0;
1506 cntrs->RxDlidFltrCnt = 0;
1507}
1508
9783ab40
BS		 1509/*
1510 * On platforms using this chip, and not having ordered WC stores, we
1511 * can get TXE parity errors due to speculative reads to the PIO buffers,
1512 * and this, due to a chip bug can result in (many) false parity error
1513 * reports. So it's a debug print on those, and an info print on systems
1514 * where the speculative reads don't occur.
1515 * Because we can get lots of false errors, we have no upper limit
1516 * on recovery attempts on those platforms.
1517 */
1518static int ipath_pe_txe_recover(struct ipath_devdata *dd)
1519{
1520 if (ipath_unordered_wc())
1521 ipath_dbg("Recovering from TXE PIO parity error\n");
1522 else {
1523 int cnt = ++ipath_stats.sps_txeparity;
1524 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS) {
1525 if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1526 ipath_dev_err(dd,
1527 "Too many attempts to recover from "
1528 "TXE parity, giving up\n");
1529 return 0;
1530 }
1531 dev_info(&dd->pcidev->dev,
1532 "Recovering from TXE PIO parity error\n");
1533 }
9783ab40
BS		 1534 return 1;
1535}
1536
dc741bbd 1537/**
525d0ca1 1538 * ipath_init_iba6120_funcs - set up the chip-specific function pointers
dc741bbd
BS		 1539 * @dd: the infinipath device
1540 *
1541 * This is global, and is called directly at init to set up the
1542 * chip-specific function pointers for later use.
1543 */
525d0ca1 1544void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
dc741bbd
BS		 1545{
1546 dd->ipath_f_intrsetup = ipath_pe_intconfig;
1547 dd->ipath_f_bus = ipath_setup_pe_config;
1548 dd->ipath_f_reset = ipath_setup_pe_reset;
1549 dd->ipath_f_get_boardname = ipath_pe_boardname;
1550 dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1551 dd->ipath_f_early_init = ipath_pe_early_init;
1552 dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1553 dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1554 dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1555 dd->ipath_f_clear_tids = ipath_pe_clear_tids;
cf5b60aa
DO		 1556 /*
1557 * this may get changed after we read the chip revision,
1558 * but we start with the safe version for all revs
1559 */
1560 dd->ipath_f_put_tid = ipath_pe_put_tid;
dc741bbd
BS		 1561 dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1562 dd->ipath_f_setextled = ipath_setup_pe_setextled;
1563 dd->ipath_f_get_base_info = ipath_pe_get_base_info;
51f65ebc 1564 dd->ipath_f_free_irq = ipath_pe_free_irq;
dc741bbd
BS		 1565
1566 /* initialize chip-specific variables */
1567 dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
60948a41 1568 dd->ipath_f_config_ports = ipath_pe_config_ports;
3029fcc3 1569 dd->ipath_f_read_counters = ipath_pe_read_counters;
dc741bbd
BS		 1570
1571 /*
1572 * setup the register offsets, since they are different for each
1573 * chip
1574 */
1575 dd->ipath_kregs = &ipath_pe_kregs;
1576 dd->ipath_cregs = &ipath_pe_cregs;
1577
f62fe77a 1578 ipath_init_pe_variables(dd);
dc741bbd
BS		 1579}
1580
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